PIXEL CIRCUIT AND DISPLAY DEVICE THEREOF

Abstract

A pixel circuit according to an embodiment of an embodiment and a display device comprising the same are disclosed. A pixel circuit includes a drive element having a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gate signal; a second switching element configured to apply a data voltage to the first node in response to a second gate signal; a third switching element configured to connect a pixel drive voltage line to the first node in response to a third gate signal; a fourth switching element configured to connect the third node to a fourth node in response to the third gate signal;a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth gate signal; a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the second gate signal; a capacitor connected between the pixel drive voltage line and the second node; and a light-emitting element connected to the fourth node and a low-potential power voltage line.

Description

This application claims priority to Korean Patent Application No. 2023-0172215 filed on Dec. 1, 2023.BACKGROUNDField of InterestThe present disclosure relates to a pixel circuit and a display device including the same.Discussion of the Prior ArtElectroluminescent display devices are divided into inorganic and organic light emitting display devices depending on the material of the light emitting layer. An active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has an advantage that a response speed is high and a luminous efficiency, luminance, and viewing angle are large.In organic light emitting display devices, organic light emitting diodes (referred to as "OLEDs") are formed in each pixel. These organic light emitting display devices not only respond quickly and have excellent luminous efficiency, luminance and viewing angle, but also have excellent contrast ratio and color rendering rate because they can reproduce black tones as complete black.Some display devices such as a liquid crystal display device or an organic light emitting display device include a display panel including a plurality of sub-pixels, a driver that outputs a drive signal for driving the display panel, a power supply that generates power to be supplied to the display panel or the driver, and the like.In such a display device, when a driving signal such as a scanning signal, an EM signal, and a data signal is supplied to a plurality of pixels formed in the display panel, the selected pixel transmits light or directly emits light, thereby displaying an image.Each of the sub-pixels includes a driving element that controls a current flowing through a light emitting element, and a plurality of switching elements that switch the current. In this case, the driving element and the plurality of switching elements may be implemented as an N-channel LTPS TFT or a P-channel LTPS TFT including low-temperature polysilicon. Particularly, when all elements are implemented as P-channel LTPS TFTs, luminance is greatly reduced due to hysteresis characteristics of the TFTs when a data voltage is changed from a black gray level to a white gray level.SUMMARYThe present disclosure aims to solve all the needs and problems described above.The present disclosure provides a pixel circuit and a display device including the same.It is an object of the present invention to provide a pixel circuit and a display device including the same, which avoid reduced luminance due to hysteresis characteristics of the TFTs.Note that the objects of the present disclosure are not limited to the above-described objects, and other objects of the present disclosure will become apparent to those skilled in the art from the following descriptions.The object is achieved by the features of the independent claims. Preferred embodiments are set out in the dependent claims.A pixel circuit according to embodiments of the present disclosure may include: a driving element having a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node to the first node in response to a first gate signal; a second switching element configured to apply a data voltage to the first node in response to a second gate signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a third gate signal; a fourth switching element configured to connect the third node to a fourth node in response to the third gate signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth gate signal; a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the second gate signal; a capacitor connected between the pixel driving voltage line and the second node; and a light emitting element connected to the fourth node and a low potential power line.In one or more embodiments, the pixel circuit may be driven in the order of an initialization step, an OBS (Power On Bias) step, a sensing step, and a light emitting step.In one or more embodiments, in the initializing step, the fifth switching element may be turned on so that the voltage of the second node may be discharged to the first initializing voltage, and the sixth switching element may be turned on so that the voltage of the fourth node may be discharged to the second initializing voltage, and at the same time, in the OBS step, the second switching element may be turned on so that the data voltage of the previous frame may be applied to the first node.In one or more embodiments, in the sensing step, both the first switching element and the second switching element may be turned on so that the data voltage of the current frame is applied to the first node.A pixel circuit according to embodiments of the present disclosure may include: a driving element having a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node to the first node in response to a first gate signal; a second switching element configured to apply a data voltage to the first node in response to the first gate signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a second gate signal; a fourth switching element configured to connect the third node to a fourth node in response to a third gate signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth gate signal; a capacitor connected between the pixel driving voltage line and the second node; and a light emitting element connected to the fourth node and a low potential power line.In one or more embodiments, the pixel circuit may include a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the fourth gate signal.In one or more embodiments, the pixel circuit may be driven in the order of a first OBS step, an initialization step, a second OBS step, a sampling step, and a light emission step.In one or more embodiments, in the initializing step, the fifth switching element may be turned on so that the voltage of the second node may be discharged to the first initializing voltage, and the sixth switching element may be turned on so that the voltage of the fourth node may be discharged to the second initializing voltage, and at the same time, in the second OBS step, the third switching element may be turned on to apply a pixel driving voltage from the pixel driving voltage line to the first node.In one or more embodiments, in the first OBS step, the third switching element may be turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.In one or more embodiments, the pixel circuit may further include: a sixth switching element that applies the initialization voltage to the fourth node in response to the first gate signal; and a seventh switching element that is connected between the pixel driving voltage line and the capacitor and is configured to connect the pixel driving voltage line to a fifth node in response to the third gate signal.In one or more embodiments, the pixel circuit may be driven in the order of a first OBS step, an initialization step, a second OBS step, a sampling step, and a light emission step.In one or more embodiments, in the initializing step, the fifth switching element may be turned on so that the voltage of the second node may be discharged to the initializing voltage, and at the same time, in the second OBS step, the third switching element may be turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.In one or more embodiments, in the first OBS step, the third switching element may be turned on to apply the pixel driving voltage from the pixel driving voltage line to the first node.A display device according to embodiments of the present disclosure may include: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver that outputs a data voltage to the plurality of data lines; and a gate driver that outputs gate signals to the plurality of gate lines, each of the pixel circuits including: a driving element having a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gate signal; a second switching element configured to apply the data voltage to the first node in response to a second gate signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a third gate signal; a fourth switching element configured to connect the third node to a fourth node in response to the third gate signal; a fifth switching element configured to apply a first initialization voltage to the second node in response to a fourth gate signal; a sixth switching element configured to apply a second initialization voltage to the fourth node in response to the second gate signal; a capacitor connected between the pixel driving voltage line and the second node; and a light emitting element connected to the fourth node and a low potential power line.A display device according to embodiments of the present disclosure may include: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver that outputs a data voltage to the plurality of data lines; and a gate driver that outputs gate signals to the plurality of gate lines, each of the pixel circuits including: a driving element having a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first switching element configured to connect the second node and the third node in response to a first gate signal; a second switching element configured to apply the data voltage to the first node in response to the first gate signal; a third switching element configured to connect a pixel driving voltage line to the first node in response to a second gate signal; a fourth switching element configured to connect the third node to a fourth node in response to a third gate signal; a fifth switching element configured to apply an initialization voltage to the second node in response to a fourth gate signal; a capacitor connected between the pixel driving voltage line and the second node; and a light emitting element connected to the fourth node and a low potential power line.The present disclosure may improve FFR performance by implementing OBS driving in an initialization phase using a pixel driving voltage or a data voltage without additional arrangements such as a separate voltage source and a control TFT.The present disclosure can improve FFR performance, so that the response time can be improved as the speed of the change from the black gray level to the white gray level increases.In the present disclosure, flicker can be improved because the stabilization time is shortened toward the white gray level.In the present disclosure, power consumption can be reduced accordingly, so that driving at low power consumption can be possible because a separate power source for OBS driving and an additional arrangement such as a control TFT are not required.The effects of the present disclosure are not limited to the above-mentioned effects, and other effects that are not mentioned will become apparent to those skilled in the art from the following description and the appended claims.BRIEF DESCRIPTION OF THE DRAWINGSThe above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art when exemplary embodiments thereof are described in detail with reference to the accompanying drawings, in which: FIG. 1 is a block diagram showing a display device according to an embodiment of the present disclosure; FIG. 2 is a cross-sectional view showing a cross-sectional structure of the display panel shown in FIG. 1 ; FIG. 3 is a diagram showing a pixel circuit according to a comparative example; FIG. 4 is a diagram showing a driving timing of the pixel circuit shown in FIG. 3; FIG. 5 is a diagram for explaining a problem occurring when the pixel circuit is connected; FIG. 4 is driven; FIG. 6 is a diagram showing the pixel circuit according to a first embodiment of the present disclosure; FIG. 7 is a diagram showing a driving timing of the pixel circuit shown in FIG. 6; FIGS. 8A to 8C are diagrams for explaining an operation principle of the pixel circuit of FIG. 7; FIG. 9 is a diagram for comparing and explaining simulation results of the pixel circuit according to the first embodiment; FIG. 10 is a diagram showing the pixel circuit according to a second embodiment of the present disclosure; FIG. 11 is a diagram showing a driving timing of the pixel circuit shown in FIG. 10; FIGS. 12A to 12C are diagrams for explaining an operation principle of the pixel circuit of FIG. 11; FIG. 13 is a diagram for comparing and explaining simulation results of a pixel circuit according to a second embodiment; FIG. 14 is a diagram showing the pixel circuit according to a third embodiment of the present disclosure; FIG. 15 is a diagram showing a driving timing of the pixel circuit shown in FIG. 14; FIGS. 16A to 16C are diagrams showing an operation principle of the pixel circuit shown in FIG. 15.DETAILED DESCRIPTION OF EMBODIMENTSAdvantages and features of the present disclosure and methods of achieving the same will become apparent from preferred embodiments described in detail in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments described below and may be implemented in various forms. The embodiments are provided only to fully disclose the present disclosure and fully convey the scope of the present disclosure to those skilled in the art, and the present disclosure is defined by the claims disclosed.Advantages and features of the present disclosure and methods of achieving the same will become apparent from preferred embodiments described in detail in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments described below and may be implemented in various forms. The embodiments are provided only to fully disclose the present disclosure and fully convey the scope of the present disclosure to those skilled in the art, and the present disclosure is defined by the claims disclosed.In the present specification, when the terms "include", "have", "consisting of", and the like are used, other parts may be added unless "only" is used. A case where a component is expressed in the singular form includes a plural form unless expressly stated otherwise.In designing the components, it should be noted that an error range is included, even if there is no separate explicit description thereof.In describing a positional relationship, when the positional relationship of two parts is described as "on", "at an upper portion", "at a lower portion", "next to", and the like, for example, one or more other parts may be located between the two parts unless "directly" or "directly" is used.Although "first / r / s", "second / r / s", and the like are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Accordingly, a first component mentioned below may also be a second component within the technical meaning of the present disclosure.The same reference numerals may refer to substantially the same elements throughout the present disclosure.The following embodiments may be partially or fully connected or combined with each other and linked and operated in technically various ways. The embodiments may be embodied independently of one another or in conjunction with one another.Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.In a display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. Transistors may be implemented as oxide thin film transistors (oxide TFTs) including an oxide semiconductor, low-temperature polysilicon TFTs (LTPS TFTs) including low-temperature polysilicon, or the like.A transistor is a three-electrode element having a gate, a source and a drain. The source is an electrode that supplies charge carriers to the transistor. In the transistor, the carriers start to flow from the source. The drain is an electrode through which the charge carriers leave the transistor. In a transistor, the carriers flow from a source to a drain. In the case of an n-channel transistor, the source voltage is lower than the drain voltage because the carriers are electrons, so that electrons can flow from a source to a drain. The n-channel transistor has a current flow direction from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), a source voltage is higher than a drain voltage because carriers are holes, so holes can flow from a source to a drain. In the p-channel transistor, since holes flow from the source to the drain, a current flows from the source to the drain. Note that a source and a drain of a transistor are not fixed. For example, a source and a drain may change according to an applied voltage. Therefore, the disclosure is not limited by a source and a drain of a transistor. In the following description, a source and a drain of a transistor are referred to as a first electrode and a second electrode.A gate signal oscillates between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than a threshold voltage of a transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.The transistor is turned on in response to the gate-on voltage and turned off in response to the gate-off voltage. In the case of the n-channel transistor, a gate-on voltage may be a gate high voltage and a gate-off voltage may be a gate low voltage. In the case of the p-channel transistor, a gate-on voltage may be a gate low voltage and a gate-off voltage may be a gate high voltage.FIG. 1 is a block diagram showing a display device according to an embodiment of the present disclosure, and FIG. 2 is a cross-sectional view showing a cross-sectional structure of the display panel shown in FIG. 1.Referring to FIGS. 1 and 2, a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel drive unit configured to write pixel data into pixels of the display panel 100, and a power supply unit 140 configured to generate power required to drive the pixels and the display panel drive unit.The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes a plurality of data lines DL, a plurality of gate lines GL crossing with the data lines DL, and pixels arranged in a matrix form.The pixel array AA includes a plurality of pixel lines L 1 to Ln. Each of the pixel lines L 1 to Ln includes a row of pixels arranged along a row direction X in the pixel array AA of the display panel 100. Pixels arranged in a pixel row share the gate lines GL. Sub-pixels arranged in a column direction Y along a data line direction share the same data line DL. A horizontal period 1H is a time obtained by dividing one frame period by the total number of pixel lines L 1 to Ln.Touch sensors may be disposed on the display panel 100. Touch input may be detected by separate touch sensors or through pixels. The touch sensors may be arranged as a cell-mounted type or an auxiliary type on the screen of the display panel or may be implemented as intra-cell touch sensors embedded in the pixel array AA.The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic thin film may be disposed on a back plate of the plastic OLED panel, and the pixel array AA may be formed on the organic thin film.The back plate of the plastic OLED may be a polyethylene terephthalate (PET) substrate. The organic thin film is formed on the back plate. The pixel array AA and a touch sensor array may be formed on the organic thin film. The back plate blocks the ingress of moisture, so that the pixel array AA is not exposed to moisture. The organic thin film may be a polyimide (PI) thin film substrate. A buffer multilayer film may be formed of an insulating material (not shown) on the organic thin film. Lines may be formed on the organic thin film to supply power or signals applied to the pixel array AA and the touch sensor array.To implement color, each of the pixels may be divided into a red sub-pixel (hereinafter referred to as "R sub-pixel"), a green sub-pixel (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as "B sub-pixel"). Each of the pixels may further include a white sub-pixel. Each of the sub-pixels 101 includes a pixel circuit. The pixel circuit is connected to the data line DL and the gate line GL.The cross-sectional structure of the display panel 100 may include a circuit layer CIR, a light emitting element layer EMIL, and an encapsulation layer ENC stacked on a substrate SUBS, as shown in FIG. 2.The circuit layer CIR may include a thin film transistor (TFT) array including a pixel circuit connected to wirings such as a data line, a gate line, a power line, and the like, and a gate driver 410 and 420. The circuit layer CIR includes a plurality of metal layers insulated with insulating layers interposed therebetween, and a semiconductor material layer. All transistors formed in the circuit layer CIR may be implemented as n-channel oxide TFTs.The light emitting element layer EMIL may include a light emitting element driven by the pixel circuit. The light emitting element may include a red sub-pixel light emitting element, a green sub-pixel light emitting element, and a blue sub-pixel light emitting element. The light emitting element layer EMIL may further include a light emitting element of a white sub-pixel. The light emitting element layer EMIL corresponding to each of the sub-pixels may have a structure in which a light emitting element and a color filter are stacked. The light emitting elements EL in the light emitting element layer EMIL may be covered by a plurality of protective layers including an organic film and an inorganic film.The encapsulation layer ENC covers the light emitting element layer EMIL to seal the circuit layer CIR and the light emitting element layer EMIL. The encapsulation layer ENC may also have a multi-insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarized the surface of the inorganic film. When the organic layer and the inorganic layer are stacked in multiple layers, the moving distance of moisture and oxygen becomes longer than that of a single layer, so that the penetration of moisture and oxygen interfering with the light emitting element layer EMIL can be effectively blocked.A touch sensor layer (not shown) may be formed on the encapsulation layer ENC, and a polarizing plate or a color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include metal wiring patterns and insulating films forming the capacitance of the touch sensors. The insulating films may isolate a region where the metal wiring patterns cross and may planarize the surface of the touch sensor layer. The polarizing plate may improve visibility and contrast ratio by converting polarization of external light reflected from metal in the touch sensor layer and the circuit layer. The polarizing plate may be a circular polarizing plate or a polarizing plate in which a linear polarizing plate and a phase retardation film are bonded to each other. A cover glass may be attached to the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer may replace the polarizing plate by absorbing a part of the wavelength of the light reflected from the circuit layer and the touch sensor layer, and increase the color purity of an image reproduced in the pixel array.The power supply unit 140 generates direct current (DC) required for driving the display panel driving unit and the pixel array of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply unit 140 may adjust a level of an input DC voltage applied from a host system (not shown) to generate constant voltages (or DC voltages) such as a gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, the pixel driving voltage ELVDD, the low potential power voltage EVSS, the initialization voltage VINIT, and the reference voltage VREF. The gamma reference voltage VGMA is supplied to a data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are supplied to a gate driver 120. The constant voltages such as the pixel driving voltage ELVDD, the low potential power voltage EVSS, the initialization voltage VINIT, and the reference voltage VREF are commonly supplied to the pixels.The display panel drive unit writes pixel data of an input image into the pixels of the display panel 100 under control of a timing controller (TCON) 130.The display panel driving unit includes the data drivers 110 and the gate drivers 120.A demultiplexer (DEMUX) may be disposed between the data driver 110 and the data lines DL. The demultiplexer is omitted from Fig. 1. The demultiplexer successively connects one channel of the data driver 110 to the plurality of data lines DL and distributes the data voltage output from one channel of the data driver 110 to the data lines DL in a time division manner, thereby reducing the number of channels of the data driver 110.The display panel driving circuit may further include a touch sensor driver for driving the touch sensors. The touch sensor driver is omitted in FIG. 1. In a mobile device, the timing controller 130, the power supply unit 140, the data driver 110, and the like may be integrated into a drive integrated circuit (drive IC).The data driver 110 generates a data voltage Vdata by converting pixel data of an input image received from the timing controller 130 with a gamma compensation voltage by a digital / analog converter (DAC) in each frame period. The gamma reference voltage VGMA is divided by a voltage dividing circuit for respective gray levels. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driver 110. The data voltage Vdata is output through the output buffer in each of the channels of the data driver 110.In the data driver 110, the output buffer included in one channel may be connected to adjacent data lines DL via the demultiplexer array 112 (not shown). The demultiplexer array 112 may be formed directly on the substrate of the display panel 100 or integrated into a driving IC together with the data driver 110.The gate driver 120 may be implemented as a gate-in-panel (GIP) circuit formed directly on a portion of a bezel BZ of the display panel 100 together with the TFT array of the pixel array AA. The gate driver 120 sequentially outputs gate signals to the gate lines GL under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signals to the gate lines GL by shifting the gate signals by a shift register.The timing controller 130 receives digital video data DA-TA of an input image from a host system (not shown) and a timing signal synchronized therewith. The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock CLK, a data enable signal DE, and the like. Since a vertical period and a horizontal period are known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has one cycle of one horizontal period (1H).The timing controller 130 multiplies an input image frequency by i and controls the operation timing of the display panel driving circuit with an image frequency of the input image frequency×i (i is a positive integer greater than 0) Hz. The input image frequency is 60 Hz in the NTSC scheme (National Television Standard Committee scheme) and 50 Hz in the PAL scheme (line phase change scheme).Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, MUX signals for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120.The voltage level of the gate-gate timing control signal output from the timing controller 130 may be converted into the gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL by a level shifter (not shown) and then supplied to the gate driver 120. That is, the level shifter converts a low voltage of the gate timing control signal into the gate-off voltages VGL and VEL, and converts a high voltage of the gate timing control signal into the gate-on voltages VGH and VEH. The gate timing signal includes the start pulse and the shift clock.The host system may include a motherboard of a television system, a set top box, a navigation system, a personal computer (PC), a home security system, a vehicle system, or a mobile device system. In this case, the data driver 110, the gate driver 120, the timing controller 130, and the like may be integrated into a driving IC (DIC) in mobile devices or portable devices.FIG. 3 is a diagram showing a pixel circuit according to a comparative example, FIG. 4 is a diagram showing a driving timing of the pixel circuit shown in FIG. 3, and FIG. 5 is a diagram for explaining a problem occurring when the pixel circuit of FIG. 4 is driven.Referring to FIGS. 3 to 4, the pixel circuit according to the comparative example includes a light emitting element EL, a driving element DT, a plurality of switching elements T 1, T 2, T 3, T 4, T 5, and T 6, and a capacitor Cst. The driving element DT and the switching elements T 1, T 2, T 3, T 4, T 5, and T 6 may be implemented as P-channel LTPS TFTs.The pixel circuit is driven in the order of an initialization step Ti, a scanning step Ts, and a light emission step Tem.TFTs of the pixel circuit in which all elements are implemented as P-channel LTPS TFTs have hysteresis characteristics. Due to the hysteresis characteristics, the value of the threshold voltage Vth decreases as the data voltage changes from the black gray level to the white gray level, resulting in a substantial decrease in luminance as compared to a change in the data voltage from the white gray level to the white gray level without changing the threshold voltage, resulting in deterioration of the FFR performance.As shown in FIG. 5, when the data voltage changes from the black gray level to the white gray level and from the first frame to the second frame of the white gray level, the amount of change in the threshold voltage at the end of the sampling step Ts and the amount of change in the threshold voltage at the beginning of the light emission step Tem are different, resulting in the occurrence of a peak in the first frame of the white gray level.To improve FFR performance, the luminance difference between the first and fourth white gray scale images needs to be improved. To this end, the driver DT needs to be initialized to a constant voltage before the sampling step in order to suppress the occurrence of hysteresis due to the difference between the data voltage of the previous image and the data voltage of the current image. That is, in the initialization step, a power-on bias (OBS) drive configured to bias the driving element DT to a constant Vgs voltage is required. However, in the pixel circuit of the comparative example, the source node of the driving element is floated in the initializing step, so that the voltage of the source node varies depending on the state of the previous data voltage. In the pixel circuit of the comparative example, since there is no separate voltage, control TFT, and timing controller for driving the OBS to apply a constant voltage to the source or drain of the driving element, it is difficult to improve the response performance in the first frame (FFR) without an additional arrangement for applying the OBS voltage to the pixel circuit.Therefore, in one embodiment, FFR performance is to be improved by implementing OBS driving using a pixel driving voltage or a data voltage without separate additional arrangement in the initialization step.Hereinafter, in the first embodiment of the present disclosure, an OBS driving using a data voltage will be described.FIG. 6 is a diagram illustrating the pixel circuit according to a first embodiment of the present disclosure, FIG. 7 is a diagram illustrating a driving time of the pixel circuit illustrated in FIG. 6, FIGS. 8A to 8C are diagrams for explaining an operation principle of the pixel circuit of FIG. 7, and FIG. 9 is a diagram for comparing and explaining simulation results of the pixel circuit according to the first embodiment.Referring to FIG. 6, a pixel circuit according to the first embodiment of the present disclosure includes a light emitting element EL, a driving element DT that supplies current to the light emitting element EL, a plurality of switching elements T 1, T 2, T 3, T 4, T 5, and T 6 for switching a current path connected to the driving element DT, and a capacitor Cst for storing a gate-source voltage of the driving element DT. The driving element DT and the switching elements T 1, T 2, T 3, T 4, T 5, and T 6 may be implemented as P-channel LTPS TFTs.The capacitor Cst is connected between the pixel driving voltage line 61 and the second node n 2. The first electrode of the capacitor Cst is connected to the pixel driving voltage line 61, and the second electrode is connected to the second node n 2. The pixel driving voltage ELVDD is supplied to the pixel circuit via the pixel driving voltage line 61. The first node n 1 is connected to a first electrode of a driving element DT, a second electrode of a third switching element T 3, and a first electrode of a second switching element T 2. The second node n 2 is connected to a second electrode of a capacitor Cst, a gate electrode of a driving element DT, a first electrode of a first switching element T 1, and a first electrode of a fifth switching element T 5.The first switching element T 1 is turned on according to the gate-on voltage VGL of a second scan signal SCAN 1(n) to connect the gate electrode and the second electrode of the driving element DT. The first switching element T 1 includes a gate electrode to which the second scan signal SCAN 1(n) is applied, a first electrode connected to the second node n 2, and a second electrode connected to the third node n 3. The third node n 3 is connected to the second electrode of the driving element DT, the second electrode of the first switching element T 1, and the first electrode of the fourth switching element T 4.The second switching element T 2 is turned on according to the gate-on voltage VGL of a third scan signal SCAN 2(n) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switching element T 2 includes a gate electrode to which the third scan signal SCAN 2(n) is applied, a first electrode connected to the first node n 1, and a second electrode connected to the data line 60. The first node n 1 is connected to the first electrode of the driving element DT, the first electrode of the second switching element T 2, and the second electrode of the third switching element T 3.The third switching element T 3 supplies the pixel driving voltage ELVDD to the first electrode of the driving element DT in response to the EM signal EM(n). The third switching element T 3 includes a gate electrode to which the EM signal EM(n) is applied, a first electrode connected to the pixel driving voltage line 61, and a second electrode connected to the first node n 1.The fourth switching element T 4 is turned on according to the gate-on voltage VGL of the EM signal EM(n) to connect the second electrode of the driving element DT to the anode of the light emitting element EL. The fourth switching element T 4 includes a gate electrode to which the EM signal EM(n) is applied, a first electrode connected to the third node n 3, and a second electrode connected to the fourth node n 4. The fourth node n 4 is connected to the anode electrode of the light emitting element EL, the second electrode of the fourth switching element T 4, and the second electrode of the sixth switching element T 6.The fifth switching element T 5 is turned on according to the gate-on voltage VGL of a first scan signal SCAN 1(n-1)], and connects the second node n 2 to the first initialization voltage line 63 to initialize the gates of the capacitor Cst and the driving element DT during the initialization step Ti. The fifth switching element T 5 includes a gate electrode to which the first scan signal SCAN 1(n- 1) is applied, a first electrode connected to the second node n 2, and a second electrode connected to the first initialization voltage line 63.The sixth switching element T 6 is turned on according to the gate-on voltage VGL of the third scan signal SCAN 2(n) to connect the second initialization voltage line 64 to the anode of the light emitting element EL during the initialization step Ti. During the initialization step Ti, the anode voltage of the light emitting element EL is discharged to the second initialization voltage Vini 2 through the sixth switching element T 6. In this case, the light emitting element EL does not emit light because the voltage between the anode and the cathode is lower than its threshold voltage. The sixth switching element T 6 includes a gate electrode to which the third scan signal SCAN 2(n) is applied, a first electrode to which the second initialization voltage line 64 is connected, and a second electrode to which the fourth node n 4 is connected.The driving element DT drives the light emitting element EL by adjusting a current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node n 2, a first electrode connected to the first node n 1, and a second electrode connected to the third node n 3.The light emitting element EL is connected between the fourth node n 4 and the low potential power line 62. The light emitting element EL may be implemented as an OLED. The OLED includes an organic compound layer formed between the anode and the cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and the cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emission layer (EML) to form excitons, and as a result, visible light is emitted from the emission layer (EML).The pixel circuit according to the first embodiment is driven in the order of an OBS step Tobs, an initialization step Ti, a scanning step Ts, and a light emission step Tem, as illustrated in FIG. 7.In the initialization step Ti of FIG. 8A, the first switching element T 1, the third switching element T 3, and the fourth switching element T 4 are turned off, and the fifth switching element T 5 is turned on by the first scan signal SCAN 1(n-1) so that the voltage of the second node n 2 is discharged to the first initialization voltage Vini 1, and the sixth switching element T 6 is turned on by the third scan signal SCAN 2(n) so that a voltage of the fourth node n 4 is discharged to the second initialization voltage Vini 2. Here, the first initialization voltage Vini 1 and the second initialization voltage Vini 2 are set as follows: Vini 1≤Vini 2.At the same time, in the OBS step Tobs, the second switching element T 2 is turned on by the third scan signal SCAN 2(n) to supply the data voltage Vdata(n-1) applied to the previous pixel row to the first electrode of the driving element DT. For example, data voltage Vdata(n-1) may be between gray levels 0 and 255 and may have a value between 2V and 5V.In this case, the initialization step Ti is executed at the same time as the OBS step Tobs. Accordingly, the voltage of the second node n 2 becomes Vg=Vini 1, the voltage of the first node n 1 becomes Vdata(n-1), and thus the source-gate voltage of the driving element becomes Vsg=Vini 1-Vdata(n-1).In the sampling step Ts of FIG. 8B, the third switching element T 3, the fourth switching element T 4, and the fifth switching element T 5 are turned off, the first switching element T 1 is turned on by the second sampling signal SCAN 1(n), and the second switching element T 2 is turned on by the third sampling signal SCAN 2(n), so that a data voltage is applied to the first node n 1 and the second node n 2.In this case, the sixth switching element T 6 is turned on together with the second switching element T 2 by the third scan signal SCAN 2(n), so that the second initialization voltage Vini 2 is applied to the fourth node n 4.Therefore, the voltage of the second node n 2 becomes Vg=Vdata-|Vth| and the voltage of the first node n 1 becomes Vs=Vdata, so that the source gate voltage of the driving element becomes Vsg=|Vth|.In the light emitting step Tem of FIG. 8C, the first switching element T 1, the second switching element T 2, the fifth switching element T 5, and the sixth switching element T 6 are turned off, and the third switching element T 3 and the fourth switching element T 4 are turned on by the EM signal EM(n), so that a current flows through the light emitting element EL through the driving element DT to emit light. The voltage of the second node n 2 becomes Vg=Vdata-|Vth| and the voltage of the first node n 1 becomes Vs=ELVDD, so that a source gate voltage of the driving element becomes Vsg=ELVDD-Vdata+|Vth|.Referring to FIG. 9, the pixel circuit according to the first embodiment performs an OBS step using a data voltage together in an initialization step, thereby improving a response performance in the first frame (FFR). That is, the pixel circuit according to the first embodiment is significantly improved when a data voltage is changed from the black gray level to the white gray level, compared with the pixel circuit according to the comparative example of FIG. 3.As described above, in the first embodiment of the present disclosure, FFR improvement may be possible by realizing OBS driving using the data voltage Vdata without separate voltage, control TFT, and timing control.In the following, in the second embodiment of the present disclosure, OBS driving using a pixel driving voltage will be described.FIG. 10 is a diagram illustrating the pixel circuit according to a second embodiment of the present disclosure, FIG. 11 is a diagram illustrating a driving timing of the pixel circuit illustrated in FIG. 10, FIGS. 12A to 12C are diagrams for explaining an operation principle of the pixel circuit of FIG. 11, and FIG. 13 is a diagram for comparing and explaining simulation results of a pixel circuit according to a second embodiment.Referring to FIG. 10, the pixel circuit according to the first embodiment of the present disclosure includes a light emitting element EL, a driving element DT that supplies current to the light emitting element EL, a plurality of switching elements T 1, T 2, T 3, T 4, T 5, and T 6 configured to switch a current path connected to the driving element DT, and a capacitor Cst configured to store a gate-source voltage of the driving element DT. The driving element DT and the switching elements T 1, T 2, T 3, T 4, T 5, and T 6 may be implemented as P-channel LTPS TFTs.The capacitor Cst is connected between the pixel driving voltage line 61 and the second node n 2. The first electrode of the capacitor Cst is connected to the pixel driving voltage line 61 and the second electrode is connected to the second node n 2. The second node n 2 is connected to the second electrode of the capacitor Cst, the gate electrode of the driving element DT, the first electrode of the first switching element T 1, and the first electrode of the fifth switching element T 5.The first switching element T 1 is turned on according to the gate-on voltage VGL of the second scan signal SCAN(n) to connect the gate electrode and the second electrode of the driving element DT. The first switching element T 1 includes a gate electrode to which the second scan signal SCAN(n) is applied, a first electrode connected to the second node n 2, and a second electrode connected to the third node n 3. The third node n 3 is connected to the second electrode of the driving element DT, the second electrode of the first switching element T 1, and the first electrode of the fourth switching element T 4.The second switching element T 2 is turned on according to the gate-on voltage VGL of the second scan signal SCAN(n) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switching element T 2 includes a gate electrode to which the second scan signal SCAN(n) is applied, a first electrode connected to the first node n 1, and a second electrode connected to the data line 60. The first node n 1 is connected to the first electrode of the driving element DT, the first electrode of the second switching element T 2, and the second electrode of the third switching element T 3.The third switching element T 3 supplies the pixel driving voltage ELVDD to the first node n 1 in response to the first EM signal EM(n+2). The third switching element T 3 includes a gate electrode to which the first EM signal EM(n+2) is applied, a first electrode connected to the pixel driving voltage line 61, and a second electrode connected to the first node n 1.The fourth switching element T 4 is turned on according to the gate turn-on voltage VGL of the second EM signal EM(n) to connect the second electrode of the driving element DT to the anode of the light emitting element EL. The fourth switching element T 4 includes a gate electrode to which the second EM signal EM(n) is applied, a first electrode connected to the third node n 3, and a second electrode connected to the fourth node n 4. The fourth node n 4 is connected to the anode electrode of the light emitting element EL, the second electrode of the fourth switching element T 4, and the second electrode of the sixth switching element T 6.The fifth switching element T 5 is turned on according to the gate turn-on voltage VGL of the first scan signal SCAN(n-2) to connect the second node n 2 to the first initialization voltage line 63, thereby initializing the gates of the capacitor Cst and the driving element DT during the initialization step Ti. The fifth switching element T 5 includes a gate electrode to which the first scan signal SCAN(n-2) is applied, a first electrode to which the second node n 2 is connected, and a second electrode to which the first initialization voltage line 63 is connected.The sixth switching element T 6 is turned on according to the gate turn-on voltage VGL of the first scan signal SCAN(n-2) to connect the second initialization voltage line 64 to the anode of the light emitting element EL during the initialization step Ti. During the initialization step Ti, the anode voltage of the light emitting element EL is discharged to the second initialization voltage Vini 2 through the sixth switching element T 6. In this case, the light emitting element EL does not emit light because the voltage between the anode and the cathode is lower than its threshold voltage. The sixth switching element T 6 includes a gate electrode to which the first scan signal SCAN(n-2) is applied, a first electrode connected to the second initialization voltage line 64, and a second electrode connected to the fourth node n 4.The driving element DT drives the light emitting element EL by adjusting a current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node n 2, a first electrode connected to the first node n 1, and a second electrode connected to the third node n 3.The light emitting element EL is connected between the fourth node n 4 and the low potential power line 62. The light emitting element EL may be implemented as an OLED. The OLED comprises a layer of organic compounds formed between anode and cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and the cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emission layer (EML) to form excitons, and as a result, visible light is emitted from the emission layer (EML).The pixel circuit according to the second embodiment is driven in the order of a first OBS step Tobs 1, a second OBS step Tobs 2, an initialization step Ti, a scanning step Ts, and a light emission step Tem, as illustrated in FIG. 11.In the first OBS step Tobs 1 before the initialization step Ti, the third switching element T 3 is turned on by the first EM signal [EM(n+2)] of the (n+2)-th pixel row to supply the pixel driving voltage ELVDD to the first electrode of the driving element DT.In the initialization step Ti of FIG. 12A, the first switching element T 1, the second switching element T 2, and the fourth switching element T 4 are turned off, and the fifth switching element T 5 is turned on, so that the voltage of the second node n 2 is discharged to the first initialization voltage Vini 1, and the sixth switching element T 6 is turned on, so that the voltage of the fourth node n 4 is discharged to the second initialization voltage Vini 2.At the same time, in the second OBS step Tobs 2, the third switching element T 3 is turned on by the first EM signal EM(n+2) to supply the pixel driving voltage ELVDD to the first electrode of the driving element DT. In this case, the fourth switching element T 4 is turned off by the second EM signal EM(n), so that the light emitting element EL is not caused to emit by the turn-on of the driving element DT.In this case, the initialization step Ti is executed at the same time as the second OBS step Tobs2. Therefore, the voltage of the second node n 2 becomes Vg=Vini 1, the voltage of the first node n 1 becomes Vs=ELVDD, and the source gate voltage of the driving element becomes Vsg=ELVDD-Vini 1.In the sampling step Ts of FIG. 12B, the third switching element T 3, the fourth switching element T 4, the fifth switching element T 5, and the sixth switching element T 6 are turned off, and the first switching element T 1 and the second switching element T 2 are turned on by the second sampling signal SCAN(n), so that a data voltage is applied to the first node n 1. As a result, the voltage of the second node n 2 becomes Vg=Vdata-|Vs|, the voltage of the first node n 1 becomes Vs=Vdata, and the source gate voltage of the driving element becomes Vsg=|Vs|.In the light emitting step Tem of FIG. 12C, the first switching element T 1, the second switching element T 2, the fifth switching element T 5, and the sixth switching element T 6 are turned off, and the fourth switching element T 4 is turned on by the second EM signal EM(n), so that a current flows through the light emitting element EL through the driving element DT to emit light. Accordingly, the voltage of the second node n 2 becomes Vg=Vdata-|Vth|, the voltage of the first node n 1 becomes Vs=ELVDD, and the source gate voltage of the driving element becomes Vsg=ELVDD-Vdata+|Vth|.Referring to FIG. 13, a pixel circuit according to a second embodiment performs an OBS step using a pixel driving voltage together in an initialization step, thereby improving a response performance in the first frame (FFR). That is, a pixel circuit according to a second embodiment is significantly improved when a data voltage is changed from the black gray level to the white gray level, compared with a pixel circuit according to a comparative example of FIG. 3.Therefore, in the second embodiment of the present disclosure, improvement of the FFR may be possible by realizing OBS driving using the pixel driving voltage ELVDD without separate voltage, control TFT, and timing control.Moreover, an improvement in FFR is possible when OBS driving using the pixel driving voltage (ELVDD) is applied to the pixel circuit of the comparative example, but when black data is applied, black floating occurs in which full black cannot be displayed. However, in the pixel circuit of the embodiment, since the third switching element T 3 and the fourth switching element T 4 are separately driven, that is, not by an EM signal but by different EM signals, improvement of black floating may be possible.FIG. 14 is a diagram showing the pixel circuit according to a third embodiment of the present disclosure, FIG. 15 is a diagram showing a driving timing of the pixel circuit shown in FIG. 14, and FIGS. 16A to 16C are diagrams showing an operation principle of the pixel circuit shown in FIG. 15.Referring to FIG. 14, the pixel circuit according to the third embodiment of the present disclosure includes a light emitting element EL, a driving element DT that supplies current to the light emitting element EL, a plurality of switching elements T 1, T 2, T 3, T 4, T 5, T 6, and T 7 for switching a current path connected to the driving element DT, and a capacitor Cst for storing a gate-source voltage of the driving element DT. The driving element DT and the switching elements T 1, T 2, T 3, T 4, T 5, T 6, and T 7 may be implemented as P-channel LTPS TFTs.The capacitor Cst is connected between the second node n 2 and the fifth node n 5. The first electrode of the capacitor Cst is connected to the fifth node n 5, and the second electrode is connected to the second node n 2. The second node n 2 is connected to the gate electrode of the driving element DT, the second electrode of the capacitor Cst, and the first electrode of the fifth switching element T 5. The fifth node n 5 is connected to the second electrode of the seventh switching element T 7 and the first electrode of the capacitor Cst.The first switching element T 1 is turned on according to the gate turn-on voltage VGL of the second scan signal SCAN(n) to connect the gate electrode and the second electrode of the driving element DT. The first switching element T 1 includes a gate electrode to which the second scan signal SCAN(n) is applied, a first electrode connected to the second node n 2, and a second electrode connected to the third node n 3. The third node n 3 is connected to the second electrode of the driving element DT, the second electrode of the first switching element T 1, and the first electrode of the fourth switching element T 4.The second switching element T 2 is turned on according to the gate turn-on voltage VGL of the second scan signal SCAN(n) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switching element T 2 includes a gate electrode to which the second scan signal SCAN(n) is applied, a first electrode connected to the first node n 1, and a second electrode connected to the data line 60. The first node n 1 is connected to the first electrode of the driving element DT, the first electrode of the second switching element T 2, and the second electrode of the third switching element T 3.The third switching element T 3 supplies the pixel driving voltage ELVDD to the first node n 1 in response to the first EM signal EM(n+2). The third switching element T 3 includes a gate electrode to which the first EM signal EM(n+2) is applied, a first electrode connected to the pixel driving voltage line 61, and a second electrode connected to the first node n 1.The fourth switching element T 4 is turned on according to the gate-on voltage VGL of the second EM signal EM(n) to connect the second electrode of the driving element DT to the anode of the light emitting element EL. The fourth switching element T 4 includes a gate electrode to which the second EM signal EM(n) is applied, a first electrode connected to the third node n 3, and a second electrode connected to the fourth node n 4. The fourth node n 4 is connected to the anode electrode of the light emitting element EL, the second electrode of the fourth switching element T 4, and the second electrode of the sixth switching element T 6.The fifth switching element T 5 is turned on according to the gate-on voltage VGL of the first scan signal SCAN(n-2) to connect the second node n 2 to the initialization voltage line 65, thereby initializing the capacitor Cst and the gate of the driving element DT during the initialization step Ti. The fifth switching element T 5 includes a gate electrode to which the first scan signal SCAN(n-2) is applied, a first electrode to which the second node n 2 is connected, and a second electrode to which the initialization voltage line 65 is connected.The sixth switching element T 6 is turned on according to the gate-on voltage VGL of the second scan signal SCAN(n) to connect the initialization voltage line 65 to the anode of the light emitting element EL during the initialization step Ti. During the initialization step Ti, the anode voltage of the light emitting element EL is discharged to the initialization voltage Vini via the sixth switching element T 6. In this case, the light emitting element EL does not emit light because the voltage between the anode and the cathode is lower than its threshold voltage. The sixth switching element T 6 includes a gate electrode to which the second scan signal SCAN(n) is applied, a first electrode connected to the initialization voltage line 65, and a second electrode connected to the fourth node n 4.The seventh switching element T 7 supplies the pixel driving voltage ELVDD to the capacitor Cst in response to the second EM signal EM(n). The seventh switching element T 7 includes a gate electrode to which the second EM signal EM(n) is applied, a first electrode connected to the pixel driving voltage line 61, and a second electrode connected to the fifth node n 5.A reference voltage line 66 to which the reference voltage Vref is applied and a control switching element Tsw for applying the reference voltage Vref to the fifth node n 5 via the reference voltage line 66 may be further connected to the fifth node n 5 of the pixel circuit.The control switching element Tsw may be disposed inside the display panel 100 and may be disposed outside the active area. The control switching element Tsw may be arranged for each pixel line to be controlled per pixel line, or may be arranged so that the display panel 100 is divided into a plurality of pixel blocks to be controlled per pixel block.The control switching element Tsw may receive a control signal from a timing controller. For example, the timing controller generates and outputs a control signal having a first voltage level, and the level shifter receives a control signal having a first voltage level to generate a control signal having a second voltage level higher than the first voltage level, and applies it to the control switching element Tsw.The reference voltage Vref applied to the pixel circuit is used to improve the influence of the voltage drop IR of the pixel driving voltage ELVDD in the pixel circuit. That is, the current flowing through the light emitting element is not IOLED=K(ELVDD-Vdata)2but IOLED=K(Vref-Vdata)2. Accordingly, in the embodiment, the reference voltage Vref is applied to the fifth node n 5 to which the capacitor is connected in the initialization and sampling step, instead of the pixel driving voltage ELVDD.The pixel circuit according to the third embodiment is driven in the order of a first OBS step Tobs, a second OBS step Tobs, an initialization step Ti, a scanning step Ts, and a light emission step Tem, as illustrated in FIG. 15.In the first OBS step Tobs 1 before the initialization step Ti, the first switching element T 1, the second switching element T 2, the fourth switching element T 4, the fifth switching element T 5, the sixth switching element T 6, and the seventh switching element T 7 are turned off, and the third switching element T 3 is turned on by the first EM signal EM(n+2) to supply the pixel driving voltage ELVDD to the first electrode of the driving element DT.In the initialization step Ti of FIG. 16A, the first switching element T 1, the second switching element T 2, the fourth switching element T 4, the sixth switching element T 6, and the seventh switching element T 7 are turned off, and the fifth switching element T 5 is turned on by the first scan signal SCAN(n-2), so that the voltage of the second node n 2 is discharged to the initialization voltage Vini.At the same time, in the second OBS step Tobs 2, the third switching element T 3 is turned on by the first EM signal [EM(n+2)] to supply the pixel driving voltage ELVDD to the first electrode of the driving element DT.In this case, the initialization step Ti is executed at the same time as the second OBS step Tobs2. Therefore, the voltage of the second node n 2 becomes Vg=Vini, the voltage of the first node n 1 becomes Vs=ELVDD, and thus a source gate voltage of the driving element becomes Vsg=ELVDD-Vini.In addition, the control switching element Tsw is turned on, so that the reference voltage Vref is applied to the fifth node n 5.In the sampling step Ts of FIG. 16B, the third switching element T 3, the fourth switching element T 4, the fifth switching element T 5, and the seventh switching element T 7 are turned off, and the first switching element T 1 and the second switching element T 2 are turned on by the second sampling signal SCAN(n), so that a data voltage Vdata is applied to the first node n 1 and the second node n 2, and the sixth switching element T 6 is turned on to apply an initialization voltage Vini to the fourth node n 4. Accordingly, the voltage of the second node n 2 becomes Vg=Vdata-|Vth| and the voltage of the first node n 1 becomes Vs=Vdata, so that a source gate voltage of the driving element becomes Vsg=|Vth|.In addition, the control switching element Tsw is turned on, so that the reference voltage Vref is supplied to the fifth node n 5.In the light emitting step Tem of FIG. 16C, the first switching element T 1, the second switching element T 2, the fifth switching element T 5, and the sixth switching element T 6 are turned off, the fourth switching element T 4 is turned on by the second EM signal EM(n), and the third switching element T 3 is turned on by the first EM signal EM(n+2), so that a current flows through the light emitting element EL through the driving element DT to emit light. Accordingly, the voltage of the second node n 2 becomes Vg=Vdata-|Vth|+(ELVDD-Vref), and the voltage of the first node n 1 becomes Vs=ELVDD, so that the source gate voltage of the driving element becomes Vsg=Vref-Vdata+|Vth|.At the same time, the control switching element Tsw is turned off to cut off the supply of the reference voltage Vref.Therefore, in the third embodiment of the present disclosure, improvement of the FFR may be possible by realizing OBS driving using the pixel driving voltage ELVDD without separate voltage, control TFT, and timing control.Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and do not limit the present disclosure.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedKR 2023-0172215

[0001]

Claims

A pixel circuit comprising: a driving element (DT) having a first electrode connected to a first node (n1), a gate electrode connected to a second node (n2), and a second electrode connected to a third node (n3); a first switching element (T1) configured to connect the second node (n2) and the third node (n3) to the first node (n1) in response to a first gate signal (Scan1(n)); a second switching element (T2) configured to apply a data voltage to the first node (n1) in response to a second gate signal (Scan2(n)); a third switching element (T3) configured to connect a pixel driving voltage line (61) to the first node (n1) in response to a third gate signal (EM(n)); a fourth switching element (T4) configured to connect the third node (n3) to a fourth node (n4) in response to the third gate signal (EM(n)); a fifth switching element (T5) configured to apply a first initialization voltage (Vini1) to the second node (n2) in response to a fourth gate signal (Scan1(n-1)); a sixth switching element (T6) configured to apply a second initialization voltage (Vini2) to the fourth node (n4) in response to the second gate signal (Scan2(n)); a capacitor (Cst) connected between the pixel driving voltage line (61) and the second node (n2); and a light emitting element (EL) connected to the fourth node (n4) and a low potential power voltage line (62).The pixel circuit according to claim 1, wherein the pixel circuit is sequentially driven in an initialization step, an OBS step, a scanning step, and a light emission step.The pixel circuit according to claim 2, wherein in the initializing step, the fifth switching element (T5) is turned on so that the voltage of the second node (n2) is discharged to the first initializing voltage (Vini1), and the sixth switching element (T6) is turned on so that the voltage of the fourth node (n4) is discharged to the second initializing voltage (Vini2), and simultaneously in the OBS step, the second switching element (T2) is turned on so that the data voltage of the previous frame is applied to the first node (n1).The pixel circuit according to claim 2 or 3, wherein in the sampling step, both the first switching element (T1) and the second switching element (T2) are turned on, so that the data voltage of the current frame is applied to the first node (n1).A pixel circuit comprising: a driving element (DT) having a first electrode connected to a first node (n1), a gate electrode connected to a second node (n2), and a second electrode connected to a third node (n3); a first switching element (T1) configured to connect the second node (n2) and the third node (n3) to the first node (n1) in response to a first gate signal (Scan(n)); a second switching element (T2) configured to apply a data voltage to the first node (n1) in response to the first gate signal (Scan(n)); a third switching element (T3) configured to connect a pixel driving voltage line (61) to the first node (n1) in response to a second gate signal (EM(n+2)); a fourth switching element (T4) configured to connect the third node (n3) to a fourth node (n4) in response to a third gate signal (EM(n)); a fifth switching element (T5) configured to apply a first initialization voltage (Vini1) to the second node (n2) in response to a fourth gate signal (Scan(n-2)); a capacitor (Cst) connected between the pixel driving voltage line (61) and the second node (n2); and a light emitting element (EL) connected to the fourth node (n4) and a low potential power voltage line (62).The pixel circuit of claim 5, further comprising a sixth switching element (T6) configured to apply a second initialization voltage (Vini2) to the fourth node (n4) in response to the fourth gate signal (Scan(n-2)).The pixel circuit according to claim 5 or 6, wherein the pixel circuit is driven in sequence in a first OBS step, an initialization step, a second OBS step, a sampling step, and a light emission step, wherein preferably in the initialization step, the fifth switching element (T5) is turned on so that the voltage of the second node (n2) is discharged to the first initialization voltage (Vi ni1), and the sixth switching element (T6) is turned on so that the voltage of the fourth node (n4) is discharged to the second initialization voltage (Vini2), and simultaneously in the second OBS step, the third switching element (T3) is turned on to apply a pixel driving voltage (ELVDD) from the pixel driving voltage line (61) to the first node (n1).The pixel circuit of claim 5, further comprising: a sixth switching element (T6) that applies an initialization voltage (Vini) to the fourth node (n4) in response to the first gate signal (Scan(n)); and a seventh switching element (T7) that is connected between the pixel driving voltage line (61) and the capacitor (Cst) and is configured to connect the pixel driving voltage line (61) to a fifth node (n5) in response to the third gate signal (EM(n)).The pixel circuit according to claim 8, wherein: the pixel circuit is driven in sequence in a first OBS step, an initialization step, a second OBS step, a sampling step, and a light emission step, in the initialization step, the fifth switching element (T5) is turned on so that the voltage of the second node (n2) is discharged to the initialization voltage (Vini), and simultaneously in the second OBS step, the third switching element (T3) is turned on to apply the pixel driving voltage (ELVDD) from the pixel driving voltage line (61) to the first node (n1).The pixel circuit according to claim 7 or 9, wherein in the first OBS step, the third switching element (T3) is turned on to apply the pixel driving voltage (ELVDD) from the pixel driving voltage line (61) to the first node (n1).A display device comprising: a pixel array in which a plurality of data lines (102, DL), a plurality of gate lines (103, GL), and a plurality of pixel circuits (101) according to any one of the preceding claims are arranged; a data driver (110) that outputs a data voltage to the plurality of data lines (102, DL); and a gate driver (120) that outputs gate signals to the plurality of gate lines (103, GL), wherein each of the pixel circuits (101) includes a driving element (DT).The display device according to claim 11, further comprising a control switching element (Tsw) arranged for at least one pixel line and configured to supply a reference voltage (Vref) to the pixel circuit in response to a control signal from a timing controller (130).

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