Tactile degree variant receiver and method for receiving

Abstract

Receivers, control systems, and methods for receiving a signal. The method includes receiving a differential communication signal comprising a first component and a second component. The method also includes generating a comparison signal with a comparator by comparing the first and second components. Furthermore, the method includes generating an unbalanced communication signal by applying a debounce time to the comparison signal. Finally, the method includes inverting a voltage offset of the comparator based on the unbalanced communication signal.

Description

BACKGROUND

[0001] In modular lighting systems, a main control device can be connected to a number of local control devices via a daisy-chain arrangement. Each local control device can control a number of light branches. Time-based coding can be used in the communication protocol to control the intensity of the light branches. For example, Manchester (differential) coding is used in automotive communication protocols due to its insensitivity to noise and its ability to function in harsh environments. Each local control device includes a comparator to convert a received differential signal into an unbalanced signal that can be decoded. The comparator has a voltage offset which, combined with the transition time of the input signal, introduces duty cycle distortion into the unbalanced signal. This duty cycle distortion can lead to decoding errors. SUMMARY

[0002] Due to various requirements for automotive systems, reducing (or eliminating) duty cycle distortion in automotive communication signals is challenging. For example, the transition time of an automotive communication signal can be shortened to reduce duty cycle distortion. However, such shorter transition times can lead to a higher emission spectrum, which violates the emission requirements for automotive systems. As another example, the amplitude of an automotive communication signal can be increased to reduce duty cycle distortion. However, such an increased amplitude is not compatible with the minimum supply requirements for automotive systems. The present disclosure provides receivers, control systems, and methods for receiving a signal that, among other things, avoid duty cycle distortion by inverting a voltage offset of a comparator based on a debounced version of the comparator output.Duty cycle distortion occurs because the comparator triggers at different transition values ​​for rising and falling input transitions. Inverting the comparator's voltage offset for falling input transitions causes the comparator to trigger at the same transition value for both rising and falling input transitions, thus avoiding duty cycle distortion. The debounced version of the comparator output is used to determine when to invert the voltage offset, as this version provides an accurate indication of whether the next input transition will be falling or rising.

[0003] The present disclosure provides a method for receiving a signal. The method includes receiving a differential communication signal comprising a first component and a second component. The method further includes generating a comparison signal with a comparator by comparing the first and second components. The method also includes generating an asymmetric communication signal by applying a debounce time to the comparison signal. Finally, the method includes inverting a voltage offset of the comparator based on the asymmetric communication signal.

[0004] The present disclosure also provides a receiver which, in one implementation, includes a first input terminal, a second input terminal, a comparator, a debouncer, and an offset inverter. The first input terminal is used to receive the first component of a differential communication signal. The second input terminal is used to receive the second component of the differential communication signal. The comparator is configured to generate a comparison signal by comparing the first and second components of the differential communication signal. The debouncer is configured to generate an unbalanced communication signal by applying a debounce time to the comparison signal. The offset inverter is configured to couple the first input terminal to either the first or second of two inputs of the comparator, based on the unbalanced communication signal.The offset inverter is also configured to couple the second input connection to either the first or the second of the comparator's two inputs, based on the unbalanced communication signal. Furthermore, the offset inverter is configured to invert the comparison signal based on the unbalanced communication signal.

[0005] The present disclosure further provides a system which, in one implementation, includes a main controller, a communication bus and a local controller.

[0006] The main controller is configured to send a differential communication signal. The local controller is communicatively connected to the main controller via the communication bus. The local controller is configured to receive the differential communication signal. The local controller is also configured to generate a comparison signal using a comparator by comparing a first component of the differential communication signal with a second component. The local controller is further configured to generate an unbalanced communication signal by applying a debounce time to the comparison signal. Finally, the local controller is configured to invert a voltage offset of the comparator based on the unbalanced communication signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a detailed description of example implementations, please refer to the accompanying drawings, which show: Fig. 1 is a block diagram of an example of a lighting system according to some implementations; Fig. 2 is a diagram of an example of a lighting system installed in a vehicle according to some implementations; Fig. 3 is a block diagram of an example of a local controller according to some implementations; Fig. 4 is a timing diagram of an example of a Manchester-coded signal and a clock signal according to some implementations; Fig. 5A is a graphical representation of an example of an ideal output of a comparator according to some implementations; Fig. 5B is a graphical representation of an example of an actual output of a comparator according to some implementations; Fig. 6 is a partial block diagram and a partial scheme of an example of a receiver according to some implementations; Fig. 7 is a diagram of an example of a switching circuit according to some implementations; Fig. 8A is a graphical representation of examples of a comparison signal generated by a comparator with a positive voltage offset and a corresponding unbalanced communication signal generated by a debouncer according to some implementations; Fig. 8B is a graphical representation of examples of a comparison signal generated by a comparator with a negative voltage offset and a corresponding unbalanced communication signal generated by a debouncer according to some implementations; Fig. 9 is a flowchart of an example of a procedure for receiving a signal according to some implementations; and Fig. Figure 10 is a graph of an example of simulation results of weddings for outputs of comparators with different voltage offsets according to some implementations. Definitions

[0008] Various terms are used to refer to specific system components. Different companies may refer to a component by different names—this document does not intend to differentiate between components that differ in name but not in function. In the following discussion and in the claims, the terms "including" and "comprehensive" are used in an open sense and should therefore be interpreted as meaning "including, but not limited to...". Similarly, the term "couple" or "couples" is intended to mean either an indirect or a direct connection. Thus, if a first device is coupled to a second device, this connection may be made by a direct connection or by an indirect connection via other devices and connections.

[0009] “A / an” and “the / a / an,” as used herein, refer to both the singular and the plural unless the context clearly indicates otherwise. For example, “a processor” programmed to perform various functions refers to a processor programmed to perform all and every function, or to more than one processor programmed together to perform each of the various functions. For the avoidance of doubt, an initial reference to “[something being referred to]” and a subsequent reference, based on the preceding one, to “[that which is being referred to]” does not preclude the possibility that the “something being referred to” referred to may be plural.

[0010] Terms defining elevation, such as "above / over," "below / under," "upper," and "lower," are intended to be positional terms in relation to the direction of light falling on a pixel array and / or image pixel. Incoming light is to be considered as interacting with or passing through objects and / or structures that are "above / over" and "upper" before interacting with or passing through objects and / or structures that are "below / under" or "below." Therefore, these positional terms may not have a relationship to the direction of gravity.

[0011] “Approximately” in relation to a specified parameter means the specified parameter plus or minus ten percent (+ / - 10%) of the specified parameter.

[0012] "Activating" means establishing or maintaining a first predetermined state of a Boolean signal. Boolean signals can be activated high or with a higher voltage, and Boolean signals can be activated low or with a lower voltage, at the discretion of the circuit designer. Similarly, "disabling" means establishing or maintaining a second predetermined Boolean state, opposite to the activated state.

[0013] With regard to electrical devices, whether individual or as part of an integrated circuit, the terms "input" and "output" refer to electrical connections to the electrical devices and are not to be understood as verbs requiring an action. For example, a differential amplifier such as an operational amplifier may have a first differential input and a second differential input, and these "inputs" define electrical connections to the operational amplifier and are not to be understood as requiring the input of signals into the operational amplifier.

[0014] “Control” means, alone or in combination, individual circuit components, an application-specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computer (RISC) with control software, a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), a field-programmable gate array (FPGA) or a programmable system-on-a-chip (PSOC) configured to read inputs and, in response to the inputs, drive outputs. DETAILED DESCRIPTION

[0015] The following explanation is directed towards various implementations of the invention. Although one or more of these implementations may be preferred, the disclosed implementations should not be interpreted or otherwise used in such a way as to limit the scope of protection of the present disclosure, including the claims. Furthermore, the person skilled in the art will understand that the following description has broad application and that the discussion of any one implementation is merely to be understood as an example of that implementation and is not intended to imply that the scope of protection of the present disclosure, including the claims, is limited to that implementation.

[0016] Several examples address receivers, control systems, and methods for receiving a signal. More specifically, at least some examples relate to receiving communication signals with time-based coding. Even more specifically, several examples aim to avoid duty cycle distortion by inverting a comparator's voltage offset based on a debounced version of the comparator output. The patent specification now considers an example system to provide the reader with an overview.

[0017] Fig. Figure 1 is a block diagram of an example of a lighting system 100. The one in Fig. The illustrated lighting system 100 includes a lighting unit 102, a main controller 104, and a communication bus 106. The lighting system 100 may include fewer components, additional components, or other components in different configurations than the one shown. Fig. 1. Illustrated lighting system 100. In some implementations, lighting system 100 includes multiple instances of the in Fig. The lighting unit 102 illustrated in Figure 1 is included. For example, the lighting system 100 can include a variety of lighting units coupled to the communication bus 106. In some implementations, the lighting system 100 includes multiple instances of the lighting unit shown in Figure 1. Fig. Figure 1 illustrates the communication bus 106. For example, the lighting system 100 can include a variety of communication buses that couple a variety of lighting units in a daisy-chain arrangement. The in Fig. The illustrated lighting unit 102 includes a plurality of light branches 108. Each of the plurality of light branches 108 includes a plurality of light sources 110 coupled in a series configuration. The plurality of light sources 110 can include light-emitting diodes (LEDs) or other types of light sources. The in Fig. The illustrated lighting unit 102 also includes a local controller 112. The local controller 112 is coupled to the plurality of light branches 108 to control the plurality of light sources 110. The local controller 112 is communicatively coupled to the main controller 104 via the communication bus 106. In some implementations, the communication bus 106 is a Controller Area Network (CAN) bus. The main controller 104 is configured to send a communication signal to the local controller 112 via the communication bus 106. The local controller 112 is configured to control the plurality of light sources 110 based on time and intensity commands included in the communication signal sent by the main controller 104.

[0018] Fig. Figure 2 shows another example of the lighting system 100. This is in Fig. 2. Illustrated lighting system 100 includes an automobile or vehicle 114. The vehicle 114 is shown for illustrative purposes as a passenger car, but the lighting system 100 can be other types of vehicles, including commercial vehicles, road vehicles, and off-road vehicles. Commercial vehicles can include buses and semi-trucks. Off-road vehicles can include tractors and harvesters. In the example of Fig. 2. The vehicle 114 includes a forward-facing lighting unit 102 arranged to illuminate the area in front of the vehicle 114. The vehicle 114 also includes a rear-facing lighting unit 102 arranged to illuminate the area behind the vehicle 114. In situations where the lighting system 100 is a vehicle, the main control 104 may be a control of the vehicle 114. The discussion now turns in more detail to the local control 112. The vehicle 114 may include additional lighting units (not illustrated). For example, the vehicle 114 may include one or more side-facing lighting units, one or more interior lighting units, or a combination thereof.

[0019] Fig. Figure 3 shows an example of local control 112. The in Fig. Figure 3 illustrates a local controller 112 that includes a driver 116, a decoder 118, and a receiver 120. The local controller 112 may include fewer components, additional components, or other components in different configurations than those shown. Fig. Figure 3 illustrates local control 112. The driver 116 is coupled to a plurality of light sources 110 via the plurality of light branches 108. The driver 116 is configured to control the plurality of light sources 110. For example, the driver 116 may include pulse-width modulators or other circuit arrangements for generating signals to operate the plurality of light sources 110. The driver 116 controls the plurality of light sources 110 based on time and intensity commands included in a communication signal sent by the main controller 104.

[0020] Decoder 118 is configured to decode the communication signal sent by the main controller 104. In some implementations, the communication signal is time-coded. For example, the communication signal may be Manchester-coded (also known as phase-coded). Manchester code is a line code in which the encoding of each data bit is either "low, then high" or "high, then low" for the same period of time. The decoding principle is based on detecting transitions and the temporal sequence between successive transitions, including deciding whether a midpoint is detected. For example, in the timing diagram of Fig. 4. The transition of the communication signal COM on the far left from low to high, which indicates a value of logic zero. Furthermore, in Fig. 4. The third transition of the COM communication signal from high to low, representing a logic one. Each COM communication signal transition occurs within a predetermined number of clock cycles of a clock signal Tclk. For example, each COM communication signal transition might occur within thirty clock cycles of the clock signal Tclk. The predetermined number of clock cycles defines a Tbit. For example, a Tbit might be one microsecond. Decoder 118 tracks the number of clock cycles of the clock signal Tclk between COM communication signal transitions using one or more counters. Furthermore, Decoder 118 determines whether a COM communication signal transition is from high to low or from low to high, based on whether the number of clock cycles since the previous COM communication signal transition is approximately equal to half a Tbit or one Tbit.

[0021] To briefly Fig. Returning to point 3, the communication signal sent by the main controller 104 is a differential communication signal that includes a first component C1 and a second component C2. As in Fig. As illustrated in Figure 3, receiver 120 receives the first component C1 and the second component C2 of the differential communication signal. Receiver 120 includes a comparator 122, which receives the first component C1 and the second component C2 of the differential communication signal at a first input 124 and a second input 126 of the comparator 122. The comparator 122 generates a comparison signal CMP by comparing the first component C1 and the second component C2 of the differential communication signal.

[0022] Fig. Figure 5A is a graphical representation of an example of an ideal output generated by the comparator 122. The in Fig. The illustrated input 5A is the voltage difference between the first component C1 and the second component C2. As shown in Fig. As illustrated in Figure 5A, the peak time of the ideal output of comparator 122 is approximately equal to the low time of the ideal output of comparator 122. In other words, the peak time and the low time each have a duty cycle of 50%. The in Fig. The illustrated duty cycle of 50% in Figure 5A occurs because the ideal output of comparator 122 switches when the input crosses a threshold of approximately zero volts. However, real implementations of comparator 122 exhibit an offset of value Voffset and switch when the input crosses a voltage threshold that is Voffset above or Voffset below zero volts. For example, Fig. 5B is a graphical representation of an actual output produced by comparator 122. As in Fig. Figure 5B illustrates that the actual output of comparator 122 switches when the input crosses a voltage threshold greater than zero volts. The voltage difference between the actual voltage at which comparator 122 switches and the ideal voltage is called the voltage offset Voffset of comparator 122. The voltage offset Voffset of comparator 122 causes a discrepancy between the peak and low times of comparator 122's output. For example, as shown in Fig. 5B further illustrates that the high time of the actual output of comparator 122 is shorter than the low time of the actual output of comparator 122. The difference between the high time and the low time of the output of comparator 122 in Fig. 5B is called duty cycle distortion. As described in more detail below, duty cycle distortion negatively affects the decoding of Manchester-coded communication signals.

[0023] As described above, Decoder 118 tracks the number of clock periods of the clock signal Tclk between transitions of the communication signal. Decoder 118 determines whether a communication signal transition is from high to low or from low to high, based on the general assumption that during a Tbit, the communication signal is at a lower voltage value for approximately half of the clock periods and at a higher voltage value for the other half of the clock periods. However, duty cycle distortion can cause the communication signal to be at the lower or higher voltage value for more than half of the clock periods during a Tbit. Consequently, Decoder 118 may incorrectly decode the communication signal due to the presence of duty cycle distortion.The discussion now turns in more detail to the receiver 120, which is configured to prevent duty cycle distortion caused by the voltage offset Voffset of the comparator 122.

[0024] Fig. Figure 6 shows an example for receiver 120. In particular, it shows Fig. 6, that the receiver 120 can comprise a substrate 128 made of semiconductor material such as silicon, which is encapsulated within a packaging to form a packed semiconductor device or packed semiconductor product. Bond contacts or other connection points of the substrate 128 are coupled to terminals of the communication bus 106. The connections can include a first input terminal 130 for receiving the first component C1 of the differential communication signal and a second input terminal 132 for receiving the second component C2 of the differential communication signal. Additional terminals such as ground, common, or power terminals are present, but these additional terminals are omitted to avoid unnecessary complexity of the figure.While a single instance of substrate 128 is shown, in other implementations multiple substrates can be combined to form the receiver 120 in the form of a multi-chip module, which is created before or after singulation.

[0025] The in Fig. The receiver 120 shown in Figure 6 includes the comparator 122, a first resistor 134, a second resistor 136, a debouncer 138, and an offset inverter 140. The receiver 120 may include fewer components, additional components, or other components in different configurations than the one shown. Fig. Figure 6 illustrates receiver 120. The first resistor 134 is connected in series between the first input terminal 130 and the offset inverter 140. The second resistor 136 is connected in series between the second input terminal 132 and the offset inverter 140. The first resistor 134 and the second resistor 136 condition the input signal so that it is compatible with the input values ​​of the comparator 122. For example, the first resistor 134 and the second resistor 136 can accept the common-mode signal without attenuating the differential amplitude of the differential communication signal.

[0026] The debouncer 138 is configured to generate an asymmetric communication signal SIG by applying a debounce time Tdebounce to the comparison signal CMP. Tdebounce is the product of Tclk and the number of positions over which the signal is debounced. The in Fig. Figure 6 illustrates the debouncer 138, which includes a debouncing circuit 146 and a set-reset flip-flop 148. The debouncer 138 may include fewer components, additional components, or other components in different configurations than the one shown. Fig. Figure 6 illustrated debouncing circuit 138. The debouncing circuit 146 includes a variety of cascading shift registers configured to generate an All1 signal (an example of a "first signal") or an All0 signal (an example of a "second signal") based on the comparison signal CMP. For example, the debouncing circuit 146 can generate the All1 signal if the comparison signal CMP remains at a logic value 1 for longer than the debounce time Tdebounce. Furthermore, the debouncing circuit 146 can generate the All0 signal if the comparison signal CMP remains at a logic value 0 for longer than the debounce time Tdebounce. The set input of the set-reset flip-flop 148 is controlled by the All1 signal generated by the debouncing circuit 146. When the debouncing circuit 146 generates the All1 signal, the set-reset flip-flop 148 sets the unbalanced communication signal SIG.For example, the set-reset flip-flop 148 can set the unbalanced communication signal SIG to a logic value 1 when the debouncing circuit 146 generates the All1 signal. The reset input of the set-reset flip-flop 148 is controlled by the All0 signal generated by the debouncing circuit 146. When the debouncing circuit 146 generates the All0 signal, the set-reset flip-flop 148 resets the unbalanced communication signal SIG. For example, the set-reset flip-flop 148 can set the unbalanced communication signal SIG to a logic value 0 when the debouncing circuit 146 generates the All0 signal.

[0027] The debouncing circuit 146 applies a debouncing time Tdebounce to the comparison signal CMP. In some implementations, the debouncing time Tdebounce is set based on a predetermined slope of the differential communication signal and a maximum voltage offset of the comparator 122. For example, the debouncing time Tdebounce can be set to the maximum time required for the input signal to exceed approximately twice the voltage offset Voffset of the comparator 122. The transition time of the input signal is predetermined based on the maximum capacitive load and the output current driving capability of the main controller 104, which drives the communication bus 106. As shown in Fig. As illustrated in Figure 6, the debounce circuit 146 receives a clock signal CLK. The cascading shift registers are updated based on the clock signal CLK. For example, the cascading shift registers can be updated at each clock period of the clock signal CLK. In some implementations, the debounce time Tdebounce is set based on the number of cascading shift registers enclosed in the debounce circuit 146 and the clock signal CLK. For example, the debounce time Tdebounce can be set to the product of the clock period of the clock signal CLK and the number of clock periods required for each of the cascading shift registers to be set to the output value of the XOR gate 144 after the output value of the XOR gate 144 changes.

[0028] The offset inverter 140 is configured to couple the first input terminal 130, based on the unbalanced communication signal SIG, to the first input 124 or the second input 126 of the comparator 122. For example, the in Fig. Figure 6 illustrates offset inverter 140 with a switching circuit 142 configured to couple the first input terminal 130 to the first input 124 of comparator 122 when the unbalanced communication signal SIG is at a first logic value (for example, a logic value 1). Furthermore, the switching circuit 142 couples the first input terminal 130 to the second input 126 of comparator 122 when the unbalanced communication signal CMP is at a second logic value (for example, a logic value 0). The offset inverter 140 is also configured to couple the second input terminal 132 to either the first input 124 or the second input 126 of comparator 122 based on the unbalanced communication signal SIG. For example, the Fig. The illustrated switching circuit 142 is configured to couple the second input terminal 132 to the second input 126 of the comparator 122 when the unbalanced communication signal SIG is at the first logic value. Furthermore, the switching circuit 142 couples the second input terminal 132 to the first input 124 of the comparator 122 when the unbalanced communication signal CMP is at the second logic value. The offset inverter 140 is also configured to invert the comparison signal CMP based on the unbalanced communication signal SIG. For example, the circuit in Figure 6 connects the second input terminal 132 to the first input 124 of the comparator 122 when the unbalanced communication signal CMP is at the second logic value. Fig. Figure 6 illustrates offset inverter 140 with an XOR gate 144 having a first input coupled to the output of comparator 122, a second input coupled to the output of debouncer 138, and an output coupled to the input of debouncer 138. Together, the switching circuit 142 and the XOR gate 144 invert both the input and output of comparator 122 to preserve the overall polarity.

[0029] Fig. Figure 7 is a schematic diagram of an example of the switching circuit 142 according to some implementations. The in Fig. 7. Illustrated switching circuit 142 includes a first pair of switches 150 and a second pair of switches 152. The first pair of switches 150 and the second pair of switches 152 can include low-voltage switches such as metal-oxide-semiconductor field-effect transistors or other types of transistors (for example, bipolar transistors). The switching circuit 142 can have fewer components, additional components, or other components in different configurations than those shown in Figure 7. Fig. 7 illustrated switching circuit 142.

[0030] The first pair of switches 150 is coupled to the first input terminal 130 via the first resistor 134 to receive the first component C1 of the differential communication signal. The first pair of switches 150 is configured to couple the first input terminal 130 to either the first input 124 or the second input 126 of the comparator 122, based on the unbalanced communication signal SIG. For example, the first pair of switches 150 can couple the first input terminal 130 to the first input 124 of the comparator 122 if the unbalanced communication signal SIG has a first value, and to the second input 126 of the comparator 122 if the unbalanced communication signal SIG has a second value.

[0031] The second pair of switches 152 is coupled to the second input terminal 132 via the first resistor 136 to receive the second component C2 of the differential communication signal. The second pair of switches 152 is configured to couple the second input terminal 132 to either the first input 124 or the second input 126 of the comparator 122, based on the unbalanced communication signal SIG. For example, the second pair of switches 152 can couple the second input terminal 132 to the second input 126 of the comparator 122 if the unbalanced communication signal SIG has the first value, and to the first input 124 of the comparator 122 if the unbalanced communication signal SIG has the second value.

[0032] Fig. Figure 8A is a graphical representation of an example of the comparison signal CMP generated by comparator 122 when comparator 122 has a positive voltage offset. The representation in Fig. Section 8A also includes an example of the asymmetric communication signal SIG generated by the debouncer 138. As in Fig. As illustrated in Figure 8A, the comparison signal CMP switches from a low value to a high value when the input crosses an initial voltage Voff1 that is greater than zero volts. As also shown in Figure 8A, the comparison signal CMP switches from a low value to a high value when the input crosses an initial voltage Voff1 that is greater than zero volts. Fig. Figure 8A illustrates how the unbalanced communication signal SIG switches from a logic value 0 to a logic value 1 after the comparator signal CMP remains high for longer than the debounce time Tdebounce. When the unbalanced communication signal SIG switches from logic value 0 to logic value 1, switching circuit 142 swaps the first input 124 and the second input 126 of comparator 122, and XOR gate 144 inverts the comparator signal CMP, resulting in an inversion of the voltage offset of comparator 122. Thus, when the input subsequently crosses a second voltage Voff2 less than zero volts, the comparator signal CMP switches from high to low, as shown in Figure 8A. Fig. Figure 8A illustrates this. The unbalanced communication signal SIG switches from logic 1 to logic 0 after the comparator signal CMP remains low for longer than the debounce time Tdebounce. When the unbalanced communication signal SIG switches from logic 1 to logic 0, circuit 142 again swaps the first input 124 and the second input 126 of comparator 122, and XOR gate 144 again inverts the comparator signal CMP, again inverting the voltage offset of comparator 122. Therefore, the comparator signal CMP switches from high to low when the input again crosses the first voltage Voff1.

[0033] Fig. Figure 8A illustrates that a certain degree of transition behavior of the comparison signal CMP is possible with durations far below the debounce time Tdebounce. As described above, the unbalanced communication signal SIG is a debounced version of the comparison signal CMP. Therefore, the unbalanced communication signal SIG does not change in response to the transition behavior of the comparison signal CMP. Rather, the unbalanced communication signal SIG changes in response to rising and falling transitions of the input. Thus, the unbalanced communication signal SIG provides an accurate indication of whether the next transition of the input will be falling or rising. For example, Figure 8A illustrates this. Fig. 8A, that the unbalanced communication signal SIG is at its high value at the beginning of a falling transition and at its low value at the beginning of a rising transition. By inverting the voltage offset of comparator 122 when the unbalanced communication signal SIG is at its high value, the offset inverter 140 inverts the voltage offset of comparator 122 for falling transitions of the input. Duty cycle distortion is caused by comparator 122 when it triggers at different transition values ​​for rising and falling transitions of the input. However, as in Fig. As illustrated in Figure 8A, the second voltage Voff2 has the same magnitude as the first voltage Voff1 because the voltage offset of comparator 122 is inverted for falling input transitions. Inverting the voltage offset of comparator 122 for falling input transitions causes comparator 122 to trigger at the same transition magnitude for both rising and falling input transitions. Therefore, there is no duty cycle distortion, as the peak and low times of the unbalanced communication signal SIG generated by debouncer 138 are essentially the same.

[0034] Fig. Figure 8B is a graphical representation of an example of the comparison signal CMP generated by comparator 122 when comparator 122 has a negative voltage offset. The representation in Fig. Section 8B also includes an example of the asymmetric communication signal SIG generated by the debouncer 138. As in Fig. Figure 8B illustrates that the comparison signal CMP switches from a low value to a high value when the input crosses a third voltage Voff3 that is less than zero volts. As also shown in Fig. Figure 8B illustrates that the unbalanced communication signal SIG switches from a logic value 0 to a logic value 1 after the comparator signal CMP remains high for longer than the debounce time Tdebounce. When the unbalanced communication signal SIG switches from logic value 0 to logic value 1, the voltage offset of comparator 122 is inverted from the third voltage Voff3 to a fourth voltage Voff4. Therefore, the comparator signal CMP switches from high to low when the input crosses the fourth voltage Voff4, as shown in Figure 8B. Fig. Figure 8B illustrates this. The unbalanced communication signal SIG switches from logic value 1 to logic value 0 after the comparator signal CMP remains low for longer than the debounce time Tdebounce. When the unbalanced communication signal SIG switches from logic value 1 to logic value 0, the voltage offset of comparator 122 is inverted from the fourth voltage Voff4 to the third voltage Voff3. Therefore, the comparator signal CMP switches from high to low when the input again crosses the third voltage Voff3. As shown in Fig. As illustrated in Figure 8B, the fourth voltage Voff4 has the same magnitude as the third voltage Voff3, since this is an inherent property of the comparator 122. Therefore, the high and low times of the unbalanced communication signal SIG generated by the debouncer 138 are still essentially the same.

[0035] Fig. Figure 9 is a flowchart of an example of a Method 200 for receiving a signal according to some implementations. For the sake of simplicity, the Method 200 is shown in Fig. Figure 9 is shown and described as a sequence of operations. However, the operations can occur in different sequences and / or simultaneously and / or with other operations not shown or described herein. In block 202, a differential communication signal is received. The differential communication signal includes the first component C1 and the second component C2. The differential communication signal can be received by the lighting unit 102, the local control unit 112, or the receiver 120. In block 204, the comparator 122 generates a comparison signal CMP by comparing the first component C1 and the second component C2. In block 206, the unbalanced communication signal SIG is generated by applying the debounce time Tdebounce to the comparison signal CMP.For example, the debouncer 138 can generate the unbalanced communication signal SIG by applying the debounce time Tdebounce to the comparison signal CMP, including the All1 / All0 detection. In block 208, the voltage offset of the comparator 122 is inverted based on the unbalanced communication signal. For example, the offset inverter 140 can apply the first component C1 of the differential communication signal, based on the unbalanced communication signal SIG, to the first input 124 or the second input 126 of the comparator 122. Furthermore, the offset inverter 140 can apply the second component C2 of the differential communication signal, based on the unbalanced communication signal SIG, to the first input 124 or the second input 126 of the comparator 122. Additionally, the offset inverter 130 can invert the comparison signal CMP based on the unbalanced communication signal SIG.By inverting the voltage offset of comparator 122 based on the asymmetric communication signal, the overall polarity of the comparison function is preserved.

[0036] Fig. Figure 10 is a graph 300 of an example simulation results of marriages for the outputs of different comparators with a 900 nanosecond long rectangular input wave and a 32-megahertz clock signal over the voltage offset of comparator 122. The graph 300 in Fig. 10 includes a first graphical representation 302 of an example of the marriage for the output of a comparator under ideal conditions without voltage offset or debouncing. As shown by the first graphical representation 302 in Fig. As illustrated in Figure 10, the mating time for the output of a comparator under ideal conditions is approximately 450 nanoseconds and is independent of the voltage offset of comparator 122. Graph 300 in Fig. Figure 10 also includes a second graphical representation 304 of an example of the marriage for the output of a standard comparator with different voltage offsets. As shown by the second graphical representation 304 in Fig. As illustrated in Figure 10, the marriage for the output of the standard comparator decreases essentially linearly as the voltage offset increases. Graph 300 in Fig. 10 further includes a third graphical representation 306 of an example of the marriage for the output of the comparator 122 described herein with different voltage offsets. As shown by the third graphical representation 306 in Fig.As illustrated in Figure 10, the timing for the output of comparator 122 is, for most voltage offsets, either essentially equal to the ideal value of 450 nanoseconds or approximately one clock pulse below the ideal value. Due to debouncing, the time resolution at the output is determined by the clock frequency of the debouncer 138.

[0037] Many of the electrical connections in the drawings are shown as direct couplings without intermediate devices, but are not explicitly identified as such in the preceding description. Nevertheless, this paragraph serves as a reference in the claims for electrical connections without intermediate device(s) shown in the drawing, in order to designate any electrical connection as "directly coupled".

[0038] The foregoing discussion is intended to illustrate the principles and various implementations of the present invention. Numerous variations and modifications will be apparent to those skilled in the art once the foregoing disclosure has been fully understood. It is intended that the following claims be interpreted as encompassing all such variations and modifications.

Claims

[1] Method for receiving a signal, the method comprising: Receiving a differential communication signal that includes a first component and a second component; Generating a comparison signal with a comparator by comparing the first component and the second component; Generating an asymmetrical communication signal by applying a debouncing time to the comparison signal; and Inverting a voltage offset of the comparator based on the asymmetrical communication signal. [2] Method according to claim 1, wherein inverting the voltage offset of the comparator based on the asymmetric communication signal further includes: Applying the first component of the differential communication signal to either the first or second of two inputs of the comparator based on the unbalanced communication signal, Applying the second component of the differential communication signal to the first or the second of the two inputs of the comparator based on the unbalanced communication signal, and Inverting the comparison signal based on the asymmetrical communication signal. [3] Method according to claim 2, wherein applying the first component of the differential communication signal to the first or the second of the two inputs of the comparator based on the unbalanced communication signal further includes applying the first component of the differential communication signal to: the first of the two inputs of the comparator when the asymmetrical communication signal is at a first logic value, and the second of the two inputs of the comparator, if the unbalanced communication signal is on a second logic value, and where applying the second component of the differential communication signal to the first or the second of the two inputs of the comparator based on the unbalanced communication signal further includes applying the second component of the differential communication signal to: the second of the two inputs of the comparator when the asymmetrical communication signal is at the first logic value, and the first of the two inputs of the comparator when the asymmetrical communication signal is at the second logic value. [4] Method according to claim 1, wherein generating the asymmetric communication signal by applying the debounce time to the comparison signal further includes: Detecting that the comparison signal remains on a first logic value for longer than the debounce time, Setting the asymmetric communication signal to the first logic value when it is detected that the comparison signal remains at the first logic value for longer than the debounce time, Detect that the comparison signal remains on a second logic value for longer than the debounce time, and Setting the asymmetric communication signal to the second logic value when it is detected that the comparison signal remains on the second logic value for longer than the debounce time. [5] Method according to claim 1, further comprising decoding the asymmetric communication signal using a time-based coding scheme. [6] Recipients, including: a first input port for receiving a first component of a differential communication signal; a second input port for receiving a second component of the differential communication signal; a comparator configured to generate a comparison signal by comparing the first and second components of the differential communication signal; a debouncer configured to generate an asymmetric communication signal by applying a debouncing time to the reference signal; and an offset inverter configured to: Coupling the first input terminal to one of the first or second of two inputs of the comparator based on the unbalanced communication signal, Coupling the second input terminal with the first or the second of the two inputs of the comparator based on the unbalanced communication signal, and Inverting the comparison signal based on the asymmetrical communication signal. [7] Receiver according to claim 6, wherein the debouncing device includes: a debouncing circuit with a multitude of cascading shift registers configured to generate a first signal or a second signal based on the comparison signal, and A set-reset flip-flop configured to generate the asymmetric communication signal based on the first signal and the second signal. [8] Receiver according to claim 7, wherein the debounce time is based on a number of cascading shift registers enclosed in the plurality of cascading shift registers and a clock signal received by the debounce circuit. [9] Receiver according to claim 6, wherein the offset inverter includes an XOR gate, including: a first input coupled to an output of the comparator, a second input coupled to the output of the debouncer, and an output that is coupled to an input of the debouncer. [10] Receiver according to claim 6, wherein the offset inverter includes a switching circuit comprising the following: a first pair of switches configured to couple the first input terminal, based on the unbalanced communication signal, to either the first or the second of the two inputs of the comparator, and a second pair of switches configured to couple the second input terminal to either the first or the second of the two inputs of the comparator based on the unbalanced communication signal. [11] Receiver according to claim 6, wherein the offset inverter, in order to couple the first input terminal to the first or the second of the two inputs of the comparator based on the unbalanced communication signal, is further configured to couple the first input terminal to: the first of the two inputs of the comparator, when the asymmetrical communication signal is at a first logic value, and the second of the two inputs of the comparator, when the unbalanced communication signal is on a second logic value, and wherein, in order to couple the second input terminal to the first or the second of the two inputs of the comparator based on the unbalanced communication signal, the offset inverter is further configured to couple the second input terminal to: the second of the two inputs of the comparator, when the asymmetrical communication signal is at the first logic value, and the first of the two inputs of the comparator, when the asymmetrical communication signal is at the second logic value. [12] Recipient according to claim 6, further comprising: a first resistor coupled in series between the first input terminal and the offset inverter, and a second resistor coupled in series between the second input terminal and the offset inverter. [13] System, encompassing: a main controller configured to send a differential communication signal; a communications bus; and a local controller that is communicatively coupled to the main controller via the communication bus, wherein the local controller is configured to: Receiving the differential communication signal, Generating a comparison signal with a comparator by comparing a first component of the differential communication signal and a second component of the differential communication signal, Generating an asymmetric communication signal by applying a debouncing time to the comparison signal, and inverting a voltage offset of the comparator based on the asymmetric communication signal. [14] System according to claim 13, wherein the local control is further configured to decode the asymmetric communication signal using a time-based coding scheme. [15] System according to claim 13, wherein the communication bus includes a Controller Area Network. [16] System according to claim 13, wherein the system is a lighting system, the lighting system further comprising a lighting unit which includes the following: a variety of light sources, and the local control, where the local control is configured to control the multitude of light sources based on the asymmetrical communication signal. [17] System according to claim 16, wherein the lighting system is an automobile or a vehicle. [18] System according to claim 13, wherein the local control for inverting the voltage offset of the comparator based on the unbalanced communication signal is further configured to: Applying the first component of the differential communication signal to either the first or second of two inputs of the comparator based on the unbalanced communication signal, Applying the second component of the differential communication signal to the first or the second of the two inputs of the comparator based on the unbalanced communication signal, and Inverting the comparison signal based on the asymmetrical communication signal. [19] System according to claim 18, wherein, in order to apply the first component of the differential communication signal to the first or the second of the two inputs of the comparator based on the unbalanced communication signal, the local control is further configured to apply the first component of the differential communication signal to: the first of the two inputs of the comparator when the asymmetrical communication signal is at a first logic value, and the second of the two inputs of the comparator, if the unbalanced communication signal is on a second logic value, and wherein, in order to apply the second component of the differential communication signal to the first or the second of the two inputs of the comparator based on the unbalanced communication signal, the local control is further configured to apply the second component of the differential communication signal to: the second of the two inputs of the comparator when the asymmetrical communication signal is at the first logic value, and the first of the two inputs of the comparator when the asymmetrical communication signal is at the second logic value. [20] System according to claim 13, wherein the debounce time is based on a predetermined slope of the differential communication signal and a maximum voltage offset of the comparator.

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