PIXEL CIRCUIT

Abstract

A pixel circuit (100) has a first connection point (PAD1), a second connection point (PAD2), a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), and a first capacitor (capacitor).A first control signal (S1), a second control signal (S2), an emission control signal (EM1), a system high voltage (VDD), a system low voltage (VSS), a first reference voltage (DC_1) and a second reference voltage (DC_2), received by the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, eighth transistor and ninth transistor, are set to electrically test the first junction point, the second junction point, the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor and the first capacitor.

Description

BACKGROUND Technical field The disclosure relates to a pixel circuit and in particular to a pixel circuit for configuring light-emitting diodes. Description of the state of the art After array manufacturing is complete, the transistor's performance is tested on the display panel to detect any defects caused by the manufacturing process. This electrical test is called "array testing," and one of its detection methods involves measuring the current flowing through the data lines. Therefore, the question of how to detect pixel circuitry via the data lines has become a key focus of array testing. SUMMARY The disclosure provides a pixel circuit that can test the transistor and connection points in the pixel circuit when the LED is not configured, thus eliminating the need to increase the signals required by the board or panel. This means the circuit area of ​​the gate driver circuitry is not increased, and the normal operation of the transistors in the pixel circuit is not affected. The pixel circuit of the revelation features a first junction point, a second junction point, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a first capacitor. The first junction point is used to connect the anode of a light-emitting element. The second junction point is used to connect the cathode of the light-emitting element and is connected to a system low voltage. The first transistor has a first terminal, a control terminal, and a second terminal that receives a system high voltage. The second transistor has a first terminal, a control terminal that receives a first control signal, and a second terminal that is connected to the second terminal of the first transistor.The third transistor has a first terminal connected to the control terminal of the first transistor, a control terminal that receives the first control signal, and a second terminal connected to the first terminal of the second transistor. The fourth transistor has a first terminal connected to the first terminal of the second transistor, a control terminal that receives the second control signal, and a second terminal that receives a first reference voltage. The fifth transistor has a first terminal that provides a data signal, a control terminal that receives a first control signal, and a second terminal. The sixth transistor has a first terminal connected to the second terminal of the fifth transistor, a control terminal that receives an emission control signal, and a second terminal that receives a first reference voltage.The first capacitor is connected between the second terminal of the fifth transistor and the control terminal of the first transistor. The seventh transistor has a first terminal connected to the second terminal of the first transistor, a control terminal that receives the emission control signal, and a second terminal connected to the first terminal. The eighth transistor has a first terminal connected to the first terminal, a control terminal that receives the emission control signal, and a second terminal. The ninth transistor has a first terminal connected to the second terminal of the eighth transistor, a control terminal that receives the second reference voltage, and a second terminal connected to the first terminal of the fifth transistor.The first control signal, the second control signal, the emission control signal, the system high voltage, the system low voltage, the first reference voltage and the second reference voltage are set to electrically test the first junction point, the second junction point, the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor and the first capacitor. Based on the above, the pixel circuit, compared to a conventional pixel circuit, can be electrically divided when the light-emitting element is not configured. By adjusting the control signal, the emission control signal, the system high voltage, the system low voltage, the first reference voltage, and the second reference voltage, the test result can be sequentially reflected from the data signal. In this way, the transistors, the capacitor, and the connection points can be tested in groups if it is necessary to increase the signals required by the board or panel. This means that the circuit area of ​​the gate driver circuit on the board is not increased, and the normal operation of the transistor in the pixel circuit is not affected. To make the above-mentioned features and advantages of the disclosure more understandable, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic system diagram of a pixel circuit according to an embodiment of the disclosure. Fig. 2A is a schematic circuit diagram of a first test operation of the pixel circuit according to an embodiment of the disclosure. Fig. 2B is a timing diagram of the first test operation of the pixel circuit according to an embodiment of the disclosure. Fig. 3A is a schematic circuit diagram of a second test operation of the pixel circuit according to an embodiment of the disclosure. Fig. 3B is a timing diagram of the second test operation of the pixel circuit according to an embodiment of the disclosure. Fig. 4A is a schematic circuit diagram of a third test operation of the pixel circuit according to an embodiment of the disclosure. Fig. 4B is a timing diagram of the third test operation of the pixel circuit according to an embodiment of the disclosure.Figure 5A is a schematic circuit diagram of a fourth test operation of the pixel circuit according to an embodiment of the disclosure. Figure 5B is a timing diagram of the fourth test operation of the pixel circuit according to an embodiment of the disclosure. DESCRIPTION OF THE EXECUTION FORMS Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by persons with normal knowledge of the field to which the revelation belongs. It is further understood that terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the revelation, and should not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein. Although terms such as "first," "second," and "third" may be used here to describe different elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be considered restrictive. These terms are used merely to distinguish one element, component, region, layer, or section from another. Thus, a "first element," "component," "region," "layer," or "section" referred to below could also be called a second element, component, region, layer, or section without this deviating from the teachings presented here. The terminology used herein serves only to describe certain embodiments and is not to be understood as restrictive. As used herein, the singular forms "a," "an," and "the" include the plural forms, including "at least a," "or," and "and / or," unless the context clearly indicates otherwise. As used herein, the term "and / or" includes all combinations of one or more of the listed items. It is also understood that, in this description, the terms "has" and / or "includes" denote the presence of listed features, regions, units, steps, operations, elements, and / or components. However, this does not preclude the presence or addition of one or more other features, regions, units, steps, operations, elements, components, and / or combinations thereof. Fig. 1 is a schematic system diagram of a pixel circuit according to one embodiment of the disclosure. Referring to Fig. 1, a pixel circuit 100 in this embodiment includes, for example, connection points PAD1 and PAD2 (corresponding to a first connection point and a second connection point), transistors T1 to T9 (corresponding to a first transistor to a ninth transistor), and a capacitor C1 (corresponding to a first capacitor). The respective transistors T1 to T9 are, for example, P-type transistors, but the embodiments of the disclosure are not limited thereto. Junction PAD1 is used to connect the anode of a light-emitting element (e.g., a micro light-emitting diode LD1). Junction PAD2 is used to connect the cathode of the micro light-emitting diode LD1 and is connected to a system low voltage VSS. Transistor T1 has a first terminal, which receives a system high voltage VDD, a control terminal, and a second terminal. Transistor T2 has a first terminal, a control terminal, which receives a control signal S2 (corresponding to a first control signal), and a second terminal, which is connected to the second terminal of transistor T1. Transistor T3 has a first terminal connected to the control terminal of transistor T1, a control terminal that receives the control signal S2, and a second terminal connected to the first terminal of transistor T2. Transistor T4 has a first terminal coupled to the first terminal of transistor T2, a control terminal that receives the control signal S1 (corresponding to a second control signal), and a second terminal that receives a first reference voltage DC_1. Transistor T5 has a first terminal that provides a data signal, a control terminal that receives the control signal S2, and a second terminal. Transistor T6 has a first terminal connected to the second terminal of transistor T5, a control terminal that receives an emission control signal EM1, and a second terminal that receives the first reference voltage DC_1. Capacitor C1 is connected between the second terminal of transistor T5 and the control terminal of transistor T1. Transistor T7 has a first terminal connected to the second terminal of transistor T1, a control terminal that receives the emission control signal EM1, and a second terminal connected to junction PAD1. Transistor T8 has a first terminal connected to junction PAD1, a control terminal that receives the emission control signal EM1, and a second terminal. Transistor T9 has a first terminal connected to the second terminal of transistor T8, a control terminal that receives a second reference voltage DC_2, and a second terminal connected to the first terminal of transistor T5. In this embodiment, the control signals S1 and S2, the emission control signal EM1, the system high voltage VDD, the system low voltage VSS, the first reference voltage DC_1 and the second reference voltage DC_2 are set to electrically test the connection points PAD1, PAD2, the transistors T1 to T3, T5 to T7 and the capacitor C1 in partitions (or in groups) in a time-divisional manner, and the test result can be read from the data signal Data in sequence (i.e. the test result can be read from the current of the data line). Based on the above, the pixel circuit 100, compared to the conventional pixel circuit when the micro LED LD1 is not configured, can be divided into several different signal paths. By setting the control signals S1 and S2, the emission control signal EM1, the system high voltage VDD, the system low voltage VSS, the first reference voltage DC_1, and the second reference voltage DC_2, the test result can be subsequently reflected from the data signal Data. To measure the electrical characteristics of transistor T1 (i.e., a driver transistor) on the right side of capacitor C1 (i.e., the storage capacitor), transistors T8 and T9 are added to the junction point PAD1 in this embodiment to establish a connection to the data line. Transistor T8 and transistor T7 share the emission control signal EM1, and transistor T9 is driven by a DC signal (i.e.,The second reference voltage (DC_2) is controlled, allowing transistor T1 to be tested without increasing the required signals. This means the circuit area of ​​the gate driver circuitry on the board is not increased, and the normal operation of the transistors in the pixel circuit is not affected. In one embodiment of the disclosure, the connection points PAD1 and PAD2 are, for example, the endpoints of the wiring, through holes or solder joints, but the embodiments of the disclosure are not limited thereto. Fig. 2A is a schematic circuit diagram of a first test operation of the pixel circuit according to an embodiment of the disclosure. Fig. 2B is a timing diagram of the first test operation of the pixel circuit according to an embodiment of the disclosure. With reference to Fig. 1, Fig. 2A, and Fig. 2B, three time periods are roughly divided in this embodiment, namely a period T11 before the test, a period T12 during the test, and a period T13 after the test. During period T11, the control signal S1, the control signal S2, the emission control signal EM1, the first reference voltage DC_1, and the second reference voltage DC_2 are at a high voltage level H, while the system high voltage VDD and the system low voltage VSS are at a low voltage level L. At this time, transistors T2 to T9 are in an off state, and transistor T1 is switched off in response to the low voltage level L of the system high voltage VDD. During this period, the data signal Data is essentially independent of the state of pixel circuit 100. During time period T12, the control signal S1, the first reference voltage DC_1, and the second reference voltage DC_2 are at the high voltage level H, while the control signal S2, the emission control signal EM1, the system high voltage VDD, and the system low voltage VSS are at the low voltage level L. At this time, transistors T2, T3, and T5 through T8 are in the on state, transistors T4 and T9 are in the off state, and transistor T1 is switched off in response to the low voltage level L of the system high voltage VDD, with transistors T5 and T6 forming an input path PH1. Since transistors T1 and T9 are off, the data signal Data is essentially related to the state of transistors T5 and T6. That is, the data signal Data reflects the test result of input path PH1. The actions in time period T13 are basically the same as in time period T11. Fig. 3A is a schematic circuit diagram of a second test operation of the pixel circuit according to an embodiment of the disclosure. Fig. 3B is a timing diagram of the second test operation of the pixel circuit according to an embodiment of the disclosure. With reference to Fig. 1, Fig. 3A, and Fig. 3B, three time periods are roughly divided in this embodiment, namely a period T21 before the test, a period T22 during the test, and a period T23 after the test. During period T21, the control signal S1, the control signal S2, the emission control signal EM1, and the system high voltage VDD are at the high-voltage level H, the system low voltage VSS is at the low-voltage level L, and the first reference voltage DC_1 and the second reference voltage DC_2 can be at any voltage level (e.g., the high-voltage level H or the low-voltage level L). At this time, transistors T2 to T8 are in the off state, and the data signal Data is fundamentally independent of the state of pixel circuit 100. During time period T22, the control signal S1, the emission control signal EM1, and the system high voltage VDD are at the high voltage level H, the control signal S2 and the system low voltage VSS are at the low voltage level L, and the first reference voltage DC_1 and the second reference voltage DC_2 can be at any voltage level. At this time, transistors T2, T3, and T5 are in the on state, transistors T4, T6, T7, and T8 are in the off state, and transistor T1 is turned on in response to the high voltage level H of the system high voltage VDD, with transistors T1, T2, T3, T5, and capacitor C1 forming a transistor compensation path PH2, and transistor T9 being either on or off. Since transistors T4, T6, T7, and T8 are off, the data signal Data is essentially based on the state of transistors T1, T2, T3, T5, and capacitor C1.This means that the data signal Data reflects the test result of the transistor compensation path PH2. At this point, the data signal Data can indicate whether capacitor C1 (i.e., the storage capacitor) is open or short-circuited. The actions in time interval T23 are essentially the same as in time interval T21. Fig. 4A is a schematic circuit diagram of a third test operation of the pixel circuit according to an embodiment of the disclosure. Fig. 4B is a timing diagram of the third test operation of the pixel circuit according to an embodiment of the disclosure. With reference to Fig. 1, Fig. 4A, and Fig. 4B, three time periods are roughly divided in this embodiment, namely a period T31 before the test, a period T32 during the test, and a period T33 after the test. During period T31, the control signals S1, S2, the emission control signal EM1, and the system low voltage VSS are at the high voltage level H, the system high voltage VDD and the second reference voltage DC_2 are at the low voltage level L, transistor T1 is switched off in response to the low voltage level L of the system high voltage VDD, and the first reference voltage DC_1 can be at any voltage level (e.g., the high voltage level H or the low voltage level L). At this time, transistors T1 to T8 are in the off state, and the data signal Data is essentially independent of the state of pixel circuit 100. During time period T32, the control signals S1, S2, and the system low voltage VSS are at the high voltage level H, the emission control signal EM1, the system high voltage VDD, and the second reference voltage DC_2 are at the low voltage level L, and transistor T1 is switched off in response to the low voltage level L of the system high voltage VDD. At this time, transistors T6 to T9 are in the on state, transistors T2 to T5 are in the off state, and transistor T1 is switched off in response to the low voltage level L of the system high voltage VDD, with junction points PAD1 and PAD2 forming a contact test path PH3. Since transistors T1 and T5 are off, the data signal Data reflects the test result of the contact test path PH3. At this time, the data signal Data can indicate whether junction points PAD1 and PAD2 are open or short-circuited.The actions in time period T33 are basically the same as in time period T31. Fig. 5A is a schematic circuit diagram of a fourth test operation of the pixel circuit according to an embodiment of the disclosure. Fig. 5B is a timing diagram of the fourth test operation of the pixel circuit according to an embodiment of the disclosure. With reference to Fig. 1, Fig. 5A, and Fig. 5B, three time periods are roughly divided in this embodiment, namely a period T41 before the test, a period T42 during the test, and a period T43 after the test. During period T41, the control signals S1, S2, the emission control signal EM1, and the system high voltage VDD are at the high-voltage level H, the system low voltage VSS and the second reference voltage DC_2 are at the low-voltage level L, and the first reference voltage DC_1 can be at any voltage level (e.g., the high-voltage level H or the low-voltage level L). At this time, transistors T2 to T8 are in the off state, and the data signal Data is fundamentally independent of the state of pixel circuit 100. During time period T42, the control signals S1, S2, and the system high voltage VDD are at the high voltage level H; the emission control signal EM1, the system low voltage VSS, and the second reference voltage DC_2 are at the low voltage level L; and the first reference voltage DC_1 can be at any voltage level (e.g., the high voltage level H or the low voltage level L). At this time, transistors T6 to T9 are switched on, transistors T2 to T5 are switched off, and transistor T1 is switched on in response to the high voltage level H of the system high voltage VDD, with transistors T1 and T7 forming a driver path PH4. Since transistors T2 and T5 are switched off, the data signal Data reflects the test result of the drive path PH4. The actions in time period T43 are essentially the same as in time period T41. In summary, compared to a conventional pixel circuit, the pixel circuit of the embodiments of the disclosure, when the micro-LED is not configured, can be divided into several different signal paths. By setting the control signal, the emission control signal, the system high voltage, the system low voltage, the first reference voltage, and the second reference voltage, the test result can be sequentially reflected from the data signal. In this way, the transistors, the capacitor, and the connection points can be tested in groups if it is necessary to increase the signals required by the panel. This means that the circuit area of ​​the gate driver circuitry on the panel is not increased, and the normal operation of the transistor in the pixel circuit is not affected. Although the disclosure above has been given by way of examples, these examples are not intended to limit the disclosure. Persons with normal knowledge in the relevant technical field can make some changes and modifications without deviating from the spirit and scope of the disclosure. Therefore, the scope of protection of the disclosure is determined by the accompanying claims. (LIST OF REFERENCE MARKS) 100 pixel circuit C1 Capacitor Data Data signal DC_1 First reference voltage DC_2 Second reference voltage EM1 Emission control signal H High voltage level L Low voltage level LD1 Micro LED PAD1, PAD2 Connection point PH1 Input path PH2 Transistor compensation path PH3 Contact test path PH4 Control path S1, S2 Control signal T1 to T9 Transistors T11, T12, T13, T21, T22, T23, T31, T32, T33, T41, T42, T43 Time interval VDD System high voltage VSS System low voltage

Claims

A pixel circuit (100) comprising: a first connection point (PAD1) configured to connect an anode of a light-emitting element; a second connection point (PAD2) configured to connect a cathode of the light-emitting element and coupled to a system low voltage (VSS); a first transistor (T1) with a first terminal receiving a system high voltage (VDD), a control terminal, and a second terminal; a second transistor (T2) with a first terminal, a control terminal receiving a first control signal (S1), and a second terminal coupled to the second terminal of the first transistor (T1);a third transistor (T3) with a first terminal connected to the control terminal of the first transistor (T1), a control terminal receiving the first control signal (S1), and a second terminal connected to the first terminal of the second transistor (T2); a fourth transistor (T4) with a first terminal connected to the first terminal of the second transistor (T2), a control terminal receiving a second control signal (S2), and a second terminal receiving a first reference voltage (DC_1); a fifth transistor (T5) with a first terminal providing a data signal (Data), a control terminal receiving the first control signal (S1), and a second terminal;a sixth transistor (T6) with a first terminal connected to the second terminal of the fifth transistor (T5), a control terminal receiving an emission control signal (EM1), and a second terminal receiving the first reference voltage (DC_1); a first capacitor (C1) connected between the second terminal of the fifth transistor (T5) and the control terminal of the first transistor (T1); a seventh transistor (T7) with a first terminal connected to the second terminal of the first transistor (T1), a control terminal receiving the emission control signal (EM1), and a second terminal connected to the first connection point (PAD1); an eighth transistor (T8) with a first terminal connected to the first connection point (PAD1), a control terminal receiving the emission control signal (EM1), and a second terminal;and a ninth transistor (T9) with a first terminal connected to the second terminal of the eighth transistor (T8), a control terminal receiving a second reference voltage (DC_2), and a second terminal connected to the first terminal of the fifth transistor (T5); wherein the first control signal (S1), the second control signal (S2), the emission control signal (EM1), the system high voltage (VDD), the system low voltage (VSS), the first reference voltage (DC_1), and the second reference voltage (DC_2) are set to electrically test the first junction point (PAD1), the second junction point (PAD2), the first transistor (T1), the second transistor (T2), the third transistor (T3), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the first capacitor (C1). Pixel circuit (100) according to claim 1, wherein the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), the eighth transistor (T8) and the ninth transistor (T9) are each P-type transistors. Pixel circuit (100) according to claim 2, wherein, in response to the second control signal (S2) being at a high voltage level (H), the first control signal (S1) being at a low voltage level (L), the emission control signal (EM1) being at the low voltage level (L), the system high voltage (VDD) being at the low voltage level (L), the system low voltage (VSS) being at the low voltage level (L), the first reference voltage (DC_1) being at the high voltage level (H) and the second reference voltage (DC_2) being at the high voltage level (H), the fifth transistor (T5) and the sixth transistor (T6) forming an input path (PH1) and the data signal (Data) reflecting a test result of the input path (PH1). Pixel circuit (100) according to claim 2, wherein, in response to the second control signal (S2) being at a high voltage level (H), the first control signal (S1) being at a low voltage level (L), the emission control signal (EM1) being at the high voltage level (H), the system high voltage (VDD) being at the high voltage level (H), and the system low voltage (VSS) being at the low voltage level (L), the first transistor (T1), the second transistor (T2), the third transistor (T3), the first capacitor (C1), and the fifth transistor (T5) forming a transistor compensation path (PH2), and the data signal (Data) reflecting a test result of the transistor compensation path (PH2). Pixel circuit (100) according to claim 2, wherein, in response to the second control signal (S2) being at a high voltage level (H), the first control signal (S1) being at the high voltage level (H), the emission control signal (EM1) being at a low voltage level (L), the system high voltage (VDD) being at the low voltage level (L), the system low voltage (VSS) being at the high voltage level (H), and the second reference voltage (DC_2) being at the low voltage level (L), the data signal (Data) reflects a test result of a contact test section (PH3) formed by the first connection point (PAD1) and the second connection point (PAD2). Pixel circuit (100) according to claim 5, wherein, in response to the second control signal (S2) being at the high voltage level (H), the first control signal (S1) being at the high voltage level (H), the emission control signal (EM1) being at the low voltage level (L), the system high voltage (VDD) being at the high voltage level (H), the system low voltage (VSS) being at the low voltage level (L), and the second reference voltage (DC_2) being at the low voltage level (L), the first transistor (T1) and the seventh transistor (T7) forming a driver path (PH4) and the data signal (Data) reflecting a test result of the driver path (PH4). Pixel circuit (100) according to claim 1, wherein the light-emitting element is a micro-light-emitting diode (LD1). Pixel circuit (100) according to claim 1, wherein the first connection point (PAD1) and the second connection point (PAD2) are each an endpoint of a wiring, a through hole or a solder joint. A pixel circuit (100) comprising: a first connection point (PAD1) configured to connect an anode of a light-emitting element; a second connection point (PAD2) configured to connect a cathode of the light-emitting element and coupled to a system low voltage (VSS); a first transistor (T1) with a first terminal receiving a system high voltage (VDD), a control terminal, and a second terminal; a second transistor (T2) with a first terminal, a control terminal receiving a first control signal (S1), and a second terminal connected to the second terminal of the first transistor (T1);a third transistor (T3) with a first terminal connected to the control terminal of the first transistor (T1), a control terminal receiving the first control signal (S1), and a second terminal connected to the first terminal of the second transistor (T2); a fourth transistor (T4) with a first terminal connected to the first terminal of the second transistor (T2), a control terminal receiving a second control signal (S2), and a second terminal receiving a first reference voltage (DC_1); a fifth transistor (T5) with a first terminal providing a data signal (Data), a control terminal receiving the first control signal (S1), and a second terminal;a sixth transistor (T6) with a first terminal connected to the second terminal of the fifth transistor (T5), a control terminal receiving an emission control signal (EM1), and a second terminal receiving the first reference voltage (DC_1); a first capacitor (C1) connected between the second terminal of the fifth transistor (T5) and the control terminal of the first transistor (T1); a seventh transistor (T7) with a first terminal connected to the second terminal of the first transistor (T1), a control terminal receiving the emission control signal (EM1), and a second terminal connected to the first connection point (PAD1); an eighth transistor (T8) with a first terminal connected to the first connection point (PAD1), a control terminal receiving the emission control signal (EM1), and a second terminal;and a ninth transistor (T9) with a first terminal connected to the second terminal of the eighth transistor (T8), a control terminal receiving a second reference voltage (DC_2), and a second terminal; wherein the first control signal (S1), the second control signal (S2), the emission control signal (EM1), the system high voltage (VDD), the system low voltage (VSS), the first reference voltage (DC_1), and the second reference voltage (DC_2) are set to electrically test the first junction point (PAD1), the second junction point (PAD2), the first transistor (T1), the second transistor (T2), the third transistor (T3), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the first capacitor (C1). Pixel circuit (100) according to claim 9, wherein the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), the eighth transistor (T8) and the ninth transistor (T9) are each P-type transistors. Pixel circuit (100) according to claim 10, wherein in response to the second control signal (S2) being at a high voltage level (H), the first control signal (S1) being at a low voltage level (L), the emission control signal (EM1) being at the low voltage level (L), the system high voltage (VDD) being at the low voltage level (L), the system low voltage (VSS) being at the low voltage level (L), the first reference voltage (DC_1) being at the high voltage level (H), and the second reference voltage (DC_2) being at the high voltage level (H), the fifth transistor (T5) and the sixth transistor (T6) forming an input path (PH1) and the data signal (Data) reflecting a test result of the input path (PH1). Pixel circuit (100) according to claim 10, wherein in response to the second control signal (S2) being at a high voltage level (H), the first control signal (S1) being at a low voltage level (L), the emission control signal (EM1) being at the high voltage level (H), the system high voltage (VDD) being at the high voltage level (H), and the system low voltage (VSS) being at the low voltage level (L), the first transistor (T1), the second transistor (T2), the third transistor (T3), the first capacitor (C1), and the fifth transistor (T5) forming a transistor compensation path (PH2), and the data signal (Data) reflecting a test result of the transistor compensation path (PH2). Pixel circuit (100) according to claim 10, wherein in response to the second control signal (S2) being at a high voltage level (H), the first control signal (S1) being at the high voltage level (H), the emission control signal (EM1) being at a low voltage level (L), the system high voltage (VDD) being at the low voltage level (L), the system low voltage (VSS) being at the high voltage level (H), and the second reference voltage (DC_2) being at the low voltage level (L), the second end of the ninth transistor (T9) provides a test result of a contact test path (PH3) formed by the first junction point (PAD1) and the second junction point (PAD2). Pixel circuit (100) according to claim 13, wherein, in response to the second control signal (S2) being at the high voltage level (H), the first control signal (S1) being at the high voltage level (H), the emission control signal (EM1) being at the low voltage level (L), the system high voltage (VDD) being at the high voltage level (H), the system low voltage (VSS) being at the low voltage level (L), and the second reference voltage (DC_2) being at the low voltage level (L), the first transistor (T1) and the seventh transistor (T7) forming a drive path (PH4) and the second end of the ninth transistor (T9) providing a test result of the drive path (PH4). Pixel circuit (100) according to claim 9, wherein the light-emitting element is a micro-light-emitting diode (LD1).

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