DYNAMIC INITIALIZATION DELAY MANAGEMENT FOR STORAGE SYSTEM

Abstract

Methods, systems, and devices for dynamic initialization delay management of a storage system are described. A storage system can perform a power transition operation from a sleep state to an active state in response to a command from a host system. The storage system and the host system may refrain from communicating signaling during the power transition operation due to power transition delays. A storage system's power transition delay can be dynamically configured based on a host system's power transition delay such that the storage system's power transition delay can be initially programmed and then updated based on receiving a power transition delay specification from the host system.The host system can transmit its power transition delay to the storage system during an initial linking operation. The storage system can update its power transition delay so that it is greater than the host system's power transition delay.

Description

CROSS-REFERENCE

[0001] The present patent application claims priority from US patent application No. 19 / 277,095 by Wu et al. entitled “DYNAMIC INITIALIZATION DELAY MANAGEMENT FOR A MEMORY SYSTEM”, filed on July 22, 2025, and from the provisional US patent application No. 63 / 683,085 by Wu et al. entitled “DYNAMIC INITIALIZATION DELAY MANAGEMENT FOR A MEMORY SYSTEM”, filed on August 14, 2024, each of these applications being transferred to the successor thereof. AREA OF TECHNOLOGY

[0002] The following concerns one or more storage systems, which includes dynamic initialization delay management for a storage system. GENERAL STATE OF THE ART

[0003] Storage devices are commonly used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital data, and others. Information is stored by programming memory cells within a storage device to different states. For example, binary memory cells can be programmed to one of two supported states, often denoted by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, each of which can be stored. To access stored information, the storage device can read states from the memory cells (e.g., capture, detect, retrieve, determine). To store information, the storage device can write states to the memory cell (e.g., program, set, assign).

[0004] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selective memory, chalcogenide memory technologies, non-OR (NOR) and non-AND (NAND) memory devices, and others. Memory cells can be described in terms of volatile or non-volatile configurations. Memory cells configured in a non-volatile configuration can retain stored logical states for extended periods, even without an external power source.Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. PRESENTATION OF THE INVENTION

[0005] The problems mentioned above are solved by the features of independent claims.

[0006] In one aspect, the present disclosure provides a storage system comprising one or more storage devices; and a processing circuit coupled to the one or more storage devices and configured to cause the storage system to: perform a linking operation between the storage system and a host system, wherein, prior to the linking operation, the storage system is configured to perform some type of power transfer operation according to a first delay; receive a specification of a second delay associated with the host system performing the type of power transfer operation, in association with the linking operation;and updating the storage system in response to receiving the indication of the second delay assigned to the host system, in order to perform the type of performance transition operation according to a third delay that is greater than the second delay.

[0007] The storage system can be configured to perform a power transition operation (e.g., a sleep-end operation) in which the storage system transitions from a sleep state (e.g., a low-power mode) to an active mode (e.g., a high-performance mode).

[0008] The processing circuit can further be configured to cause the memory system to: store an indication of the third delay in non-volatile memory of the memory system in response to the memory system update to perform the type of power transition operation according to the third delay.

[0009] The processing circuit can further be configured to cause the storage system to receive a command from the host system to perform a power transition operation; to initiate the third delay in response to the command to perform the power transition operation; and to transition the storage system from a first power mode to a second power mode in response to receiving the command to perform the power transition operation.

[0010] The second delay can occur in response to the command to perform the power transition operation.

[0011] The processing circuit can further be configured to cause the storage system to communicate a signaling from the storage system to the host system after the third delay has elapsed.

[0012] The storage system can be configured to receive a signal from the host system after the second delay has elapsed.

[0013] The second delay can be assigned a duration for which the host system is configured to refrain from communicating a signaling message to the storage system while performing the type of power transition operation.

[0014] The third delay can be assigned to a duration for which the storage system is configured to refrain from communicating a signal with the host system while performing the type of power transition operation.

[0015] The processing circuit can further be configured to perform the linking operation, causing the storage system to communicate a signal specifying operating parameters between the storage system and the host system. The processing circuit can also be configured to cause the storage system to receive the second delay value according to the communicated signal.

[0016] To perform the linking operation, the processing circuit can further be configured to cause the storage system to establish an initial connection between the storage system and the host system. The processing circuit can also be configured to cause the storage system to communicate signaling in response to the establishment of the initial connection.

[0017] The first delay can be greater than or equal to the second delay.

[0018] The third delay can be smaller than the first delay.

[0019] In one aspect, the present disclosure provides a non-transitory, computer-readable medium that stores code comprising instructions executable by one or more processors. The one or more processors can be configured according to the processing circuit described above.

[0020] The code, comprising instructions executable by one or more processors, is for performing a linking operation between a storage system and a host system, wherein, prior to the linking operation, the storage system is configured to perform a type of power transfer operation according to a first delay; receive a notification of a second delay associated with the host system performing the type of power transfer operation in association with the linking operation; and update the storage system in response to receiving the notification of the second delay associated with the host system to perform the type of power transfer operation according to a third delay greater than the second delay.

[0021] The instructions can further be executed by one or more processors to store an indication of the third delay in non-volatile memory of the storage system in response to the updating of the storage system to perform the type of power transition operation according to the third delay.

[0022] The instructions can further be executed by one or more processors to receive an instruction from the host system to perform a power transition operation of the type power transition operation; to initiate the third delay in response to the instruction to perform the power transition operation; and to transition the memory system from a first power mode to a second power mode in response to receiving the instruction to perform the power transition operation.

[0023] The second delay can occur in response to the command to perform the power transition operation.

[0024] The instructions can be executed by the processor to communicate a signaling from the memory system to the host system after the third delay has elapsed.

[0025] The instructions can also be executed by the processor to receive a signal from the host system after the second delay has elapsed.

[0026] The second delay can be assigned a duration for which the host system is configured to refrain from communicating a signaling message to the storage system while performing the type of power transition operation.

[0027] The third delay can be assigned to a duration for which the storage system is configured to refrain from communicating a signal with the host system while performing the type of power transition operation.

[0028] To perform the linking process, instructions can be executed by one or more processors to communicate a signal specifying operating parameters between the storage system and the host system. These instructions can also be executed by one or more processors to receive the second delay value as communicated in the signal.

[0029] To perform the linking process, instructions can be executed by one or more processors to establish an initial connection between the storage system and the host system. Instructions by one or more processors can also be executed to communicate the signaling in response to the establishment of the initial connection.

[0030] The first delay can be greater than or equal to the second delay.

[0031] The third delay can be smaller than the first delay.

[0032] In one aspect, the present disclosure provides a method for operating a storage system. The method comprises the steps of performing a linking operation between the storage system and a host system, wherein the storage system is configured prior to the linking operation to perform a type of power transfer operation according to a first delay; receiving an indication of a second delay associated with the host system performing the type of power transfer operation in association with the linking operation; and updating the storage system in response to receiving the indication of the second delay associated with the host system to perform the type of power transfer operation according to a third delay that is greater than the second delay.

[0033] The procedure may further include the step of storing an indication of the third delay in a non-volatile memory of the storage system in response to the updating of the storage system to perform the type of power transition operation according to the third delay.

[0034] The procedure may further include the step of receiving a command from the host system to perform a power transition operation of the type power transition operation; initiating the third delay in response to the command to perform the power transition operation; and transitioning the storage system from a first power mode to a second power mode in response to receiving the command to perform the power transition operation.

[0035] The second delay can occur in response to the command to perform the power transition operation.

[0036] The procedure may further include the step of communicating a signal from the storage system to the host system after the third delay has elapsed.

[0037] This allows a storage system and a host system to communicate to facilitate different types of power transition operations between different performance modes. For example, the storage system can be configured to perform a power transition operation (such as a sleep-to-wake operation) where the storage system moves from a sleep state (such as a low-power mode) to an active mode (such as a high-performance mode).

[0038] During the power transfer process, the storage system and the host system may be configured to become active at least partially simultaneously (e.g., capable of communication, configured to transmit signals), which may result in signaling occurring between the storage system and the host system for the same duration.

[0039] The storage system and the host system can be configured to communicate such signaling over one or more identical communication channels (e.g., interfaces, buses) between the storage system and the host system in such a way that signaling occurring for the same duration can cause collisions (e.g., crosstalk) and / or noise over these same communication channels. In some cases, the collision and / or noise can lead to reduced reliability and performance during communication between the storage system and the host system.

[0040] The storage system and the host system can each be configured to become active at least partially simultaneously, based on the fact that the storage system and the host system are programmed with similar power transition delays (e.g., tActivation times). For example, the storage system can be configured to refrain from signaling its power transition delay (e.g., tActivation of the storage system) during the power transition process, and the host system can be configured to refrain from signaling its power transition delay (e.g., tActivation of the host system). However, the power transition delays of the storage system and the power transition delay of the host system can be similar in duration, so the storage system and the host system can be configured to begin transmitting a signal during the same duration.

[0041] In some cases, the storage system power transition delay and the host system power transition delay can be programmed such that their values ​​differ sufficiently in duration to avoid collisions and / or noise, but this may cause unnecessary latency for performing access operations after the power transition.

[0042] As described in this document, the storage system's power transition delay can be dynamically configured based on the host system's power transition delay. For example, the storage system's power transition delay can initially be programmed to be relatively long (e.g., the duration of a maximum expected power transition delay of the host system).

[0043] In some such examples, during an initial linking operation (e.g., establishing a connection between the storage system and the host system), the host system can transmit an indication of the host system's power transition delay to the storage system. Based on this indication, the storage system can update its own power transition delay so that it is greater (e.g., incrementally greater) than the host system's power transition delay. After updating its power transition delay, the storage system can store this indication so that it can use the updated power transition delay during the power transition delay operation.

[0044] Implementing the dynamically configured power transfer delay can prevent collisions and / or noise over the same communication channels without causing unnecessary latency that would otherwise be associated with pre-programming the storage system's power transfer delay (e.g., by ensuring that its value differs sufficiently in duration to avoid collisions and / or noise).

[0045] In addition to the relevant memory system management described in this document, dynamic initialization delay management techniques for a memory system can be generally implemented to improve the performance of various electronic devices and systems (including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and games). Some applications on electronic devices, including high-performance applications such as AI, AR, VR, and games, may have relatively high processing demands to meet user expectations.Therefore, increasing the processing capabilities of electronic devices by reducing response times, improving power consumption, reducing complexity, increasing data throughput or access speeds, reducing communication times, or increasing storage capacity or density, among other performance indicators, can improve user experience or attractiveness.

[0046] Implementing the techniques described in this paper can improve the performance of electronic devices by preventing collisions and / or noise over shared communication channels between a storage system and a host system after a power transfer operation, which, among other benefits, can improve the reliability of the electronic devices.

[0047] In addition to their applicability in storage systems as described in this document, dynamic initialization delay management techniques for a storage system can be implemented more generally to support increased connectivity in electronic systems. With the growing use of systems that rely on interconnected electronic devices, the connectivity of these devices becomes an increasingly critical factor in system operation. For example, delays associated with signals communicated between devices can become increasingly significant as critical systems rely more heavily on connectivity, as a system uses a larger number of interconnected devices, or as the number and complexity of signals communicated between devices increase.Implementing the techniques described in this paper can support techniques for increased connectivity in electronic systems by preventing collisions and / or noise over shared communication channels between a storage system and a host system after a power transfer operation, which, among other benefits, can improve data transmission between devices. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates an example of a system that supports dynamic initialization delay management for a storage system according to the examples disclosed in this document. Fig. Figure 2 shows an example of a process flow timing diagram that supports dynamic initialization delay management for a storage system according to the examples disclosed in this paper. Fig. Figure 3 shows a block diagram of a memory system that supports dynamic initialization delay management for a memory system according to the examples disclosed in this paper. Fig. Figure 4 shows a flowchart illustrating one or more procedures that support dynamic initialization delay management for a storage system according to the examples disclosed in this document. DETAILED DESCRIPTION

[0048] Features of the disclosure are illustrated and described in connection with systems, devices, and circuits. Features of the disclosure are further illustrated and described in connection with process flow timing and a flowchart.

[0049] Fig. Figure 1 illustrates an example of a System 100 that supports dynamic initialization delay management for a storage system according to examples disclosed in this document. The System 100 includes a host system 105 coupled to a storage system 110. The System 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle, an Internet of Things (IoT)-enabled device, an embedded computer (e.g., one included in a vehicle, industrial plant, or networked commercial device), or any other computing device that includes a storage and processing device.

[0050] A Storage System 110 can be or include any device or collection of devices, wherein the device or collection of devices includes at least one storage array. For example, a Storage System 110 can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small-outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0051] System 100 may include a host system 105, which may be coupled to the storage system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described in this document. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the storage system 110 or a device within it. The processor chipset may include one or more cores, one or more caches (e.g., local memory or memory included in the host system 105), a memory controller (e.g., a memory chip), a memory controller, ...The system includes an NVDIMM controller, a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller), and a Serial Advanced Technology Attachment (SATA) controller. The host system 105 can use the storage system 110, for example, to write data to and read data from the storage system 110. Although in . Fig. Where a storage system 110 is shown, the host system 105 can be coupled to any number of storage systems 110.

[0052] The host system 105 can be connected to the storage system 110 via at least one physical host interface. In some cases, the host system 105 and the storage system 110 can be configured to communicate via a physical host interface using an associated protocol (e.g., to exchange control, address, data, and other signals between the storage system 110 and the host system 105, or to communicate otherwise). Examples of a physical host interface include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, and a DIMM interface (e.g., a 12V / 16D ...The interfaces may include a DIMM socket interface that supports DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in a Host Control Panel 106 of the Host System 105 and a Storage Control Panel 115 of the Storage System 110, or may be supported in some other way. In some examples, the Host System 105 may be coupled to the Storage System 110 (e.g., the Host Control Panel 106 may be coupled to the Storage Control Panel 115) via a corresponding physical host interface for each storage device 130 included in the Storage System 110, or via a corresponding physical host interface for each type of storage device 130 included in the Storage System 110.

[0053] The storage system 110 can include a storage control unit 115 and one or more storage devices 130. A storage device 130 can include one or more storage arrays of any type of memory cell (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in the example from Fig. Figure 1 shows two storage devices 130-a and 130-b. The storage system 110 can include any number of storage devices 130. Furthermore, if the storage system 110 includes more than one storage device 130, different storage devices 130 within the storage system 110 can contain the same or different types of memory cells.

[0054] The storage control unit 115 can be coupled to and communicate with the host system 105 (e.g., via the host's physical interface) and can be an example of a controller or control component configured to cause the storage system 110 to perform various operations according to the examples described in this document. The storage control unit 115 can also be coupled to and communicate with storage devices 130 to perform operations such as reading data, writing data, deleting data, or refreshing data in a storage device 130—among other such operations—which can be generally referred to as access operations. In some cases, the storage control unit 115 can receive commands from the host system 105 and communicate with one or more storage devices 130 to execute such commands (e.g.,in storage arrays within the one or more storage devices 130). For example, the storage control unit 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the storage devices 130. In some cases, the storage control unit 115 can exchange data with the host system 105 and with one or more storage devices 130 (e.g., in response to commands from the host system 105 or in association with them). For example, the storage control unit 115 can convert responses (e.g., data packets or other signals) associated with the storage devices 130 into corresponding signals for the host system 105.

[0055] The storage control unit 115 can be configured to perform other operations associated with the storage devices 130. For example, the storage control unit 115 can perform or manage operations such as wear compensation operations, garbage collection operations, error control operations such as error detection or error correction operations, encryption operations, caching operations, media management operations, background refresh operations, state monitoring, and address translations between logical addresses (e.g., logical block addresses - LBAs) assigned to commands from the host system 105 and physical addresses (e.g., physical block addresses) assigned to memory cells within the storage devices 130.

[0056] The Memory Control Unit 115 may include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations attributed to the Memory Control Unit 115 in this document. The Memory Control Unit 115 may be, or include, a microcontroller, a special logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit.

[0057] The memory control unit 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory capable of storing the operating code (e.g., executable instructions) that the memory control unit 115 can execute to perform functions assigned to it in this document. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that the memory control unit 115 may use for internal storage or calculations, such as those related to the functions assigned to it in this document. Additionally or alternatively, the local memory 120 may serve as a cache for the memory control unit 115.For example, data can be stored in local storage 120 if it is read from or written to a storage device 130, and the data can be available in local storage 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency compared to a storage device 130) according to a cache policy.

[0058] Although the example of storage system 110 serves as an illustration in Fig. Although a storage system 110 may include a storage control 115 as described in section 1, in some cases it may not include a storage control 115. For example, the storage system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, each of which may be located internally within the storage devices 130, to perform the functions attributed to the storage control 115 in this document. In general, one or more functions attributed to the storage control 115 in this document may, in some cases, instead be performed by the host system 105, a local controller 135, or any combination thereof. In some cases, a storage device 130 that is at least partially managed by a storage control 115 may be referred to as a managed storage device.An example of a managed storage device is a managed NAND (MNAND) device.

[0059] A storage device 130 can include one or more arrays of non-volatile memory cells. For example, a storage device 130 can include NAND memory (e.g., NAND flash), ROM, phase-change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric random-access memory (FeRAM), magneto-RAM (MRAM), NOR memory (e.g., NOR flash memory), spin-transfer-torque (STT) MRAM, conductive-bridging RAM (CBRAM), resistive random-access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, a storage device 130 can include one or more arrays of volatile memory cells.A storage device 130 can, for example, include RAM memory cells such as dynamic RAM memory cells (dynamic RAM - DRAM) and synchronous DRAM memory cells (synchronous DRAM - SDRAM).

[0060] In some examples, a storage device 130 (e.g., on the same chip, in the same package) may include a local controller 135 that can perform operations on one or more memory cells of that storage device 130. A local controller 135 may operate in conjunction with a memory system controller 115 or perform one or more functions that are assigned to the memory system controller 115 in this document. For example, as in Fig. Figure 1 illustrates that a storage device 130-a may include a local controller 135-a, and a storage device 130-b may include a local controller 135-b. A local controller 135 may be or include a microcontroller, a special logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit.

[0061] In some cases, a storage device 130 may be or include a NAND device (e.g., a NAND flash device). A storage device 130 may be or include a chip 160 (e.g., a memory chip). For example, in some cases, a storage device 130 may be a package containing one or more chips 160. A chip 160 may, in some examples, be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon chip cut from a silicon wafer). Each chip 160 may contain one or more layers 165, and each layer 165 may contain a corresponding set of blocks 170, with each block 170 containing a corresponding set of pages 175, and each page 175 containing a set of memory cells.

[0062] In some cases, a NAND flash memory device can contain 130 memory cells configured to store one bit of information each, which can be referred to as single-level cells (SLC). Additionally or alternatively, a NAND flash memory device can contain 130 memory cells configured to store multiple bits of information each, which are referred to as multi-level cells (MLC) if configured to store two bits of information each, tri-level cells (TLC) if configured to store three bits of information each, quad-level cells (QLC) if configured to store four bits of information each, or more generally, multi-level memory cells.Multi-level memory cells can provide higher storage density compared to SLC memory cells, but in some cases may result in narrower read or write spans or greater complexity in supporting circuitry.

[0063] In some cases, levels 165 can refer to groups of blocks 170, and in some cases, simultaneous operations can be performed on different levels 165. For example, simultaneous operations can be performed on memory cells within different blocks 170, as long as the different blocks 170 are located on different levels 165. In some cases, a single block 170 can be referred to as a physical block, and a virtual block 180 can refer to a group of blocks 170 in which simultaneous operations can take place. For example, simultaneous operations can be performed on blocks 170-a, 170-b, 170-c and 170-d, which are each located within levels 165-a, 165-b, 165-c, and 165-d, and blocks 170-a, 170-b, 170-c and 170-d can be collectively referred to as a virtual block 180.In some cases, a virtual block can contain blocks 170 from different memory devices 130 (e.g., including blocks in one or more levels of memory device 130-a and memory device 130-b). In some cases, the blocks 170 within a virtual block can have the same block address in their respective levels 165 (e.g., block 170-a can be "block 0" of level 165-a, block 170-b "block 0" of level 165-b, etc.). In some cases, the execution of concurrent operations in different levels 165 can be subject to one or more restrictions, such as the execution of concurrent operations on memory cells within different pages 175 that have the same page address in their respective levels 165 (e.g., with respect to instruction decoding, the circuitry for decoding the page address, or other circuitry shared across levels 165).

[0064] In some cases, a block can contain 170 memory cells, organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells on the same page 175 can share a common word line (e.g., be coupled to it), and memory cells on the same string can share a common digit line (e.g., be coupled to it) (which can alternatively be called a bit line).

[0065] In some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at a page level, or a section thereof), but erased at a second granularity level (e.g., at a block level). That is, a page can be the smallest unit of storage (e.g., a set of memory cells) that can be programmed or read independently (e.g., programmed or read simultaneously as part of a single program or read operation), and a block can be the smallest unit of storage (e.g., a set of memory cells) that can be erased independently (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data.For example, in some cases a page 175 that is in use can only be updated once the entire block 170, which contains page 175, has been deleted.

[0066] In some cases, a memory system 110 can utilize a memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry in combination with a local (e.g., on-chip or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0067] In some cases, the storage system 110 and the host system 105 can communicate to facilitate different types of power transition operations between different power modes. For example, the storage system 110 can be configured to perform a power transition operation (e.g., a sleep-to-wake operation) in which the storage system 110 transitions from a sleep state (e.g., a low-power mode) to an active mode (e.g., a high-performance mode). In some cases, the storage system 110 and the host system 105 can be configured to become active during the power transition operation in such a way that the storage system 110 and the host system 105 are able to communicate a signaling over one or more identical communication channels (e.g., interfaces, buses).In some cases, storage system 110 and host system 105 can each be configured to become active based on the fact that storage system 110 and host system 105 are programmed with power transition delays (e.g., tActivation times). For example, storage system 110 can be configured to refrain from signaling the storage system's power transition delay (e.g., tActivation of the storage system) during the power transition process, and host system 105 can be configured to refrain from signaling the host system's power transition delay (e.g., tActivation of the host system).

[0068] As described in the examples in this document, the storage system's power transition delay can be dynamically configured based on the host system's power transition delay. For example, the storage system's power transition delay can initially be programmed to be relatively long (e.g., the duration of a maximum expected power transition delay of the host system). In some such examples, during an initial linking operation (e.g., establishing a connection between storage system 110 and host system 105), host system 105 can transmit a specification of the host system's power transition delay to storage system 110. Storage system 110 can then update the storage system's power transition delay based on the specified host system power transition delay, making the storage system's power transition delay longer (e.g.,The dynamically configured power transition delay is incrementally larger than the host system's power transition delay. After updating the storage system's power transition delay, storage system 110 can store a value of the storage system's power transition delay such that it can use the updated power transition delay during the power transition delay operation. Implementing the dynamically configured power transition delay can prevent collisions and / or noise over the same communication channels without introducing unnecessary latency that would otherwise be associated with pre-programming the storage system's power transition delay (e.g., by ensuring its value is sufficiently different in duration to avoid collisions and / or noise).

[0069] System 100 can include any number of non-volatile, machine-readable media that support dynamic initialization delay management for a storage system. For example, the host system 105 (e.g., a host control panel 106), the storage system 110 (e.g., a storage control panel 115), or a storage device 130 (e.g., a local control panel 135), or any combination thereof, can include or otherwise access one or more non-transient, machine-readable media that store instructions (e.g., firmware, logic, code) for performing the functions attributed in this document to the host system 105, the storage system 110, or the storage device 130, or any combination thereof. For example, such instructions, when accessed by the host system 105 (e.g., by a host control panel 106), by the storage system 110 (e.g., by a local control panel 135), can be executed by the local control panel 130.by a storage control unit 115) or by a storage device 130 (e.g. by a local control unit 135), cause the host system 105, the storage system 110 or the storage device 130 to perform one or more associated functions as described in this document.

[0070] Fig. Figure 2 shows an example of a process flow timing diagram 200 that supports dynamic initialization delay management for a storage system according to examples disclosed in this document. The process flow timing diagram 200 can implement aspects of a system, or be implemented by a system, which can be an example of a system 100 as described with reference to Fig. 1 is described. For example, the process flow timing diagram 200 can illustrate operations of a host system and a storage system, which can be examples of a host system 105 and a storage system 110, respectively, as described with reference to Fig. 1 is described. The process flow timing diagram 200 illustrates the signaling capabilities of the host system and the storage system during various power transition operations.

[0071] Process Flow Timing Diagram 200 illustrates durations during which the host system and the storage system can be configured to transmit signaling to each other. That is, Process Flow Timing Diagram 200 illustrates a transmission capacity of the host system relative to time, such that the host system may be configured to transmit signaling to the storage system for some durations (e.g., signaling may be enabled), and during other durations, the host system may not be configured to transmit signaling to the storage system (e.g., signaling may be disabled). Likewise, Process Flow Timing Diagram 200 illustrates a transmission capacity of the storage system relative to time, such that the storage system may be configured to transmit signaling to the storage system for some durations (e.g., signaling may be disabled).The host system may have signaling enabled at certain times, and at other times it may not be configured to transmit signaling to the storage system (e.g., signaling may be disabled). For example, the host system's transmit capability may illustrate a transmit line (e.g., a transmit driver) of the host system, and the storage system's transmit capability may illustrate a transmit line (e.g., a transmit driver) of the storage system. Although not illustrated (e.g., for clarity), the host system may also be associated with a host system receive capability, which may indicate a receive line (e.g., a receiver) of the host system. Likewise, although not illustrated (e.g., for clarity), the storage system may also be associated with a storage system receive capability, which may indicate a receive line (e.g., a receiver).a receiver) of the storage system. In some examples, the host system and the storage system may be configured to communicate signaling over one or more shared communication channels, which may be examples of interfaces or buses between the host system and the storage system. In some such examples, signaling may be transmitted over the one or more shared communication channels if signaling is enabled for the host system and / or if signaling is enabled for the storage system.

[0072] The host system and the storage system can be configured to perform various power transition operations. For example, the storage system can be configured to perform different types of power transition operations. That is, the storage system can be configured to switch between different power modes based on signaling from the host system. For example, the storage system can be configured to perform a sleep operation (a type of power transition operation) in which the storage system transitions from an active mode to a sleep mode. In some such examples, the active mode might be a high-performance mode in which the storage system can be configured to transmit signaling (e.g., commands, information) to the host system, as well as perform internal storage operations (e.g., access operations, management operations).Conversely, hibernation can be a low-power mode in which the storage system may not be configured to communicate with the host system or perform internal storage operations. In some cases, the storage system may be configured to perform a hibernation exit operation (e.g., another type of power transition operation), in which the storage system transitions from a hibernation mode to an active mode. In some examples, the storage system may be configured to perform the power transition operations (e.g., hibernation operation, hibernation exit operation) based on commands received from the host system. For example, the storage system may perform the hibernation operation based on receiving a command (e.g.,the storage system can perform the hibernation process based on receiving a command (e.g., a hibernation termination command) from the host system, and the storage system can perform the hibernation termination process based on receiving a command (e.g., a hibernation termination command) from the host system.

[0073] In some cases, the storage system may be configured to transition from sleep to active during a sleep termination process over a duration associated with powering on various components of the storage system. In some such cases, the storage system and the host system may refrain from communicating any signaling during the transition period. In some examples, the transition period may be associated with power transition delays of the storage system and the host system. That is, the storage system and the host system may refrain from communicating signaling based on power transition delays, which could be examples of tActivation times.For example, during a power transition delay (e.g., a storage system activation time), which can generally correspond to the duration it takes for the storage system to transition from a sleep state to an active state, the storage system may refrain from transmitting a signal to the host system. Similarly, during a power transition delay (e.g., a host system activation time), which can generally correspond to the duration it takes for the storage system to transition from a sleep state to an active state, the host system may refrain from transmitting a signal to the storage system.

[0074] In some cases, the power transition delays can be at least partially preconfigured before the operation. That is, during a manufacturing phase of the system lifecycle, the storage system can be programmed with its power transition delay, and the host system can be programmed with its power transition delay (e.g., before an operational phase, before an initial linking operation between the storage system and the host system). In some such cases, the storage system's power transition delay can be stored as an entry in a register of the storage system, or as data in non-volatile memory or read-only memory of the storage system. Similarly, the host system's power transition delay can be stored in a register, non-volatile memory, read-only memory, or in the host system's firmware.In some cases, the storage system's power transition delay can be preconfigured to a relatively long duration. For example, the storage system's power transition delay can initially be configured to have a duration greater than or equal to the host system's power transition delay. This means that the power transition delay for each host system can vary depending on the host system manufacturer and can be preconfigured based on the manufacturer. Thus, the storage system's power transition delay can be greater than or equal to the largest expected power transition delay of the host system, based on the various known power transition delays of the host system.

[0075] The storage system's power transition delay can be dynamically configured after it has been preconfigured. For example, the storage system's power transition delay can be dynamically configured based on the host system's power transition delay. That is, the storage system's power transition delay can be dynamically configured to have a threshold duration greater than the host system's power transition delay (e.g., a threshold difference between the storage system's power transition delay and the host system's power transition delay). In some examples, the storage system's transition delay can be greater than the threshold duration in addition to the host system's power transition delay, and the storage system's transition delay can be reduced such that it meets the threshold duration.In other examples, the storage system's transition delay can be less than the threshold duration in addition to the host system's power transition delay, and the storage system's transition delay can be increased such that it meets the threshold duration. For example, if the storage system's power transition delay is 150 µs, the host system's power transition delay is 100 µs, and the threshold duration is 100 µs, the storage system's power transition delay can be dynamically configured (e.g., updated, increased) to 200 µs (e.g., because the storage system's power transition delay must meet the threshold duration in combination with the host system's power transition delay).However, if the storage system power transition delay is 200 µs, the host system power transition delay is 100 µs, and the threshold duration is 50 µs, the storage system power transition delay can be dynamically configured to 150 µs.

[0076] In some cases, the storage system can update its power transition delay as part of an initial linking operation. That is, the storage system and the host system can perform an initial linking operation (for example, after the storage system and host system have established a connection) to establish a link between the storage system and the host system. In some cases, the linking operation may involve communication signaling between the storage system and the host system to establish the connection and set operating parameters for both systems. In some such cases, the host system may transmit an indication of its power transition delay to the storage system during the linking operation (for example, as part of the signaling to establish the connection).The storage system can use the host system's power transition delay to dynamically configure its own power transition delay. After updating the power transition delay, the storage system can store a value of the power transition delay in a register, non-volatile memory, or read-only memory. After performing the initial linking operation and storing the power transition delay value, the storage system can use the power transition delay while performing the sleep / hibernation operation.

[0077] Process Flow Timing Diagram 200 illustrates how the host system and the storage system perform a sleep operation and a sleep exit operation after executing the initial linking operation (e.g., not shown). First, the storage system may be operating in an active mode before t1; that is, both the host system and the storage system may be operational (e.g., normal) and capable of transmission. This means that signaling may be enabled for both the host system and the storage system during this duration. At t1, the host system may transmit a sleep command to the storage system. Upon receiving the sleep command, the storage system may perform the sleep operation, transitioning from active mode to sleep mode. After entering sleep mode (e.g.,At least until t2, the storage system may be incapable of receiving data and signaling may be disabled. However, after the storage system enters a sleep state (e.g., at least until t2), it may remain capable of receiving data and signaling may be enabled. In some cases, the storage system may remain capable of receiving signals after t1.

[0078] Second, at t2, the host system can transmit a sleep-out command to the storage system. Upon receiving the sleep-out command, the storage system can perform the sleep-out operation, transitioning from sleep mode to active mode. During the sleep-out operation, the storage system can activate various components, initiate internal startup (e.g., boot) operations, increase power consumption, or any combination thereof. After receiving the sleep-out command, the storage system's power transition delay can be initiated, rendering the storage system unresponsive and disabling signaling for the duration of the delay. The storage system's power transition delay can occur between t2 and t4 of the process flow timing diagram.After the hibernation termination command is transmitted, the host system's power transition delay may begin, rendering the host system incapable of transmitting and potentially disabling signaling for the duration of this delay. The host system's power transition delay can occur between t2 and t3 of process flow timing diagram 200. In some cases, the host system and storage system may remain capable of receiving signals after t2.

[0079] Third, at t3, the host system's power transition delay may be complete. After the host system's power transition delay is complete, the host system may be transferable and signaling may be enabled. The host system may begin transmitting signaling to the storage system after the host system's power transition delay is complete. For example, the host system may begin transmitting access commands, such as read and write commands, to the storage system. However, at t3, the host system's power transition delay may not be complete. That is, because the storage system's power transition delay is dynamically configured to be greater than the host system's power transition delay, the storage system may remain transferable and signaling may be disabled.During the period between t3 and t4, the storage system may not be configured to transmit signals to the host system, but the host system may be configured to transmit signals to the storage system. In some cases, the sleep-wake process may be complete, but the storage system's power transition delay may remain. In some such cases, the storage system may be functionally active, but it may still choose not to transmit any signaling to the host system. In some cases, the storage system may remain capable of receiving signals after t3.

[0080] Finally, at t4, the storage system's power transition delay may be complete. After the storage system's power transition delay is complete, the storage system may be transponderable and signaling may be enabled. The storage system may begin transmitting a signal to the host system after the storage system's power transition delay is complete. For example, the storage system may begin transmitting access command responses, such as read command responses and write command responses, to the host system. After t4, both the storage system and the host system may be transponderable and configured to support the transmission of a signal over one or more shared communication channels.

[0081] As described in the examples in this document, the storage system can be configured to support dynamic configuration of the storage system's power transfer delay based on the host system's power transfer delay. Dynamically configuring the storage system's power transfer delay so that it is greater than the host system's power transfer delay can prevent the host system and the storage system from becoming transferable simultaneously, thus preventing collisions associated with concurrent signaling between the host system and the storage system.This means that by allowing the host system to become transmittable before the storage system, signaling between the host and storage systems can be communicated in stages, thus avoiding the noise that would otherwise be associated with simultaneously transmitting signaling over one or more shared communication channels. Consequently, the storage system can support reduced collisions and noise without increasing the latency of access operations that would otherwise be associated with pre-configuring the power transmission delay without dynamic configuration support.

[0082] Fig. Figure 3 shows a block diagram 300 of a memory system 320 that supports dynamic initialization delay management for a memory system according to the examples disclosed in this document. The memory system 320 can be an example of aspects of a memory system as described with reference to Fig. 1 to Fig. 2 described. The memory system 320, or various components thereof, can be an example of means for performing various aspects of dynamic initialization delay management for a memory system, as described in this document. The memory system 320 can, for example, include a linking component 325, a communication component 330, an update component 335, a memory component 340, a delay component 345, a power transition component 350, or any combination thereof. Each of these components, or components of subcomponents thereof (e.g., one or more processors, one or more memories), can communicate directly or indirectly with each other (e.g., via one or more buses).

[0083] The linking component 325 can be configured as a means of performing a linking operation between the storage system and a host system, or otherwise support this operation, wherein the storage system is configured, prior to the linking operation, to perform some type of power transfer operation according to a first delay. The communication component 330 can be configured as a means of receiving a specification of a second delay associated with the host system performing the type of power transfer operation, in association with the linking operation, or otherwise support this operation.The update component 335 can be configured as a means of updating the storage system in response to receiving the specification of the second delay associated with the host system, or otherwise assist in performing the type of performance transition operation according to a third delay that is greater than the second delay.

[0084] In some examples, the update component 340 may be configured as a means of storing an indication of the third delay in non-volatile memory of the storage system in response to a storage system update, or otherwise assisting it to perform the type of performance transition operation according to the third delay.

[0085] In some examples, the communication component 330 may be configured to receive a command from the host system to perform a performance transition operation, or otherwise support this. In some examples, the delay component 345 may be configured to initiate the third delay in response to the command to perform the performance transition operation, or otherwise support this. In some examples, the performance transition component 350 may be configured to transition the storage system from a first performance mode to a second performance mode in response to receiving the command to perform the performance transition operation, or otherwise support this.

[0086] In some examples, the second delay occurs in response to the command to perform the power transition operation.

[0087] In some examples, the communication component 330 may be configured as a means of communicating a signaling from the storage system to the host system after the third delay has elapsed, or may otherwise support this.

[0088] In some examples, a signal from the host system is received by the storage system after the second delay has elapsed.

[0089] In some examples, the second delay is associated with a duration for which the host system refrains from communicating signaling to the storage system while performing the type of power transition operation, and the third delay is associated with a duration for which the storage system refrains from communicating signaling to the host system while performing the type of power transition operation.

[0090] In some examples, to assist in performing the linking operation, the communication component 330 may be configured as a means of communicating signals specifying operating parameters between the storage system and the host system, or may otherwise assist in this, receiving the specification of the second delay according to the communication of the signaling.

[0091] In some examples, the linking component 325 may be configured to assist in performing the linking operation by serving as a means of establishing an initial connection between the storage system and the host system, or by otherwise assisting in this process, with communication of signaling occurring in response to the establishment of the initial connection.

[0092] In some examples, the first delay is greater than or equal to the second delay. In some examples, the third delay is less than the first delay.

[0093] In some examples, the described functionality of the Memory System 320 or various components thereof can be supported by at least one processor or relate to at least one section thereof, wherein such at least one processor can include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more such elements). In some examples, the described functionality of the Memory System 320 or various components thereof can be implemented at least partially by instructions (e.g., stored in memory or a non-transitory computer-readable medium) that are executable by such at least one processor.

[0094] Fig. Figure 4 shows a flowchart illustrating a Method 400 that supports dynamic initialization delay management for a memory system according to examples disclosed in this document. The operations of Method 400 can be implemented by a memory system or its components as described in this document. For example, the operations of Method 400 can be performed by a memory system as described with reference to Fig. 1, Fig. 2 to Fig. Section 3 describes this. In some examples, a memory system can execute a set of instructions to control the functional elements of the device in order to perform the described functions. Additionally or alternatively, the memory system can perform aspects of the described functions using special hardware.

[0095] In the case of a 405 operation, the procedure may involve performing a link operation between the storage system and a host system, with the storage system being configured prior to the link operation to perform some kind of performance transition operation according to an initial delay. In some examples, aspects of the 405 operations can be performed by a 325 link component, as referenced in Fig. 3 described.

[0096] In case 410, the procedure may involve receiving a specification of a second delay associated with the host system performing the type of power transfer operation, in association with the linking operation. In some examples, aspects of the operations of 410 may be performed by a communication component 330, as referenced in Fig. 3 described.

[0097] In procedure 415, the process may involve updating the storage system in response to receiving the specification of the second delay associated with the host system, in order to perform the type of performance transition operation according to a third delay that is greater than the second delay. In some examples, aspects of the operations of 415 may be performed by an update component 335, as referenced in Fig. 3 described.

[0098] In some examples, a device described in this document can perform one or more procedures, such as Procedure 400. The device may include features, circuits, logic, means, or instructions (e.g., a non-transitory, computer-readable medium that stores instructions executable by a processor), or any combination thereof, for performing the following aspects of the present disclosure:

[0099] Aspect 1: A method, device, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for performing a linking operation between the storage system and a host system, wherein, prior to the linking operation, the storage system is configured to perform a type of power transfer operation according to a first delay; receive a specification of a second delay associated with the host system performing the type of power transfer operation in association with the linking operation; and update the storage system in response to receiving the specification of the second delay associated with the host system to perform the type of power transfer operation according to a third delay greater than the second delay.

[0100] Aspect 2: Method, device or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuits, logic, means or instructions or any combination thereof for storing an indication of the third delay in non-volatile memory of the storage system in response to an update of the storage system to perform the type of power transition operation according to the third delay.

[0101] Aspect 3: Method, device or non-transitory computer-readable medium according to any of Aspects 1 to 2, further comprising operations, features, circuits, logic, means or instructions or any combination thereof for receiving a command from the host system to perform a power transition operation of the type power transition operation; initiating the third delay in response to the command to perform the power transition operation; and transitioning the storage system from a first power mode to a second power mode in response to receiving the command to perform the power transition operation.

[0102] Aspect 4: Procedure, device or non-transitory computer-readable medium according to Aspect 3, wherein the second delay occurs in response to the command to perform the power transition operation.

[0103] Aspect 5: Method, device or non-transitory computer-readable medium according to any of Aspects 3 to 4, further comprising operations, features, circuits, logic, means or instructions or any combination thereof for communicating a signaling through the storage system to the host system after the third delay has elapsed.

[0104] Aspect 6: Method, device or non-transitory computer-readable medium according to Aspect 5, wherein a signaling from the host system is received by the storage system after the second delay has elapsed.

[0105] Aspect 7: Method, device or non-transitory computer-readable medium according to any of Aspects 1 to 6, wherein the second delay is associated with a duration for which the host system refrains from communicating a signaling to the storage system while performing the type of power transition operation, and wherein the third delay is associated with a duration for which the storage system refrains from communicating a signaling to the host system while performing the type of power transition operation.

[0106] Aspect 8: Method, device or non-transitory computer-readable medium according to any of aspects 1 to 7, wherein operations, features, circuits, logic, means or instructions or any combination thereof for performing the linking operation, operations, features, circuits, logic, means or instructions or any combination thereof for communicating a signal specifying operating parameters between the storage system and the host system, wherein the receiving of the specification of the second delay is carried out according to the communication of the signal.

[0107] Aspect 9: Method, device or non-transitory computer-readable medium according to Aspect 8, wherein operations, features, circuits, logic, means or instructions or any combination thereof for performing the linking operation include operations, features, circuits, logic, means or instructions or any combination thereof for establishing an initial connection between the storage system and the host system, wherein the communication of signaling occurs in response to the establishment of the initial connection.

[0108] Aspect 10: Method, device or non-transitory computer-readable medium according to any of aspects 1 to 9, wherein the first delay is greater than or equal to the second delay and the third delay is less than the first delay.

[0109] It should be noted that the described techniques include possible implementations and that the processes and steps can be rearranged or otherwise modified, and that other implementations are possible. Furthermore, sections of two or more of the procedures can be combined.

[0110] The information and signals described in this document can be represented using a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips referenced in the description above can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate signals as a single signal; however, the signal may represent a bus of signals, with the bus having a variety of bit widths.

[0111] The terms "electronic communication," "conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between them. Components are considered to be electronically communicating with each other (or in conductive contact, connected, or coupled) if there is a conductive path between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact, connected, or coupled) can be an open or a closed circuit, depending on the operation of the device that includes the connected components.The conductive path between the connected components can be a direct conductive path between the components themselves, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be temporarily interrupted, for example, by using one or more intermediate components such as switches or transistors.

[0112] The term "coupling" (e.g., "electrical coupling") can refer to a state in which there is a transition from an open circuit between components, where signals cannot currently be transmitted via a conductive path between the components, to a closed circuit between components, where signals can be transmitted via the conductive path between the components. If a component, such as a controller, couples other components, the component initiates a change that allows signals to flow between the other components via a conductive path that previously did not permit signal flow.

[0113] The term "isolated" refers to a relationship between components in which no signals can currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch located between them are isolated when the switch is open. If a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using a conductive path that previously allowed signal flow.

[0114] The terms "if", "when", "based on", or "at least partially based on" can be used interchangeably. In some examples, if the terms "if", "when", "based on", or "at least partially based on" are used to describe a conditional action, a conditional process, or a connection between sections of a process, the terms can be used interchangeably.

[0115] The term "in response to" can refer to a condition or action occurring at least partially, if not entirely, as a consequence of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a consequence of the occurrence of the preceding condition or action (either directly after or following one or more other intermediate conditions or actions that occur after the first condition or action).

[0116] Furthermore, the terms "directly in response to" or "in direct response to" can refer to a condition or action that occurs as a direct consequence of a previous condition or action. In some examples, a first condition or action may be performed, and a second condition or action may occur directly as a consequence of the occurrence of the previous condition or action, regardless of whether other conditions or actions occur.In some examples, a first condition or action may be performed, and a second condition or action may occur directly as a consequence of the occurrence of the previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Any condition or action described in this writing as being performed "based on," "at least partly based on," or "in response to" another step, action, event, or condition may be additionally or alternatively (e.g.,(in an alternative example) “as a direct response to” or “directly in response to” such other condition or action, unless otherwise specified.

[0117] The devices discussed in this paper, including a storage array, can be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate or parts thereof can be controlled by doping using various chemicals, including, but not limited to, phosphorus, boron, or arsenic.Doping can be carried out during the initial formation or growth of the substrate by ion implantation or by any other doping agent.

[0118] A switching component or transistor discussed in this paper may be a field-effect transistor (FET) and comprise a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic elements by conductive materials, such as metals. The source and drain may be conductive and may comprise a heavily doped, such as degenerate, semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., most charge carriers are holes), the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate.For example, applying a positive or negative voltage to an n-type or p-type FET can cause the channel to conduct. A transistor can be "on" or "enabled" if a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor can be "off" or "disabled" if a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0119] The description contained in this document, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that can be implemented or that fall within the scope of the claims. The term "exemplary" as used in this document means "serving as an example, case, or illustration" and not "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can also be practiced without this detailed information. In some cases, known structures and devices are represented in the form of a block diagram to avoid obscuring the concepts of the described examples.

[0120] In the accompanying figures, similar components or features may share the same reference designation. Furthermore, different components of the same type can be distinguished by following the reference designation with a hyphen and a second designation that differentiates the similar components. If only the first reference designation is used in the description, the description applies to each of the similar components with the same first reference designation, regardless of the second reference designation.

[0121] The functions described in this document can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuits, processing circuits, logic circuits), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored on a computer-readable medium or transferred to it as one or more instructions (e.g., code). Due to the nature of software, the functions described in this document can be implemented using software executed by a processing system, hardware, firmware, hardwiring, or any combination thereof.Features that implement functions can be physically located in different positions, including a distribution such that sections of functions are implemented in different physical locations.

[0122] Illustrative blocks and modules that can be described in this document can be implemented or carried out using a processor, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, another programmable logic device, or any combination thereof, to perform the functions described in this document. A processor can be, for example, a microprocessor, a controller, a microcontroller, a state machine, or other types of processors. A processor can also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0123] As used in this document, including in the claims, "or" in a list of elements (e.g., in a list of elements preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or CA, or B or C, or AB or AC, or BC or ABC (i.e., A and B and C) means A and B and C. The expression "based on" as used in this document is not to be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without going beyond the scope of the present disclosure. In other words, as used in this document, the expression "based on" is to be interpreted in the same way as the expression "at least partly based on"

[0124] As used in this document, including in the claims, the article "a" before a noun is open and is to be understood as referring to "at least one" of these nouns or "one or more" of these nouns. The terms "a," "at least one," "one or more," and "at least one of one or more" can thus be used interchangeably. For example, if a claim refers to "a component" that performs one or more functions, each of the individual functions can be performed by a single component or by any combination of several components. Thus, the term "a component" that has features or performs functions can refer to "at least one of one or more components" that has a specific feature or performs a specific function.Subsequent references to a component introduced by the article "a" or "a" using the pronouns "the" or "a" can refer to one or all of the components. For example, a component introduced by the article "a" or "a" can be understood as "one or more components," and the subsequent reference to "the component" in the claims can be understood as equivalent to a reference to "at least one of the one or more components." Similarly, subsequent references to a component introduced by the article "one or more components" using the pronouns "the" or "a" can refer to one or all of the components. For example, the subsequent reference to "the one or the several components" in the claims can be understood as equivalent to a reference to "at least one of the one or the several components."

[0125] Computer-readable media include both non-transitory computer storage media and communication media, including all media that facilitate the transfer of a computer program from one location to another. A non-transitory storage medium can be any available medium that a computer can access.As an example, and not limited to, non-transitory computer-readable media may include: RAM, ROM, electrically erasable programmable read-only memory (EEPROM), other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory medium or combination of media that can be used to carry or store desired program code resources in the form of instructions or data structures and that can be accessed by a computer or one or more processors. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 19 / 277,095

[0001] US 63 / 683,085

[0001] Cited non-patent literature

[0000] Wu et al. entitled “DYNAMIC INITIALIZATION DELAY MANAGEMENT FOR A MEMORY SYSTEM”, which was issued on July 22, 2025

[0001] Wu et al. entitled “DYNAMIC INITIALIZATION DELAY MANAGEMENT FOR A MEMORY SYSTEM”, which was issued on August 14, 2024

[0001]

Claims

[1] A storage system (110), comprising: one or more storage devices (130-a, 130-b); and a processing circuit coupled to the one or more storage devices (130-a, 130-b) and configured to cause the storage system (110) to do the following: Performing (405) a linking operation between the storage system (110) and a host system (105), wherein the storage system (110) is configured prior to the linking operation to perform some type of power transfer operation according to an initial delay; Receiving (410) a specification of a second delay associated with the host system (105) performing the type of power transfer operation, in association with the linking operation; and Updating (415) the storage system (110) in response to receiving the indication of the second delay assigned to the host system (105) to perform the type of performance transition operation according to a third delay which is greater than the second delay. [2] The storage system (110) according to claim 1, wherein the processing circuit is further configured to cause the storage system (110) to: Storing an indication of the third delay in a non-volatile memory of the storage system (110) in response to the updating of the storage system (110) to perform the type of power transition operation according to the third delay. [3] The storage system (110) according to claim 1 or 2, wherein the processing circuit is further configured to cause the storage system (110) to: Receiving a command from the host system (105) to perform a power transition operation of the type Power Transition Operation; Initiating the third delay in response to the command to perform the power transition operation; and Transition of the storage system (110) from a first power mode to a second power mode in response to receiving the instruction to perform the power transition operation. [4] The storage system (110) according to claim 3, wherein the second delay occurs in response to the instruction to perform the power transfer operation. [5] The storage system (110) according to any of the preceding claims, wherein the processing circuit is further configured to cause the storage system (110) to: Communicating a signal from the storage system (110) to the host system (105) after the third delay has elapsed. [6] The storage system (110) according to claim 5, wherein the storage system (110) is configured to receive a signaling from the host system (105) after the second delay has elapsed. [7] The storage system (110) according to any one of the preceding claims, wherein: the second delay is assigned a duration for which the host system (105) is configured to refrain from communicating a signaling signal with the storage system (110) while performing the type of power transition operation; and the third delay is assigned a duration for which the storage system (110) is configured to refrain from communicating a signaling to the host system (105) while performing the type of power transition operation. [8] The storage system (110) according to any of the preceding claims, wherein the processing circuit is further configured to perform the linking operation, causing the storage system (110) to: Communicating a signaling that specifies operating parameters between the storage system (110) and the host system (105), wherein the processing circuit is configured to cause the storage system (110) to receive the specification of the second delay according to the communication of the signaling. [9] The storage system (110) according to claim 8, wherein the processing circuit is further configured to perform the linking operation, causing the storage system (110) to: Establishing an initial connection between the storage system (110) and the host system (105), wherein the processing circuit is configured to cause the storage system (110) to communicate signaling in response to the establishment of the initial connection. [10] The storage system according to any one of the preceding claims, wherein: the first delay is greater than or equal to the second delay and the third delay is smaller than the first delay. [11] A non-transitory computer-readable medium that stores a code, wherein the code comprises instructions executable by one or more processing circuits of one of the preceding claims processors. [12] A method for operating a storage system (110) wherein the method comprises the following steps: Performing (405) a linking operation between the storage system (110) and a host system (105), wherein the storage system (110) is configured prior to the linking operation to perform some type of power transfer operation according to an initial delay; Receiving (410) a specification of a second delay associated with the host system (105) performing the type of power transfer operation, in association with the linking operation; and Updating (415) the storage system (110) in response to receiving the indication of the second delay assigned to the host system (105) to perform the type of performance transition operation according to a third delay which is greater than the second delay. [13] The method according to claim 12, further comprising: Storing an indication of the third delay in a non-volatile memory of the storage system (110) in response to the updating of the storage system (110) to perform the type of power transition operation according to the third delay. [14] The method of claim 12, further comprising: Receiving a command from the host system (105) to perform a power transition operation of the type Power Transition Operation; Initiating the third delay in response to the command to perform the power transition operation; and Transition of the storage system (110) from a first power mode to a second power mode in response to receiving the instruction to perform the power transition operation. [15] The method according to claim 14, wherein the second delay occurs in response to the command to perform the power transfer operation. [16] The method of claim 14, further comprising: Communicating a signal from the storage system (110) to the host system (105) after the third delay has elapsed.

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