NANO WIRE STACK FUSES IN THE FRONT-END-OF-LINE PHASE OF MANUFACTURING

Abstract

FEOL (Front End of Line) nanowire stack fuses are described. In one example, an integrated circuit structure comprises a fin containing a stack of alternating nanowire layers and interlayers, with a gap provided between the upper two nanowire layers by the absence of an interlayer between them. A gate stack is located above the fin, the gate stack containing a gate electrode metal along the sides of the fin and in the gap.

Description

BACKGROUND

[0001] In recent decades, the scaling of features in integrated circuits has been a driving force behind the ever-expanding semiconductor industry. Scaling down to ever smaller features enables higher densities of functional units on the limited usable area of ​​semiconductor chips. For example, shrinking transistor size allows for the integration of a greater number of memory or logic devices on a single chip, thus enabling the production of products with higher capacities. However, the trend toward ever-increasing capacities also presents challenges. The need to optimize the performance of each device is becoming increasingly critical.

[0002] Due to the variability of conventional and currently known manufacturing processes, the possibility of extending them to the 10-nanometer node range or nodes below 10 nanometers may be limited. Consequently, manufacturing the functional components required for future technology nodes may necessitate the introduction of new methodologies or the integration of new technologies into, or replacement of, current manufacturing processes.

[0003] With the reduction in the dimensions of these fundamental building blocks of microelectronic circuit assemblies and the increase in the sheer number of basic building blocks fabricated in a given area, the limitations on the lithographic processes used to structure these building blocks have become overwhelming. In particular, there can be a trade-off between the smallest dimension of a feature structured in a semiconductor stack (the critical dimension) and the spacing between such features. Furthermore, the limitations on incorporating passive features beneath active components have increased. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates cross-sectional views depicting two conventional locking devices. Fig. Figure 2 illustrates a cross-sectional view of a safety structure according to an embodiment of the present disclosure. Fig. Figures 3A-3D illustrate top and cross-sectional views depicting various processes in a method for manufacturing a fuse structure integrated with a nanowire-based transistor according to an embodiment of the present disclosure. Fig. Figures 4A-4J illustrate cross-sectional views of various processes in a method for manufacturing an integrated gate all-around circuit structure according to an embodiment of the present disclosure. Fig. Figure 5 illustrates a cross-sectional view of a non-planar integrated circuit structure along a gate line according to an embodiment of the present disclosure. Fig. Figure 6 is a diagram of a grid-division quartering approach used to produce trenches for intermediate connection structures according to an embodiment of the present disclosure. Fig. Figure 7A illustrates a cross-sectional view of a metallization layer produced using a grid-dimensioned quartering scheme, according to an embodiment of the present disclosure. Fig. Figure 7B illustrates a cross-sectional view of a metallization layer produced using a grid-dimensioning scheme above a metallization layer produced using a grid-dimensioning scheme, according to an embodiment of the present disclosure. Fig. Figure 8A illustrates a cross-sectional view of an integrated circuit structure comprising a metallization layer with one metal conductor composition above a metallization layer with a different metal conductor composition, according to an embodiment of the present disclosure. Fig. Figure 8B illustrates a cross-sectional view of an integrated circuit structure comprising a metallization layer with a metal conductor composition coupled to a metallization layer with a different metal conductor composition, according to an embodiment of the present disclosure. Fig. Figures 9A to 9C illustrate cross-sectional views of individual intermediate connecting lines having different lining and conductive cover structure arrangements, according to an embodiment of the present disclosure. Fig. Figure 10 illustrates a cross-sectional view of an integrated circuit structure comprising four metallization layers with a metal conductor composition and a grid dimension above two metallization layers with a different metal conductor composition and a smaller grid dimension, according to an embodiment of the present disclosure. Fig. Figure 11 illustrates a cross-sectional view of a stack of metallization layers having a conductive conduit plug on a lower metal conduit, according to an embodiment of the present disclosure. Fig. 12 illustrates a computing device according to an implementation of the disclosure. Fig. Figure 13 illustrates an interposer that includes one or more embodiments of the disclosure. Fig. Figure 14 is an isometric view of a mobile computing platform utilizing an IC manufactured according to one or more processes described herein or comprising one or more features described herein, according to an embodiment of the present disclosure. Fig. Figure 15 illustrates a cross-sectional view of a chip mounted in flip-chip assembly according to an embodiment of the present disclosure. DESCRIPTION OF THE EXECUTION FORMS

[0004] An advanced fabrication process for an integrated circuit structure is described. Numerous specific details, such as specific integration and material conditions, are set forth in the following description to provide a comprehensive understanding of embodiments of the present disclosure. It is understood by a person skilled in the art that embodiments of the present disclosure can also be implemented in practice without these specific details. In other cases, known features, such as the layout of integrated circuits, are not described in detail in order to avoid unnecessarily complicating the embodiments of the present disclosure. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0005] The following detailed description is purely illustrative and is not to be understood as limiting the embodiments of the subject matter of the invention or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, case, or illustration." Any implementation described herein as exemplary is not necessarily to be considered preferred or advantageous over other implementations. Furthermore, there is no intention, either express or implied, to be bound by any theories set forth in the preceding technical field, background, summary, or the following detailed description.

[0006] This description includes references to "an embodiment." The occurrences of the phrase "in an embodiment" do not necessarily refer to the same embodiment. Particular features, structures, or properties may be combined in a suitable manner compatible with this disclosure.

[0007] Terminology. The following paragraphs provide definitions or context for terms in this disclosure (including the attached claims):

[0008] "Comprehensive." This term is to be understood in its broadest sense. As used in the attached claims, this term does not exclude any additional structures or operations.

[0009] "Designed to do so." It may be described or claimed that various units or components are "designed to do" a task or tasks. In such contexts, "designed to do so" is used to suggest a structure by stating that the units or components have a structure that performs that task or tasks during operation. Therefore, it may be said that the unit or component is designed to do the task even if the stated unit or component is not currently functioning (for example, not turned on or active). The statement that a unit, circuit, or component is "designed to do" one or more tasks is expressly not intended to fall under 35 USC §112, sixth paragraph, for that unit or component.

[0010] “First”, “second”, etc. As used herein, these terms are used as labels for the nouns they precede, and they do not imply any order (e.g., spatial, temporal, logical, etc.).

[0011] "Coupled" - The following description refers to elements, nodes, or features that are "coupled" to one another. As used herein, unless expressly stated otherwise, "coupled" means that an element, node, or feature is directly or indirectly connected to (or communicates with) another element, node, or feature, and not necessarily mechanically.

[0012] Furthermore, certain terminology in the following description may be used for reference purposes only and should therefore not be considered restrictive. For example, terms such as "top," "bottom," "above," and "below" refer to directions in the referenced drawings. Terms such as "front," "back," "rear," "side," "outside," and "inside" describe the orientation or location, or both, of sections of the component within a consistent but arbitrary frame of reference, clarified by reference to the text and related drawings describing the component under discussion. Such terminology may include the words expressly mentioned above, derivatives thereof, and words of similar meaning.

[0013] "Inhibition" – As used here, inhibition is used to describe a reduction or minimization effect. When a component or feature is described as inhibiting an action, movement, or condition, this can completely prevent the result, outcome, or future state. Additionally, "inhibition" can also refer to a reduction or decrease of the result, performance, or effect that might otherwise occur. Therefore, when it is stated that a component, element, or feature inhibits a result or state, the result or state need not be completely prevented or eliminated.

[0014] The embodiments described here can relate to front-end-of-line semiconductor processing and structuring (FEOL semiconductor processing and structuring). FEOL is the first stage of integrated circuit (IC) manufacturing, in which the individual devices (e.g., transistors, capacitors, resistors, etc.) are structured within the semiconductor substrate or semiconductor layer. FEOL generally covers everything up to (but not including) the deposition of metallic interconnect layers. Following the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0015] The embodiments described here can relate to back-end-of-line semiconductor processing and structures (BEOL semiconductor processing and structures). BEOL is the second stage of IC manufacturing, in which the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, such as the metallization layer(s). BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-to-package connections. In the BEOL stage of the manufacturing process, contacts (pads), interconnects, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers can be added in the BEOL.

[0016] The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both. Even if an exemplary processing scheme is illustrated using an FEOL processing scenario, these approaches can also be applied to BEOL processing. Likewise, even if an exemplary processing scheme is illustrated using a BEOL processing scenario, these approaches can be equally applicable to FEOL processing.

[0017] It is understood that FEOL is a technology driver for a given process. In another embodiment, FEOL considerations are driven by requirements for BEOL processing in the 10-nanometer range or below. For example, material selection and layouts for FEOL layers and devices may require consideration of BEOL processing. In such an embodiment, material selection and gate-stack architectures are chosen to support high-density metallization of the BEOL layers, for example, to reduce edge capacitance in transistor structures formed in the FEOL layers but coupled to each other by high-density metallization of the BEOL layers.

[0018] One or more embodiments described herein relate to gate-all-around-based devices or circuits that incorporate an embedded nanowire fuse for low-program-current applications. Unless otherwise specified, reference to nanowires may refer to nanowires, nanoribbons, or nanoplates.

[0019] For context: Fuses are used as overcurrent protection for sensitive circuits and to disable transistors by isolating them from their neighbors, thus reprogramming them. There are two types of fuses to consider. The first type is a heat dissipation fuse. The principle is that a sufficiently high current is passed through the fuse, which is made of a conductive material. Since conductors in integrated circuit structures typically have a finite resistance, the resulting heat dissipation is proportional to the square of the current. At a sufficiently high current, the conductive material (e.g., metal) melts and ceases to conduct, causing the fuse to "blow."One limitation is that with aggressive scaling of CMOS technology, lower program currents for fuses may be desirable. This may require a relatively higher fuse resistance, which can primarily be achieved by scaling the cross-sectional area to ensure control. Such scaling is determined by defining the width of metal traces (e.g., using lithography), which can be a very expensive technique.

[0020] A second type of fuse is one based on electromigration. When different metals are stacked on top of each other, the resulting lattice can be uneven and susceptible to damage from impulse transfer between conductive electrons and metal ions. One limitation is that electromigration contributes to device safety. Accordingly, modern CMOS metal interconnects are designed to mitigate this effect. This may require higher program currents for programming the fuses. The program is proportional to the overlap area, which can again be problematic in lithography, with concerns about critical dimensions and registration potentially contributing to the unevenness.

[0021] For further context: A fuse is a sacrificial device used to provide overcurrent protection. When an excessively high current is applied, the fuse switches from conducting to open. For certain circuits that are sensitive to current surges, fuses with a low programming current may be advantageous.

[0022] Previous approaches involved implementing the locking function using the back-end metal properties. An example illustrates this. Fig. 1 Cross-sectional views depicting two conventional fuse devices. Since a sufficiently high current flows through a thin metal conductor, the metal conductor can melt and create an open circuit, as shown in part (a): A structure 100 comprises a metal 104 in a dielectric 102, with current along the arrow providing a melting region 106. To achieve a low programming current, the cross-section of the fuse device must be small compared to the conductor tracks. Another approach involves using the property of electromigration observed between two different metal materials, as shown in part (b): A structure 150 comprises a metal conductor 154, a via 156, and a metal conductor 158 in a dielectric 152, with current along the arrow providing an electromigration region 162.When two or more conductive metal stacks are stacked on top of each other, momentum transfer between the conducting electrons and the metal ions can be significant due to the non-uniform lattice structure of the metal ions at the interface. Above a certain current level, atoms move and create vacancies near the interface, thus interrupting the current flow. In this diagram, the overlap region between metals and the electromigration property of the metals are determined by the programming current.

[0023] According to one embodiment of the present disclosure, a narrow Si-Si nanowire or nanotape space and thin metal gate conductors between Si nanowires or nanotapes are used in the manufacture of fuses for a low programming current. In one embodiment, the two terminals of the fuse can be separated by etching and cutting the metal gates without the use of an additional masking layer.

[0024] In one embodiment, the fuse described herein is an auxiliary device. Due to the small cross-sectional area between the silicon ribbons in this embodiment, this metal fuse can achieve a low programming current. The fuse design can be fully integrated into a nanowire process without requiring an additional mask.

[0025] In one embodiment, a fuse is designed using gate metal as the fuse material. The two terminals are separated by the metal-gate cut (MGC) and the MGC dielectric. The fuse thickness is defined by the Si-Si nanoband space, which is shared with the nanowire or nanoband FET transistors.

[0026] Fig. Figure 2 illustrates, for example, a cross-sectional view of a safety structure according to an embodiment of the present disclosure.

[0027] With reference to Fig. 2 A fuse structure 200 comprises a stack of alternating nanowires 210 and interlayers 208, such as silicon nanowires and silicon germanium interlayers, over a substrate 202 and adjacent to a trench insulation structure 206. A dielectric cap 212, for example a silicon nitride cap, is located on the stack of alternating nanowires 210 and interlayers 208. A dielectric metal gate cut plug 214 is located on or embedded in the dielectric cap 212 and separates (or cuts) a metal gate material stack to provide an anode 216 and a cathode 218 of the fuse structure 200. A fuse 220 is provided by a section of the metal gate material stack located at the point where one of the interlayers 208 has been removed.In contrast to a nanowire or nanoribbon-based transistor, the fuse structure holds 200 lower interlayers 208. It is understood that in a used (blown) fuse, the section of metal gate material vertically between the nanowires at the location of the removed interlayer is or comprises a melting area.

[0028] In one embodiment, a silicon substrate is structured and etched prior to the deposition of nanowire stacks to ensure contrast for subsequent layers during lithography. By adjusting the aperture size and etch depth for the protective layer, a local structure can be created in which the nanowire stack effectively shifts downwards compared to the unetched area. Since nitride material is deposited on top of the nanowire stack for fin structuring, the recessed area has a thicker nitride layer than the protective layer due to the narrowing during conformal deposition.

[0029] According to one embodiment illustrated Fig. Figure 3A-3D shows the development of a fuse device along with a typical transistor device. The top left image shows a top-down view of the fuse (left) and a regular transistor (right). Two cross-sectional views are shown, direction 1 (direction of the poly-section) and direction 2 (direction of the fin section). The first step involves deposition after the fin stack has been deposited. The silicon substrate surface of a fuse structure region is recessed, and the nanowire stack in the fuse region is shifted downwards relative to the regular transistor region. The nitride thickness on the fuse structure is increased due to the nitride's narrowing. To achieve a better surface topology, an additional nitride supernatant layer and a polishing agent can be used. As shown, fin structures are formed using nitride as a hard mask.In the reinforcement area, the drawn fin structure is completely enclosed by a structure to ensure that the horizontal nanowire stack is etched away during fin etching. The FGI is then formed on the structures, polished, and hollowed out. It is understood that the nitride on the transistor fins is polished away during STI polishing, while some of the nitride remains in the reinforcement structure. In the STI well, only the first SiGe layer is exposed in the reinforcement area. This can be achieved by optimizing the depth of the STI well relative to the depth of the substrate well. A pass can then be performed following the structuring of the poly-gate. It is understood that the width of the poly-gate in the reinforcement structure may need to be larger in the direction of the poly-cut than the fin defined by the nitride hard mask.This allows the nanowires to be successfully exposed downstream in the fuse region. Subsequently, passes to polish the spacer and poly opening can be performed, followed by a replacement gate process in which a dummy poly gate stack is removed. The nanowires can then be exposed. In the regular transistor region, all SiGe layers between Si bands are removed. In the fuse region, only the first SiGe layer above the insulating oxide is removed, while the lower SiGe layers between the Si bands remain. Operations can then be performed on high-k dielectrics and metal gates. Processing can then proceed via metal-gate cuts and dielectric filling. In such an approach, a metal-gate cut (MGC) is performed on the fuse structure to separate the two fuse terminals.In one embodiment, the metal gate cut must be selective for the nitride materials to ensure that the MGC etching does not etch into the metal fuse itself. A different hard mask material can be used to provide good selectivity for the MGC etching.

[0030] To illustrate as an exemplary process and exemplary structure formation Fig. 3A-3D top and cross-sectional views showing various processes in a method for manufacturing a fuse structure integrated with a nanowire-based transistor according to an embodiment of the present disclosure.

[0031] With reference to Fig. Figure 3A shows a top view 300, a substrate etch mark 302, and transistor fins 304. The viewing direction of the cross-sectional views is along (1) a poly-cut or gate-cut direction and (2) a fin-cut direction. In part (a), a starting structure comprises a substrate 310 with a substrate depression therein. A stack of alternating interlayers 312 and nanowire layers 314 is formed conformally to the depression of the substrate. A hard mask 316, such as a silicon nitride hard mask, is formed to have a planar top surface over the structure. In part (b), the stack of alternating interlayers 312 and nanowire layers 314 is etched to form fins 320 and 322, which can be referred to as a locking fin and a transistor fin, respectively. The structure 318 shows the locking fin along an orthogonal direction.In part (c) a trench insulation structure 324 is formed, and the hard mask 316 is removed from the transistor fin 322 and thinned on the fuse fin 320 (318) to form the hard mask 316A.

[0032] With reference to Fig. 3B, a dummy gate dielectric 326, a dummy gate electrode 328 and a hard mask 330 are placed on the structure of part (c) in part (d). Fig. 3A is formed. In part (e), gate spacers 332 and a dielectric intermediate layer 334 are formed. In part (f), the dummy gate electrode 328 and the hard mask 330 are removed to create a cavity 336.

[0033] With reference to Fig. In part (g), the upper intermediate layer 312 is removed from the fuse fin in part (3C) to create a gap 338, while all intermediate layers 312 are removed from the transistor fin. In part (h), a gate stack 340, for example, a gate stack consisting of high-k dielectric and metal gate electrode, is formed over the fuse fin and the transistor fin. The metal gate electrode material of the gate stack is located in the gap 338 of the fuse fin and is situated between all exposed nanowires 314 of the transistor fin. In part (i), a gate cut is performed (allowing the formation of a recessed hard mask 316B), and a gate-cut dielectric plug 342 is formed to separate the resulting gate stack 340A on both sides of a fuse area 339.

[0034] With reference to Fig. Figure 3D comprises an integrated circuit structure 350, a fuse structure (top and bottom left), and a nanowire-based gate all-around transistor structure (bottom right). In one embodiment, the gate stack 340B and 340C of the fuse structure transitions continuously into the gate stack of the transistor structure, as shown. It is understood that in the case of a used (blown) fuse structure, the melting region 339 comprises a metal melting region that can be detected by a change in the morphology of the gate electrode material at the location of the fuse region 339. In structure 350, the final fuse structure is shown in relation to a transistor. The two fuse terminals are separated by the dielectric metal gate cut plug.In one embodiment, the programming current of the fuse is controlled via the cross-sectional area of ​​the fuse, which is defined by the Si-Si space (fuse thickness) and the fin length defined in the direction of the poly-section.

[0035] As described here, the above safeguard structures can be integrated together with active components. Such structures can be or include gate-all-around device layers.

[0036] It is understood that in a particular embodiment, nanowires or nanoribbons or fins or intervening sacrificial layers may be composed of silicon. As is used throughout, a silicon layer can be used to describe a silicon material composed of a very substantial amount of, if not entirely of, silicon. However, it is understood that in practice, 100% pure Si can be difficult to form and therefore might contain a tiny percentage of carbon, germanium, or tin. Such impurities may be present as an unavoidable contaminant or component during the deposition of Si or may "contaminate" the Si by diffusion during post-deposition processing. Therefore, embodiments described here relating to a silicon layer may have a silicon layer containing a relatively small amount, e.g.,It contains an "impurity level" of non-Si atoms or species, such as Ge, C, or Sn. A silicon layer as described here can be undoped or doped with dopant atoms such as boron, phosphorus, or arsenic.

[0037] It is understood that in a particular embodiment, nanowires or nanoribbons or fins or sacrificial interlayers may be composed of silicon germanium. A silicon germanium layer can be used throughout to describe a silicon germanium material that is composed substantially of both silicon and germanium, for example, at least 5% of each. In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, a silicon germanium layer comprises approximately 60% germanium and approximately 40% silicon (Si₂). 40 Ge 60In other embodiments, the amount of silicon is greater than the amount of germanium. In certain embodiments, a silicon-germanium layer comprises approximately 30% germanium and approximately 70% silicon (Si₂). 70 Ge 30It is understood that in practice it can be difficult to form 100% pure silicon germanium (generally referred to as SiGe), and therefore a minute percentage of carbon or tin may be present. Such impurities may be present as an unavoidable contaminant or component during the deposition of SiGe, or they may "contaminate" the SiGe during diffusion during post-deposition processing. Therefore, embodiments described here relating to a silicon germanium layer may contain a silicon germanium layer with a relatively small amount, e.g., an "impurity level," of non-Ge and non-Si atoms or species, such as carbon or tin. A silicon germanium layer as described here may be undoped or doped with dopant atoms such as boron, phosphorus, or arsenic.

[0038] It is understood that the embodiments described here may also include other implementations, for example, nanowires and / or nanoribs and / or ribs with different widths, thicknesses and / or materials, including, but not limited to, Si and SiGe. For example, materials from groups III-V may be used.

[0039] The following describes various devices and processing schemes that can be used to fabricate a device. It is understood that the exemplary embodiments do not necessarily require all of the described features or may include more features than described. For example, processing to expose nanowires can be performed via a substitute gate trench. Examples of such exposure processes are described below. Furthermore, backend (BE) interconnect scaling can lead to lower performance and higher manufacturing costs due to the complex structuring. The embodiments described here can be implemented to enable the integration of front- and back-end interconnects for nanowire transistors.The embodiments described here can offer an approach to achieving a relatively larger interconnect spacing. This can lead to improved product performance and lower structuring costs. These embodiments can be implemented to enable robust functionality of scaled nanowire or nanoband transistors with low power consumption and high performance.

[0040] One or more embodiments described herein are directed towards dual epitaxial connections (EPI connections) for nanowire or nanoribbon transistors using a partial source or drain (SD) and an asymmetric trench contact depth (TCN depth). In one embodiment, an integrated circuit structure is fabricated by forming source-drain openings of nanowire / nanoribbon transistors that are partially filled with SD epitaxy. The remainder of the opening is filled with a conductive material. Deep trenching on the source or drain side allows direct contact with a backside interconnect plane.

[0041] To illustrate an exemplary process flow for manufacturing a gate-all-around device of an integrated gate-all-around circuit structure Fig. 4A-4J Cross-sectional views of various processes in a method for manufacturing an integrated gate all-around circuit structure according to an embodiment of the present disclosure.

[0042] With reference to Fig. 4A comprises a method for fabricating an integrated circuit structure by forming an output stack having alternating sacrificial layers 404 and nanowires 406 above a fin 402, such as a silicon fin. The nanowires 406 can be described as a vertical array of nanowires. A protective cap 408 can be formed above the alternating sacrificial layers 404 and nanowires 406, as shown. A relaxed buffer layer 452 and a defect modification layer 450 can be formed below the alternating sacrificial layers 404 and nanowires 406, as also shown.

[0043] With reference to Fig. 4B A gate stack 410 is formed above the vertical array of horizontal nanowires 406. Parts of the vertical array of horizontal nanowires 406 are then exposed by removing portions of the sacrificial layers 404 to create recessed sacrificial layers 404' and cavities 412, as shown in Fig. 4C shown.

[0044] It goes without saying that the structure consists of Fig. 4C can be completely manufactured without first performing the deep etching and processing to asymmetric contacts described below. In both cases (e.g., with or without processing to asymmetric contacts), a manufacturing process in one embodiment includes the use of a process scheme that provides an integrated gate all-around circuit structure with epitaxial studs, which may be vertically discrete source or drain structures.

[0045] With reference to Fig. 4D upper gate spacers 414 are formed on the side walls of the gate structure 410. The cavity spacers 416 are formed in the cavities 412 below the upper gate spacers 414. Subsequently, deep trench contact etching is optionally performed to form trenches 418 and recessed nanowires 406'. A structured relaxed buffer layer 452' and a structured defect modification layer 450' may also be present, as shown.

[0046] A sacrificial material 420 is then formed in the trenches 418, as in Fig. Figure 4E is shown. In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0047] With reference to Fig. In 4F, a first epitaxial source or drain structure (e.g., features 422 on the left) is formed at a first end of the vertical arrangement of horizontal nanowires 406'. A second epitaxial source or drain structure (e.g., features 422 on the right) is formed at a second end of the vertical arrangement of horizontal nanowires 406'. In one embodiment, the epitaxial source or drain structures 422, as shown, are vertically discrete source or drain structures and can be referred to as epitaxial studs.

[0048] An interlayer dielectric (ILD) material 424 is then formed on the sides of the gate electrode 410 and adjacent to the source or drain structures 422, as shown in Fig. 4G is depicted. With reference to Fig. In step 4H, a replacement gate process is used to form a permanent gate dielectric 428 and a permanent gate electrode 426. The ILD material 424 is then removed, as shown in Fig. 4I is shown. The sacrificial material 420 is then removed from one of the source-drain points (e.g. on the right side) and thus trench 432 is formed, but is not removed from the other of the source-drain points and thus trench 430 is formed.

[0049] With reference to Fig. 4J A first conductive contact structure 434 is formed, which is coupled to the first epitaxial source or drain structure (e.g., the features 422 on the left side). A second conductive contact structure 436 is formed, which is coupled to the second epitaxial source or drain structure (e.g., the features 422 on the right side). The second conductive contact structure 436 is formed deeper along the fin 402 than the first conductive contact structure 434. In one embodiment, the method also includes, although this is not explicitly stated in Fig. 4J is not shown, furthermore, the formation of an exposed surface of the second conductive contact structure 436 on a bottom side of the fin 402. Conductive contacts can have a contact resistance reducing layer and a primary contact electrode layer, with examples including Ti, Ni, Co (for the former layer and W, Ru, Co for the latter layer).

[0050] In one embodiment, the second conductive contact structure 436 is located deeper along the fin 402 than the first conductive contact structure 434, as shown. In another embodiment, the first conductive contact structure 434 is not located along the fin 402, as shown. In yet another embodiment, not shown, the first conductive contact structure 434 is located partially along the fin 402.

[0051] In one embodiment, the second conductive contact structure 436 is located along the entire length of the fin 402. In another embodiment, although not shown, the second conductive contact structure 436 has an exposed surface on the underside of the fin 402 when the underside of the fin 402 is exposed by a backside substrate removal process.

[0052] To enable access to both conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structures described here can be fabricated using a backside exposure of frontside structures. In some exemplary embodiments, backside exposure of a transistor or other device structure involves backside processing at the wafer level. Unlike conventional TSV technology, backside exposure of a transistor as described here can be performed at the device cell density and even within subregions of a device.Furthermore, such backside exposure of a transistor can be performed to essentially remove the entire donor substrate on which a device layer was deposited during frontside device processing. A micrometer-scale TSV (Technical Soil Structure) is therefore unnecessary, with the thickness of a semiconductor in the device cells following backside exposure potentially being only tens or hundreds of nanometers.

[0053] The exposure techniques described here can enable a paradigm shift from bottom-up fixture fabrication to center-out fabrication, where the center is any layer that is inserted during front-side fabrication, exposed from the back, and then inserted again during back-side fabrication. By processing both the front and exposed back sides of a fixture structure, many of the challenges associated with 3D IC fabrication when primarily relying on front-side processing can be overcome.

[0054] One approach for exposing the back side of a transistor can be used, for example, to remove at least a portion of a support layer and an interlayer of a donor-host substrate assembly. The process flow begins with the insertion of a donor-host substrate assembly. A thickness of the support layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry etching process (e.g., plasma etching). Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the support layer can be employed. For example, if the support layer is a group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning the semiconductor can be used. Likewise, any wet etching or plasma etching process known to be suitable for thinning the group IV semiconductor can be employed.

[0055] In some embodiments, the foregoing is preceded by splitting the support layer along a fracture plane that is substantially parallel to the intermediate layer. The splitting or fracture process can be used to remove a substantial portion of the support layer as bulk mass, thereby reducing the polishing or etching time required to remove the support layer. For example, if a support layer has a thickness of 400–900 µm, 100–700 µm can be cleaved off by performing any area-wide implantation known to promote at-wafer-level fracture. In some embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the support layer where the fracture plane is desired.Following such a cleavage process, the remaining thickness of the support layer in the donor-host substrate assembly can be polished or etched to complete the removal. Alternatively, if the support layer is not cleaved, the grinding, polishing, and / or etching process can be used to remove a greater thickness of the support layer.

[0056] Next, the exposure of an intermediate layer is detected. This detection identifies a point where the back surface of the donor substrate has almost reached the device layer. It is known that any endpoint detection technique suitable for detecting a transition between the materials used for the support layer and the intermediate layer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting a change in the optical absorption or emission of the back surface of the donor substrate during polishing or etching. In other embodiments, the endpoint criteria are related to a change in the optical absorption or emission of byproducts during polishing or etching of the donor substrate back surface.For example, the absorption or emission wavelengths associated with byproducts from substrate etching can change depending on the different compositions of the substrate and the interlayer. In other embodiments, the endpoint criteria are associated with a change in the mass of species in byproducts from polishing or etching the back surface of the donor substrate. For example, the processing byproducts can be sampled by a quadrupole mass analyzer, and a change in species mass can be correlated with the different compositions of the substrate and the interlayer. In another embodiment, the endpoint criteria are associated with a change in the friction between a back surface of the donor substrate and a polishing surface in contact with the back surface of the donor substrate.

[0057] Interlayer detection can be improved if the removal process is selective relative to the substrate and the interlayer, as any inconsistency in the substrate removal process can be mitigated by an etch rate delta between the substrate and the interlayer. Detection can even be skipped if, during the grinding, polishing, and / or etching process, the interlayer is removed at a rate sufficiently lower than the substrate removal rate. If no endpoint criteria are used, a grinding, polishing, and / or etching process of a predetermined fixed duration can stop at the interlayer material if the interlayer thickness is sufficient for etch selectivity. In some examples, the substrate etch rate to interlayer etch rate ratio is 3:1–10:1 or greater.

[0058] When exposing the interlayer, at least a portion of the interlayer can be removed. For example, one or more component layers of the interlayer can be removed. A thickness of the interlayer can be removed uniformly by polishing. Alternatively, a thickness of the interlayer can be removed using an etching process with a mask or an area etching process. The same polishing or etching process used for thinning the substrate can be employed, or it can be a separate process with its own parameters. For example, if the interlayer provides an etch stop for the substrate removal process, the latter can employ a different polishing or etching process that favors the removal of the interlayer compared to the removal of the fixture layer.When removing an intermediate layer less than a few hundred nanometers thick, the removal process can be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than the process used to remove the substrate layer. For example, a CMP process can employ a slurry that offers very high selectivity (e.g., 100:1 to 300:1 or more) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO₂) surrounding the device layer and embedded within the intermediate layer, for example, as electrical insulation between adjacent device areas.

[0059] For embodiments in which the fixture layer is exposed by complete removal of the intermediate layer, backside processing can commence on an exposed backside of the fixture layer or on specific fixture regions therein. In some embodiments, backside fixture layer processing includes further polishing or wet / dry etching through a thickness of the fixture layer located between the intermediate layer and a fixture region previously fabricated in the fixture layer, for example, a source or drain region.

[0060] In some embodiments where the substrate, intermediate layer, or back surface of the device layer is deepened by wet and / or plasma etching, such etching can be a structured etch or a material-selective etch, imparting significant non-planarity or topography to the back surface of the device layer. As described below, the structuring can occur within a device cell (i.e., "intra-cell structuring") or across device cells (i.e., "inter-cell structuring"). In some embodiments with structured etching, at least a partial thickness of the intermediate layer is used as a hard mask for structuring the back surface of the device layer. Therefore, a mask-based etching process can precede a corresponding mask-based etching of the device layer.

[0061] The processing scheme described above can result in a donor-host substrate arrangement featuring IC devices where the back side of an intermediate layer, the back side of the device layer, and / or the back side of one or more semiconductor regions within the device layer, and / or a front-side metallization are exposed. Additional back-side processing of any of these exposed regions can then be performed during a subsequent processing step.

[0062] It is understood that the structures resulting from the above exemplary processing schemes can be used in the same or a similar form for subsequent processing operations to complete fixture manufacturing, such as PMOS and / or NMOS fixture manufacturing. An example of a completed fixture is illustrated below. Fig. 5 a cross-sectional view of a non-planar integrated circuit structure along a gate line according to an embodiment of the present disclosure.

[0063] With reference to Fig. 5 comprises a semiconductor structure or device 500 with a non-planar active region (e.g., a fin structure, including a protruding fin section 504 and an underfin region 505) within a trench isolation region 506. In one embodiment, the non-planar active region is subdivided into nanowires (such as nanowires 504A and 504B) above the underfin region 505 instead of a solid fin, as indicated by the dashed lines. In both cases, for the sake of simplicity, a non-planar active region 504 is referred to below as a protruding fin section in the non-planar integrated circuit structure 500. In one embodiment, the underfin region 505 also includes a relaxed buffer layer 542 and a defect modification layer 540, as shown.

[0064] A gate conductor 508 is arranged over the protruding sections 504 of the non-planar active region (and, where applicable, surrounds the nanowires 504A and 504B) and over a section of the trench insulation region 506. As shown, the gate conductor 508 has a gate electrode 550 and a gate dielectric layer 552. In one embodiment, the gate conductor 508 may also have a dielectric cap layer 554. A gate contact 514 and an overlying gate contact via 516, together with an overlying metal intermediate 560, all arranged in dielectric intermediate layer stacks or layers 570, are also visible from this perspective. As also shown from the perspective of Fig. As can be seen in Figure 5, in one embodiment the gate contact 514 is arranged above the trench isolation area 506, but not above the non-planar active areas. In another embodiment, the gate contact 514 is located above the non-planar active areas.

[0065] In one embodiment, the semiconductor structure or device 500 is a non-planar device such as, among others, a FinFET device, a tri-gate device, a nanoband device, or a nanowire device. In such an embodiment, a corresponding semiconducting channel region is constructed from or formed within a three-dimensional body. In such an embodiment, the gate electrode stacks of the gate lines 508 surround at least one upper surface and a pair of side walls of the three-dimensional body.

[0066] As in Fig. As shown in Figure 5, in one embodiment an interface 580 is present between a projecting fin section 504 and a lower fin region 505. The interface 580 can be a transition region between a doped lower fin region 505 and a weakly or undoped upper fin part 504. In such an embodiment, each fin is approximately 10 nanometers wide or narrower, and lower fin dopants are optionally supplied from an adjacent solid doping layer at the location of the lower fins. In a particular embodiment, each fin is less than 10 nanometers wide.

[0067] Although this in Fig. Since Figure 5 is not shown, it is understood that source or drain regions are located on or adjacent to the protruding fin sections 504 on both sides of the gate line 508, i.e., extending into and out of the figure sheet. In one embodiment, the material of the protruding fin sections 504 at the source or drain location is removed and replaced by another semiconductor material, e.g., by epitaxial deposition, to form epitaxial source or drain structures. The source or drain regions may extend below the height of the dielectric layer of the trench insulation region 506, i.e., into the underfin region 505. According to one embodiment of the present disclosure, the more heavily doped underfin regions, i.e., the doped sections of the fins below the interface 580, prevent source-to-drain leakage through this section of the bulk semiconductor fins.In one embodiment, the source and drain regions have associated asymmetric source and drain contact structures, as described above in conjunction with . Fig. 4J is described.

[0068] With renewed reference to Fig. 5 In one embodiment, the fins 504 / 505 (and possibly the nanowires 504A and 504B) are made up of a crystalline silicon germanium layer which may be doped with a charge carrier, such as phosphorus, arsenic, boron, gallium or a combination thereof.

[0069] In one embodiment, the trench isolation region 506 and trench isolation regions (trench isolation structures or trench isolation layers) described throughout this description can be constructed of a material suitable for ultimately electrically isolating or contributing to the isolation of sections of a permanent gate structure from an underlying bulk substrate, or for isolating active regions formed within an underlying bulk substrate, for example, active fin regions. In one embodiment, the trench isolation region 506 is, for example, constructed of a dielectric material such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride, but is not limited to such materials.

[0070] The gate conductor 508 can be composed of a gate-electrode stack comprising a dielectric gate layer 552 and a gate-electrode layer 550. In one embodiment, the gate electrode of the gate-electrode stack is composed of a metal gate, and the dielectric gate layer is composed of a high-k material. In one embodiment, the dielectric gate layer 552 is, for example, composed of a material such as hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc cniobate, or a combination thereof. In addition, part of the dielectric gate layer 552 may contain a layer of native oxide formed from the upper few layers of the substrate fin 504.In one embodiment, the dielectric gate layer 552 is composed of an upper high-k portion and a lower portion composed of an oxide of a semiconductor material. In another embodiment, the dielectric gate layer 552 is composed of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride. In some implementations, a section of the gate dielectric is a "U"-shaped structure comprising a lower portion that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the upper surface of the substrate.

[0071] In one embodiment, the gate electrode layer 550 consists of a metal layer, such as metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a particular embodiment, the gate electrode layer 550 is composed of a non-work function-setting filler material formed above a work function-setting metal layer. The gate electrode layer 550 can consist of a p-type or n-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer 550 can consist of a stack of two or more metal layers, wherein one or more metal layer(s) are work function metal layers and at least one metal layer is a conductive filler layer.For a PMOS transistor, metals that can be used for the gate electrode include ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides, such as ruthenium oxide. A p-type metal layer allows the formation of a PMOS gate electrode with a work function between approximately 4.9 eV and approximately 5.2 eV. For an NMOS transistor, metals that can be used for the gate electrode include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will allow the formation of an NMOS gate electrode with a work function between approximately 3.9 eV and approximately 4.2 eV.In some implementations, the gate electrode may consist of a "U"-shaped structure having a lower section that is essentially parallel to the surface of the substrate and two sidewall sections that are essentially perpendicular to the upper surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer that is essentially parallel to the upper surface of the substrate and has no sidewall sections that are essentially perpendicular to the upper surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0072] Spacers associated with the gate electrode stacks can be made of a material suitable for electrically isolating, or contributing to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligning contacts. For example, in one embodiment, the spacers are made of a dielectric material, such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0073] The gate contact 514 and the overlying gate contact via 516 can be made of a conductive material. In one embodiment, one or more of the contacts or vias are made of a specific metal. The metal can be a pure metal such as tungsten, nickel, or cobalt, or it can be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (such as a silicide material).

[0074] In one embodiment (though not shown), a contact structure is formed that is essentially perfectly aligned with an existing gate structure 508, while simultaneously eliminating the need for a lithographic step with an extremely tight budget regarding overlap accuracy. In one embodiment, the contact structure is a vertically symmetrical contact structure or an asymmetrical contact structure, such as in conjunction with Fig. 4J is described. In other embodiments, all contacts on the front face are connected and not asymmetrical. In such an embodiment, the self-aligning approach enables the use of an intrinsically highly selective wet etching (e.g., compared to conventionally implemented dry or plasma etching) to create contact openings. In one embodiment, a contact structure is formed by using an existing gate structure in combination with a contact plug lithography process. In such an embodiment, the approach eliminates the need for an otherwise critical lithography process to create a contact structure, as used in conventional approaches. In one embodiment, a trench contact grid is not structured separately but is instead formed between poly(gate) conductors.For example, in such an embodiment, a trench contact grid is formed after the structuring of gate grids, but before the cutting of the gate grids.

[0075] In one embodiment, providing the structure 500 involves fabricating the gate stack structure 508 by a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride column material, can be removed and replaced by a permanent gate electrode material. In such an embodiment, a permanent dielectric gate layer is also formed in this process, rather than being carried over from a previous processing step. In one embodiment, dummy gates are removed by a dry etching or wet etching process. In another embodiment, dummy gates are constructed of polycrystalline silicon or amorphous silicon and are removed in a dry etching process that involves the use of SF6.In another embodiment, dummy gates are made of polycrystalline silicon or amorphous silicon and are removed by a wet etching process involving the use of aqueous NH4OH or tetramethylammonium hydroxide. In another embodiment, dummy gates are made of silicon nitride and are removed by a wet etching process involving aqueous phosphoric acid.

[0076] With renewed reference to Fig. In the arrangement of the semiconductor structure or semiconductor device 500, the gate contact is placed over insulating regions. Such an arrangement can be considered an inefficient use of layout space. In another embodiment, however, a semiconductor device has contact structures that contact sections of a gate electrode formed over an active region, e.g., over a fin 505, and in the same layer as a trench contact via.

[0077] It is understood that not all aspects of the processes described herein need to be implemented to fall within the spirit and scope of protection of embodiments of this disclosure. Furthermore, the processes described herein can be used to fabricate one or more semiconductor devices. The semiconductor devices may be transistors or similar devices. For example, in one embodiment, the semiconductor devices are metal-oxide-semiconductor transistors (MOS transistors) for logic or memory applications, or they are bipolar transistors. In another embodiment, the semiconductor devices also have a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, a dual-gate device with independent access, or a FinFET.One or more embodiments may be particularly useful for manufacturing semiconductor devices in a technology node below 10 nanometers (10 nm).

[0078] In one embodiment, as used throughout this description, the dielectric interlayer material (ILD material) is composed of or comprises a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known from the prior art, and combinations thereof. The dielectric interlayer material can be formed by conventional techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0079] In one embodiment, also used throughout this description, metal conductors or an interconnection material (and via material) are constructed from one or more metal or other conductive structures. A common example is the use of copper conductors and structures, which may or may not have barrier layers between the copper and the surrounding ILD material. As used here, the term "metal" includes alloys, stacks, and other combinations of several metals. For example, the metal interconnection conductors may have barrier layers (e.g., layers containing Ta, TaN, Ti, and / or TiN), stacks of different metals or alloys, etc. Thus, the interconnection conductors may be a single layer of material, or they may be formed from multiple layers, including conductive lining layers and filler layers.Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form interconnects. In one embodiment, the interconnects are made of a conductive material such as Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. In the field, these interconnects are sometimes also referred to as conductors, wires, conductors, metal, or simply as interconnects.

[0080] In one embodiment, also used throughout this description, hard mask materials, cap layers, or plugs are constructed of dielectric materials different from the dielectric interlayer material. In one embodiment, different hard mask, cap, or plug materials can be used in different regions to provide varying growth or etch selectivity with respect to each other and to the underlying dielectric and metal layers. In some embodiments, a hard mask layer, cap layer, or plug layer comprises a layer of silicon nitride (e.g., silicon nitride), a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials.Depending on the specific implementation, other hard mask, cap, or plug layers known in the field can be used. These hard mask, cap, or plug layers can be formed by CVD, PVD, or other deposition methods.

[0081] In one embodiment, also used throughout this description, lithographic processes are performed using 193 nm immersion lithography (i193), EUV and / or EBDW lithography, or the like. A positive or negative photoresist may be used. In one embodiment, a lithographic mask is a three-layer mask consisting of a topographic masking section, an anti-reflective coating (ARC) layer, and a photoresist layer. In one particular embodiment, the topographic masking section is a carbon hard mask (CHM) layer, and the anti-reflective layer is a silicon ARC layer.

[0082] In another aspect, a grid-division approach is used to structure trenches in a dielectric layer (permanent or sacrificial layer) for forming BEOL interlink structures or for directly structuring metal features in a subtractive approach. According to one embodiment of the present disclosure, grid division is applied to the fabrication of metal conductors in a BEOL fabrication scheme. With these embodiments, continuous scaling of the grid dimension of metal layers beyond the resolution capabilities of modern lithography equipment is possible.

[0083] Fig. Figure 6 is a diagram of a grid dimension quartering approach 600, which is used according to an embodiment of the present disclosure for the manufacture of intermediate connection structures.

[0084] With reference to Fig. In process (a), backbone features 602 are formed using direct lithography. For example, a photoresist layer or stack can be structured, and the structure can be transferred to a hard mask material to ultimately form the backbone features 602. The photoresist layer or stack used to form backbone features 602 can be structured using standard lithographic processing techniques, such as 193 nm immersion lithography. Initial spacer features 604 are then formed adjacent to the sidewalls of the backbone features 602.

[0085] In process (b), the backbone features 602 are removed, leaving only the first spacer features 604. At this stage, the first spacer features 604 are actually a half-grid dimension mask, representing, for example, a grid dimension halving process. The first spacer features 604 can either be used directly for a grid dimension quartering process, or the structure of the first spacer features 604 can first be transferred into a new hard mask material, the latter approach being shown.

[0086] In process (c), the structure of the first spacer features 604 is transferred to a new hard mask material to form first spacer features 604'. Second spacer features 606 are then formed adjacent to the side walls of the first spacer features 604'.

[0087] In process (d), the first spacer features 604' are removed, leaving only the second spacer features 606. In this phase, the second spacer features 606 are actually a quarter-grid dimension mask, which, for example, represents a grid dimension quartering process.

[0088] In process (e), the second spacer features 606 are used as a mask to structure a plurality of trenches 608 in a dielectric layer or a hard mask layer. The trenches can subsequently be filled with conductive material to form conductive intermediate connections in the metallization layers of an integrated circuit. The trenches 608 labeled “B” correspond to the backbone features 602. The trenches 608 labeled “S” correspond to the first spacer features 604 or 604’. The trenches 608 labeled “C” correspond to a complementary region 607 between the backbone features 602.

[0089] Since some of the trenches 608 in Fig. 6 exhibit a structuring origin that corresponds to one of the backbone features 602, first spacer features 604 or 604', or a complementary area 607 in Fig. As stated in section 6, it is understood that differences in the width and / or grid dimension of these features can appear as artifacts of a grid dimension quartering process in the finally formed conductive intermediates in metallization layers of an integrated circuit. As an example, this illustrates... Fig. 7A is a cross-sectional view of a metallization layer produced according to an embodiment of the present disclosure using a grid-dimensioned quartering scheme. It is understood that a FEOL nanowire stack fuse as described above can be electrically coupled to a metal layer, which in conjunction with Fig. 7A is described

[0090] With reference to Fig. 7A comprises an integrated circuit structure 700 and a dielectric intermediate layer (ILD layer) 704 above a substrate 702. A plurality of conductive interconnects 706 are located in the ILD layer 704, and some of the conductive interconnects 706 are spaced apart from each other by sections of the ILD layer 704. Some of the conductive interconnects 706 comprise a conductive barrier layer 708 and a conductive filler material 710.

[0091] Referring to both Fig. On both 6 and 7A, conductive intermediate links 706B are formed in trenches with a structure originating from the backbone features 602. The conductive intermediate links 706S are formed in trenches with a structure originating from the first spacer features 604 or 604'. The conductive intermediate links 706C are formed in trenches with a structure originating from the complementary area 607 between the backbone features 602.

[0092] Again with reference to Fig. In one embodiment, 7A comprises the plurality of conductive intermediate connecting lines 706, a first intermediate connecting line 706B having a width (W1). A second intermediate connecting line 706S is located immediately adjacent to the first intermediate connecting line 706B, the second intermediate connecting line 706S having a width (W2) that differs from the width (W1) of the first intermediate connecting line 706B. A third intermediate connecting line 706C is located immediately adjacent to the second intermediate connecting line 706S, the third intermediate connecting line 706C having a width (W3). A fourth intermediate connecting line (second 706S) is located immediately adjacent to the third intermediate connecting line 706C, the fourth intermediate connecting line having a width (W2) that is identical to the width (W2) of the second intermediate connecting line 706S.A fifth intermediate connection (second 706B) is located immediately adjacent to the fourth intermediate connection (second 706S), the fifth intermediate connection (second 706B) having a width (W1) that is identical to the width (W1) of the first intermediate connection 706B.

[0093] In one embodiment, the width (W3) of the third intermediate connection line 706C differs from the width (W1) of the first intermediate connection line 706B. In another such embodiment, the width (W3) of the third intermediate connection line 706C differs from the width (W2) of the second intermediate connection line 706S. In another such embodiment, the width (W3) of the third intermediate connection line 706C is identical to the width (W2) of the second intermediate connection line 706S. In yet another embodiment, the width (W3) of the third intermediate connection line 706C is identical to the width (W1) of the first intermediate connection line 706B.

[0094] In one embodiment, the grid dimension (P1) between the first intermediate connection line 706B and the third intermediate connection line 706C is equal to a grid dimension (P2) between the second intermediate connection line 706S and the fourth intermediate connection line (second 706S). In another embodiment, a grid dimension (P1) between the first intermediate connection line 706B and the third intermediate connection line 706C differs from a grid dimension (P2) between the second intermediate connection line 706S and the fourth intermediate connection line (second 706S).

[0095] Again with reference to Fig. In another embodiment, 7A comprises a plurality of conductive intermediate connecting lines 706, a first intermediate connecting line 706B having a width (W1). A second intermediate connecting line 706S is located immediately adjacent to the first intermediate connecting line 706B, the second intermediate connecting line 706S having a width (W2). A third intermediate connecting line 706C is located immediately adjacent to the second intermediate connecting line 706S, the third intermediate connecting line 706S having a width (W3) that differs from the width (W1) of the first intermediate connecting line 706B. A fourth intermediate connecting line (second 706S) is located immediately adjacent to the third intermediate connecting line 706C, the fourth intermediate connecting line having a width (W2) that is identical to the width (W2) of the second intermediate connecting line 706S.A fifth intermediate connection (second 706B) is located immediately adjacent to the fourth intermediate connection (second 706S), the fifth intermediate connection (second 706B) having a width (W1) that is identical to the width (W1) of the first intermediate connection 706B.

[0096] In one embodiment, the width (W2) of the second intermediate connecting line 706S differs from the width (W1) of the first intermediate connecting line 706B. In another such embodiment, the width (W3) of the third intermediate connecting line 706C differs from the width (W2) of the second intermediate connecting line 706S. In yet another such embodiment, the width (W3) of the third intermediate connecting line 706C is identical to the width (W2) of the second intermediate connecting line 706S.

[0097] In one embodiment, the width (W2) of the second intermediate connection 706S is identical to the width (W1) of the first intermediate connection 706B. In another embodiment, a grid dimension (P1) between the first intermediate connection 706B and the third intermediate connection 706C is identical to a grid dimension (P2) between the second intermediate connection 706S and the fourth intermediate connection (second 706S). In yet another embodiment, a grid dimension (P1) between the first intermediate connection 706B and the third intermediate connection 706C differs from a grid dimension (P2) between the second intermediate connection 706S and the fourth intermediate connection (second 706S).

[0098] Fig. Figure 7B illustrates a cross-sectional view of a metallization layer fabricated using a half-grid layout above a metallization layer fabricated using a quarter-grid layout, according to an embodiment of the present disclosure. It is understood that a FEOL nanowire stack fuse, such as the one described above, can be electrically coupled to a metal layer fabricated using a quarter-grid layout. Fig. 7B is described.

[0099] With reference to Fig. 7B includes an integrated circuit structure 750, a first dielectric intermediate layer (ILD layer) 754 above a substrate 752. A first plurality of conductive interconnects 756 is located in the first ILD layer 754, and individual conductive interconnects 756 are spaced apart from each other by sections of the first ILD layer 754. Individual conductive interconnects 756 comprise a conductive barrier layer 758 and a conductive filler material 760. The integrated circuit structure 750 further comprises a second dielectric intermediate layer (ILD layer) 774 above the substrate 752. A second plurality of conductive interconnects 776 is located in the second ILD layer 774, and individual conductive interconnects 776 are spaced apart from each other by sections of the second ILD layer 774.Some of the many conductive intermediate connecting lines 776 comprise a conductive barrier layer 778 and a conductive filler material 780.

[0100] Again with reference to Fig. 7B comprises a method for fabricating an integrated circuit structure according to an embodiment of the present disclosure, forming, above a substrate 752, a first plurality of conductive interconnects 756 spaced apart by a first dielectric intermediate layer (ILD layer) 754. The first plurality of conductive interconnects 756 are formed using a spacer-based grid-dimensioning process, e.g., the one described in conjunction with processes (a) to (e) in Fig. The approach described in section 6 is used. Above the first ILD layer 754, a second plurality of conductive interconnects 776 are formed in a second ILD layer 774 and spaced apart by it. The second plurality of conductive interconnects 776 are formed using a spacer-based grid-division halving process, e.g., the one described in conjunction with processes (a) and (b) in Fig. 6 described approach, trained.

[0101] In one embodiment, the first plurality of the conductive interconnects 756 have a grid spacing (P1) between immediately adjacent conductors of more than 40 nanometers. The second plurality of the conductive interconnects 776 have a grid spacing (P2) between immediately adjacent conductors of more than 44 nanometers. In one embodiment, the spacer-based grid-squaring process and the spacer-based grid-squaring process are based on a 193 nm immersion lithography process.

[0102] In one embodiment, some of the first plurality of conductive intermediate connecting lines 754 comprise a first conductive barrier lining 758 and a first conductive filler material 760. Some of the second plurality of conductive intermediate connecting lines 756 comprise a second conductive barrier lining 778 and a second conductive filler material 780. In such an embodiment, the first conductive filler material 760 has a different composition than the second conductive filler material 780. In another embodiment, the first conductive filler material 760 has the same composition as the second conductive filler material 780. In one embodiment, the first conductive barrier lining 758 and / or the second conductive barrier lining 778 are a single nitrogen-free tantalum barrier layer (Ta barrier layer).

[0103] Although not shown, in one embodiment the method further comprises forming, above the second ILD layer 774, a third plurality of conductive interconnects in and spaced apart by a third ILD layer. The third plurality of conductive interconnects is formed without the use of a grid spacing.

[0104] Although not shown, in one embodiment the method further comprises, prior to forming the second plurality of conductive intermediate connections 776, forming a third plurality of conductive intermediate connections in and spaced apart by the first ILD layer 754. The third plurality of conductive intermediate connections is formed using a spacer-based grid-division quartering process. In such an embodiment, following the formation of the second plurality of conductive intermediate connections 776, a fourth plurality of conductive intermediate connections is formed in and spaced apart by the second ILD layer 774. The fourth plurality of conductive intermediate connections is formed using a spacer-based grid-division halving process.In one embodiment, such a method further comprises forming, above the fourth ILD layer, a fifth plurality of conductive interconnects in and spaced by a fifth ILD layer, wherein the fifth plurality of conductive interconnects is formed using a spacer-based grid-bivision process. A sixth plurality of conductive interconnects is then formed above the fifth ILD layer in and spaced by a sixth ILD layer, wherein the sixth plurality of conductive interconnects is formed using a spacer-based grid-bivision process. A seventh plurality of conductive interconnects is then formed above the sixth ILD layer in and spaced by a seventh ILD layer.The seventh majority of conductive intermediate connecting lines are formed without the use of a grid scale.

[0105] In another aspect, the metal conductor compositions vary between the different metallization layers. Such an arrangement can be described as heterogeneous metallization layers. In one embodiment, copper is used as the conductive filler material for relatively larger interconnects, while cobalt is used as the conductive filler material for relatively smaller interconnects. The smaller conductors containing cobalt as filler material can provide lower electromigration while maintaining a low resistivity.By using cobalt instead of copper for smaller interconnects, problems associated with scaling copper conduits can be overcome, where a conductive barrier layer occupies a larger interconnect volume and copper is reduced, essentially eliminating the benefits that normally come with a copper interconnect.

[0106] A first example illustrates Fig. 8A A cross-sectional view of an integrated circuit structure which, according to an embodiment of the present disclosure, has a metallization layer with one metal conductor composition above a metallization layer with a different metal conductor composition. It is understood that one or more of the interconnects or layers of interconnects, which are connected in conjunction with Fig. 8A described, can be coupled with a FEOL nanowire stack fuse, as described above.

[0107] With reference to Fig. 8A comprises an integrated circuit structure 800 above a substrate 802, a first plurality of conductive interconnects 806 in and spaced apart by a first dielectric intermediate layer (ILD layer) 804. One of the conductive interconnects 806A is shown to have an underlying via 807. Individual members of the first plurality of conductive interconnects 806 comprise a first conductive barrier material 808 along side walls and a bottom surface of a first conductive filler material 810.

[0108] A second plurality of conductive interconnects 816 is located in and spaced apart by a second ILD layer 814 above the first ILD layer 804. One of the conductive interconnects 816A is shown to have an underlying via 817. Individual members of the second plurality of conductive interconnects 816 comprise a second conductive barrier material 818 along the side walls and underside of a second conductive filler material 820. The second conductive filler material 820 differs in composition from the first conductive filler material 810. In one embodiment, the second conductive barrier material 818 is a single nitrogen-free tantalum barrier layer (Ta barrier layer).

[0109] In one embodiment, the second conductive filler material 820 consists essentially of copper, and the first conductive filler material 810 consists essentially of cobalt. In such an embodiment, the first conductive barrier material 808 has a different composition than the second conductive barrier material 818. In another such embodiment, the first conductive barrier material 808 has the same composition as the second conductive barrier material 818.

[0110] In one embodiment, the first conductive filler material 810 comprises copper with a first concentration of a dopant atom, and the second conductive filler material 820 comprises copper with a second concentration of the dopant atom. The second concentration of the dopant atom is lower than the first concentration of the dopant atom. In such an embodiment, the dopant atom is selected from the group consisting of aluminum (Al) and manganese (Mn). In one embodiment, the first conductive barrier material 810 and the second conductive barrier material 820 have the same composition. In another embodiment, the first conductive barrier material 810 and the second conductive barrier material 820 have different compositions.

[0111] Again with reference to Fig. In 8A, the second ILD layer 814 is located on an etch stop layer 822. The conductive via 817 is located in the second ILD layer 814 and in an opening of the etch stop layer 822. In one embodiment, the first and second ILD layers 804 and 814 comprise silicon, carbon, and oxygen, and the etch stop layer 822 comprises silicon and nitrogen. In another embodiment, some of the first plurality of conductive interconnects 806 have a first width (W1), and some of the second plurality of conductive interconnects 816 have a second width (W2) that is greater than the first width (W1).

[0112] A second example illustrates Fig. Figure 8B, according to an embodiment of the present disclosure, shows a cross-sectional view of an integrated circuit structure with a metallization layer having a metal conductor composition coupled to a metallization layer having a different metal conductor composition. It is understood that one or more of the interconnections or layers of interconnections coupled to Fig. 8B described, can be coupled with a FEOL nanowire stack fuse, as described above.

[0113] With reference to Fig. 8B comprises an integrated circuit structure 850 above a substrate 852, a first plurality of conductive interconnects 856 in and spaced apart by a first dielectric intermediate layer (ILD layer) 854. One of the conductive interconnects 856A is shown to have an underlying via 857. Individual members of the first plurality of conductive interconnects 856 comprise a first conductive barrier material 858 along side walls and a bottom surface of a first conductive filler material 860.

[0114] A second plurality of conductive interconnects 866 are located in and spaced apart by a second ILD layer 864 above the first ILD layer 854. One of the conductive interconnects 866A is shown to have an underlying via 867. Individual members of the second plurality of conductive interconnects 866 comprise a second conductive barrier material 868 along the side walls and underside of a second conductive filler material 870. The second conductive filler material 870 differs in composition from the first conductive filler material 860. In one embodiment, the second conductive barrier material 868 is a single nitrogen-free tantalum barrier layer (Ta barrier layer).

[0115] In one embodiment, the conductive via 857 is located on and electrically coupled to a single 856B of the first plurality of conductive intermediate connections 856, coupling the single 866A of the second plurality of conductive intermediate connections 866 to the single 856B of the first plurality of conductive intermediate connections 856. As shown, in one embodiment, single connections of the first plurality of conductive intermediate connections 856 are arranged along a first direction 898 (e.g., into and out of the figure sheet), and single connections of the second plurality of conductive intermediate connections 866 are arranged along a second direction 899 orthogonally to the first direction 898.As shown, in one embodiment the conductive via 867 comprises the second conductive barrier material 868 along the side walls and underside of the second conductive filler material 870.

[0116] In one embodiment, the second ILD layer 864 is located on an etch stop layer 872 on the first ILD layer 854. The conductive via 867 is located in the second ILD layer 864 and in an opening of the etch stop layer 872. In one embodiment, the first and second ILD layers 854 and 864 comprise silicon, carbon, and oxygen, and the etch stop layer 872 comprises silicon and nitrogen. In one embodiment, some of the first plurality of conductive interconnects 856 have a first width (W1), and some of the second plurality of conductive interconnects 866 have a second width (W2) that is greater than the first width (W1).

[0117] In one embodiment, the second conductive filler material 870 consists essentially of copper, and the first conductive filler material 860 consists essentially of cobalt. In such an embodiment, the first conductive barrier material 858 has a different composition than the second conductive barrier material 868. In another such embodiment, the first conductive barrier material 858 has the same composition as the second conductive barrier material 868.

[0118] In one embodiment, the first conductive filler material 860 comprises copper with a first concentration of a dopant atom, and the second conductive filler material 870 comprises copper with a second concentration of the dopant atom. The second concentration of the dopant atom is lower than the first concentration of the dopant atom. In such an embodiment, the dopant atom is selected from the group consisting of aluminum (Al) and manganese (Mn). In one embodiment, the first conductive barrier material 860 and the second conductive barrier material 870 have the same composition. In another embodiment, the first conductive barrier material 860 and the second conductive barrier material 870 have different compositions.

[0119] Fig. Figures 9A to 9C illustrate cross-sectional views of individual intermediate connecting lines which, according to an embodiment of the present disclosure, have different arrangements of a barrier lining and a conductive cover structure, which are used in conjunction with the Fig. 8A and Fig. The structures described in section 8B are suitable.

[0120] With reference to Fig. 9A comprises an intermediate connecting conductor 900 in a dielectric layer 901, a conductive barrier material 902, and a conductive filler material 904. The conductive barrier material 902 has an outer layer 906 distal to the conductive filler material 904 and an inner layer 908 close to the conductive filler material 904. In one embodiment, the conductive filler material comprises cobalt, the outer layer 906 comprises titanium and nitrogen, and the inner layer 908 comprises tungsten, nitrogen, and carbon. In such an embodiment, the outer layer 906 has a thickness of approximately 2 nanometers, and the inner layer 908 has a thickness of approximately 0.5 nanometers. In another embodiment, the conductive filler material comprises cobalt, the outer layer 906 comprises tantalum, and the inner layer 908 comprises ruthenium. In such an embodiment, the outer layer 906 further comprises nitrogen.

[0121] With reference to Fig. 9B comprises an intermediate connecting conductor 920 in a dielectric layer 921, a conductive barrier material 922, and a conductive filler material 924. A conductive cover layer 930 is located on a top surface of the conductive filler material 924. As shown, in one embodiment, the conductive cover layer 930 is also located on a top surface of the conductive barrier material 922. In another embodiment, the conductive cover layer 930 is not located on a top surface of the conductive barrier material 922. In one embodiment, the conductive cover layer 930 consists essentially of cobalt, and the conductive filler material 924 consists essentially of copper.

[0122] With reference to Fig. 9C comprises an intermediate connecting conductor 940 in a dielectric layer 941, a conductive barrier material 942, and a conductive filler material 944. The conductive barrier material 942 has an outer layer 946 distal to the conductive filler material 944 and an inner layer 948 close to the conductive filler material 944. A conductive cover layer 950 is located on a top surface of the conductive filler material 944. In one embodiment, the conductive cover layer 950 is only a top surface of the conductive filler material 944. In another embodiment, however, the conductive cover layer 950 is also located on a top surface of the inner layer 948 of the conductive barrier material 942, i.e., at location 952. In such an embodiment, the conductive cover layer 950 is also located on a top surface of the outer layer 946 of the conductive barrier material 942, i.e., at location 954.

[0123] With reference to Fig. 9B and Fig. 9C comprises a method for fabricating an integrated circuit structure, in one embodiment forming a dielectric intermediate layer (ILD layer) 921 or 941 above a substrate. A plurality of conductive interconnects 920 or 940 are formed in trenches in and spaced apart by the ILD layer, wherein individual conductive interconnects 920 or 940 are located in a corresponding number of the trenches. The majority of the conductive intermediate connecting lines are first formed by forming a conductive barrier material 922 or 924 on the undersides and side walls of the trenches and then by forming a conductive fill material 924 or 944 on the conductive barrier material 922 or 942 and filling the trenches, wherein the conductive barrier material 922 or 942 is located along an underside of and along side walls of the conductive fill material 930 or 950.The top surface of the conductive filler material 924 or 944 is then treated with a gas containing oxygen and carbon. Following this treatment, a conductive top layer 930 or 950 is formed on the surface of the conductive filler material 924 or 944.

[0124] In one embodiment, treating the top surface of the conductive filler material 924 or 944 with the gas comprising oxygen and carbon includes treating the top surface of the conductive filler material 924 or 944 with carbon monoxide (CO). In another embodiment, the conductive filler material 924 or 944 comprises copper, and forming the conductive top layer 930 or 950 on the top surface of the conductive filler material 924 or 944 includes forming a layer comprising cobalt using chemical vapor deposition (CVD). In another embodiment, the conductive top layer 930 or 950 is formed on the top surface of the conductive filler material 924 or 944, but not on the top surface of the conductive barrier material 922 or 924.

[0125] In such an embodiment, forming the conductive barrier material 922 or 944 comprises forming a first conductive layer on the undersides and sidewalls of the trenches, wherein the first conductive layer comprises tantalum. A first section of the first conductive layer is formed first using atomic layer deposition (ALD), and then a second section of the first conductive layer is formed using physical vapor deposition (PVD). In such an embodiment, forming the conductive barrier material further comprises forming a second conductive layer on top of the first conductive layer on the undersides and sidewalls of the trenches, wherein the second conductive layer comprises ruthenium, and wherein the conductive filler material comprises copper. In one embodiment, the first conductive layer further comprises nitrogen.

[0126] Fig. Figure 10 illustrates a cross-sectional view of an integrated circuit structure comprising four metallization layers with a metal conductor composition and a grid spacing above two metallization layers with a different metal conductor composition and a smaller grid spacing, according to an embodiment of the present disclosure. It is understood that one or more of the interconnects or layers of interconnects, which are connected in conjunction with Fig. 10 described, can be coupled with a FEOL nanowire stack fuse, as described above.

[0127] With reference to Fig. Figure 10 comprises an integrated circuit structure 1000 comprising a first plurality of conductive interconnects 1004 in and spaced apart by a first dielectric intermediate layer (ILD layer) 1002 above a substrate 1001. Individuals of the first plurality of conductive interconnects 1004 comprise a first conductive barrier material 1006 along side walls and a bottom surface of a first conductive filler material 1008. Individuals of the first plurality of conductive interconnects 1004 are arranged along a first direction 1098 (e.g., into and out of the figure sheet).

[0128] A second plurality of conductive intermediate interconnects 1014 is located in and spaced apart by a second ILD layer 1012 above the first ILD layer 1002. Individuals of the second plurality of conductive intermediate interconnects 1014 encompass the first conductive barrier material 1006 along side walls and a bottom surface of the first conductive filler material 1008. Individuals of the second plurality of conductive intermediate interconnects 1014 are arranged along a second direction 1099 orthogonal to the first direction 1098.

[0129] A third plurality of conductive interconnects 1024 is located within and spaced apart by a third ILD layer 1022 above the second ILD layer 1012. Individual members of the third plurality of conductive interconnects 1024 comprise a second conductive barrier material 1026 along the side walls and underside of a second conductive filler material 1028. The second conductive filler material 1028 differs in composition from the first conductive filler material 1008. Individual members of the third plurality of conductive interconnects 1024 are located along the first direction 1098. In one embodiment, the second conductive barrier material 1026 is a single nitrogen-free tantalum barrier layer (Ta barrier layer).

[0130] A fourth plurality of conductive intermediate interconnects 1034 is located in and spaced apart by a fourth ILD layer 1032 above the third ILD layer 1022. Individuals of the fourth plurality of conductive intermediate interconnects 1034 encompass the second conductive barrier material 1026 along side walls and a bottom surface of the second conductive filler material 1028. Individuals of the fourth plurality of conductive intermediate interconnects 1034 are located along the second direction 1099.

[0131] A fifth plurality of conductive intermediate interconnects 1044 is located in and spaced apart by a fifth ILD layer 1042 above the fourth ILD layer 1032. Individuals of the fifth plurality of conductive intermediate interconnects 1044 encompass the second conductive barrier material 1026 along side walls and a bottom surface of the second conductive filler material 1028. Individuals of the fifth plurality of conductive intermediate interconnects 1044 are located along the first direction 1098.

[0132] A sixth plurality of conductive intermediate interconnects 1054 is located above the fifth ILD layer in a sixth ILD layer 1052 and is spaced by it. Individuals of the sixth plurality of conductive intermediate interconnects 1054 encompass the second conductive barrier material 1026 along side walls and a bottom surface of the second conductive filler material 1028. Individuals of the sixth plurality of conductive intermediate interconnects 1054 are located along the second direction 1099.

[0133] In one embodiment, the second conductive filler material 1028 consists essentially of copper, and the first conductive filler material 1008 consists essentially of cobalt. In another embodiment, the first conductive filler material 1008 comprises copper with a first concentration of a dopant atom, and the second conductive filler material 1028 comprises copper with a second concentration of the dopant atom, wherein the second concentration of the dopant atom is lower than the first concentration of the dopant atom.

[0134] In one embodiment, the composition of the first conductive barrier material 1006 differs from that of the second conductive barrier material 1026. In another embodiment, the first conductive barrier material 1006 and the second conductive barrier material 1026 have the same composition.

[0135] In one embodiment, a first conductive via 1019 is located on a single 1004A of the first plurality of conductive intermediate connections 1004 and is electrically coupled to it. A single 1014A of the second plurality of conductive intermediate connections 1014 is located on the first conductive via 1019 and is electrically coupled to it.

[0136] A second conductive via 1029 is located on a single 1014B of the second plural of conductive intermediate connections 1014 and is electrically coupled to it. A single 1024A of the third plural of conductive intermediate connections 1024 is located on the second conductive via 1029 and is electrically coupled to it.

[0137] A third conductive via 1039 is located on a single 1024B of the third plural of conductive intermediate connections 1024 and is electrically coupled to it. A single 1034A of the fourth plural of conductive intermediate connections 1034 is located on the third conductive via 1039 and is electrically coupled to it.

[0138] A fourth conductive via 1049 is located on a single 1034B of the fourth plural of conductive intermediate connections 1034 and is electrically coupled to it. A single 1044A of the fifth plural of conductive intermediate connections 1044 is located on the fourth conductive via 1049 and is electrically coupled to it.

[0139] A fifth conductive via 1059 is located on a single 1044B of the fifth plural of conductive intermediate connections 1044 and is electrically coupled to it. A single 1054A of the sixth plural of conductive intermediate connections 1054 is located on the fifth conductive via 1059 and is electrically coupled to it.

[0140] In one embodiment, the first conductive via 1019 comprises the first conductive barrier material 1006 along side walls and a bottom surface of the first conductive filler material 1008. The second 1029, third 1039, fourth 1049 and fifth 1059 conductive vias comprise the second conductive barrier material 1026 along side walls and a bottom surface of the second conductive filler material 1028.

[0141] In one embodiment, the first 1002, second 1012, third 1022, fourth 1032, fifth 1042, and sixth 1052 ILD layers are separated from each other by a corresponding etch stop layer 1090 between adjacent ILD layers. In one embodiment, the first 1002, second 1012, third 1022, fourth 1032, fifth 1042, and sixth 1052 ILD layers comprise silicon, carbon, and oxygen.

[0142] In one embodiment, some of the first 1004 and second 1014 majority of the conductive intermediate connecting lines have a first width (W1). Some of the third 1024, fourth 1034, fifth 1044 and sixth 1054 majority of the conductive intermediate connecting lines have a second width (W2) that is greater than the first width (W1).

[0143] In one aspect, one or more of the embodiments described here relate to approaches for forming non-conductive spaces or breaks between metal conductors (also referred to as "conductor ends," "plugs," or "cuts") and, in some embodiments, between associated conductive vias. Conductive vias are, by definition, used such that they terminate on a previous layered metal structure. In this sense, the embodiments described here enable a more robust fabrication scheme for the intermediate connections, as the dependence on alignment by lithography equipment is reduced. Such a fabrication scheme for intermediate connections can be used to relax constraints regarding alignment / exposure; it can be used to improve electrical contact (e.g.,by reducing a via resistance); and it can be used to reduce the overall processing steps and processing time that would otherwise be required to structure these features when using conventional approaches.

[0144] It is understood that dielectric plugs whose composition differs from that of the ILD material in which they are housed may only be present in selected metallization layers, such as lower metallization layers. As an example, this is illustrated Fig. 11 A cross-sectional view of a stack of metallization layers according to an embodiment of the present disclosure, comprising a conductive conduit plug in place of a lower metal conduit. It is understood that one or more of the intermediate connections or layers of intermediate connections, which are in conjunction with Fig. 11 described, can be coupled with a FEOL nanowire stack fuse, as described above.

[0145] With reference to Fig. 11 comprises an integrated circuit structure 1150 comprising a first plurality of conductive interconnects 1156 in and spaced apart by a first dielectric intermediate layer (ILD layer) 1154 above a substrate 1152. Individuals of the first plurality of conductive interconnects 1156 run continuously, interrupted by one or more dielectric plugs 1158. In one embodiment, the one or more dielectric plugs 1158 comprise a material other than the ILD layer 1152. A second plurality of conductive interconnects 1166 are located in and spaced apart by a second ILD layer 1164 above the first ILD layer 1154. In one embodiment, individuals of the second plurality of conductive interconnects 1166 run continuously, interrupted by one or more sections 1168 of the second ILD layer 1164.As shown, it is understood that other metallization layers may be included in the integrated circuit structure 1150.

[0146] In one embodiment, the one or more dielectric plugs 1158 comprise a metal oxide material. In such an embodiment, the metal oxide material is aluminum oxide. In another embodiment, the first ILD layer 1154 and the second ILD layer 1164 (and therefore the one or more sections 1168 of the second ILD layer 1164) comprise a carbon-doped silicon oxide material.

[0147] In one embodiment, some of the first plurality of conductive intermediate connecting lines 1156 comprise a first conductive barrier lining 1156A and a first conductive filler material 1156B. Some of the second plurality of conductive intermediate connecting lines 1166 comprise a second conductive barrier lining 1166A and a second conductive filler material 1166B. In such an embodiment, the composition of the first conductive filler material 1156B differs from that of the second conductive filler material 1166B. In a particular such embodiment, the first conductive filler material 1156B comprises cobalt and the second conductive filler material 1166B comprises copper.

[0148] In one embodiment, the first plurality of conductive interconnects 1156 have a first grid dimension (P1, as shown in comparison layer 1170). The second plurality of conductive interconnects 1166 have a second grid dimension (P2, as shown in comparison layer 1180). The second grid dimension (P2) is larger than the first grid dimension (P1). In another embodiment, some of the first plurality of conductive interconnects 1156 have a first width (W1, as shown in comparison layer 1170). Some of the second plurality of conductive interconnects 1166 have a second width (W2, as shown in comparison layer 1180). The second width (W2) is larger than the first width (W1).

[0149] It is understood that the layers and materials described above in connection with back-end-of-line structures and processing (BEOL structures and processing) can be formed on or above an underlying semiconductor substrate or structure, such as one or more underlying device layers of an integrated circuit. In one embodiment, the underlying semiconductor substrate represents a general working object used to fabricate integrated circuits. The semiconductor substrate often comprises a wafer or other component made of silicon or another semiconductor material.Suitable semiconductor substrates include, among others, single-crystal silicon, polycrystalline silicon, and silicon-on-insulator (SOI), as well as similar substrates composed of other semiconductor materials, such as germanium, carbon, or Group III-V materials. Depending on the fabrication stage, the semiconductor substrate often incorporates transistors, integrated circuits, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the depicted structures can be fabricated on underlying interconnect layers at lower levels.

[0150] Although the preceding procedures for producing a metallization layer or sections of a metallization layer, a BEOL metallization layer, are described in detail with reference to selection processes, it is understood that additional operations or intermediate manufacturing operations include standard microelectronic manufacturing processes such as lithography, etching, thin-film deposition, planarization (such as chemical-mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, or any other action associated with the manufacture of microelectronic components.It is also understood that the process operations described for the preceding process flow can be carried out in alternative sequences, whereby not every operation has to be carried out, or additional process operations can be carried out, or both.

[0151] In one embodiment, as used throughout this description, the dielectric interlayer material (ILD material) is composed of or comprises a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known from the prior art, and combinations thereof. The dielectric interlayer material can be formed by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0152] In one embodiment, also used throughout this description, metal conductors or an interconnection material (and via material) are constructed from one or more metal or other conductive structures. A common example is the use of copper conductors and structures, which may or may not have barrier layers between the copper and the surrounding ILD material. As used here, the term "metal" includes alloys, stacks, and other combinations of several metals. For example, the metal interconnection conductors may have barrier layers (e.g., layers containing Ta, TaN, Ti, and / or TiN), stacks of different metals or alloys, etc. Thus, the interconnection conductors may be a single layer of material, or they may be formed from multiple layers, including conductive lining layers and filler layers.Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form interconnects. In one embodiment, the interconnects are made of a conductive material such as Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. In the field, these interconnects are sometimes also referred to as conductors, wires, conductors, metal, or simply as interconnects.

[0153] In one embodiment, also used throughout this description, hard mask materials are composed of dielectric materials that differ from the dielectric interlayer material. In one embodiment, different hard mask materials can be used in different areas to achieve varying growth or etch selectivity with each other and with the underlying dielectric and metal layers. In some embodiments, a hard mask layer comprises a layer of silicon nitride (e.g., silicon nitride), a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hard mask material comprises a metal species.For example, a hard mask or other overlying material may have a layer of titanium nitride or another metal (e.g., titanium nitride). Potentially, smaller amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, depending on the specific implementation, other hard mask layers known in the field may be used. The hard mask layers can be fabricated by CVD, PVD, or other deposition methods.

[0154] In one embodiment, also used throughout this description, lithographic processes are performed using 193 nm immersion lithography (i193), extreme ultraviolet lithography (EUV lithography), or electron beam lithography as a direct writing process (EBDW lithography), or the like. A positive or negative photoresist may be used. In one embodiment, a lithographic mask is a three-layer mask consisting of a topographic masking section, an antireflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking section is a carbon hardmask (CHM) layer, and the antireflective layer is a silicon ARC layer.

[0155] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits or microelectronic components. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processing units (GPUs), digital signal processors (DSPs), microcontrollers, and the like. In other embodiments, semiconductor memory can be manufactured. Furthermore, the integrated circuits or other microelectronic components can be used in a wide variety of electronic devices known in the field. For example, in computer systems (e.g., a desktop computer, laptop computer, server), mobile phones, consumer electronics, etc. The integrated circuits can be coupled to a bus and other components in the systems. For example, a processor can be coupled to a memory device, a chipset, etc., via one or more buses.Both the processor, the memory, and the chipset can potentially be manufactured using the approaches disclosed here.

[0156] Fig. Figure 12 describes a computing device 1200 according to an implementation of the disclosure. A circuit board 1202 is housed within the computing device 1200. The circuit board 1202 can comprise a number of components, including, among others, a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the circuit board 1202. In some implementations, the at least one communication chip 1206 is also physically and electrically coupled to the circuit board 1202. In other implementations, the communication chip 1206 forms part of the processor 1204.

[0157] Depending on the application, the computer device 1200 may include other components, which may or may not be physically and electrically coupled to the circuit board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a loudspeaker, a camera, and a mass storage device (such as a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), and the like).

[0158] The 1206 communication chip enables wireless communication for the transmission of data to and from the 1200 computing device. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., by which data can be transmitted through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices contain no wires whatsoever, although this may be the case in some embodiments. The 1206 communication chip can implement any number of wireless standards or protocols, including, but not limited to, WiFi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), and IEEE 802.11.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. The computing device 1200 can include a plurality of communication chips 1206. For example, a first communication chip 1206 can be designated for shorter-range wireless communication, such as WiFi and Bluetooth, and a second communication chip 1206 can be designated for longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0159] The processor 1204 of the computing device 1200 comprises an integrated circuit die that is housed within the processor 1204. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor has one or more structures, for example, integrated circuit structures, constructed according to implementations of the disclosure. The term "processor" can refer to any device or any section of a device that processes electronic data from registers or a memory or both in order to convert such electronic data into other electronic data that can be stored in registers or a memory or both.

[0160] The communication chip 1206 also includes an integrated circuit die, which is housed within the communication chip 1206. According to another implementation of the disclosure, the integrated circuit die of the communication chip is constructed according to implementations of the disclosure.

[0161] In further implementations, another component housed within the computing device 1200 may contain a die with integrated circuit constructed according to implementations of embodiments of the disclosure.

[0162] In various embodiments, the Computing Device 1200 can be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultramobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other implementations, the Computing Device 1200 can be any other electronic device that processes data.

[0163] Fig. Reference 13 describes an interposer 1300 comprising one or more embodiments of the disclosure. The interposer 1300 is an intermediate substrate used as a bridge from a first substrate 1302 to a second substrate 1304. The first substrate 1302 can, for example, be an integrated circuit die. The second substrate 1304 can, for example, be a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of an interposer 1300 is to spread a connection to a wider grid dimension or to redirect a connection to another connection. For example, an interposer 1300 can couple an integrated circuit die to a ball grid array (BGA) 1306, which can then be coupled to the second substrate 1304.In some embodiments, the first and second substrates 1302 / 1304 are attached to opposite sides of the interposer 1300. In other embodiments, the first and second substrates 1302 / 1304 are attached to the same side of the interposer 1300. And in further embodiments, three or more substrates are connected to each other via the interposer 1300.

[0164] The Interposer 1300 can be made from an epoxy resin, a glass fiber-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the Interposer 1300 can be made from alternating rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials.

[0165] The interposer 1300 can include metal interconnects 1308 and vias 1310, including, but not limited to, silicon vias (TSVs) 1312. The interposer 1300 can further include embedded components 1314, comprising both passive and active components. These components include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and ESD (electrostatic discharge) components. More complex components, such as high-frequency (HF) components, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, can also be implemented on the interposer 1300.According to embodiments of the disclosure, the facilities or processes disclosed herein can be used in the manufacture of the Interposer 1300 or in the manufacture of components contained in the Interposer 1300.

[0166] Fig. Figure 14 is an isometric view of a mobile computing platform 1400 in which an integrated circuit (IC) is used which was manufactured according to one or more of the processes described herein or which includes one or more of the features described herein, according to an embodiment of the present disclosure.

[0167] The mobile computing platform 1400 can be any portable device designed for displaying electronic data, processing electronic data, and transmitting electronic data wirelessly. For example, the mobile computing platform 1400 can be a tablet, a smartphone, a laptop computer, etc., and includes a screen 1405, which in this embodiment is a (capacitive, inductive, resistive, etc.) touchscreen, an integrated system at the chip level (SoC) or at the package level 1410, and a battery 1413.The higher the level of integration in the System 1410, made possible by a higher transistor packing density, the greater the proportion of the Mobile Computing Platform 1400 that the Battery 1413 or non-volatile storage such as a solid-state drive can occupy, or the greater the number of transistor gates for improved platform functionality, as illustrated. Likewise, the functionality increases with the greater charge carrier mobility at each transistor in the System 1410. Therefore, the techniques described here can enable improvements in performance and form factor in the Mobile Computing Platform 1400.

[0168] The integrated system 1410 is further shown in the enlarged view 1420. In the exemplary embodiment, the enclosed device 1477 comprises at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or a graphics processor) manufactured according to one or more of the processes described herein or having one or more of the features described herein. The enclosed device 1477 is further coupled to the circuit board 1460, together with a power management integrated circuit (PMIC) 1415 and / or an integrated (wireless) RF integrated circuit (RFIC) 1425, which includes a (wireless) broadband RF transmitter and / or receiver (e.g., with a digital baseband and an analog front-end module, further comprising a power amplifier on a transmit path and a low-noise amplifier on a receive path), and a controller therefor 1411.The PMIC 1415 functionally performs battery power regulation, DC-to-DC conversion, etc., and therefore has an input coupled to the battery 1413 and an output that powers all other functional modules. As further illustrated, in the exemplary embodiment, the RFIC 1425 has an output coupled to an antenna to provide an implementation of any number of wireless standards or protocols, including, but not limited to, WiFi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond.In alternative implementations, each of these modules can be integrated at the board level on separate ICs coupled to the package substrate of the packaged device 1477, or in a single IC (SoC) coupled to the package substrate of the packaged device 1477.

[0169] In another aspect, semiconductor packages are used to protect an integrated circuit chip or die (IC chip or die) and to provide the die with an electrical interface to an external circuit arrangement. With the increasing demand for smaller electronic devices, semiconductor packages are being designed to be even more compact and to support higher circuit densities. Furthermore, the demand for higher-performance devices is creating a need for improved semiconductor packages that allow for a thin package profile and low overall distortion, compatible with subsequent processing of the assembly.

[0170] In one embodiment, wire bonding is used on a ceramic or organic package substrate. In another embodiment, a C4 process is used to mount a die onto a ceramic or organic package substrate. In particular, C4 solder ball connections can be used to create flip-chip interconnects between semiconductor devices and substrates. A flip-chip connection, or C4 connection (controlled collapse chip connection), is a type of mounting used for semiconductor devices such as integrated circuit (IC) chips, MEMS, or components that use solder pads instead of wire bonds. The solder pads are deposited on the C4 pads located on the top side of the substrate package. To mount the semiconductor device onto the substrate, it is flipped so that the active side faces down toward the mounting surface.The solder points are used to connect the semiconductor device directly to the substrate.

[0171] Fig. Figure 15 illustrates a cross-sectional view of a chip mounted in flip-chip assembly according to an embodiment of the present disclosure.

[0172] With reference to Fig.Figure 15 comprises a device 1500 comprising a die 1502, such as an integrated circuit (IC), which is manufactured according to one or more processes described herein or incorporates one or more features described herein, according to an embodiment of the present disclosure. The die 1502 has metallized pads 1504 arranged thereon. A housing substrate 1506, for example a ceramic or organic substrate, has connections 1508 arranged thereon. The die 1502 and the housing substrate 1506 are electrically connected by solder balls 1510, which are coupled to the metallized pads 1504 and the connections 1508. An underfill material 1512 surrounds the solder balls 1510.

[0173] The processing of a flip chip can be similar to conventional IC manufacturing, with a few additional steps. Near the end of the manufacturing process, the mounting pads are metallized to make them more receptive to solder. This typically involves several treatments. A small dot of solder is then applied to each metallized pad. The chips are then cut from the wafer as usual. To integrate the flip chip into a circuit, the chip is flipped over so that the solder dots face down onto leads on the underlying electronics or printed circuit board. The solder is then remelted to create an electrical connection, usually using an ultrasonic or, alternatively, a reflow soldering process. This also leaves a small gap between the chip's circuitry and the underlying mounting.In most cases, an electrically insulating adhesive is then "underfilled" to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joints are not stressed due to differential heating of the chip and the rest of the system.

[0174] In other embodiments, newer package and die-to-die interconnection approaches, such as silicon vias (TSV) and silicon interposers, are implemented according to an embodiment of the present disclosure to fabricate a high-performance multi-chip module (high-performance MCM) and system-in-package (SiP) containing an integrated circuit (IC) that is fabricated according to one or more of the processes described herein or incorporates one or more of the features described herein.

[0175] This revealed front-end-of-line (FEOL) nanowire stack fuses.

[0176] The above description of illustrated implementations of embodiments of the disclosure, including the description in the abstract, is not intended to be exhaustive or to limit the disclosure to precisely the disclosed forms. Although specific implementations of the disclosure and examples thereof are described here for illustrative purposes, various equivalent modifications are possible within the scope of protection of the disclosure, as those skilled in the field will recognize. These modifications can be made to the disclosure taking into account the above detailed description. The terms used in the following claims are not to be understood as limiting the disclosure to the specific implementations disclosed in the description and the claims.

[0177] Even though specific embodiments have been described above, these embodiments are not intended to limit the scope of protection of the present disclosure, even if only a single embodiment is described with respect to a particular feature. Examples of features listed in the disclosure are intended to be illustrative rather than limiting, unless otherwise stated. The foregoing description is intended to cover such alternatives, modifications, and equivalents as are obvious to a person skilled in the art with knowledge of the present disclosure.

[0178] The scope of protection of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, regardless of whether it mitigates any one or all of the problems addressed herein. Accordingly, during the further pursuit of the present application (or an application claiming priority thereof), new claims may be formulated for any such combination of features. In particular, with reference to the accompanying claims, features from dependent claims may be combined with those of the independent claims, and features from respective independent claims may be combined in any suitable manner, not limited to the specific combinations listed in the accompanying claims.

[0179] Various embodiments or aspects of the disclosure are described herein. In some implementations, the different embodiments are implemented separately. However, the embodiments are not limited to isolated implementations. For example, two or more different embodiments can be combined to be implemented as a single device, a single process, a single structure, or the like. In some cases, the entirety of different embodiments can be combined. In other cases, parts of a first embodiment can be combined with parts of one or more other embodiments.For example, a part of a first embodiment can be combined with a part of a second embodiment, or a part of a first embodiment can be combined with a part of a second embodiment and a part of a third embodiment. The following examples relate to further embodiments. The various features of the different embodiments can be combined in different ways, including some features and excluding others to enable a wide variety of applications.

[0180] Exemplary embodiment 1: An integrated circuit structure comprises a fin containing a stack of alternating nanowire layers and interlayers, with a gap provided between the upper two nanowire layers by the absence of an interlayer between them. A gate stack is located above the fin, the gate stack comprising a gate electrode metal along the sides of the fin and in the gap.

[0181] Exemplary embodiment 2: The integrated circuit structure according to exemplary embodiment 1, which further comprises a gate-cut dielectric plug over the fin that laterally separates a first and a second section of the gate stack.

[0182] Exemplary embodiment 3: The integrated circuit structure according to exemplary embodiment 2, wherein the first section of the gate stack is an anode of a fuse, the second section of the gate stack is a cathode of the fuse, and the gate electrode in the gap is a fuse area of ​​the fuse.

[0183] Exemplary embodiment 4: The integrated circuit structure according to exemplary embodiment 1, 2 or 3, which further comprises a nanowire-based transistor that is laterally adjacent to the fin.

[0184] Exemplary embodiment 5: The integrated circuit structure according to exemplary embodiment 4, wherein the nanowire-based transistor has a gate stack that continuously transitions into the gate stack above the fin.

[0185] Exemplary embodiment 6: An integrated circuit structure comprises a fin containing a stack of alternating nanowire layers and interlayers, with a gap provided between the upper two nanowire layers by the absence of an interlayer between them. A gate stack is located above the fin, the gate stack comprising a gate electrode metal along the sides of the fin. A molten metal region is located in the gap and is coupled to the gate electrode metal.

[0186] Exemplary embodiment 7: The integrated circuit structure according to exemplary embodiment 6, which further comprises a gate-cut dielectric plug over the fin and laterally separates a first and a second section of the gate stack.

[0187] Exemplary embodiment 8: The integrated circuit structure according to exemplary embodiment 6 or 7, wherein the first section of the gate stack is an anode of a fuse, the second section of the gate stack is a cathode of the fuse, and the metal melting area in the gap is a blown melting area of ​​the fuse.

[0188] Exemplary embodiment 9: The integrated circuit structure according to exemplary embodiment 6, 7 or 8, which further comprises a nanowire-based transistor adjacent laterally to the fin.

[0189] Exemplary embodiment 10: The integrated circuit structure according to exemplary embodiment 9, wherein the nanowire-based transistor has a gate stack that continuously transitions into the gate stack above the fin.

[0190] Exemplary embodiment 11: A computing device comprises a circuit board and a component coupled to the circuit board. The component comprises an integrated circuit structure having a fin comprising a stack of alternating nanowire layers and interlayers, wherein a gap between the upper two nanowire layers is provided by a missing interlayer between the upper two nanowire layers. A gate stack is located above the fin, the gate stack comprising a gate electrode metal along the sides of the fin and in the gap; or a gate stack is located above the fin, the gate stack comprising a gate electrode metal along the sides of the fin, and a metal melting region is located in the gap and coupled to the gate electrode metal.

[0191] Exemplary embodiment 12: The computing device according to exemplary embodiment 11, comprising a gate stack above the fin, wherein the gate stack comprises the gate electrode metal along sides of the fin and in the gap.

[0192] Exemplary embodiment 13: The computing device according to exemplary embodiment 11, which has the gate stack above the fin, wherein the gate stack comprises the gate electrode metal along sides of the fin, and has the metal melting region in the gap that is coupled to the gate electrode metal.

[0193] Exemplary embodiment 14: Computing device according to exemplary embodiment 11, 12 or 13, which further comprises a memory coupled to the circuit board.

[0194] Exemplary embodiment 15: Computing device according to exemplary embodiment 11, 12, 13 or 14, which further comprises a communication chip coupled to the circuit board.

[0195] Exemplary embodiment 16: The calculating device according to exemplary embodiment 11, 12, 13, 14 or 15, which further comprises a battery coupled to the circuit board.

[0196] Exemplary embodiment 17: The computing device according to exemplary embodiment 11, 12, 13, 14, 15 or 16, which further comprises a camera coupled to the circuit board.

[0197] Exemplary embodiment 18: The calculating device according to exemplary embodiment 11, 12, 13, 14, 15, 16 or 17, which further comprises a display coupled to the circuit board.

[0198] Exemplary embodiment 19: The computing device according to exemplary embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a housed die with integrated circuit.

[0199] Exemplary embodiment 20: Computing device according to exemplary embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

[1] Integrated circuit structure, comprising: a fin comprising a stack of alternating nanowire layers and interlayers, wherein a gap between the upper two nanowire layers is provided by a missing interlayer between them; and a gate stack above the fin, wherein the gate stack comprises a gate electrode metal along sides of the fin and in the gap. [2] Integrated circuit structure according to claim 1, further comprising: a gate-cut dielectric plug over the fin, which laterally separates a first and second section of the gate stack. [3] Integrated circuit structure according to claim 2, wherein the first section of the gate stack is an anode of a fuse, the second section of the gate stack is a cathode of the fuse and the gate electrode in the gap is a fuse area of ​​the fuse. [4] Integrated circuit structure according to claim 1, 2 or 3, further comprising: a nanowire-based transistor that is laterally adjacent to the fin. [5] Integrated circuit structure according to claim 4, wherein the nanowire-based transistor has a gate stack which continuously transitions into the gate stack above the fin. [6] Integrated circuit structure, comprising: a fin comprising a stack of alternating nanowire layers and intermediate layers, wherein a gap between the upper two nanowire layers is provided by a missing intermediate layer between the upper two nanowire layers; a gate stack above the fin, wherein the gate stack comprises a gate electrode metal along sides of the fin; and a metal melting area in the gap that is coupled to the gate electrode metal. [7] Integrated circuit structure according to claim 6, further comprising: a gate-cut dielectric plug over the fin, which laterally separates a first and second section of the gate stack. [8] Integrated circuit structure according to claim 6 or 7, wherein the first section of the gate stack is an anode of a fuse, the second section of the gate stack is a cathode of the fuse and the metal melting area in the gap is a blown melting area of ​​the fuse. [9] Integrated circuit structure according to claim 6, 7 or 8, further comprising: a nanowire-based transistor that is laterally adjacent to the fin. [10] Integrated circuit structure according to claim 9, wherein the nanowire-based transistor has a gate stack which continuously transitions into the gate stack above the fin. [11] Computing device comprising: a circuit board and a component coupled to the circuit board, wherein the component has an integrated circuit structure, comprising: a fin comprising a stack of alternating nanowire layers and interlayers, wherein a gap between the upper two nanowire layers is provided by a missing interlayer between them; and a gate stack above the fin, wherein the gate stack comprises a gate electrode metal along sides of the fin and in the gap; or a gate stack above the fin, wherein the gate stack comprises a gate electrode metal along sides of the fin and a metal melting region in the gap coupled to the gate electrode metal. [12] Computing device according to claim 11, comprising a gate stack above the fin, wherein the gate stack comprises the gate electrode metal along sides of the fin and in the gap. [13] Computing device according to claim 11, comprising the gate stack above the fin, wherein the gate stack comprises the gate electrode metal along sides of the fin and the metal melting region in the gap coupled to the gate electrode metal. [14] Computing device according to claim 11, 12 or 13, further comprising: a memory that is coupled to the circuit board. [15] Computing device according to claim 11, 12, 13 or 14, further comprising: a communication chip that is coupled to the circuit board. [16] Computing device according to claim 11, 12, 13, 14 or 15, further comprising: a battery that is coupled to the circuit board. [17] Computing device according to claim 11, 12, 13, 14, 15 or 16, further comprising: a camera that is coupled to the circuit board. [18] Computing device according to claim 11, 12, 13, 14, 15, 16 or 17, further comprising: a display that is coupled to the circuit board. [19] Computing device according to claim 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a housed die with integrated circuit. [20] Computing device according to claim 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

Images