Mechanism for clock synchronization

Abstract

Method comprising: Receiving a series of time synchronization messages (310; 500; 700) at a first Peripheral Component Interconnect Express, PCIe, device (111-118, 141-145) via a PCIe bus from a second PCIe device (111-118, 141-145), wherein the time synchronization messages are each formatted as Transaction Layer Protocol Layout Packets, TLP, of the PCIe bus and each have a header that identifies the respective time synchronization message as such, and the time synchronization messages are used to compute a master time.

Description

GENERAL STATE OF THE ART This disclosure relates generally to the field of clock control and in particular to systems and methods for synchronizing clock signals between computer devices connected via a computer network. Precise time synchronization is difficult to achieve for devices connected via a network. Mechanisms such as the IEEE 802.1 AS / D5.0 standard, entitled "Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks," published on February 6, 2009, enable the standard network elements of such a system to maintain precise time synchronization. However, synchronization between different networks and other connection technologies can only be achieved through software mechanisms.Since precise timing of software processes is not supported on most CPU architectures, and since software communication via Peripheral Component Interconnect Express (PCIe) uses Transaction Layer Packets (TLPs) which are subject to queue delays and other non-deterministic delays (at least from the software's perspective), it is not possible to control the latency of communication between components. This leads to a significant reduction in accuracy, to the point where some applications cannot be supported at acceptable quality levels (e.g., multi-channel audio), and obviously requires specific system software, which is less desirable than a hardware solution. What is needed is a hardware mechanism that makes it possible to synchronize devices connected via a PCIe or PCIe-derived architecture (such as DMI (Direct Media Interface)) in terms of timing. DE 10 2007 045 083 A1 discloses a system comprising at least two IEEE 1588 nodes. The nodes are connected by two paths: a low-latency communication path and a high-bandwidth path. The clocks in the nodes are synchronized at a network interface. Data and timing are transmitted over the high-bandwidth path, while critical timing signals are forwarded over the low-latency communication path. The invention is defined in main claim 1 and in dependent claims 8 and 15. Embodiments of the invention are defined in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram illustrating a system capable of using PCIe packets according to several aspects of the present disclosure. Fig. 2 schematically illustrates an exemplary embodiment according to one aspect of the present disclosure. Fig. 3 is a schematic block diagram illustrating the structure of a PCIe packet according to several aspects of the present disclosure. Fig. 4 illustrates a modified frame formation mechanism used for first- and second-generation encoding (2.5 and 5 GT / s with 8b / 10b encoding) according to several aspects of the present disclosure. Fig. 5 illustrates a modified frame formation mechanism used for third-generation encoding (8 GT / s with 128b / 130b encoding) according to several aspects of the present disclosure.Figure 6 illustrates a protocol for exchanging messages that enables the elimination of communication delays according to several aspects of the present disclosure. Figure 7 is a software configuration mechanism implemented using a PCIe Enhanced Capability Structure according to several aspects of the present disclosure. DETAILED DESCRIPTION In the following description, similar components are identified by the same reference numerals, regardless of whether they are shown in different embodiments. For the clear and concise illustration of one or more embodiments of the present invention, the drawings are not necessarily to scale, and certain features may be shown in a somewhat schematic form. Features described and / or illustrated with respect to one embodiment may be used in the same or a similar manner in one or more other embodiments and / or together with or instead of the features of the other embodiments. According to several embodiments of this disclosure, a method is disclosed which includes sending a first message at a first time point from a master device to a target device in order to synchronize the time between the master device and the target device established via a network, wherein the target device communicates with the master device via a PCIe connection, wherein the first message includes a message indicator; and receiving a reply message from the target device to the master device at a subsequent time point, wherein the reply message includes the message indicator. According to several embodiments of this disclosure, a computer program product is disclosed comprising a computer-usable medium containing machine-readable program code, wherein the machine-readable program code is adapted to be executed to implement a method comprising appending a head to a transaction layer protocol layout packet at a master device for synchronizing the time between the master device and a target device established over a network, wherein the head is configured to identify the packet as a time synchronization packet; and sending the packet with the appended head from a master device to a target device for synchronizing the time between the master and the target device. According to several embodiments of this disclosure, a system is disclosed comprising a control unit configured to apply a modified frame to the head of a transaction layer protocol layout packet at a master device, the head being configured to identify the packet as a time synchronization packet; a sender configured to send the packet with the modified frame from the master device to a destination device to synchronize the time between the master device and the destination device; and a receiver configured to receive the sent packet. These and other features and properties, as well as the operating methods and functions of the associated structural elements and the combination of parts and manufacturing savings, will become apparent from consideration of the following description and the attached claims with regard to the accompanying drawings, all of which form part of this patent specification, with the same reference numerals designating corresponding parts in the various figures. It is expressly understood, however, that the drawings are provided solely for the purpose of illustration and description and are not intended to define the limitations of the claims. As used in the description and in the claims, the singular forms of "a," "an," "the," "a," and "a" include plural references unless the context clearly indicates otherwise. Now, regarding the various aspects of this revelation, most modern computing devices use input / output (I / O) adapters and buses that employ some version or implementation of the Peripheral Component Interconnect standard, originally created by Intel in the 1990s. The Peripheral Component Interconnect (PCI) standard specifies a computer bus for connecting peripheral devices to a computer motherboard. PCI Express, or PCIe, is an implementation of the PCI computer bus that uses existing PCI programming concepts but in which the computer bus is based on a completely different and much faster serial communication protocol at the physical layer. The physical layer does not consist of a bidirectional bus that can be shared by multiple devices, but rather of individual unidirectional connections that are linked to exactly two devices. Although sections of this discussion relate to PCIe communications or devices for illustrative purposes, embodiments of the invention can be used with other types of communications or devices, for example, with communications or devices that utilize the transmission of packetized data over high-speed serial links, communications or devices that utilize flow-control-based link management, communications or devices that utilize credit-based flow control, communications or devices that utilize a purely serial interface, communications or devices that utilize a split-transaction protocol implemented with allocated packets, communications or devices that prioritize packets for improved or optimal packet transmission, communications or devices that utilize scalable links that use one or more lanes (e.g.,Point-to-point connections), communications or devices that use a high-speed serial connection, communications or devices that use differentiation between different traffic types, communications or devices that use a highly reliable data transmission mechanism (e.g., using serial numbers and / or end-to-end cyclic redundancy check (ECRC)), communications or devices that use a data link layer to achieve the integrity of the transmitted data, communications or devices that use a physical layer of two differentially controlled pairs of low-voltage signals (e.g.,a transmit pair and a receive pair), communications or devices that use link initialization that includes negotiating lane widths and operating frequencies, communications or devices that only allow sending a data packet if it is known that the receive buffer is available on the receiving side to receive the packet, communications or devices that use request packets and / or response packets, communications or devices that use message space and / or message signaled interrupt (MSI) and / or in-band messages, communications or devices that use a software layer configuration space, communications or devices that use a maximum payload size (MPS) parameter, or the like. Fig. 1 schematically illustrates a block diagram of a system 100 capable of utilizing PCIe packets that incorporate a modified frame formation mechanism according to some illustrative embodiments of the invention. The system 100 may, for example, be or comprise a computing device, a computer, a personal computer (PC), a server computer, a client-server system, a mobile computer, a portable computer, a laptop, a notebook, a tablet computer, a network of interconnected devices, or the like. The System 100 can, for example, include a processor 111, an input unit 112, an output unit 113, a RAM / ROM unit 114, a memory unit 115, a communication unit 116, and a graphics card 117. The System 100 can optionally include other suitable hardware and / or software components. The processor 111 can, for example, comprise a central processing unit (CPU), a digital signal processor (DSP), a microprocessor, a host processor, a control unit, multiple processors or control units, a chip, a microchip, one or more circuits, a logic unit, an integrated circuit (IC), an application-specific integrated circuit (ASIC), or any other suitable general-purpose or specific processor or control unit. The processor 111 can execute instructions, for example, from an operating system (OS) 171 of the system 100 or from one or more software applications 172. The input unit 112 may, for example, include a keyboard, keypad, mouse, touchpad, stylus, microphone, or other suitable pointing or input device. The output unit 113 may, for example, include a cathode ray tube monitor or display unit, a liquid crystal monitor or display unit (LCD), a screen, a monitor, a loudspeaker, or other suitable display or output device. The graphics card 117 may, for example, include a graphics or video processor, adapter, control unit, or accelerator. The RAM / ROM unit 114 may, for example, include random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, volatile memory, non-volatile memory, cache memory, buffer, short-term memory unit, long-term memory unit, or other suitable RAM / ROM units or memory units. The memory unit 115 may, for example, include a hard disk drive, a floppy disk drive, a CD drive (compact disk), a CD-ROM drive, a DVD drive (digital versatile disk), or other suitable removable or non-removable memory units. The RAM / ROM unit 114 and / or memory unit 115 may, for example, store data that is processed by the system 100. The communication unit 116 may, for example, include a wired or wireless network interface card (NIC), a wired or wireless modem, a wired or wireless receiver and / or transmitter, a wired or wireless transceiver and / or transmit / receive device, a radio frequency (RF) communication unit or transmit / receive device, or other units capable of transmitting and / or receiving signals, blocks, frames, transmit streams, packets, messages, and / or data. The communication unit 116 may optionally include, for example, one or more antennas, such as a dipole antenna, a monopole antenna, an omnidirectional antenna, an end-fed antenna, a circularly polarized antenna, a microstrip antenna, a diversity antenna, or the like. In some embodiments, the components of System 100 may, for example, be enclosed in a common housing, packaging, or the like, and be interconnected or operationally linked using one or more wired or wireless connections. In other embodiments, components of System 100 may, for example, be distributed across multiple or separate devices, operate using a client / server configuration or system, communicate using remote access methods, or the like. The System 100 may further include a PCIe host bridge 120, which is capable of connecting between multiple components of the System 100, e.g., between multiple PCIe devices or PCIe endpoints. The PCIe host bridge 120 may include a memory bridge 121 or another memory control unit to which the RAM / ROM unit 114 and / or the graphics card 117 may be connected. The PCIe host bridge 120 may further include an input / output (I / O) bridge 122 to which the input unit 112, the output unit 113, the storage unit 115, the communication unit 116, and one or more USB (Universal Serial Bus) devices 118 may be connected. The system 100 may further include a PCIe switch 125 capable of connecting between multiple PCIe devices or PCIe endpoints. In some embodiments, the PCIe switch 125 may be implemented as a separate or independent unit or component; in other embodiments, the PCIe switch 125 may be integrated, embedded, or otherwise implemented using the PCIe host bridge 120 or another suitable component. The topology or architecture of Fig. 1 is shown for illustrative purposes, and embodiments of the invention can be used in conjunction with other suitable topologies or architectures. For example, in some embodiments, the memory bridge 121 is implemented as a memory control unit and is contained in or embedded within the PCIe host bridge 120. In some embodiments, a northbridge or a southbridge is used, optionally comprising the PCIe host bridge 120 and / or a similar PCIe host component. In some embodiments, the memory bridge 121 and the PCIe host bridge 120 (and optionally the processor 111) are implemented using a single or common integrated circuit or using multiple integrated circuits. Other suitable topologies or architectures may also be used. The PCIe host bridge 120 and / or the PCIe switch 125 can connect multiple PCIe devices or endpoints, for example, endpoints 141 to 145. Some PCIe devices or endpoints (e.g., PCIe endpoints 141 and 142) are directly connected via the PCIe host bridge 120; whereas other PCIe endpoints (e.g., PCIe endpoints 143 to 145) are indirectly connected using the PCIe switch 125.Some embodiments permit or enable communications using PCIe packets with a modified framing mechanism only between (or below) PCIe devices or endpoints directly connected via the PCIe host bridge 120 (namely, only between endpoints 141 and 142); and do not permit or enable communications using PCIe packets with a modified framing mechanism between (or below) PCIe devices or endpoints that are indirectly connected or not directly connected via the PCIe host bridge 120 or indirectly connected via the PCIe switch 125 (namely, below endpoints 143 to 145 or between endpoint 141 and endpoints 143 to 145 or between endpoint 142 and endpoints 143 to 145). The PCIe host bridge 120 and / or the PCIe switch 125 can connect to multiple PCIe endpoints or PCIe devices, for example, endpoints 141 to 145. For illustrative purposes, PCIe endpoint 141 can send data to memory bridge 121 via ports 151 and 152; accordingly, endpoint 141 is referred to here as the "send endpoint" or "transmitter," whereas memory bridge 121 is referred to as the "receive endpoint" or "receiver." Other components can operate as a transmitter and / or a receiver. For example, processor 111 can be a transmitter and RAM / ROM unit 114 can be a receiver; USB device 118 can be a transmitter and storage unit 115 can be a receiver. The storage bridge 121 can be operated as a receiving device (e.g., in relation to a first endpoint or component) and / or as a transmitting device (e.g.,operated opposite a second endpoint or component); or the like. In some embodiments, the receiving device can send data or control data back to the transmitting device or vice versa; for example, the communication between the transmitting device and the receiving device can be unilateral or bilateral. Fig. 2 schematically illustrates an exemplary embodiment according to one aspect of the present disclosure. The disclosure can be applied to a wide range of applications, from the synchronization of multiple audio channels in an audio-video system, generally shown at 200, to industrial applications in plant and machinery and test instrument equipment. The notebook 205, which includes components such as a CPU, a chipset, high-resolution audio (e.g., Azalia from Intel), and wired Gigabit Ethernet, is connected to the front speakers 210 and the subwoofer 215. The notebook 205 is connected via the connection 225 (e.g., PCIe, DMI) to a wireless access point 220 (e.g., WiFi, wireless Ethernet). The rear speakers 230 are connected to the notebook 205 via the wireless access point 220.The networks can be replaced with other networking or connection technologies / mechanisms, such as USB (Universal Serial Bus), Bluetooth, other PAN (Personal Area Network), high-resolution (High Definition - HD) audio, etc., as can be seen. In systems like the one shown in Fig. 2, precise time synchronization (accuracy – microseconds) is required to maintain the correct phase relationships between the sound produced by the front speakers 210 and the rear speakers 230 for the listener. This cannot be achieved in conventional systems because there is no precise mechanism for controlling the "display time" for the front speakers 210 and the rear speakers 230. Since the latency due to the WiFi connection is relatively long, it is necessary to buffer and delay the signals displayed for the front speakers 210. However, because the WiFi latency is not precisely controlled, without precisely synchronized local clocks, conventional methods can at best only approximate the expected latency and delay the signals from the front speakers accordingly.With precisely synchronized local clocks, the audio data can specify a "presentation time" that is maintained by the loudspeakers, making it possible to buffer the data itself with only loose conditions necessary to avoid buffer underflow / overflow conditions. Figure 3 schematically illustrates the structure of a PCIe packet 310 comprising a message switching mechanism used in conjunction with a modified frame-forming mechanism for exchanging time-sampling information according to several aspects of the present disclosure. Although sections of the present discussion relate, for example, to a PCIe TLP structure utilizing 64-bit addressing, the embodiments of the disclosure are not limited in this respect and can be used in conjunction with other PCIe TLP structures, for example, structures utilizing 32-bit addressing, or other suitable structures or sizes. Package 310 is a four-doubleword structure comprising a header section 320, a data section 330, and a summary section (not shown). The terms "doubleword" or "D-word" or "DW," as used here, can refer to, for example, a data unit that is four bytes in size. The first line, 311, specifies the byte offset (for example, +0, +1, +2, and +3); and the second line, 312, specifies the number of bits (for example, eight bits numbered from 0 to 7). The header, 320, comprises fields of control information (which include, for example, a format field, a type field, a length field, an ID field, a tag field, and the like) that occupy eight bytes, as specified in lines 313 and 314. Line 315 is a 64-bit address that is reserved. Lines 313 to 315 correspond to header section 320 of package 310. Data section 330 of TLP 310 is used to carry payload data where applicable. Some TLPs may include a payload section 330, while others may not. Data section 330 may include one or more specific bits, flags, or fields of header 330. For example, M bit or flag 332 and / or reserved field 333 may be used to indicate whether the message is sent by the time master on a particular link or by the time target. The TNumber field 334 may be used to specify the sequential number of this measurement, which is used by the receiver to correlate timestamps. The TimeSampleNS field 335 may be used to specify a sampled time value in nanoseconds, for example, for measurement TNumber-1 (mod 256).The TimeDiffNS field 336 can be used to specify a time difference value in nanoseconds, for example for the measurement TNumber-1 (mod 256). The overview section (not shown) includes an optional TLP overview that can be appended to the TLP. In some respects, package 310 includes additional essential or non-ECRC data that is stored and / or carried in the space corresponding to a TLP overview. The additional space in the overview does not store ECRC information and instead stores other or alternative information, such as application-specific or non-ECRC data. In some respects, the head of TLP 310 includes one or more indicator bits, flags, or fields to indicate the presence of a TLP overview containing application-specific or non-ECRC data. For example, a TLP overview indicator bit (TD) 399 can indicate the presence of an overview. One or more specific bits, flags, or fields of head 320, such as reserved bit 397 and / or reserved field 398, can be used to indicate that the overview contains application-specific or non-ECRC data, to indicate that the overview does not contain ECRC information, to indicate that ECRC checking is to be ignored, and / or to indicate that essential data or non-ECRC data is to be read or acquired from the space corresponding to the TLP overview or from a predefined portion of that space (e.g., by the receiving device). Figure 4 illustrates a modified frame formation mechanism used for first- and second-generation encoding (2.5 and 5 GT / s with 8b / 10b encoding) according to several aspects of this disclosure. The structure of a PCIe packet includes a modified frame formation message relay mechanism for exchanging time-sampling information. A TLP with unchanged frame formation is shown above, and the Time Sync TLP with modified frame formation is shown below. The section labeled "TLP message" for the Time Sync TLP is shown in Figure 3. The fields Seq[11:0] and LCRC[31:0] are the sequence number and connect to the CRC added by the data link layer. One difference is the use of the STS start symbol instead of the STP frame formation symbol. Fig. 5 illustrates a modified frame-building mechanism used for third-generation encoding (8 GT / s with 128b / 130b encoding) according to several aspects of the present disclosure. Fig. 5 is analogous to Fig. 4, except that, unlike the first- and second-generation encoding shown in Fig. 4, Fig. 5 shows the third generation. The time synchronization transport layer protocol packet 500 includes the header 501, which is configured to identify the packet 500 as containing time synchronization information. Field 502 includes Len[10:0], which refers to the length of the entire packet. For example, the length can be represented as four bytes of double words (DW). Field 504 includes Seq[11:0], which is the TLP sequence number. Field 503 includes Check[4:0], which provides data integrity for the Len, Check, and Seq fields. Instead of a frame-building symbol STS, as shown in Fig.As shown in Figure 4, the four-bit field 501 at the beginning identifies the type of packet, such that a normal TLP can be distinguished from a time-sync message as the physical layer. Field 505, labeled "TLP message," is again the packet shown in Figure 3. It should be noted that Figures 4 and 5 are not to scale. Figure 6 is a protocol for exchanging modified messages which, according to several aspects of the present disclosure, enables the elimination of communication delays. At time t1ns, the master device sends a TimeSync message to a destination device. The destination device receives the message at time t2n. The TimeSync message comprises M bits, or flag 332 set to 1, TNumber field 134 set to n, TimesamplesNS field 135 set to t1n-1, and TimeDiffNS field 136 set to t4n-1-t1n-1. For example, the format of the TimeSync message would be TimeSync(M:=1, TNumber:=n, TimeSampleNS:=t1n-1, TimeDiffNS:=(t4n-1-t1n-1)). The master device maintains the TNumber counter and sets TNumber++ in every TimeSync message. The master device also sets M:=1 and retains t1 and t4.In response, the target device sends the TimeSync message at time t3n, and the master device receives the TimeSync message at time t4n. The TimeSync message sent by the target device at time t3n includes TimeSync (M:= 0, TNumber:= n, TimeSampleNS:= . <undefined>, TimeDiffNS: = <undefined>The target device responds to each received TimeSync message, retains the received TNumber, and outputs it as a response, setting M = 0. The time values ​​reflect actual send / receive times for successful TLP transmissions. Values ​​corresponding to failed TLPs must be discarded. At time t1n+1, the master device sends a TimeSync message to a target device. The target device receives the message at time t2n+1. For example, the format of the TimeSync message would be TimeSync(M:=1, TNumber:=n + 1 mod 256, TimeSampleNS:=t1n, TimeDiffNS:=(t4n+t1n)). In response, the target device sends the TimeSync message at time t3n+1, and the master device receives the TimeSync message at time t4n+1. The TimeSync message sent by the target device at time t3n+1 includes TimeSync(M:=0, TNumber:=n + 1 mod 256, TimeSampleNS:= <undefined>, TimeDiffNS: = <undefined>). Special symbols, known as K-codes, used in PCIe 2.5GT / s and 5GT / s operating modes are shown in Table 1. As shown in the table, a new K-code, K28.6, is used with PCIe versions 2.5GT / s and 5GT / s for Start of Time Sync Messages (TLPs). Table 1 K28.5COMComma Use for lane and connection initialization and management K27.7STPStart TLP marks the beginning of a transaction layer package K28.2SDPStart DLLP marks the beginning of a data link layer package. K29.7EndEnd marks the end of a transaction layer packet or a data link layer packet. K30.7EDBEnD BadMarks the end of a cancelled TLP K23.7PADPad Used in frame formation and in negotiating link width and lane order K28.0SKPSkip Used to compensate for different bit rates between two communicating ports K28.1FTSFast TrainingSequence Use in an ordered set to exit L0s to L0 K28.3IDLIdleUse in the Electrical Idle Ordered Set (EIOS) K28.4 Reserved K28.6STSStart TimeSync TLPStart Time Sync TLP K28.7EIEE Electrical Idle Exit Reserved in 2.5GT / s Use in Electrical Idle Exit Ordered Set (EIEOS) and transmission before sending the FTS at speeds other than 2.5GT / s Figure 7 is a software configuration mechanism implemented using a PCIe Enhanced Capability Structure according to several aspects of this disclosure. The mechanism, generally shown at 700, includes the PCIe Express Capability Header 605. The TS[1:0] field 710 is a read-only field and provides the device's time synchronization capability. If the device is capable of being a grand master device, TS 710 is set to 11. If the device is capable of being a master device, TS 710 is set to 1x. If the device is only capable of being a target device, TS 710 is set to 00. A grand master is a device selected to be the source from which all other associated master devices derive their time values. The MT[1:0] field 715 is a read / write field and can be set depending on the device's assigned functionality. If the device is to be a grand master, MT is set to 11. MT 715 can be set to grand master by default for a root complex. The setting 10 for MT 715 is reserved for future use and designation. If the device is a master device, MT 715 is set to 01, which is the default for downstream ports. If the device is a target device, MT 715 is set to 00, which is the default for upstream ports. The Time[47:0] field 720 is a sample of the device's clock. For all devices except a Grand Master device, this field is read-only. If the device is a Grand Master device, the field is a software read / write field and can also be set by hardware using implementation-specific mechanisms. Writing bytes (in any order) is only allowed when the value is "Disabled," and the Grand Master clock starts counting from the written time when the value is "Enabled." The Frq[7:0] field 725 is designated for a message transmission frequency and is a read / write field. This field is implemented only for Grand-Master and Master devices and is fixed for Target-only devices. Field 725 is encoded to cover a range from once every 10 seconds to 100 kHz. Field 730 is a enable / disable bit. Bit 730 allows master and grandmaster devices to send time synchronization messages and causes target devices to respond to received messages. For a grandmaster device, it is possible to implement a hardware mechanism that further increases accuracy by synchronizing the grandmaster device's activation with an implementation-specific reference that follows the software setting of the enable bit. Although the preceding disclosure discusses a selection of embodiments currently considered useful, it is understood that such details are provided only for this purpose and that the attached claims are not limited to the disclosed embodiments, but on the contrary, are intended to cover modifications and equivalent arrangements that are within the scope and intent of the attached claims.< / undefined> < / undefined> < / undefined> < / undefined>

Claims

Method comprising: Receiving a series of time synchronization messages (310; 500; 700) at a first Peripheral Component Interconnect Express, PCIe, device (111-118, 141-145) via a PCIe bus from a second PCIe device (111-118, 141-145), wherein the time synchronization messages are each formatted as Transaction Layer Protocol Layout Packets, TLP, of the PCIe bus and each have a header that identifies the respective time synchronization message as such, and the time synchronization messages are used to compute a master time. Method according to claim 1, wherein one of the series of time synchronization messages (310; 500; 700) includes a timestamp (135; 335) and a time difference (136; 336), wherein the time difference indicates a delay between a previous of the series of time synchronization messages (310; 500; 700) and a response to the previous of the series of time synchronization messages (310; 500; 700). Method according to claim 2, wherein the timestamp (135; 335) is determined by the second device (111-118, 141-145) based on a clock of the second device (111-118, 141-145). Method according to claim 2, wherein the master time is calculated based on the timestamp (135; 335) and the time difference (136; 336). Method according to claim 4, wherein the master time is further calculated based on a reception time of one of the series of time synchronization messages (310; 500; 700). The method of claim 1, comprising: receiving a subsequent second series of time synchronization messages (310; 500; 700) at the first device (111-118, 141-145) via the PCIe bus from the second device (111-118, 141-145), wherein the second series of time synchronization messages (310; 500; 700) is designed to update a master time and includes a timestamp (135; 335). Method according to claim 1, wherein one of the time synchronization messages (310; 500; 700) includes a serial number (134; 334) and wherein the method comprises correlating timestamps (135; 335) based on the serial number (134; 334). PCIe device comprising: a means of appending and setting a header (501) in a transaction layer protocol layout packet (500) at the PCIe device (111-118, 141-145) specifying a time synchronization packet (310; 505) for synchronizing the time between the PCIe device (111-118, 141-145) and a second PCIe device (111-118, 141-145) arranged via a PCIe bus (120, 125); and a means of transmitting the packet (500) for synchronizing the time between the PCIe device (111-118, 141-145) and the second PCIe device (111-118, 141-145). PCIe device according to claim 8, wherein the package (500) includes a timestamp (135; 335). PCIe device according to claim 8, wherein the packet (500) includes a timestamp (135; 335) and a time difference (136; 336) indicating a delay between a previous time synchronization message (310; 505) and a response to the previous time synchronization message (310; 505). PCIe device according to claim 8, wherein the device further comprises a means (700) for calculating a master time based on a series of time synchronization packets (310; 505) that are sent and received between the PCIe device (111-118, 141-145) and the second PCIe device (111-118, 141-145) via the PCIe bus (120, 125). Component of the PCIe device according to claim 11, wherein the master time is calculated based on a receive time of one of the time synchronization packets (310; 505) received by the second PCIe device (111-118, 141-145). Component of the PCIe device according to claim 8, wherein the header field (501; 705) is a message code field. Component of the PCIe device according to claim 8, comprising a clock (720). Device comprising: at least one circuit (100) configured to: apply a header (501) of a Peripheral Component Interconnect Express, PCIe, transaction layer protocol layout packet (500) to a first device (111-118, 141-145), wherein the header (501) is configured to identify the packet (500) as a time synchronization packet (310; 505); transmit the packet (500) from the device (111-118, 141-145) via a PCIe bus (120, 125) to a second device (111-118, 141-145) to synchronize the time between the device (111-118, 141-145) and the second device (111-118, 141-145). synchronize; and receive time synchronization packets (310; 505) from the second facility. Device according to claim 15, wherein the package (500) includes a time synchronization marker. Device according to claim 15, wherein the package (500) includes a timestamp (135; 335). Device according to claim 15, wherein the packet (500) includes a timestamp (135; 335) and a time difference (136; 336) indicating a delay between a previous timeout message and a response to the previous timeout message. Device according to claim 18, wherein the at least one circuit (100) is configured to calculate a time based on a time of the at least one circuit (100), the timestamp (135; 335) and the time difference (136; 336). Device according to claim 19, wherein the header (501) comprises a message code field.

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