Techniques for refreshing a semiconductor memory device

Abstract

Method for refreshing a semiconductor memory device (10) comprises the following steps: Applying a plurality of voltage potentials to a memory cell (12) in an array (20) of memory cells, wherein the application of a plurality of voltage potentials to the memory cell (12) has: Applying a first voltage potential across a first region (120) of the storage cell (12) of a respective source line (EN, 32) of the field (20); Applying a second voltage potential to a second region (124) of the memory cell (12) via a respective local bit line (LCN, 404, 504) and a respective selection transistor (SEL, 514) of the field (20); Applying a third voltage potential to a respective word line (WL, 28) of the field (20), wherein the word line (WL, 28) is spaced from and capacitive to a body region (122) of the storage cell, which is ground-free and located between the first region (120) and the second region (124); and Applying a fourth voltage potential to a third region (126) of the storage cell via a respective carrier injection line (EP, 34) of the field (20).

Description

Territory of Revelation

[0001] The present disclosure relates generally to semiconductor storage devices and more specifically to techniques for refreshing a semiconductor storage device. Background of the Revelation

[0002] The semiconductor industry has experienced technological advancements that have allowed for increases in the density and / or complexity of semiconductor memory devices. Likewise, technological advancements have enabled reductions in power consumption and package sizes of various types of semiconductor memory devices. There is a continuing trend toward the use and / or fabrication of advanced semiconductor memory devices utilizing techniques, materials, and fixtures that improve performance, reduce power loss, and enhance overall scalability.

[0003] Silicon-on-insulator (SOI) and bulk substrates are examples of materials that can be used to fabricate such semiconductor memory devices. These semiconductor memory devices can include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multi-gate devices (e.g., dual-gate, triple-gate, or surrounding gate devices), and FinFET devices.

[0004] A semiconductor memory device can comprise a memory cell that has a storage transistor with an electrically floating body region where electrical charge can be stored. When excess majority charge carriers are stored in the floating body region, the memory cell can store a logic high (e.g., a binary "1" data state). When the floating body region is depleted of majority charge carriers, the memory cell can store a logic low (e.g., a binary "0" data state). Similarly, the semiconductor memory device can be fabricated on substrates with silicon on an insulator (SOI) or on bulk substrates (e.g., enabling body isolation). A semiconductor memory device can, for example, be fabricated as a three-dimensional (3D) device.Device with multiple gates, a Fin-FET device and a device with a vertical pillar.

[0005] In a conventional technique, the memory cell of the semiconductor storage device can be read by applying bias signals to a source / drain region and a gate of the storage transistor. As such, a conventional read technique may involve measuring the amount of current supplied by / generated in the ground-free body region of the memory cell in response to the application of the source / drain region and gate bias signals to determine a data state of the memory cell. The memory cell may, for example, have two or more distinct current states corresponding to two or more distinct logical states (e.g., two distinct current conditions / states corresponding to two distinct logical states: a binary "0" data state and a binary "1" data state).

[0006] In another conventional technique, the memory cell of the semiconductor memory device can be written by applying bias signals to the source / drain region(s) and the gate of the memory transistor. As such, a conventional writing technique can lead to an increase / decrease in majority charge carriers in the ground-free body region of the memory cell, which in turn determines the data state of the memory cell. Such an excess of majority charge carriers can result from channel impact ionization, band-to-band tunneling (gate-induced drain leakage, or GIDL), or direct injection.Majority charge carriers can be removed by drain region hole removal, source region hole removal, or drain and source region hole removal, for example using back gate pulsing.

[0007] Conventional read and / or write operations can often lead to relatively high energy consumption and large voltage potential oscillations, which can affect unselected memory cells in the semiconductor storage device. Similarly, pulsing between positive and negative gate bias voltages during read and write operations can reduce the net quantity of majority charge carriers in the ground-free region of the memory cell, which in turn can lead to an inaccurate determination of the data state in the memory cell. Furthermore, if a bias signal with a voltage potential below the threshold voltage of the memory transistor is applied to the memory transistor's gate, a channel of minority charge carriers below the gate can be blocked. However, some of the minority charge carriers can become trapped in interface errors.Some of the trapped minority charge carriers can combine with majority charge carriers, which can be attracted by the gate as a consequence of the applied bias signal. As a result, the net quantity of majority charge carriers in the ground-free region can be reduced. This phenomenon, commonly characterized as charge pumping, is problematic because the reduction in the net quantity of majority charge carriers in the ground-free region of the memory cell can lead to an inaccurate determination of the memory cell's data state.

[0008] US 2006 / 0011940 A1 discloses a thyristor device with doped regions of opposite polarity and a first word line used to provide read and write access to the memory cell. The device includes a second word line located adjacent to one of the doped regions of the thyristor device and separated from it by an insulating material to enable write operations to the memory cell. CN 1 981 344 A discloses a thyristor-based memory cell. The cell is formed in a floating substrate using silicon-on-insulator (SOI) technology and contains a lateral thyristor that is fully formed in the floating substrate and controlled by a second word line.The cathode of the thyristor comprises the source of a trap transistor, whose drain is connected to the device's bit line and which is driven by a first word line. A trapping layer is embedded in the floating substrate, and pulses are added when the cell is written to, causing holes to be trapped on the trapping layer for a logic state "1" and electrons to be trapped on the trapping layer for a logic state "0".

[0009] From the perspective of the foregoing, it can be understood that there may be several significant problems and shortcomings associated with conventional techniques for operating a semiconductor storage device. Summary of Revelation

[0010] Techniques for refreshing a semiconductor memory device are disclosed. According to the invention, a method for refreshing a semiconductor memory device comprises applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell comprises applying a first voltage potential via a first region of the memory cell to a respective source line of the array. Applying a plurality of voltage potentials to the memory cells also comprises applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array.Applying multiple voltage potentials to the memory cells further includes applying a third voltage potential to a respective word line of the field, wherein the word line is spaced and capacitive to a body region of the memory cell that is ground-free and located between the first region and the second region. Applying multiple voltage potentials to the memory cells further includes applying a fourth voltage potential to a third region of the memory cell via a respective carrier injection line of the field.

[0011] In accordance with other aspects of this particular exemplary embodiment, the respective local bit line can be coupled with a multiplexer.

[0012] In accordance with other aspects of this particular exemplary embodiment, the multiplexer can be coupled to a global bit line.

[0013] In accordance with additional aspects of this particular exemplary embodiment, the multiplexer may include at least one masking transistor coupled to the respective local bit line.

[0014] In accordance with yet another aspect of this particular exemplary embodiment, the multiplexer may further include at least one holding transistor coupled to the respective local bit line.

[0015] In accordance with other aspects of this particular exemplary embodiment, the respective selection transistor can be coupled with the at least one masking transistor and the at least one holding transistor.

[0016] In accordance with other aspects of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells can further feature a maintenance of the first voltage potential, which is applied to the first region at a constant level via the respective source line during the refreshing of the semiconductor memory device.

[0017] In accordance with additional aspects of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells may further include applying a selection control signal to the respective selection transistor in order to activate the respective selection transistor.

[0018] In accordance with yet another aspect of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells can further increase the second voltage potential applied to the respective source line from the second voltage potential applied to the respective source line during a hold operation, via the activated respective selection transistor.

[0019] In accordance with other aspects of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells may further feature an increase in the fourth voltage potential applied to the respective carrier injection line from the fourth voltage potential applied to the respective carrier injection line during a hold operation.

[0020] In accordance with other aspects of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells may also include applying decoupling control signals to the respective selection transistor in order to deactivate the respective selection transistor.

[0021] In accordance with additional aspects of this particular exemplary embodiment, the respective local bit line can become ground-free after the respective selection transistor is deactivated.

[0022] In accordance with yet another aspect of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells may further increase the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during a hold operation to perform a read operation.

[0023] In accordance with other aspects of this particular exemplary embodiment, increasing the third voltage potential can activate the memory cell to decrease the second voltage potential applied to the respective local bit line.

[0024] In accordance with other aspects of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells may further include a reduction of the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during a write logic low operation in order to perform a write logic high operation.

[0025] In accordance with additional aspects of this particular exemplary embodiment, the third voltage potential applied to the respective word line during the write logic high operation can be higher than the third voltage potential applied to the respective word line during a hold operation.

[0026] In accordance with yet another aspect of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells may also include applying coupling control signals to the respective selection transistor in order to activate the respective selection transistor to perform an end for a write logic high operation.

[0027] In accordance with other aspects of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells may further include discharging the second voltage potential applied to the respective local bit line to bias a connection between the second region and the third region in the forward direction.

[0028] In accordance with other aspects of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells may further reduce the fourth voltage potential applied to the respective carrier injection line from the fourth voltage potential applied to the respective carrier injection line during a write logic high operation to perform a hold operation.

[0029] In accordance with additional aspects of this particular exemplary embodiment, applying a plurality of voltage potentials to the memory cells may further feature a reduction of the second voltage potential applied to the respective local bit line from the second voltage potential applied to the respective local bit line during a write logic high operation to perform a hold operation.

[0030] The present disclosure will now be described in more detail with reference to exemplary embodiments as illustrated in the accompanying drawings. While the present disclosure is described below with reference to exemplary embodiments, it should be understood that the present disclosure is not limited thereto. Those skilled in the art who have access to the teachings contained therein will recognize additional implementations, modifications, and embodiments, as well as other areas of application, which lie within the scope of the present disclosure described therein and with respect to which the present disclosure may be of significant usefulness. Brief description of the drawings

[0031] To facilitate a more thorough understanding of the present revelation, reference is now made to the accompanying drawings, in which identical elements are designated with the same numbers. These drawings should not be interpreted as limiting the present revelation, but are intended to serve only as examples. Fig. Figure 1 shows a block diagram of a semiconductor memory device comprising a memory cell array, a data write and read circuit, and a memory cell selection and control circuit in accordance with an embodiment of the present disclosure. Fig. Figure 2 shows a schematic diagram of at least one section of a memory cell array having a plurality of memory cells, in accordance with an embodiment of the present disclosure. Fig. Figure 3 shows a cross-sectional view of the in Fig. 2 memory cell field shown in accordance with an embodiment of the present disclosure. Fig. Figure 4 shows a schematic diagram of at least one section of a memory cell array comprising a plurality of memory cells coupled to a plurality of read amplifier circuits via a hierarchical bit line configuration, in accordance with another embodiment of the present disclosure. Fig. Figure 5 shows a schematic diagram of a multiplexer for a hierarchical bit line configuration in accordance with an embodiment of the present disclosure. Fig. Figure 6 shows a schematic diagram of a source line driver for a hierarchical bit line configuration in accordance with an embodiment of the present disclosure. Fig. Figure 7 shows control signal voltage waveforms for performing a refresh operation in accordance with an embodiment of the present disclosure. Detailed description of exemplary embodiments

[0032] With reference to Fig. Figure 1 shows a block diagram of a semiconductor storage device 10 comprising a memory cell array 20, a data write and read circuit 36, and a memory cell selection and control circuit 38, in accordance with an embodiment of the present disclosure. The memory cell array 20 can have a plurality of memory cells 12, each of which is coupled to the memory cell selection and control circuit 38 via a word line (WL) 28 and a carrier injection line (EP) 34, and to the data write and read circuit 36 ​​via a bit line (CN) 30 and a source line (EN) 32.

[0033] It should be noted that the bit line (CN) 30 and the source line (EN) 32 are designations used to distinguish between two signal lines that are interchangeable.

[0034] The data write and read circuit 36 ​​can read data from and write data to selected memory cells 12. In an exemplary embodiment, the data write and read circuit 36 ​​can comprise a plurality of data read amplifier circuits. Each data read amplifier circuit can receive a current or voltage reference signal on at least one bit line (CN) 30. Each data read amplifier circuit can, for example, be a type of cross-coupled read amplifier for reading a data state stored in a memory cell 12. The data write and read circuit 36 ​​can comprise at least one multiplexer that couples a data read amplifier circuit to at least one bit line (CN) 30. In an exemplary embodiment, the multiplexer can couple a plurality of bit lines (CN) 30 to a data read amplifier circuit.

[0035] The data read amplifier circuit can employ voltage and / or current read circuits and / or techniques. In an exemplary embodiment, each data read amplifier circuit can employ current read circuits and / or techniques. For example, a current read amplifier can compare the current from a selected memory cell 12 with a reference current (e.g., the current of one or more reference cells). From this comparison, it can be determined whether the selected memory cell 12 stores a logic high (e.g., binary "1" data state) or a logic low (e.g., binary "0" data state). It can be recognized by those skilled in the art that numerous types and forms of the data write and read circuit 36 ​​(comprising one or more read amplifiers that use voltage or current read techniques to read a data state stored in a memory cell 12) can be employed to read data stored in the memory cells 12.

[0036] The memory cell selection and control circuit 38 can select and / or activate one or more predetermined memory cells 12 to facilitate reading data from them by applying control signals on one or more word lines (WL) 28 and / or carrier injection lines (EP) 34. The memory cell selection and control circuit 38 can generate such control signals from address signals, for example, row address signals. Furthermore, the memory cell selection and control circuit 38 can include a word line decoder and / or driver. The memory cell selection and control circuit 38 can, for example, include one or more different control / selection techniques (and circuits thereof) to select and / or activate one or more predetermined memory cells 12.

[0037] In particular, all such control / selection techniques, and circuits thereof, whether now known or later developed, are intended to fall within the scope of the present disclosure.

[0038] In an exemplary embodiment, the semiconductor memory device 10 can implement a two-step read operation, wherein all memory cells 12 in a row of memory cells 12 can be written to a predetermined data state by first performing a "erase" or a logical low (e.g., binary "0" data state) write operation, whereby all memory cells 12 in the row of memory cells 12 are written to a logical low (e.g., binary "0" data state). Then, selected memory cells 12 in the row of memory cells 12 can be selectively written to the predetermined data state (e.g., logical high (binary "1" data state)). The semiconductor memory device 10 can also implement a one-step read operation, wherein selected memory cells 12 in a row of memory cells 12 are selectively written to either a logical high (e.g., binary "1" data state) or a logical low (e.g.,(binary “0” data state) can be written without first implementing a “delete” operation. The semiconductor memory device 10 can also employ any of the exemplary write, prepare, hold, refresh, and / or read techniques described herein.

[0039] The memory cells 12 can contain N-type, P-type, and / or both types of transistors. Circuits peripheral to the memory cell array 20 (for example, read amplifiers or comparators, row and column address decoders, as well as row drivers (not shown here)) can contain N-type and / or P-type transistors. Regardless of whether P-type or N-type transistors are used in memory cells 12 in the memory cell array 20, suitable voltage potentials (for example, positive or negative voltage potentials) for reading from the memory cells 12 will be described further herein.

[0040] With reference to Fig. Figure 2 shows a memory cell array 20 comprising a plurality of memory cells 12, in accordance with an embodiment of the present disclosure. Each of the memory cells 12 can comprise a first bipolar transistor 14a and a second bipolar transistor 14b coupled together. The first bipolar transistor 14a and / or the second bipolar transistor 14b can, for example, be an NPN bipolar transistor or a PNP bipolar transistor. As shown in Fig. As illustrated in Figure 2, the first bipolar transistor 14a can be an NPN bipolar transistor and the second bipolar transistor 14b can be a PNP bipolar transistor. In another exemplary embodiment, the first storage transistor 14a can be a PNP bipolar transistor and the second storage transistor 14b can be an NPN bipolar transistor. In yet another exemplary embodiment, each of the memory cells 12 can comprise a first field-effect transistor (FET) 14a and a second bipolar transistor 14b. The first field-effect transistor (FET) 14a can, for example, be a metal-oxide-semiconductor field-effect transistor (MOSFET) or a junction field-effect transistor (JFET). The memory cells 12 can be coupled to a respective word line (WL) 28, a respective bit line (CN) 30, a respective source line (EN) 32, and / or a respective carrier injection line (EP) 34.Data can be written to or read from a selected memory cell 12 by applying suitable control signals to a selected word line (WL) 28, a selected bit line (CN) 30, a selected source line (EN) 32, and / or a selected carrier injection line (EP) 34. In one exemplary embodiment, the word line (WL) 28 can extend horizontally parallel to the carrier injection line (EP) 34. In another exemplary embodiment, the bit line (CN) 30 can extend vertically parallel to the source line (EN) 32.

[0041] In an exemplary embodiment, one or more respective bit lines (CN) 30 can be coupled to a data read amplifier circuit of the data write and read circuit 36. For example, one or more control signals can be applied to one or more selected memory cells 12 via a selected word line (WL) 28, a selected bit line (CN) 30, a selected source line (EN) 32, and / or a selected carrier injection line (EP) 34. A voltage potential and / or a current can be generated by the one or more selected memory cells 12 and output to the data read amplifier circuit of the data write and read circuit 36 ​​via a corresponding bit line (CN) 30.

[0042] A data state can also be written to one or more selected memory cells 12 by applying one or more control signals via one or more corresponding bit lines (CN) 30. The one or more control signals applied via the corresponding bit lines (CN) 30 can control the second bipolar transistor 14b of the memory cell 12 to write a desired data state to the memory cell 12. In the case that a data state is read from and / or written to the memory cell 12 via the bit line (CN) 30, then the bit line (CN) 30 can be coupled to the data read amplifier circuit of the data read / write circuit 36, while the source line (EN) 32 can be controlled separately via a voltage / current source (e.g., a voltage / current driver) of the data read / write circuit 36.In one exemplary embodiment, the data read amplifier circuit and the voltage / current source of the data read / write circuit 36 ​​can be arranged on opposite sides of the memory cell array 20. In another exemplary embodiment, the data read / write circuit 36 ​​can comprise a plurality of data read amplifier circuits arranged on opposite sides of the memory cell array 20.

[0043] In the case that the source power (EN) 32 is coupled to the data read amplifier circuit of the data write and read circuit 36, a voltage potential and / or a current generated by one or more selected memory cells 12 can be output to the data read amplifier circuit of the data write and read circuit 36 ​​via the corresponding source line (EN) 32. A data state can also be written to one or more selected memory cells 12 by applying one or more control signals via one or more corresponding bit lines (CN) 30. The one or more control signals applied via the corresponding bit lines (CN) 30 can control the second bipolar transistor 14b of the memory cell 12 to write a desired data state to the memory cell 12.The bit line (CN) 30 and the source line (EN) 32 can, for example, be coupled to dissimilar sub-circuits (e.g., drivers and / or read amplifiers) of the data write and read circuit 36, which is located on opposite sides of the memory cell array 20. In an exemplary embodiment, the bit line (CN) 30 can be coupled to a driver and / or a read amplifier circuit of the data write and read circuit 36, while the source line (EN) 32 can be coupled to a driver and / or a read amplifier circuit of the data write and read circuit 36. Likewise, the driver and / or the data read amplifier circuit coupled to the bit line (CN) 30 and the driver and / or the data read amplifier circuit coupled to the source line (EN) 32 can be located on opposite sides of the memory cell array 20.By reading a data state via the source line (EN) 32 and writing a data state via the bit line (CN) 30, the resistance of the memory cell 12 can be reduced because the source line (EN) 32 and the bit line (CN) 30 are driven on opposite sides of the memory cell array 20.

[0044] With reference to Fig. 3 shows a cross-sectional view of the Fig. The memory cell 12 shown in Figure 1 is in accordance with an embodiment of the present disclosure. As discussed above, the memory cell 12 can have two bipolar transistors. In one exemplary embodiment, the first bipolar transistor 14a can be an NPN bipolar transistor and the second bipolar transistor 14b can be a PNP bipolar transistor. In another exemplary embodiment, the first bipolar transistor 14a and the second bipolar transistor 14b can share one or more common regions. The first NPN bipolar transistor 14a can have an N+ emitter region 120, a P- base region 122, and an N+ collector region 124. The second PNP bipolar transistor 14b can have a P- collector region 122, an N+ base region 124, and a P+ emitter region 126.The N+ region 120, the P- region 122, the N+ region 124, and / or the P+ region 126 can be arranged in a sequentially connected relationship within a column or rib configuration extending vertically or perpendicularly to a plane defined by an N-well region 128 and / or a P-substrate 130. In an exemplary embodiment, the P- region 122 can be an earth-free body region of the storage cell 12 configured to accumulate / store charges, which can be spaced from and capacitively coupled to the word line (WL) 28.

[0045] The N+ emitter region 120 of the first bipolar transistor 14a can be coupled to the source line (EN) 32, which is formed by a metal layer. Likewise, the P-base region 122 of the first bipolar transistor 14a and / or the P-collector region 122 of the second bipolar transistor 14b can be capacitively coupled to the word line (WL) 28, which is formed by a metal layer. In another exemplary embodiment, the N+ region 124 of the memory cell 12 can be coupled to a bit line (CN) 30, which is formed by a metal layer. The bit line (CN) 30 can surround the N+ region 124 of the memory cell 12. In another exemplary embodiment, the bit line (CN) 30 can be coupled to the N+ region 124 on one or more side regions (e.g., one side region or two side regions) of the N+ region 124. The bit line (CN) 30 can reduce its influence on the memory cell 12.In particular, the bit line (CN) 30 can be formed from a metal layer, and therefore a hole can reduce the influence on the memory cell 12. The bit line (CN) 30 can extend horizontally parallel to the source line (EN) 32, which is coupled to a plurality of memory cells 12 (e.g., a column of memory cells 12). For example, the bit line (CN) 30 and the source line (EN) 32 can be arranged in different planes and configured to be parallel to each other. The source line (EN) 32 can provide an alternative means for addressing or accessing the memory cell 12. The memory cell 12 can be addressed or accessed via either the bit line (CN) 30, the source line (EN) 32, or a combination of the bit line (CN) 30 and the source line (EN) 32.

[0046] With reference to Fig. 4 A schematic diagram of at least one section of a memory cell array 20, comprising a plurality of memory cells 12 coupled to a plurality of read amplifier circuits 402 via a hierarchical bit line configuration, is shown in accordance with another embodiment of the present disclosure.

[0047] Each of the memory cells 12 of the memory cell array 20 can be coupled to a data read amplifier circuit 402 via the hierarchical bitline configuration. The hierarchical bitline configuration can include a local bitline (LCN) 404 (e.g., bitline (CN) 30), which is directly coupled to a respective memory cell 12. Each local bitline (LCN) 404 can be coupled to a global bitline (GCN) 406 via a multiplexer (MUX) 408. The hierarchical bitline configuration can reduce bitline capacitance and resistance and can lead to lower signal attenuation during various operations on the memory cell 12. Likewise, the reduction in bitline capacitance can lead to lower power consumption on a selected column of memory cells 12.Furthermore, the hierarchical bitline configuration can reduce the amount of interference on unselected memory cells 12 because only unselected local bit lines (LCNs) 404 adjacent to a selected local bit line (LCN) 404 are affected. Additionally, energy consumption can be reduced by applying masking control signals only on unselected local bit lines (LCNs) 404 adjacent to a selected local bit line (LCN) 404.

[0048] The hierarchical bitline configuration can comprise a plurality of local bitlines (LCNs) 404, each coupled to a respective multiplexer (MUX) 408. In one exemplary embodiment, four local bitlines (LCNs) 404 can be coupled to each multiplexer (MUX) 408. It can be seen by those skilled in the art that the number of local bitlines (LCNs) 404 coupled to each multiplexer (MUX) 408 can vary. For example, eight local bitlines (LCNs) 404, sixteen local bitlines (LCNs) 404, thirty-two local bitlines (LCNs) 404, sixty-four local bitlines (LCNs) 404, etc., can be coupled to each multiplexer (MUX) 408.

[0049] The hierarchical bitline configuration can comprise a global bitline (GCN) 406 coupled to a plurality of multiplexers (MUXs) 408. In one exemplary embodiment, a global bitline (GCN) 406 can be coupled to four multiplexers (MUXs) 408. It can be recognized by a person skilled in the art that the number of multiplexers (MUXs) 408 coupled to a global bitline (GCN) 406 can vary. For example, eight multiplexers (MUXs) 408, sixteen multiplexers (MUXs) 408, thirty-two multiplexers (MUXs) 408, sixty-four multiplexers (MUXs) 408, etc., can be coupled to a global bitline (GCN) 406. Each global bitline (GCN) 406 can be coupled to a plurality of local bitlines (LCNs) 404 via a plurality of multiplexers (MUXs) 408.In an exemplary embodiment, each global bit line (GCN) 406 can be coupled to sixteen local bit lines (LCNs) 404 via four multiplexers (MUXs) 408.

[0050] Each memory cell 12 can be biased by a respective source line driver 412. Each source line driver 412 can be coupled to a plurality of memory cells 12 via a plurality of local source lines (LENs) 410. In an exemplary embodiment, each source line driver 412 can be coupled to four memory cells 12. It can be seen by those skilled in the art that the number of memory cells 12 coupled to a source line driver 412 can vary. For example, eight local source lines (LENs) 410, sixteen local source lines (LENs) 410, thirty-two local source lines (LENs) 410, sixty-four local source lines (LENs) 410, etc., can be coupled to a source line driver 412.In an exemplary embodiment, the number of memory cells 12 coupled to a source line driver 412 can be equal to the number of memory cells 12 coupled to a multiplexer (MUX) 408.

[0051] With reference to Fig. Figure 5 shows a schematic diagram of a multiplexer 508 for a hierarchical bit line configuration in accordance with an embodiment of the present disclosure. As in Fig. As shown in Figure 5, a global bit line (GCN) 506 can be coupled to a plurality of local bit lines (LCNs) 504 via the multiplexer 508. In an exemplary embodiment, the multiplexer 508 can comprise a plurality of selection transistors (SELs) 514, which are coupled to a plurality of local bit lines (LCNs) 504 and the global bit line (GCN) 506. Each selection transistor 514 can, for example, be an N-type or a P-type bipolar junction transistor or an N-channel or a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Each of the plurality of selection transistors (SELs) 514 can be biased to selectively couple a local bit line (LCN) 504 to the global bit line (GCN) 506. In an exemplary embodiment, the selection transistor (SEL) <0> ) 504 biased to form a local bit line (LCN) <o>) 504 to couple with the global bit line (GCN) 506, while the selection transistors (SEL) <1> SEL <2> and SEL <3> ) may be biased to the local bit lines (LCN) <1> , LCN <2> and LCN <3> ) to decouple 504 from the global bitline (GCN) 506.

[0052] The multiplexer 508 can also comprise a plurality of biased transistor pairs 516. Each biased transistor pair 516 can, for example, be an N-type or a P-type bipolar junction transistor and / or an N-channel or a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Each biased transistor pair 516 can be coupled to a global hold line (GHL) 510 and / or a global mask line (GML) 512. Each biased transistor pair 516 can comprise a hold transistor (HD) 518 and a mask transistor (MSK) 520. In an exemplary embodiment, each hold transistor (HD) 518 can be coupled to a global hold line (GHL) 510, and each mask transistor (MSK) 520 can be coupled to the global mask line (GML) 512.Control signals can be applied to the gates of the hold transistors (HD) 518 to bias the hold transistors (HD) 518 to apply a hold voltage potential to a memory cell 12 during a hold operation via the local bit line (LCN) 504. For example, if control signals are applied to the gates of the hold transistors (HD) 518, the control signals can bias the majority of the hold transistors (HD). <o>, HD <1> , HD <2> and HD <3> ) 518 cause it to assume an "ON" state. Subsequently, the majority of holding transistors (HD) <o>, HD <1> , HD <2> and HD <3> ) 518 a holding voltage potential to a corresponding plurality of memory cells 12 via the local bit lines (LCN) <o>, LCN <1> , LCN <2> and LCN <3> Output 504.

[0053] Similarly, control signals can be applied to the gates of the masking transistors (MSK) 520 to bias the masking transistors (MSK) 520 in order to apply a masking voltage potential to a memory cell 12 during a read and / or write operation via the local bit line (LCN) 504. For example, if control signals are applied to the gates of the masking transistors (MSK) 520, the control signals can control the majority of the masking transistors (MSK). <0> , MSK <1> , MSK <2> and / or MSK <3> ) 520, which are associated with the unselected memory cells 12, cause them to assume an "ON" state. Subsequently, the majority of masking transistors (MSK) can <0> , MSK <1> , MSK <2> and / or MSK <3> ) 518 a masking voltage potential to a corresponding plurality of unselected memory cells 12 via the local bit lines (LCN) <o>, LCN <1> , LCN <2> and / or LCN <3> ) Output 504, which are associated with the unselected memory cells 12.

[0054] With reference to Fig. Figure 6 shows a schematic diagram of a source line driver 608 for a hierarchical bit line configuration in accordance with an embodiment of the present disclosure. The source line driver 608 can have a plurality of biased transistor pairs 616. Each biased transistor pair 616 can be, for example, an N-type or a P-type bipolar junction transistor and / or an N-channel or a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Each biased transistor pair 616 can be coupled to a global hold line (GHL) 610 and / or a global mask line (GML) 612. Each biased transistor pair 616 can include a hold transistor (HD) 618 and a mask transistor (MSK) 620.In an exemplary embodiment, each hold transistor (HD) 618 can be coupled to a global hold line (GHL) 610, and each mask transistor (MSK) 620 can be coupled to the global mask line (GML) 612. Control signals can be applied to the gates of the hold transistors (HD) 618 to bias the hold transistors (HD) 618 to apply a hold voltage potential to memory cells 12 during a hold operation via the local source line (LEN) 604. For example, when control signals are applied to the gates of the hold transistors (HD) 618, the control signals can bias the majority of hold transistors (HD) 618. <o>, HD <1> , HD <2> and HD <3> ) 618 cause it to assume an "ON" state. Subsequently, the majority of holding transistors (HD) <0> , HD <1> , HD <2> and HD <3> ) 618 a holding voltage potential to a corresponding plurality of memory cells 12 via the local source lines (LEN) <0> , LEN <1> , LEN <2> and LEN <3> Output 604.

[0055] Similarly, control signals can be applied to the gates of the masking transistors (MSK) 620 to bias the masking transistors (MSK) 620 in order to apply a masking voltage potential to memory cells 12 during a read and / or write operation via the local source line (LEN) 604. For example, if control signals are applied to the gates of the masking transistors (MSK) 620, the control signals can control the majority of the masking transistors (MSK). <0> , MSK <1> , MSK <2> and / or MSK <3> ) 620, which are associated with the unselected memory cells 12, cause an “ON” state.The majority of masking transistors (MSK) can be described below. <0> , MSK <1> , MSK <2> and / or MSK <3> ) 618 a masking voltage potential to a corresponding plurality of unselected memory cells 12 via the local source lines (LEN <0> , LEN <1> , LEN <2> and / or LEN <3> ) Output 604, which are associated with the unselected memory cells 12.

[0056] With reference to Fig. 7 Control signal voltage waveforms for performing a refresh operation in accordance with an embodiment of the present disclosure are shown. The refresh operation may, for example, comprise one or more steps. The refresh operation can reduce energy consumption because a read operation does not need to be performed (e.g., not activating a data read amplifier circuit). Likewise, the refresh operation can reduce energy consumption by simultaneously refreshing all memory cells 12 that are coupled to selected local bit lines (LCNs) 30 and that are coupled to a selected word line (WL) 28. Furthermore, the refresh operation can reduce energy consumption because the voltage potential applied to the source line (EN) 32 remains constant throughout the refresh operation.Furthermore, by maintaining the constant voltage potential applied to the source line (EN) 32 throughout the entire refresh operation, a significant amount of influence on the memory cells 12 can be reduced.

[0057] The refresh operation can include control signals configured to execute one or more steps. Before executing a refresh operation, the control signals can be configured to perform a hold operation to maintain a data state (e.g., a logical high (binary "1" data state) or a logical low (binary "0" data state)) stored in memory location 12. Specifically, the control signals can be configured to perform a hold operation to maximize the storage time of a data state (e.g., a logical low (binary "0" data state) and / or a logical high (binary "1" data state)) stored in memory location 12. Likewise, the hold operation control signals can be configured to execute activities or fields (e.g.,to avoid or reduce electric fields between connections (which can lead to charge loss) within memory cell 12. In an exemplary embodiment, a negative voltage potential can be applied to the word line (WL) 28, which may be capacitively coupled to the P-region 122 of memory cell 12, during a hold operation, while the voltage potential applied to other regions (e.g., the N+ region 120, the N+ region 124, and / or the P+ region 126) can be maintained at 0 V. The negative voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P-region 122 of memory cell 12) may, for example, be -1.8 V. During the hold operation, the connection between the N+ region 124 and the P-region 122, and the connection between the N+ region 120 and the P-region 122, can be reverse-biased to maintain a data state (e.g.,to maintain a logical high (binary “1” data state) or a logical low (binary “0” data state) that is stored in memory cell 12.

[0058] In an exemplary embodiment, a first step of a refresh operation can include control signals to perform a preparation to start an operation, where the control signals can be applied to a memory cell 12 to prepare the memory cell 12 for one or more subsequent steps. For example, precharge control signals can be applied to one or more selected local bit lines (LCNs) 30 at a predetermined voltage potential. The precharge control signals can be applied to one or more selected local bit lines (LCNs) 30 via the multiplexer (MUX) 408. Select control signals can be applied to one or more select transistors (SELs) 514 to activate the one or more select transistors (SELs) 514.The selection control signals can switch one or more selection transistors (SELs) 514 to an "ON" state to couple the precharge control signal to one or more corresponding local bit lines (LCNs) 30. In an exemplary embodiment, the precharge control signal can precharge the one or more local bit lines (LCNs) 30 to 0.7 V.

[0059] The second step of the refresh operation can include applying control signals to one or more memory cells 12 to perform a preparation to start an operation where the control signals can be applied to a memory cell 12. The control signals can be applied to the P+ region 126 of the memory cell 12 via the carrier injection line (EP) 34. The control signals can apply a predetermined voltage potential to the P+ region 126 of the memory cell 12 via the carrier injection line (EP) 34. In an exemplary embodiment, the control signals can apply approximately 1.0 V to 1.2 V to the P+ region 126 of the memory cell 12 via the carrier injection line (EP) 34. The control signals applied to the P+ region 126 of the memory cell 12 will not cause the second bipolar transistor 14b to turn on in an "ON" state.In one exemplary embodiment, the second step of the refresh operation can be performed simultaneously with the first step of the refresh operation. In another exemplary embodiment, the second step of the refresh operation can be performed after the first step of the refresh operation.

[0060] The third step of the refresh operation can include control signals to perform a preparation to start an operation, where the control signals can be applied to a memory cell 12. For example, after precharging the one or more local bit lines (LCNs) 30 to a predetermined voltage potential, decoupling control signals can be applied to the one or more select transistors (SELs) 514 and switch the one or more select transistors (SELs) 514 to an "OFF" state. In another exemplary embodiment, after precharging the one or more local bit lines (LCNs) 30 to a predetermined voltage potential, the select control signals can be removed from the one or more select transistors (SELs) 514 to switch the one or more select transistors (SELs) 514 to an "OFF" state.The one or more switched-off "OFF" selection transistors (SELs) 514 can decouple the one or more local bit lines (LCNs) 30 from the precharge control signals. In an exemplary embodiment, the one or more local bit lines (LCNs) 30 can be floating.

[0061] The fourth step of the refresh operation may include control signals configured to perform a read operation. The read operation may include control signals configured to perform one or more write operations to one or more selected memory cells 12 and one or more selected rows of the memory cell array 20. For example, the read operation may be performed on one or more selected memory cells 12 and one or more selected rows of the memory cell array 20. For example, an increase in the voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P-region 122) may be a predetermined voltage potential greater than a voltage potential applied to the local bit line (LCN) 30 and / or the source line (EN) 32.The predetermined voltage potential can be a threshold voltage potential or a forward bias voltage potential of the first bipolar transistor 14a and / or the second bipolar transistor 14b. The predetermined voltage potential can be, for example, approximately 0.7 V.

[0062] In an exemplary embodiment, a voltage potential applied to word line (WL) 28 (e.g., capacitively coupled to P-region 122) can be increased from -1.8 V to 0 V. If a logic high (e.g., binary "1" data state) is stored in memory cell 12, the first bipolar transistor 14a can be switched to an "ON" state. For example, the connection between N+ region 120 and P-region 122 can be forward-biased, and the connection between P-region 122 and N+ region 124 can be reverse-biased, and the first bipolar transistor 14a can be switched to an "ON" state. When the first bipolar transistor 14a is switched to an “ON” state, the N+ region 124 (e.g., ground-free) can be discharged to approximately 0.2 V in order to switch the second bipolar transistor 14b to an “ON” state.By switching the second bipolar transistor 14b to an “ON” state, the majority charge carriers can be injected into the P-region 122 to refresh a logic high (e.g. binary “1” data state) stored in memory cell 12.

[0063] If a logic low (e.g., binary "0" data state) is stored in memory cell 12, the first bipolar transistor 14a can remain in an "OFF" state. For example, the connection between the N+ region 120 and the P- region 122 does not need to be forward-biased, or can be weakly forward-biased, and the connection between the P- region 122 and the N+ region 124 does not need to be forward-biased, or can be weakly forward-biased, so that the first bipolar transistor 14a can remain in an "OFF" state. If the first bipolar transistor 14a remains in an "OFF" state, the N+ region 124 (e.g., floating) does not need to be discharged and can remain at a predetermined voltage potential (e.g., a pre-charge voltage potential).The second bipolar transistor 14b can remain in an "OFF" state if the N+ region is not discharged. If the second bipolar transistor 14b remains in an "OFF" state, the majority charge carriers cannot be injected into the P- region 122 to refresh a logic low (e.g., binary "0" data state) stored in memory cell 12. In an exemplary embodiment, if no charges or only a small amount of charges are accumulated in the P- region 122 to indicate a logic low (e.g., binary "0" data state), the junction between the P- region 122 and the N+ region 124 is not forward-biased, and the N+ region 124 does not need to be discharged (e.g., maintaining a pre-charge voltage potential). The second bipolar transistor 14b can remain in an “OFF” state if the N+ region 124 is not discharged, and the logic low (e.g.A binary “0” data state can be maintained in memory cell 12. However, if a larger amount of charges are accumulated in the P-region 122 to indicate a logical low (e.g., binary “0” data state) stored in memory cell 12, the connection between the P-region 122 and the N+ region 124 can be weakly forward-biased to reduce or discharge excess charges stored in the P-region 122, thus maintaining a logical low (e.g., binary “0” data state) in memory cell 12.

[0064] The fifth step of the refresh operation can include control signals configured to perform a logic high (e.g., binary "1" data state) write operation on memory cells 12, which can cause the discharge of a voltage potential (e.g., to approximately 0.2 V) at the N+ region 124. The logic high write operation can include control signals configured to write a logic high (e.g., binary "1" data state) to one or more selected memory cells 12. A predetermined voltage potential can, for example, be applied to word line (WL) 28 (e.g., capacitively coupled to P- region 122). In an exemplary embodiment, a voltage potential applied to word line (WL) 28 (e.g., capacitively coupled to P- region 122) can be reduced from 0 V to -1.0 V.

[0065] With such a bias, the majority charge carriers can continue to be injected into the P-region 122 because of the second bipolar transistor 14b, which can be switched to an "ON" state in step four. The majority charge carriers can continue to be injected into the P-region 122 even if the voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P-region 122) switches from 0 V to -1.0 V. The connection between the N+ region 124 and the P+ region 126 can, for example, be forward-biased, and majority charge carriers (e.g., holes) can be injected into the P-region 122. The P-region 122 can accumulate / store a quantity of charge carriers that can represent a predetermined voltage potential above the voltage potential at the N+ region 120.In an exemplary embodiment, the predetermined voltage potential can be 0.7 V above the voltage potential at the N+ region 120. If a logic low (e.g., binary "0" data state) is stored in memory cell 12, the second bipolar transistor 14b can remain in an "OFF" state, and the majority charge carriers do not need to be injected into the P- region 122. Similarly, when the voltage potential applied by the word line (WL) 28 (e.g., capacitively coupled to the P- region 122) switches from 0 V to -1.0 V, the second bipolar transistor 14b can remain in the "OFF" state, and the majority charge carriers do not need to be injected into the P- region 122. If the majority charge carriers are not injected into the P-region 122, a logical low (e.g., binary "0" data state) can be maintained in memory cell 12.

[0066] The sixth step of the refresh operation can include control signals to terminate the logic high (e.g., binary "1" data state) write operation. For example, coupling control signals can be applied to one or more selection transistors (SELs) 514, switching them to an "ON" state. The one or more switched "ON" selection transistors (SELs) 514 can couple a predetermined voltage potential to one or more local bit lines (LCNs) 30 to switch the second bipolar transistor 14b to an "OFF" state, thus terminating the logic high (e.g., binary "1" data state) write operation in the selected memory cells 12. The predetermined voltage potential applied to one or more local bit lines (LCNs) 30 to switch the logic high (e.g., binary "1" data state)The threshold voltage potential below which the majority charge carriers injected through the connection between the N+ region 124 and the P+ region 126 may be negligible can be determined, at least in part, based on the binary “1” data state write operation. For example, a predetermined voltage potential applied to one or more local bit lines (LCNs) 30 may be approximately 0.7 V.

[0067] As discussed above, the voltage potential applied to word line (WL) 28 (e.g., capacitively coupled to P-region 122) can be reduced from 0 V to -1.0 V, and the voltage potential applied to local bit lines (LCNs) 30 can be discharged to approximately 0.2 V, while the voltage potential applied to P+ region 126 via carrier injection line (EP) 34 can be maintained at 1.0 V. With such biasing, the connection between P-region 122 and N+ region 124 can be forward-biased so that a logic high (e.g., binary "1" data state) can be written to P-region 122 (e.g., charge injection into P-region 122 from P+ region 126).

[0068] The seventh step of the refresh operation can also include control signals configured to perform a preparation to complete an operation. During the seventh step of the refresh operation, the voltage potentials applied to the memory cells 12 can adjust the amount of charge (e.g., an indication of a data state) stored in the memory cells 12. In an exemplary embodiment, a voltage potential applied to the P+ region 126 via the carrier injection line (EP) 34 can be reduced to 0 V. The P- region 122, which can be charged to approximately 0.7 V above the voltage potential at the N+ region 124 during the logic high (e.g., binary "1" data state) write operation, can be coupled low to approximately 0 V by the voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P- region 122).The voltage potential applied to word line (WL) 28 (e.g., capacitively coupled to P-region 122) can be reduced to -1.8 V and can determine a quantity of charge (e.g., an indication of a data state) stored in P-region 122 of memory cells 12. Similarly, a voltage potential applied to N+ region 124 via bit line (CN) 30 can be reduced to 0 V to return to the hold operation in order to retain a data state (e.g., logic low (e.g., binary "0" data state) or logic high (e.g., binary "1" data state)).

[0069] It should be noted that providing techniques for refreshing a semiconductor memory device in accordance with the present disclosure described above typically involves processing input data and generating output data to some extent. This input data processing and output data generation can be implemented in hardware or software. For example, specific electronic components in a semiconductor memory device or similar or related circuits can be used to implement the functions associated with refreshing a semiconductor memory device in accordance with the present disclosure described above.Alternatively, one or more processors operating in accordance with instructions can implement the functions associated with refreshing a semiconductor memory device in accordance with the present disclosure described above. If so, it is within the scope of the present disclosure that such instructions can be stored in one or more processor-readable media (e.g., a magnetic disk or other storage medium) or transmitted to one or more processors via one or more signals embodied in one or more carrier waves.< / o> < / o> < / o> < / o> < / o> < / o>

Claims

[1] A method for refreshing a semiconductor memory device (10) comprises the steps of: Applying a plurality of voltage potentials to a memory cell (12) in an array (20) of memory cells, wherein applying a plurality of voltage potentials to the memory cell (12) comprises: Applying a first voltage potential across a first region (120) of the memory cell (12) of a respective source line (EN, 32) of the array (20); Applying a second voltage potential to a second region (124) of the memory cell (12) via a respective local bit line (LCN, 404, 504) and a respective selection transistor (SEL, 514) of the array (20); Applying a third voltage potential to a respective word line (WL, 28) of the array (20), wherein the word line (WL, 28) is spaced from and capacitive to a body region (122) of the memory cell that is floating and disposed between the first region (120) and the second region (124); and Applying a fourth voltage potential to a third region (126) of the memory cell via a respective carrier injection line (EP, 34) of the array (20). [2] The method of claim 1, wherein the respective local bit line (LCN, 404, 504) is coupled to a multiplexer (408, 508). [3] The method of claim 2, wherein the multiplexer (408, 508) is coupled to a global bit line (GCN, 506). [4] The method of claim 2, wherein the multiplexer comprises at least one masking transistor (520, 620) coupled to the respective local bit line (LCN, 404, 504). [5] The method of claim 4, wherein the multiplexer (408, 508) further comprises at least one hold transistor (HD, 518, 618) coupled to the respective local bit line (LCN, 404, 504). [6] The method of claim 5, wherein the respective selection transistor (SEL, 514) is coupled to the at least one masking transistor (520, 620) and the at least one holding transistor (HD, 518, 618). [7] The method of claim 1, further comprising maintaining the first voltage potential applied to the first region (120) at a constant level via the respective source line (EN, 32) during refreshing the semiconductor memory device (10). [8] The method of claim 1, further comprising applying a selection control signal to the respective selection transistor (SEL, 514) to activate the respective selection transistor (SEL, 514). [9] The method of claim 8, further comprising increasing the second voltage potential applied to the respective source line (EN, 32) from the second voltage potential applied to the respective source line (EN, 32) during a hold operation via the activated respective select transistor (SEL, 514). [10] The method of claim 1, further comprising increasing the fourth voltage potential applied to the respective carrier injection line (EP, 34) from the fourth voltage potential applied to the respective carrier injection line (EP, 34) during a hold operation. [11] The method of claim 1, further comprising applying decoupling control signals to the respective selection transistor (SEL, 514) to deactivate the respective selection transistor (SEL, 514). [12] The method of claim 11, wherein the respective local bit line (LCN, 404, 504) becomes floating after the respective selection transistor (SEL, 514) is deactivated. [13] The method of claim 1, further comprising increasing the third voltage potential applied to the respective word line (WL, 28) from the third voltage potential applied to the respective word line (WL, 28) during a hold operation to perform a read operation. [14] The method of claim 13, wherein increasing the third voltage potential activates the memory cell (12) to decrease the second voltage potential applied to the respective local bit line (LCN, 404, 504). [15] The method of claim 1, further comprising decreasing the third voltage potential applied to the respective word line (WL, 28) from the third voltage potential applied to the respective word line (WL, 28) during a write logic low operation to perform a write logic high operation. [16] The method of claim 15, wherein the third voltage potential applied to the respective word line (WL, 28) during the write logic high operation is higher than the third voltage potential applied to the respective word line (WL, 28) during a hold operation. [17] The method of claim 1, further comprising applying coupling control signals to the respective selection transistor (SEL, 514) to activate the respective selection transistor (SEL, 514) to perform an end for a write logic high operation. [18] The method of claim 17, further comprising discharging the second voltage potential applied to the respective local bit line (LCN, 404, 504) to forward bias a connection between the second region (124) and the third region (126). [19] The method of claim 1, further comprising decreasing the fourth voltage potential applied to the respective carrier injection line (EP, 34) from the fourth voltage potential applied to the respective carrier injection line (EP, 34) during a write logic high operation to perform a hold operation. [20] The method of claim 1, further comprising decreasing the second voltage potential applied to the respective local bit line (LCN, 404, 504) from the second voltage potential applied to the respective local bit line (LCN, 404, 504) during a write logic high operation to perform a hold operation.

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