Displaypanel

Abstract

Display panel (100, 200), comprising: a pixel block (PB1) comprising: a first subpixel (B2) coupled to a first data line (D6); and N second subpixels (R1, G1, B1, R2, G2), wherein each second subpixel of the N second subpixels is coupled to an associated second data line (D1 to D5) of N second data lines (D1 to D5); a data circuit (DC) comprising: N switches (S1 to S5), each of the N switches being coupled to an associated second subpixel (R1, G1, B1, R2, G2); and a data source (DS) coupled to the first data line (D6) and the N second data lines (D1 to D5); wherein the N switches (S1 to S5) are sequentially turned off when N voltage levels are sequentially output from the data source (DS) to the first data line (D6) and the N second data lines (D1 to D5), such that when a corresponding voltage level is written to the first subpixel (B2), the corresponding voltage level is written to at least one second subpixel (R1, G1, B1, R2, G2) of the N second subpixels, and N is a positive integer, where each of the N voltage levels passes through the first subpixel (D6) before reaching each of the N switches (S1 to S5).

Description

Field of the invention

[0001] The present invention generally provides a display panel and, more particularly, a narrow bezel display panel. Description of the state of the art

[0002] With the advancement of technology, various screens and display panels are used in our daily lives. Display panels can be used in smartphones, tablet PCs, laptops, or personal computers, for example. The display panel embedded in a device must meet the requirements of narrowness, lightness, low power consumption, and high display quality. Since a display panel with a maximum pixel capacity can provide satisfactory display quality, display developers and manufacturers strive to improve the pixel density of the display panel in combination with a narrow bezel to enhance display quality and market competitiveness.

[0003] Various non-rectangular display panels are also commonly used for electronic devices. For example, the display panel of a smartwatch (e.g., an Apple i-Watch) and some measurement panels of sensors are manufactured with curved or rounded corners. Generally, the display panel includes a data source for generating a data signal. The data signal is transmitted to each pixel block of the display via a fanout circuit. In a non-rectangular display panel, data circuits are coupled to corresponding pixel blocks, particularly according to predetermined arrangements. For example, data circuits are arranged alternately on a top and bottom surface of pixel blocks to reduce the layout area required for the display panel. As a result, the display panel has a narrow bezel.Based on this structure, the fanout circuits of all pixel blocks are coupled to the corresponding data circuits and are therefore also arranged alternately on two sides of pixel blocks. In other words, the fanout circuits are also arranged alternately on a top and bottom side of pixel blocks. In another conventional display panel, the data circuits are arranged on one side of pixel blocks. The fanout circuits of all pixel blocks are similarly coupled to the corresponding data circuits and arranged on one side of the pixel blocks. Although conventional display panels use various arrangement methods to reduce the layout area required for the display panel, additional layout area of the display panel is still required. The bezel width cannot therefore be optimized.

[0004] Therefore, developing a rectangular or non-rectangular display panel that can further reduce the layout area to optimize the bezel width and achieve a narrow bezel is a very important problem.

[0005] US 2008 / 0 043 012 A1 discloses a method for operating a display device in which a source output of a source driver is connected to a first to N-th data line via a first to N-th time-division multiplex switch.

[0006] From CN 1 04 732 908 A is a display panel in which the number of data lines in a layout area is reduced by a demultiplexer and the data lines can be grouped to be coupled with differential demultiplexers. Summary of the invention

[0007] The present invention discloses a display panel. The display panel comprises a pixel block, a data circuit, and a data source. The pixel block comprises a first subpixel coupled to a first data line and N second subpixels. Each second subpixel of the N second subpixels is coupled to an associated one of N second data lines. The data circuit comprises N switches. Each switch of the N switches is coupled to an associated second subpixel. The data source is coupled to the first data line and the N second data lines.When N voltage levels are sequentially output from the data source to the first data line and the N second data lines, the N switches are sequentially turned off such that when a corresponding voltage level is written to the first subpixel, the corresponding voltage level is written to at least one of the N second subpixels, where N is a positive integer. Each of the N voltage levels passes through the first subpixel before reaching each of the N switches. Short description of the drawings Fig. 1 shows a structure of a display panel according to a first embodiment of the present invention. Fig. 2 shows arrangements of fanout circuits of the display panel in Fig. 1. Fig. 2A shows a control method of the display panel in Fig. 2 by using gate circuits. Fig.3 shows a circuit structure of pixel blocks and data circuits of the display panel in Fig. 1. Fig. 4 shows a structure of a display panel according to a second embodiment of the present invention. Brief description of the reference symbols contained in the figures: 100, 200 display panels DS data source DC data circuit GC, GC A , GC B , GC C , GC D , GC E and GC F Gate circuit Fanout Fanout circuit 10 display area 11 pixel range PB1 to PB Q Pixel block W1 to W Q Width R1, G1, B1, R2, G2, B2, R3, G3, B3, R4, G4 and B4 subpixels D1 to D 12 data line S1 to S 10 Switch SL scan line DSIL1 to DSIL2 data source line RA1, RA2, RA3, RA4, RA5, RA6 and RA7 subpixel area Detailed description

[0008] Reference will now be made in detail to embodiments of the invention illustrated in the accompanying drawings. The provided embodiments are not to be considered as limitations on practical implementations, but merely as examples.

[0009] Fig. 1 shows a structure of a display panel 100 according to a first embodiment of the present invention. As shown in Fig. 1, the display panel 100 is a circular display panel. The display panel 100 includes a circular display area 10. The display area 10 includes a plurality of rectangular pixel blocks PB1 to PB Q . Q is a positive integer. The majority of pixel blocks PB1 to PB Q forms a pixel area 11. The pixel blocks PB1 to PB Qcomprise a plurality of subpixels. The display panel 100 further comprises a plurality of data circuits DC. These data circuits DC are respectively coupled to the pixel blocks PB1 to PB Q and alternately at the top and bottom of pixel blocks PB1 to PB Q As in the Fig. 1, the pixel block PB1 is coupled to an associated data circuit DC. The associated data circuit DC is arranged at the bottom of the pixel block PB1. The pixel block PB2 is coupled to an associated data circuit DC. The associated data circuit DC is arranged at the top of the pixel block PB2, etc. The display panel 100 further includes a plurality of gate circuits GC. These gate circuits GC are alternately arranged at the top and bottom of pixel blocks PB1 to PB Q arranged. As in Fig.1, the pixel block PB1 has a corresponding gate circuit GC arranged at the top. The pixel block PB2 has a corresponding gate circuit GC arranged at the bottom, and so on. A method for driving the pixel blocks PB1 to PB Q by using the gate circuits GC will be shown later (ie shown in Fig. 3). In other words, in the display panel 100, the gate circuit GC and the data circuit are arranged on two opposite sides of each pixel block PB1 to PB Qarranged. In this embodiment, the display panel 100 further comprises a data source DS and a fanout circuit (labeled "fanout"). The data source DS can be any device that has the ability to generate or receive image data. The data source DS can generate suitable data signals that are supported by the display panel 100. The data signals can be supplied via the fanout circuit to each pixel block PB1 to PB Q The layout of the fanout circuit of the display panel 100 is not limited to the Fig. 1 shown layout. The fanout circuit can be designed, for example, according to a Fig. 2. When the data circuits DC receive the data signals generated by the data source DS, the subpixels of the pixel blocks PB1 to PB Qcontrolled to display the image. In the display panel 100, W1 denotes a width of a data circuit DC associated with the pixel block PB1. W2 denotes a width of a data circuit DC associated with the pixel block PB2, etc. W Q denotes a width of a pixel block PB Q associated data circuit DC. W1 to W Q can be identical values. W1 to W Q can also be different or partially identical values. In particular, when Q becomes large, the values from W1 to W Q small to increase the subpixel density (or capacity) of the pixel blocks PB1 to PB Q in the display area 10. In this way, the shape of the pixel area 11 formed by the pixel blocks PB1 to PB Q formed, consistent with the shape of the display surface 10. The method for driving subpixels of the pixel blocks PB1 to PB Qby using the data signals generated by the data source DS via the data circuits DC is shown below.

[0010] Fig. 2 shows arrangements of fanout circuits of the display panel 100. In Fig. 2, the fanout circuits can be placed on one side (bottom) of the pixel blocks PB1 to PB QFor the pixel block PB1, a corresponding gate circuit GC is arranged at the top of the pixel block PB1. A corresponding data circuit DC is arranged at the bottom of the pixel block PB1. A corresponding fanout circuit may be arranged at the bottom of the corresponding data circuit DC. For the pixel block PB2, a corresponding data circuit DC is arranged at the top of the pixel block PB2. A corresponding fanout circuit may be arranged at the bottom of the pixel block PB2. A corresponding gate circuit GC may be arranged at the bottom of the corresponding fanout circuit. However, the arrangements of the fanout circuits of the display panel 100 are not limited to those shown in Fig. 2. In other embodiments, each fanout circuit may be appropriately located at a different location to reduce the required layout area.

[0011] Fig.2A shows a control method of the display panel 100. In Fig. 2A, the pixel blocks PB1 to PB Q controlled by the gate circuits GC. For simplicity, Q = 6 is used as an example. The pixel blocks of the display panel 100 are referred to as pixel blocks PB1 to pixel block PB6. The gate circuits GC of the display panel 100 are referred to as gate circuits GC A , Gate circuit GC B , gate circuit GCc, gate circuit GC D , Gate circuit GC E and gate circuit GC F . Furthermore, the dotted areas RA1 to RA6 indicate areas (areas) of subpixels of the display panel 100 (hereinafter referred to as subpixel area RA1 to subpixel area RA6). As shown in Fig. As shown in Figure 2A, the gate circuit GC generates ADrive currents. The drive currents are transmitted to the subpixel region RA1 along the direction of the arrow. The subpixel region RA1 can then be driven by the drive currents. The subpixel region RA1 specifically includes a portion of the subpixels of the pixel block PB3 and the pixel block PB4. The gate circuit GC Bgenerates drive currents. The drive currents are transmitted to the subpixel region RA2 along the direction of the arrow. The subpixel region RA2 can then be driven by the drive currents. The subpixel region RA2 specifically comprises a portion of the subpixels from the pixel block PB2 to the pixel block PB5. The gate circuit GCc generates drive currents. The drive currents are transmitted along the direction of the arrow to the subpixel region RA3. The subpixel region RA3 can then be driven by the drive currents. The subpixel region RA3 specifically comprises a portion of the subpixels from the pixel block PB2 to the pixel block PB5. The gate circuit GCc also generates further drive currents. The drive currents are transmitted along the direction of the arrow to the subpixel region RA4. The subpixel region RA4 can then be driven by the drive currents.The subpixel area RA4 specifically includes a portion of the subpixels from the pixel block PB1 to the pixel block PB6. The gate circuit GC. D generates drive currents. The drive currents are transmitted along the direction of the arrow to the subpixel region RA5. The subpixel region RA5 can then be driven by the drive currents. The subpixel region RA5 specifically includes a portion of the subpixels from the pixel block PB1 to the pixel block PB6. The gate circuit GC E generates drive currents. The drive currents are transmitted along the direction of the arrow to the subpixel region RA6. The subpixel region RA6 can then be driven by the drive currents. The subpixel region RA6 specifically includes a portion of the subpixels from the pixel block PB2 to the pixel block PB5. The gate circuit GC Egenerates drive currents. The drive currents are transmitted along the direction of the arrow to the subpixel region RA7. The subpixel region RA7 can then be driven by the drive currents. The subpixel region RA7 specifically comprises a portion of the subpixels of the pixel block PB3 and the pixel block PB4. In this way, all subpixels of the display panel 100 can be driven by sequentially controlling the gate circuit GC A , the gate circuit GC B , the gate circuit GCc, the gate circuit GC D , the gate circuit GC E and the gate circuit GC F However, the control method of the present invention is not limited to the control method in Fig. 2A. The direction of the drive currents with respect to the gate circuits GC A to GC F in Fig. 2A can also be changed. For example, the drive currents of the gate circuit GC Falong an opposite direction in Fig. 2A can be transmitted. Furthermore, the gate circuits GC A to GC F control specific subpixel areas. For example, the gate circuit GC F also drive the subpixel region RA6. In other words, a single gate circuit can drive a plurality of subpixel regions. For a single subpixel region, drive currents can be supplied from a plurality of gate circuits. For example, the subpixel region RA4 can be driven by the gate circuit GC D and the gate circuit GCc are used.

[0012] Fig. 3 shows a circuit structure of pixel blocks PB1 and PB2 and the associated data circuits DC of the display panel 100. As in Fig.3, the pixel block PB1 comprises a subpixel R1, a subpixel G1, a subpixel B1, a subpixel R2, a subpixel G2, a subpixel B2, and a scan line SL. These subpixels are respectively coupled to the data lines D1 to D6. The pixel block PB2 of the display panel 100 comprises a subpixel R3, a subpixel G3, a subpixel B3, a subpixel R4, a subpixel G4, a subpixel B4, and a scan line SL. These subpixels are respectively coupled to the data lines D7 to D 12coupled. In the display panel 100, the structure of the paired pixel blocks is similar to the structure of the pixel blocks PB1 and PB2. Furthermore, the subpixels are arranged according to a pixel sequence formed by a red subpixel, a green subpixel, and a blue subpixel. For the sake of brevity, two pixel blocks PB1 and PB2 are considered. A data circuit DC arranged at the bottom of the pixel block PB1 can be a demultiplexer. The dimension of the demultiplexer is six in this embodiment. The data circuit DC of the pixel block PB1 comprises a switch S1, a switch S2, a switch S3, a switch S4, and a switch S5. The data circuit DC of the pixel block PB2 comprises a switch S6, a switch S7, a switch S8, a switch S9, and a switch S 10. A data source line DSIL1 is coupled to the data line D6, wherein the data source line DSIL1 is also coupled to a data source DS (shown in Fig. 1). The data lines D1 to D5 of the pixel block PB1 are each coupled to the data line D6 via the switches S1 to S5. Similarly, a data source line DSIL2 is connected to the data line D 12 coupled, whereby the data source line DSIL2 is also coupled to a data source DS (shown in Fig. 1). The data lines D7 to D 11 of the pixel block PB2 are each controlled via switches S6 to S 10 coupled with the data line D 12 . The method for driving subpixels (ie, a row of subpixels) of the display panel 100 is shown below.

[0013] Here, an example is presented to illustrate a method for driving subpixel R1, subpixel G1, subpixel B1, subpixel R2, subpixel G2, and subpixel B2 of pixel block PB1. Similarly, subpixel R3, subpixel G3, subpixel B3, subpixel R4, subpixel G4, and subpixel B4 of pixel block PB2 can be driven accordingly. The example is illustrated below. For pixel block PB1, V R1 a target voltage level of subpixel R1. A target voltage level of subpixel G1 is V G1 . A target voltage level of subpixel B1 is V B1 . A target voltage level of subpixel R2 is V R2 . A target voltage level of subpixel G2 is V G2 . A target voltage level of subpixel B2 is V B2First, the scanning line SL is activated to turn on the subpixels R1 to B2. The switches S1 to S5 of the data circuit DC, which correspond to the pixel block PB1, are turned off sequentially. The data source DS generates the voltage level V R1 . The voltage level V R1 is transmitted to the data line D6 via a data source line DSIL1 during a first time interval T1. At this time, the switch S1 is turned on. The voltage level V received from the data line D6 R1 can therefore also be transmitted to the data line D1. This allows the subpixel B2 and the subpixel R1 to be charged via the data line D6 and the data line D1 during the first time interval T1, respectively, to reach the voltage level V R1 After the first time interval T1 has elapsed, switch S1 is turned off. Subsequently, the data source DS generates the voltage level V G1 . The voltage level V G1is transmitted to the data line D6 via the data source line DSIL1 during a second time interval T2. At this time, the switch S2 is turned on. The voltage level V received from the data line D6 G1 can therefore also be transmitted to the data line D2. This allows the subpixel B2 and the subpixel G1 to be charged via the data line D6 and the data line D2 during the second time interval T2, respectively, to reach the voltage level V G1 After the second time interval T2 has elapsed, switch S2 is turned off. Subsequently, the data source DS generates the voltage level V B1 . The voltage level V B1 is transmitted to the data line D6 via the data source line DSIL1 during a third time interval T3. At this time, the switch S3 is turned on. The voltage level V received from the data line D6 B1can therefore also be transmitted to the data line D3. This allows the subpixel B2 and the subpixel B1 to be charged via the data line D6 and the data line D3 during the third time interval T3, respectively, to reach the voltage level V B1 After the third time interval T3 has elapsed, switch S3 is turned off. Subsequently, the data source DS generates the voltage level V R2 . The voltage level V R2 is transmitted via the data source line DSIL1 to the data line D5 during a fourth time interval T4. At this time, the switch S4 is turned on. The voltage level V received from the data line D6 R2 can therefore also be transferred to the data line D4. This allows the subpixel B2 and the subpixel R2 to be charged via the data line D6 and the data line D4, respectively, during the fourth time interval T4 to reach the voltage level V R2After the fourth time interval T4 has elapsed, switch S4 is turned off. Subsequently, the data source DS generates the voltage level V G2 . The voltage level V G2 is transmitted to the data line D6 via the data source line DSIL1 during a fifth time interval T5. At this time, the switch S5 is turned on. The voltage level V received from the data line D6 G2 can therefore also be transferred to the data line D5. This allows the subpixel B2 and the subpixel G2 to be charged via the data line D6 and the data line D5, respectively, during the fifth time interval T5 to reach the voltage level V G2 After the fifth time interval T5 has elapsed, switch S5 is turned off. Subsequently, the data source DS generates the voltage level V B2 . The voltage level V B2is transmitted via the data source line DSIL1 to the data line D6 during a sixth time interval T6. This allows the subpixel B2 to be charged via the data line D6 during the sixth time interval T6 to reach the voltage level V B2 In this embodiment, the data source DS generates different voltage levels during multiple time intervals and transmits these voltage levels to the data line D6 via the data source line DSIL1. This allows the subpixel R1, the subpixel G1, the subpixel B1, the subpixel R2, the subpixel G2, and the subpixel B2 of the pixel block PB1 to be charged to the corresponding target voltage levels. The aforementioned control method can be illustrated using the following table. TABLE A S1 S2 S3 S4 S5 Charging status R1 G1 B1 R2 G2 B2 T1 ONE HAZE HAZE HAZE HAZE VR1 VR1 T2 HAZE ONE HAZE HAZE HAZE VR1 VG1 VG1 T3 HAZE HAZE ONE HAZE HAZE VR1 VG1 V B1 V B1 T4 HAZE HAZE HAZE ONE HAZE VR1 VG1 V B1 VR2 VR2 T5 HAZE HAZE HAZE HAZE ONE VR1 VG1 V B1 VR2 V G2 V G2 T6 HAZE HAZE HAZE HAZE HAZE VR1 VG1 V B1 VR2 V G2 V B2

[0014] In Table A, the first row represents switches S1 to S5. The first column represents time intervals T1 to T6. The label "EN" denotes an on-state switch. The label "DIS" denotes an off-state switch. Obviously, six subpixels of pixel block PB1 can each be charged to reach the corresponding target voltage levels in a stable state. In particular, the number of mischarges of subpixel B2 of pixel block PB1 is 5. Although the mischarge status of subpixel B2 occurs during a transient state, it can be ignored because the duration of the transient state is significantly shorter than the duration of the stable state. In other words, the driving method of pixel block PB1 is to sequentially turn on the switches (i.e., switch S1, switch S2, switch S3, switch S4, and switch S5) and then turn them off when multiple voltage levels (i.e., voltage levels VR1 , voltage level V G1 , voltage level V B1 , voltage level V R2 , voltage level V G2 and voltage level V B2 ) are sequentially transmitted from the data source DS to the data line D6 and the data lines D1 to D5. Therefore, when a corresponding voltage level is written to the subpixel B2, the corresponding voltage level is written to at least one of the subpixels R1, G1, B1, R2, and G2. In addition, only the voltage (V B2 -V G2 ) is needed to charge subpixel B2 to maintain the voltage level V B2 during the sixth time interval T6, since the subpixel B2 is switched to the voltage level V G2 is summoned.

[0015] However, the method for driving the row of subpixels of the pixel block PB1 is not limited to the method shown in Table A. The method can be modified or changed to achieve that six subpixels of the pixel block PB1 can each be charged to reach the corresponding target voltage levels in a stable state (i.e., voltage level V R1 , voltage level V G1 , voltage level V B1 , voltage level V R2 , voltage level V G2 , voltage level V B2 ). The operating modes of switches S1 to S5 can also be changed. For example, in another embodiment, switches S1 to S5 may be initially turned on. The method for driving the row of subpixels of pixel block PB1 can be performed according to the following table. TABLE B S1 S2 S3 S4 S5 Charging status R1 G1 B1 R2 G2 B2 T1 ONE ONE ONE ONE ONE VR1 VR1 VR1 VR1 VR1 VR1 T2 HAZE ONE ONE ONE ONE VR1 VG1 VG1 VG1 VG1 V G1 T3 HAZE HAZE ONE ONE ONE VR1 VG1 V B1 V B1 V B1 V B1 T4 HAZE HAZE HAZE ONE ONE VR1 VG1 V B1 VR2 VR2 VR2 T5 HAZE HAZE HAZE HAZE ONE VR1 VG1 V B1 VR2 V G2 V G2 T6 HAZE HAZE HAZE HAZE HAZE VR1 VG1 V B1 VR2 V G2 V B2

[0016] In Table B, the switches (i.e., switch S1, switch S2, switch S3, switch S4, and switch S5) are turned off sequentially. Although six subpixels of the pixel block PB1 can each be charged to the corresponding target voltage levels (i.e., voltage level V R1 , voltage level V G1 , voltage level V B1 , voltage level V R2 , voltage level V G2 , voltage level V B2) in a steady state, however, in the transient state, mischarge states of subpixels G1 to B2 occur. Specifically, the number of mischarges of subpixel G1 is 1. The number of mischarges of subpixel B1 is 2. The number of mischarges of subpixel R2 is 3. The number of mischarges of subpixel G2 is 4. The number of mischarges of subpixel B2 is 5. Accordingly, the number of mischarges of all subpixels is 15. The number of mischarges of all subpixels in Table B is greater than the number of mischarges of all subpixels in Table A. Therefore, the method of driving the row of subpixels of pixel block PB1 using the switches that are sequentially turned on and then off outperforms the method of driving the row of subpixels of pixel block PB1 using the switches that are sequentially turned off.

[0017] The driving method of pixel block PB2 of display panel 100 is similar to the driving method of pixel block PB1 of display panel 100. For pixel block PB1, the driving currents are transmitted from data source line DSIL1 to the corresponding subpixels via data lines D1 to D6, so that the corresponding subpixels can be charged to reach the target voltage levels. For pixel block PB2 in Fig. 3 the control currents generated by the data source DS are transferred via the data source line DSIL2 to the data line D 12 to charge subpixel B4 to reach a target voltage level. Similarly, switches S6 to S 10sequentially switched on and off, or they can be selectively switched off sequentially. This allows a target voltage level to be supplied to a corresponding subpixel (ie, a corresponding subpixel of the subpixels R3 to G4) via a corresponding switch. Since the driving method of the pixel block PB2 is similar to the driving method of the pixel block PB1, the illustration is omitted here. In particular, in the pixel block PB2, since the data line D 12 can be regarded as an embedded connection line for transmitting a data signal from the data source DS to the pixel block PB2, the number of connection lines in the fanout circuit can be reduced, resulting in an optimization of the arrangement of the data circuit DC and the fanout circuit. Furthermore, since the structure of each pixel block of the remaining pixel blocks in the display panel 100 is similar to the structure of the Fig.3 is PB1 or PB2, the layout area requirement of the display panel 100 can be further reduced, which leads to an optimization of the frame width of the display panel 100.

[0018] Fig. 4 shows a structure of a display panel 200 according to a second embodiment of the present invention. As in Fig.4, a gate circuit GC and a data circuit DC are arranged as a pair on one side of two pixel blocks of the display panel 200. Another pair of a gate circuit GC and a data circuit DC is arranged on another side of two pixel blocks of the display panel 200. Specifically, a fanout circuit may be arranged between the gate circuit GC and the data circuit DC. In the display panel 200, the data circuit DC arranged at the bottom of the pixel block PB1 and the pixel block PB2 may be used to drive the pixel block PB1. The data circuit DC arranged at the top of the pixel block PB1 and the pixel block PB2 may be used to drive the pixel block PB2. Thereby, a height (or length) of the data circuit DC can be further reduced. For example, in the display panel 100, a width of the data circuit DC is less than or equal to a width of a pixel block.In the display panel 200, the width of the data circuit corresponds to one to two times the width of the pixel block. The height (or length) of the data circuit DC of the display panel 200 is significantly smaller (i.e., approximately 1 / 5) than the height (or length) of the data circuit DC of the display panel 100. The layout area required by the data circuit DC of the display panel 200 is therefore smaller than the layout area required by the data circuit DC of the display panel 100. The width of the frame of the display panel 200 can therefore be further reduced.

[0019] Although display panel 100 and display panel 200 are circular display panels, the present invention is not limited to circular display panels. In other embodiments, the display panel may be, for example, a rectangular display panel, a triangular display panel, or any arcuate display panel. Display panels 100 and 200 use a demultiplexer with a dimension of 6. However, the present invention is not limited to using a demultiplexer with a dimension of 6. In other embodiments, any demultiplexer with a dimension of at least 2 may be used for the display panel. Furthermore, the rows of subpixels of display panels 100 and 200 are arranged sequentially according to a pixel sequence formed by a red subpixel, a green subpixel, and a blue subpixel.However, the row of subpixels of the present invention is not limited to using the specified pixel sequence. In other embodiments, each pixel block may comprise a subset of three primary color subpixels. For example, a first pixel block may comprise a red subpixel R and a green subpixel G. A second pixel block may comprise a blue subpixel B and a red subpixel R. A third pixel block may comprise a green subpixel G and a blue subpixel B.

[0020] In summary, the present invention discloses a display panel with a narrow frame. Some data lines of pixel blocks can be considered as embedded interconnect lines for transmitting a data signal. A method for driving a display panel is also disclosed. The idea behind this is to charge at least two subpixels simultaneously to achieve a voltage level generated by a data source. Since the number of interconnect lines in the fanout circuit can be reduced, arrangements of the data circuit DC and the fanout circuit can be optimized. Therefore, a width or layout area requirement of the display panel frame can be further reduced.

[0021] Those skilled in the art will recognize that numerous modifications and variations of the apparatus and method can be made while retaining the teachings of the invention. Accordingly, the foregoing disclosure should be construed solely by the scope of the appended claims. Commercial applicability

[0022] The disclosure provides a narrow-bezel display panel. The design concept of the invention is to make the data lines of some pixels into paths that transmit a data signal from a data source to a pixel area. The data circuit of the display panel can provide specific voltages to at least two subpixels at the same time. The display panel can reduce the layout area of the fanout circuit. The display panel can also optimize the position of the circuits in the fanout area and optimize the position of the data circuit. The display panel can therefore further reduce the bezel width.

Claims

[1] Display panel (100, 200), comprising: a pixel block (PB1) comprising: a first subpixel (B2) coupled to a first data line (D6); and N second subpixels (R1, G1, B1, R2, G2), wherein each second subpixel of the N second subpixels is coupled to an associated second data line (D1 to D5) of N second data lines (D1 to D5); a data circuit (DC) comprising: N switches (S1 to S5), each of the N switches being coupled to an associated second subpixel (R1, G1, B1, R2, G2); and a data source (DS) coupled to the first data line (D6) and the N second data lines (D1 to D5); wherein the N switches (S1 to S5) are sequentially turned off when N voltage levels are sequentially output from the data source (DS) to the first data line (D6) and the N second data lines (D1 to D5), such that when a corresponding voltage level is written to the first subpixel (B2), the corresponding voltage level is written to at least one second subpixel (R1, G1, B1, R2, G2) of the N second subpixels, and N is a positive integer, where each of the N voltage levels passes through the first subpixel (D6) before reaching each of the N switches (S1 to S5). [2] The display panel (100, 200) of claim 1, wherein the N switches are sequentially turned on and then turned off when the N voltage levels are sequentially output from the data source (DS) to the first data line (D6) and the N second data lines (D1 to D5). [3] Display panel (100, 200) according to claim 1, wherein two data circuits (DC) connected to two adjacent pixel blocks (PB1 to PB Q ) are coupled to different sides of the two adjacent pixel blocks (PB1 to PB Q ) are arranged. [4] The display panel (100, 200) according to claim 1, wherein the N second subpixels (R1, G1, B1, R2, G2) and the first subpixel (B2) are arranged according to a pixel sequence formed by a red subpixel, a green subpixel and a blue subpixel. [5] The display panel (100, 200) of claim 1, further comprising: a gate circuit (GC) configured to gate a plurality of subpixels (R1, G1, B1, R2, G2, B2) of at least one pixel block (PB1 to PB Q ), wherein the gate circuit (GC) and the data circuit (DC) are arranged on opposite sides of the pixel block. [6] A display panel (100, 200) according to claim 1, wherein the widths of a plurality of pixel blocks (PB1 to PB Q ) of the display panel (100, 200) are identical. [7] Display panel (100, 200) according to claim 1, wherein a width of the data circuit (DC) is less than or equal to a width of the pixel block (PB1 to PB Q ) is. [8] Display panel (100, 200) according to claim 1, wherein a width of the data circuit (DC) is between one and two times a width of the pixel block (PB1 to PB Q ) amounts. [9] A display panel (100, 200) according to claim 1, wherein the widths of a plurality of pixel blocks (PB1 to PB Q ) of the display panel (100, 200) are not all the same. [10] Display panel (100, 200) according to claim 1, wherein the data circuit (DC) is a demultiplexer.

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