Decoding data using bitline defect information

Abstract

Data storage device (102) comprising: a memory (104) containing a plurality of memory elements; and a control unit (120) coupled to the memory, the control unit being configured: receive first bit line defect information (134) from the memory, the first bit line defect information identifying bit lines affecting a first group of memory elements (103) of the plurality of memory elements; receive second bit line defect information (135) from the memory, the second bit line defect information identifying bit lines affecting a second group of memory elements (105) of the plurality of memory elements; generate a first group of soft bits (172) based on the first bit line defect information, wherein the first group of soft bits indicates a probability that a first group of bits corresponding to the first group of memory elements (103) is correct, and generate a second group of soft bits (174) based on the second bit line defect information, the second group of soft bits indicating a probability that a second group of bits corresponding to the second group of memory elements (105) is correct.

Description

Area of ​​Revelation

[0001] The present disclosure generally relates to decoding data using bitline defect information. background

[0002] Data storage devices may include decoders such as error-correcting code (ECC) engines, which are used to correct errors in data stored in memories of the data storage devices. Some ECC engines use soft bits, which indicate probabilities that one or more bits are correct (or erroneous), to decode a representation of data and correct one or more errors. One type of information used to generate the soft bits is bitline defect information. Bitline defect information may indicate which bitlines of a memory are "bad bitlines." Bad bitlines refer to bitlines that have defects (e.g., glitches, manufacturing defects, and / or "faults"). At least some memory elements coupled to bad bitlines may have a high probability of storing incorrect data.A first type of bitline defect is called a "closed defect" (e.g., a short circuit). A closed defect occurs when one bitline is in contact with another bitline, causing all memory elements coupled to the two bitlines to have a high probability of storing incorrect data. A second type of bitline defect is called an "open defect" (e.g., a "break"). An open defect occurs when a "break" exists in a bitline. Memory elements on one side of a break have a high probability of storing incorrect data, but memory elements on the other side of the break do not have an increased probability of storing incorrect data.

[0003] During the manufacturing and production of a data storage device, tests are performed to identify bad bitlines (e.g., bitlines that have closed defects and open defects) in the memory. Bitline defect information for the entire memory is stored in the memory and used to generate soft bits available to the ECC engine for use in decoding data. Because a bitline that has an open defect is identified as a bad bitline, at least some memory elements (e.g., memory elements to one side of the bitline break) that do not have a high probability of storing faulty data are erroneously identified as elements that have a high probability of storing faulty data.Providing a decoder with soft bits that erroneously identify bits as bits that have a high probability of being erroneous reduces decoder efficiency, increasing the processing time and power consumption of the decoder during the decoding process.

[0004] US 2015 / 0 194 201 A1 discloses systems and methods for real-time correction of bit errors in a resistive memory, wherein the memory is divided into memory banks and single-bit repair arrays are used. Brief description of the drawings Fig. 1 is a block diagram of a specific illustrative example of a system configured to decode data stored in a group of storage elements of a memory of a memory device using bitline defect information that identifies bitlines that affect the group of storage elements; Fig. 2 is a block diagram illustrating several blocks of memory 104 of Fig. 1 and several bit lines having open defects; Fig. 3 is a flowchart showing a specific example of a method for operating the control unit of the data storage device of Fig. 1; and Fig. 4 is a flowchart illustrating a specific example of a method for operating the memory of the data storage device of Fig. 1 represents. Detailed description

[0005] According to the invention, a data storage device and a method having the features of the independent claims are provided; dependent claims relate to preferred embodiments.

[0006] Specific implementations are described with reference to the drawings. In the description, common features are designated by common reference numerals throughout the drawings. As used herein, an ordering term (e.g., "first," "second," "third," etc.) used to modify an element such as a structure, component, operation, etc., does not in and of itself indicate a priority or order of the element with respect to another element, but rather merely distinguishes the element from another element having the same name (except for use of the ordering term).

[0007] Referring to Fig. 1, a specific illustrative example of a system is depicted and generally designated 100. System 100 includes a data storage device 102 and an access device 150. Data storage device 102 includes a controller 120 and a memory 104 coupled to controller 120. In some implementations, memory 104 is non-volatile memory. In other implementations, memory 104 is volatile memory.

[0008] The memory 104 may include multiple memory elements configured to store data, such as a first group of memory elements 103 and a second group of memory elements 105. The first group of memory elements 103 and the second group of memory elements 105 may be coupled to a common set of bitlines. The memory 104 may also store bitline defect information associated with groups of memory elements. The memory 104 may include multiple chips, and each chip may be organized into multiple groups of memory elements (e.g., blocks, logical pages, and / or physical pages). Bitline defect information may correspond to a portion of a chip (e.g., a group of memory elements) rather than the entire chip.The bitline defect information associated with or corresponding to a particular group of memory elements of memory 104 identifies one or more bitlines having defects (e.g., faults, manufacturing defects, and / or "errors") that affect or impact (e.g., affect) the particular group of memory elements. In some implementations, the particular group of memory elements corresponds to a particular block of memory 104. In other implementations, the particular group of memory elements may correspond to a wordline of memory 104 or a group of wordlines of memory 104. The bitline defect information does not identify bitlines having defects that do not affect the particular group of memory elements.For example, the bitline defect information corresponding to the specific group of storage elements may only identify a bitline having an open defect if the open defect affects the storage elements in the specific group of storage elements of memory 104 (e.g., if the open defect causes the storage elements in the specific group of storage elements to have a high probability of storing faulty data). The bitline defect information indicating bitlines having defects affecting the specific group of storage elements may be used by the control unit 120 to increase the speed and reduce the power consumption of a data process, as further described herein.

[0009] The memory 104 may be configured to store bitline defect information for different groups of memory elements (e.g., blocks) of the memory 104. For example, a dedicated portion 142 of the memory 104 may store first bitline defect information 134 associated with the first group of memory elements 103 (e.g., a first block) of the memory 104, and the dedicated portion 142 may store second bitline defect information 135 associated with the second group of memory elements 105 (e.g., a second block) of the memory 104. The first bitline defect information 134 and the second bitline defect information 135 each identify bitlines having defects (e.g., bitline errors) affecting the corresponding group of memory elements.For example, the first bitline defect information 134 may identify bitlines that have defects affecting the first group of memory elements 103. The first bitline defect information may identify bitlines that have "closed defects" (e.g., shorts) affecting an entire bitline and bitlines that have "open defects" (e.g., breaks) affecting the first group of memory elements 103. An open defect that "affects" or "affects" the first group of memory elements 103 refers to a break in a bitline located on a specific side of the wordlines in the first group of memory elements 103, such that memory elements coupled to the wordlines have a high probability of storing faulty data.The first bit line defect information 134 does not identify bit lines that have open defects that do not affect the first group of memory elements 103. Open defects are described with reference to FIG. Fig. 2. The second bitline defect information 135 may identify bitlines having defects affecting the second group of memory elements 105. Because one or more open defects affecting the first group of memory elements 103 may not affect the second group of memory elements 105, or vice versa, the first bitline defect information 134 may be different from the second bitline defect information 135.

[0010] To retrieve the bitline defect information, the memory 104 includes a selection module 144. The selection module 144 may be configured to retrieve the first bitline defect information 134 relating to the first group of memory elements 103, and the selection module 144 may be configured to retrieve the second bitline defect information 135 relating to the second group of memory elements 105. In a particular implementation, the first bitline defect information 134 and the second bitline defect information 135 may be stored in a table in the memory 104. The selection module 144 may be configured to retrieve bitline defect information based on an address in a request for data received from the control unit 120. To illustrate this, the memory 104 may first receive a first request for data 130 that specifies a first address where read data is stored in the memory 104.The selection module 144 may retrieve the first bitline defect information 134 in response to a determination that the first address corresponds to the first group of memory elements 103. The first bitline defect information 134 may be provided to the control unit 120 with a representation of first read data 132 stored in the first group of memory elements 103, and the control unit 120 may use the first bitline defect information 134 to decode the representation of the first read data 132.

[0011] The control unit 120 may be configured to receive bitline defect information related to a specific group of memory elements and to use the bitline defect information during a decoding process of read data stored in the specific group of memory elements. The control unit may be configured to receive the first bitline defect information 134 from the memory 104 and generate a first set of soft bits 172 (e.g., probability information) based on sensed information from the first group of memory elements 103 and the first bitline defect information 134. For example, a soft bit generator 170 of the control unit 120 may be configured to generate the first set of soft bits 172 based on the first bitline defect information 134 and information indicating voltage levels sensed from the first set of memory elements 103.The control unit 120 may also be configured to receive the second bitline defect information 135 from the memory 104 and generate a second set of soft bits 174 (e.g., second probability information) based on the second bitline defect information 135 and sensed information from the second group of memory elements 105. Because the sets of soft bits 172 and 174 are generated based on bitline defect information pertaining to a specific group of memory elements, the sets of soft bits 172 and 174 may include a reduced number of bits erroneously identified as having a high probability of being defective, compared to sets of soft bits generated based on bitline defect information for the entire memory 104.

[0012] The control unit 120 may be configured to decode a representation of read data based on a corresponding set of soft bits. For example, the control unit 120 may include a decoder 176 configured to generate first decoded data 138 based on the first set of soft bits 172 and the representation of the first read data 132. The decoder 176 may also be configured to generate second decoded data 139 based on the second set of soft bits 174 and the representation of the second read data 133.Because the first set of soft bits 172 is generated based on an identification of bit lines having defects that affect the first group of memory elements 103 (and not defects that do not affect the first group of memory elements 103), the first set of soft bits 172 may have fewer bits that are falsely indicated as having a high probability of being faulty compared to a set of soft bits generated based on a list of all bit lines having defects, regardless of whether the defects affect the first group of memory elements 103.Reducing a number of bits that are erroneously indicated as having a high probability of being erroneous increases the efficiency of the decoder 176, thereby increasing the speed and reducing the power consumption of the decoder 176 during a process of generating the first decoded data 138. After generating the first decoded data 128 (and / or additional decoded data, as further described herein), the first decoded data 138 may be provided to the access device 150 in response to a request for data from the access device 150 (e.g., a request sent as part of a read operation).

[0013] The data storage device 102 and the access device 150 may be coupled via a connection (e.g., a communication path 110), such as a bus or a wireless connection. For example, the data storage device 102 may include an access interface 108 that enables communication via the communication path 110 between the data storage device 102 and the access device 150, such as when the access device 108 is communicatively coupled to the access device 150. In some implementations, the data storage device 102 may be embedded within the access device 150, such as in accordance with a Joint Electron Devices Engineering Council (JEDEC) Solid State Technology Association universal flash memory (UFS) configuration. Alternatively, the data storage device 102 may be removable from the access device 150 (i.e., "removably" coupled to the access device 150).As one example, data storage device 102 may be removably coupled to access device 150 in accordance with a detachable universal serial bus (USB) configuration. In some implementations, data storage device 102 may include or correspond to a solid-state drive (SSD) that may be included in or distinct from (and accessible through) access device 150. For example, data storage device 102 may include or correspond to an SSD that may be used as an embedded storage drive (e.g., a mobile embedded storage drive), an enterprise storage drive (ESD), a client storage device, or a cloud storage drive, as illustrative and non-limiting examples. In some implementations, data storage device 102 may be indirectly coupled to access device 150, e.g., via a network.For example, the data storage device 102 may be a network-attached storage (NAS) device or a component (e.g., a solid-state drive (SSD) device) of a data center storage system, an enterprise storage system, or a storage area network.

[0014] In some implementations, data storage device 102 may be configured to couple with access device 150 as embedded storage, such as eMMC® (trademark of JEDEC Solid State Technology Association, Arlington, Virginia) and eSD as illustrative examples. To illustrate, data storage device 102 may correspond to an eMMC (Embedded MultiMedia Card). As another example, data storage device 102 may comprise a memory card, such as a microSD card. B. a "Secure Digital" card (SD® card), a microSD® card, a miniSD™ card (trademark of SD-3C LLC, Wilmington, Delaware), a MultiMediaCard™ card (MMC™ card) (trademark of JEDEC Solid State Technology Association, Arlington, Virginia), or a CompactFlash® card (CF card) (trademark of SanDisk Corporation, Milpitas, California). The data storage device 102 can operate in accordance with a JEDEC industry specification.For example, the data storage device 102 may operate in accordance with a JEDEC eMMC specification, a JEDEC Universal Flash Memory (UFS) specification, one or more other specifications, or a combination thereof.

[0015] In some implementations, the data storage device 102 and the access device 150 may be configured to communicate using one or more protocols, such as an eMMC protocol, a Universal Flash Memory (UFS) protocol, a Universal Serial Bus (USB) protocol, a Serial Attached Storage (SATA) protocol, and / or another protocol, as illustrative, non-limiting examples. The one or more protocols may include a standardized protocol and / or a non-standardized protocol, such as a proprietary protocol. In some implementations, the data storage device 102 and the access device 150 may be configured to communicate using dual-channel communication (e.g., both devices may issue and receive commands from the other device).

[0016] The access device 150 may include a memory interface (not shown) and may be configured to communicate with the data storage device 102 via the memory interface to read and write data to the memory 104 of the data storage device 102. For example, the access device 150 may operate in accordance with a Joint Electron Devices Engineering Council (JEDEC) industry specification, such as a Universal Flash Memory (UFS) Access Controller Interface Specification. As other examples, the access device 150 may operate in accordance with one or more other specifications, such as a Secure Digital (SD) Access Controller Specification as an illustrative, non-limiting example. The access device 150 may communicate with the memory 104 in accordance with any other suitable communication protocol.

[0017] The access device 150 may include a processor and a memory. The memory may be configured to store data and / or instructions executable by the processor. The memory may be a single memory or may include multiple memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof. The access device 150 may issue one or more commands to the data storage device 102, such as one or more requests to delete data, read data from the memory 104 of the data storage device 102, or write data to the memory. For example, the access device 150 may be configured to provide data to be stored in the memory 104 or to request data to be read from the memory 104.The access device 150 may be a mobile phone, a music player, a video player, a game console, an electronic reading device, a personal digital assistant (PDA), a computer such as a laptop computer or notebook computer, a network computer, a server, any other electronic device, or a combination thereof, as illustrative non-limiting examples.

[0018] The control unit 120 may be configured to receive data and / or instructions from the access device 150 and provide data and / or instructions to the memory 104. The control unit 120 is coupled to the memory 104 via a bus 106, an interface (e.g., interface circuitry such as a memory interface 109), another structure, or a combination thereof. The control unit 120 and the memory 104 may exchange information via the bus 106, the memory interface 109, or a combination thereof. For example, one or more of representations of read data, bitline defect information, requests for data, and other data or instructions may be exchanged between the control unit 120 and the memory 104 via the bus 106, the memory interface 109, or a combination thereof.

[0019] The control unit 120 is configured to receive data and instructions from the access device 150 and to send data to the access device 150. For example, the control unit 120 may send data to the access device 150 via the access interface 108, and the control unit 120 may receive data from the access device 150 via the access interface. The control unit 120 is configured to send data and commands to the memory 104 and to receive data from the memory 104. For example, the control unit 120 is configured to send data and a write command to cause the memory 104 to store data at a specified address of the memory 104. The write command may specify a physical address of storage element(s) within a portion (e.g., a block) of the memory 104 that is to store the data.The control unit 120 is configured to send a read command to the memory 104 to access data from a specified address of the memory 104. The read command may specify the physical address of the memory element(s) of a portion (e.g., a block) of the memory 104 (e.g., a physical address of a word line coupled to the memory elements).

[0020] The read command may be based on a data request received from the access device 150. For example, the access device 150 may send data requests to the control unit 120 via the communication path 110, the access interface 108, or a combination thereof. Based on the data requests, the control unit 120 is configured to send requests for data (e.g., read commands) to the memory 104 and receive representations of data from the memory 104 in response to the request for data. The control unit 120 is configured to decode the representations of data based on the bitline defect information, as further described herein. The control unit 120 is also configured to send decoded data to the access device 150 via the communication path 110, the access interface 108, or a combination thereof.

[0021] The memory 104 of the data storage device 102 may include non-volatile memory. In a particular implementation, the memory 104 includes flash memory. The memory 104 includes a plurality of memory elements configured to store data. The memory 104 may have a two-dimensional (2D) memory configuration. Alternatively, the memory 104 may have another configuration, such as a three-dimensional (3D) memory configuration. For example, the memory 104 may include a three-dimensional (3D) memory configuration monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. In other implementations, the memory 104 may include volatile memory. The memory 104 may include one or more memory chips.In some implementations, memory 104 includes circuitry associated with the operation of the memory elements (e.g., the memory cell).

[0022] The memory 104 may include multiple groups of memory elements. For example, the memory 104 may include the first group of memory elements 103 and the second group of memory elements 105. The multiple groups of memory elements may include or correspond to specific groupings of the memory 104. In one particular implementation, the multiple groups of memory elements correspond to multiple blocks of the memory 104. For example, the first group of memory elements 103 corresponds to a first block of the memory 104, and the second group of memory elements 105 corresponds to a second block of the memory 104. In other implementations, the multiple groups of memory elements may correspond to other groupings, such as logical pages or physical pages. If the memory 104 includes multiple chips, each chip may be organized into multiple groups of memory elements.In one particular implementation, each block of memory 104 includes storage elements coupled to 128 wordlines. In other implementations, blocks of memory 104 may include more than or fewer than 128 wordlines. In one particular implementation, memory 104 includes or corresponds to flash memory including multiple blocks, where the first group of storage elements 103 includes a first block of the multiple blocks and the second group of storage elements 105 includes a second block of the multiple blocks. Although an example of memory 104 including two groups of storage elements is described, such an example is for illustrative purposes only. In other implementations, memory 104 may include more than two groups of storage elements (e.g., blocks) or may include a single group of storage elements (e.g., block).

[0023] The memory 104 also includes the dedicated section 142 configured to store bitline defect information. For example, the dedicated section 142 may store the first bitline defect information 134 and the second bitline defect information 135. In a particular implementation, the bitline defect information may be stored in a table (e.g., a bitline defect information table). A first entry in the table may contain the first bitline defect information 134, and a second entry in the table may contain the second bitline defect information 135. In other implementations, as a non-limiting example, the bitline defect information may be stored in a different data structure, e.g., as a list. In some implementations, the bitline defect information may be compressed, as further described herein.In some implementations, each group of storage elements of memory 104 may have corresponding bitline defect information stored in the dedicated section 142. If memory 104 includes multiple chips, groups of storage elements from multiple chips may have corresponding bitline defect information stored in the dedicated section 142. In other words, bitline defect information may correspond to a portion of a chip (e.g., a group of storage elements of the chip) rather than the entire chip.

[0024] In a particular implementation, the dedicated section 142 includes one or more read-only memory (ROM) fuses. In this implementation, the bitline defect information (e.g., the first bitline defect information 134 and the second bitline defect information 135) may be generated during one or more factory tests during the manufacture of the data storage device 102. For example, after the memory 104 is welded to a printed circuit board (PCS) of the data storage device 102, tests may be performed for each group of memory elements of the memory 104 to determine which bitlines have defects (e.g., glitches, manufacturing defects, or faults) affecting the tested group of memory elements.After one or more bitlines having defects affecting the tested group of memory elements have been identified, one or more ROM fuses may be "blown" to store information identifying the bitlines. The information may be read by memory 104, such as selection module 144, as part of retrieving the bitline defect information corresponding to a particular group of memory elements of memory 104. Although the one or more ROM fuses are described as being included in memory 104, such description is non-limiting and is for illustrative purposes only. In other implementations, the one or more ROM fuses may be part of a read-only memory (ROM) separate from memory 104, or the one or more ROM fuses may be included in control unit 120.

[0025] Additionally or alternatively, the dedicated section 142 includes one or more single-level cell (SLC) memory elements. In this implementation, the bitline defect information may be generated during one or more tests during production of the data storage device 102. For example, production tests may be performed for each group of memory elements of the memory 104 to determine which bitlines have defects that affect the tested group of memory elements. To illustrate this, data having a specific pattern may be written to a group of memory elements of the memory 104, and a representation of the data stored in the group of memory elements may be read and compared to the data that was written (e.g., the specific pattern).Based on the comparison, bitlines having defects affecting the group of storage elements may be identified. The production test may be performed on each group of storage elements of memory 104 to determine bitline defect information corresponding to each group of storage elements. In another implementation, the bitline defect information may be generated or updated during the lifetime of data storage device 102. For example, control unit 120 or circuitry in memory 104 may be configured to initiate one or more tests to detect bitline defect information corresponding to each group of storage elements of memory 104.The tests may be the same as the tests described above, except that the tests are performed during production of the data storage device 102, and the test for each group of memory elements of the memory 104 may determine one or more bit lines that have defects affecting the tested group of memory elements.

[0026] The bitline defect information (e.g., the first bitline defect information 134 and the second bitline defect information 135) identifies bitlines having defects affecting a corresponding group of storage elements of the memory 104. For example, the first bitline defect information 134 identifies bitlines having defects affecting the first group of storage elements 103, and the second bitline defect information 135 identifies bitlines having defects affecting the second group of storage elements 105. In a particular implementation, the bitline defect information includes an identifier of each bitline identified as having a defect affecting the corresponding group of storage elements of the memory 104.In another implementation, the bitline defect information includes up to a specific number of identifiers of bitlines identified as having a defect affecting the corresponding group of memory elements. In some implementations, the groups of memory elements of memory 104 may include blocks of memory 104. In other implementations, the groups of memory elements may be smaller than blocks. For example, in some implementations, bitline defect information may be generated for each wordline in memory 104 or for other groups of memory elements of memory 104 that are smaller than blocks.In still other implementations, the groups of memory elements may be larger than blocks so that less bitline defect information is stored in the memory 104 and the dedicated portion 142 may be smaller, reducing a size of the memory 104.

[0027] In some implementations, the bitline defect information (e.g., the first bitline defect information 134 and the second bitline defect information 135) may identify at most one (e.g., a maximum of one) specific number of bitlines. In a particular implementation, the bitline defect information identifies up to twenty bitlines having defects affecting a corresponding group of storage elements of the memory 104. For example, if twenty or more bitlines have defects affecting the corresponding group of storage elements of the memory 104, the bitline defect information indicates twenty bitlines.If fewer than twenty bitlines have defects affecting the corresponding group of storage elements of memory 104, the bitline defect information identifies each of the bitlines that have defects affecting the corresponding group of storage elements of memory 104. In other implementations, the maximum number of bitlines identified by the bitline defect information may be more than or fewer than twenty bitlines. The number of bitlines identified by the bitline defect information may be selected during the design of data storage device 102 based on a target size of dedicated portion 142 of memory 104, a target speed or performance of decoder 176, or a combination thereof.To illustrate, increasing a number of bitlines identified by the bitline defect information may increase a size of the dedicated portion 142 of the memory 104 used to store the bitline defect information or may reduce a speed of the decoder 176 during a decoding process based on the bitline defect information.

[0028] The bitline defect information (e.g., the first bitline defect information 134 and the second bitline defect information 135) may identify bitlines having multiple types of defects. As one example, the bitline defect information may identify bitlines having "closed defects" (e.g., short circuits). A closed defect occurs when a bitline is in contact with another bitline, causing any memory elements coupled to the second bitline to have a high probability of storing faulty data. As another example, the bitline defect information may identify bitlines having "open defects" (e.g., "breaks"). An open defect occurs when a "break" (e.g., an open circuit) is present in a wordline.Memory elements coupled to the bit line on one side of a break have a high probability of storing faulty data, but memory elements coupled to the bit line on the other side of the break do not have an increased probability of storing faulty data. The bit line defect information corresponding to a particular group of memory elements of memory 104 includes an identifier of a bit line having an open defect if the word lines of the particular group of memory elements and the memory elements coupled to the word lines are on one side of the break affected by the break. If a break occurs in a bit line, the bit line on one side of the break may be defective, but not on the other side of the break. Memory elements coupled to word lines on the side of the break that is affected (e.g.,Bit lines coupled to the other side of the break (i.e., the side that is defective) have a high probability of storing faulty data, and memory elements coupled to word lines on the other side of the break do not have an increased probability of storing faulty data. Because the bit line defect of data stored in memory elements of the specific group of memory elements of memory 104 decreases if bit lines have breaks that affect the specific group of memory elements, the bit line defect information corresponding to the specific group of memory elements indicates bit lines that have breaks that affect the specific group of memory elements, but not bit lines that have breaks that do not affect the specific group of memory elements.In other examples, the bitline defect information identifies bitlines having other types of defects affecting the corresponding group of memory elements of memory 104.

[0029] Memory 104 may include support circuitry, such as read / write circuitry 140, to support the operation of memory 104. Although illustrated as a single component, read / write circuitry 140 may be separated into separate components of memory 104, such as read circuitry and write circuitry. Read / write circuitry 140 may be configured to read or write a representation of data from one or more groups of storage elements of memory 104 based on requests from controller 120. For example, read / write circuitry 140 may be configured to sense read data stored in a particular group of storage elements in response to a request for the data from controller 120.To illustrate this, the control unit 120 may send a first request for read data 130 to the memory 104. The first request for read data 130 may specify an address corresponding to storage element(s) within the first group of storage elements 103 of the memory 104. In response to the first request for read data 130, the read / write circuitry 140 may sense first read data 132 stored in the first group of storage elements 103, and a representation of the first read data 132 may be provided to the control unit 120. The representation of the first read data 132 may be provided with the first bitline defect information 134, as further described herein.

[0030] Memory 104 may include selection module 144 configured to retrieve bitline defect information from dedicated portion 142 in response to an address included in a request received from control unit 120. In some implementations, selection module 144 may include or correspond to selection circuitry, such as digital logic circuitry, configured to perform the operations of selection module 144. In another implementation, selection module 144 may include or correspond to an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) device, or other dedicated hardware configured to perform the operation of selection module 144.In another implementation, the selection module 144 may include or correspond to processor-executable instructions executed by a processor or controller, as non-limiting examples, to perform the operations of the selection module 144.

[0031] The selection module 144 may retrieve bitline defect data based on an address in a request for data. To illustrate this, the memory 104 may receive from the control unit 120 a first request for data 130 indicating a first address that stores the read data being requested. The selection module 144 may be configured to retrieve the first bitline defect information 134 from the dedicated portion 142 of the memory 104 in response to the first address corresponding to the first group of storage elements 103. To further illustrate this, the control unit 120 may send a second request for data 131 to the memory 104, and the second request for data 131 may indicate a second address that stores the read data being requested.The selection module 144 may be configured to retrieve the second bitline defect information 135 from the dedicated section 142 based on the second address corresponding to the second group of storage elements 105. In this way, the selection module 144 is configured to retrieve different bitline defect information based on requests for data indicating addresses corresponding to different groups of storage elements of the memory 104. After the bitline defect information has been retrieved, the bitline defect information may be provided to the control unit 120.

[0032] In some implementations, the request for data may include a request for the bitline defect information. For example, the first request for data 130 may include a request for the first bitline defect information 134. In these implementations, the selection module 144 may retrieve the first bitline defect information 134 in response to the first request for data 130 including the request for the first bitline defect information 134. If the memory 104 receives an additional request for data that does not include a request for bitline defect information, the selection module 144 does not retrieve any bitline defect information based on the additional request for data.In these implementations, control unit 120 may determine whether or not to retrieve bitline defect information, as further described herein, and selection module 144 may retrieve the bitline defect information if requested by control unit 120. In other implementations, requests for data do not include requests for bitline defect information, and selection module 144 automatically retrieves the bitline defect information in response to each request for data based on an address specified by the request for data. In these implementations, bitline defect information is retrieved in response to each request for data and provided to control unit 120.

[0033] In some implementations, the selection module 144 may be configured to retrieve and provide the bitline defect information concurrently (e.g., in parallel) or substantially concurrently with the read / write circuitry 140 sensing and providing the representation of read data. For example, the read / write circuitry 140 may sense the first read data 132 and provide the representation of the first read data 132 to the control unit 120 during a first period of time, and the selection module 144 may retrieve the first bitline defect information 134 and provide it to the control unit 120 during a second period of time. At least a portion of the second period of time may overlap the first period of time.In a particular implementation, the first bitline defect information 134 is provided to the control unit 120 prior to completing the sensing of the first read data 132, so that the control unit 120 is enabled to perform one or more operations (e.g., a decompression operation) using the first bitline defect information 134 prior to receiving the representation of the first read data 132.

[0034] In addition to memory 104, data storage device 102 includes control unit 120. Control unit 120 may include a second memory 160, a soft bit generator 170, a decoder 176, and a compression module 178. In a particular implementation, second memory 160 is a volatile memory. Control unit 120 may be configured to store bitline defect information in second memory 160. For example, control unit 120 may store first bitline defect information 134 in second memory 160.

[0035] In some implementations, the second memory 160 may act as a cache for bitline defect information. In these implementations, the control unit 120 may be configured to store bitline defect information in the second memory 160 (e.g., the volatile memory) after receiving the bitline defect information. For example, the control unit 120 may store the first bitline defect information 134 in the second memory 160 in response to receiving the first bitline defect information 134 from the memory 104.

[0036] In a particular implementation, the control unit 120 may be configured to suppress the storage of additional bitline defect information in the second memory 160 if an address of a request for additional read data corresponds to storage element(s) within the most recently accessed group of storage elements. For example, after storing the first bitline defect information 134 in the second memory 160, the control unit 120 may determine whether the address indicated by the second request for data 131 corresponds to storage element(s) within the first group of storage elements 103 (e.g., the most recently accessed group of storage elements). Based on a determination that the address indicated by the second request for data 131 does not correspond to storage element(s) within the first group of storage elements 103 (e.g.,the address corresponds to a different group of memory elements), the control unit 120 includes a request for bit line defect information in the second request for data 131. In response to including the request for bit line defect information in the second request for data 131, the control unit 120 receives the second bit line defect information 135 and stores the second bit line defect information 135 in the second memory 160.

[0037] As another example, after storing the first bitline defect information 134 in the second memory 160, the control unit 120 may send a request for additional data (not shown) to the memory 104 and may receive additional bitline defect information (not shown). The control unit 120 may determine that an address indicated by the additional request for data corresponds to storage element(s) within the first group of storage elements 103 (e.g., the most recently accessed group of storage elements). Based on a determination that the address indicated by the additional request for data corresponds to storage element(s) from the first group of storage elements 103, the control unit 120 suppresses storing the additional bitline defect information in the second memory 160. Because the additional request for data corresponds to the same group of storage elements (e.g.,If the address specified by the additional request for data corresponds to the same address (e.g., the first group of storage elements 103) as the first request for data 130, the additional bitline defect information is the same as the first bitline defect information 134 already stored in the second memory 160. Instead of storing a copy of the first bitline defect information 134 in the second memory 160, the control unit 120 accesses the first bitline defect information 134 from the second memory 160 for use in data decoding. In an alternative implementation, if the address specified by the additional request for data corresponds to storage element(s) from the first group of storage elements 103, the control unit 120 does not include a request for bitline defect information in the additional request for data (e.g., suppresses its inclusion).In this implementation, the additional bit line defect information is not received in the control unit 120 based on the additional request for data not including a request for bit line defect information.

[0038] In some implementations, the control unit 120 may include a request for bitline defect information in each request for data, or the control unit 120 may receive bitline defect information in each response to a request for data. To illustrate, after storing the first bitline defect information 134 in the second memory 160, the control unit 120 may send the second request for data 131 to the memory 104. In response to the second request for data 131, the control unit 120 receives the second bitline defect information 135. The control unit 120 may be configured to determine whether the address indicated by the second request for data 131 corresponds to storage element(s) within the first group of storage elements 103 (e.g., the most recently accessed group of storage elements of the memory 104).In response to the control unit 120 determining that the address specified by the second request for data 131 does not correspond to storage element(s) within the first group of storage elements 103, the control unit 120 stores the second bitline defect information 135 in the second memory 160. In a particular implementation, the second memory 160 is configured to overwrite bitline defect information stored in the second memory 160 each time bitline defect information is stored, and the control unit 120 overwrites the first bitline defect information 134 with the second bitline defect information 135. Alternatively, the control unit 120 may store the second bitline defect information 135 in addition to the first bitline defect information 134.In a particular implementation, if the second memory 160 becomes full, bit line defect information may be overwritten using a least recently used (LRU) scheme, as a non-limiting example.

[0039] Soft bit generator 170 may be configured to generate sets of soft bits based on bitline defect information. A set of soft bits may indicate the probability that a set of bits is correct (or erroneous). For example, a set of soft bits associated with a representation of read data may indicate probabilities that bits of the representation of read data are correct. In some implementations, the set of soft bits may be generated based on bitline defect information. In other implementations, the set of soft bits may be generated based on bitline defect information and sensed data from memory 104.For example, in addition to sensing the first read data 132 from the first group of storage elements 103, the memory 104 may also sense whether charges stored in the storage elements are within an overlap between thresholds corresponding to different data values. Storage elements storing these charges may have a high probability of being faulty. Sets of soft bits may be generated based on the sensed data to indicate a probability that bits in the representation of the first read data 132 are correct (or in error).

[0040] The sets of soft bits may further be generated based on bitline defect data. The soft bit generator 170 may be configured to generate a set of soft bits associated with a representation of read data based on bitline defect information corresponding to the representation of the read data. For example, the soft bit generator 170 may generate a first set of soft bits 172 associated with the representation of the first read data 132 based on sensed information and based on the first bitline defect information 134. As another example, the soft bit generator 170 may generate a second set of soft bits 174 associated with the representation of the second read data 133 based on sensed information and based on the second bitline defect information 135.As described above, the first bit line defect information 134 indicates bit lines that have defects affecting memory elements from the first group of memory elements 103. Thus, soft bits associated with particular bits of the representation of the first read data 132 (e.g., bits stored in memory elements coupled to the bit lines that have the defects) may indicate that these particular bits have a high probability of being defective. The sets of soft bits may be used by the decoder 176 to decode the representations of the read data received from the memory 104. For example, the first set of soft bits 172 may be used to decode the representation of the first read data 132, and the second set of soft bits 174 may be used to decode the representation of the second read data 133.

[0041] Decoder 176 may be configured to decode representations of data received from memory 104. Decoder 176 may be part of, or included within, an error correction code (ECC) engine. The ECC engine may be configured to receive data and generate one or more error correction code (ECC) codewords (e.g., including a data portion and a parity portion) based on the data. For example, the ECC engine may receive write data (e.g., based on a write command from access device 150) and generate a codeword. To illustrate, the ECC engine may include an encoder configured to encode the data using an ECC encoding technique.The ECC engine may include a Reed-Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a Low-Density Parity Check (LDPC) encoder, a Turbo encoder, an encoder configured to encode the data according to one or more ECC techniques, or a combination thereof, as illustrative non-limiting examples.

[0042] The ECC engine may include a decoder (e.g., decoder 176) configured to decode a representation of data read from memory 104 to detect and correct bit errors that may be present in the representation of the data. For example, decoder 176 may correct a number of bit errors up to an error correction capability of an ECC technique used by decoder 176. To decode the representation of data, decoder 176 may use one or more sets of soft bits from soft bit generator 170. For example, decoder 176 may generate first decoded data 138 based on the representation of first read data 132 and the first set of soft bits 172. As another example, the decoder 176 may generate second decoded data 139 based on the representation of the second read data 133 and the second set of soft bits 174.

[0043] In some implementations, the bitline defect information is compressed before being stored in the dedicated portion 142 of the memory 104. In implementations where the control unit 120 generates and sends the bitline defect information (e.g., the first bitline defect information 134 and the second bitline defect information 135) to the memory 104, the compression module 178 is configured to perform a data compression operation on the first bitline defect information 134 and the second bitline defect information 135 before storing the first bitline defect information 134 and the second bitline defect information 135 in the second memory 160. In a particular implementation, the data compression operation may be a "start-flow" compression operation. In other implementations, the data compression operation may be a different compression operation.The compression module 178 is configured to perform a data decompression operation on the first bitline defect information 134 and the second bitline defect information 135 before generating the first set of soft bits 172 and the second set of soft bits 174. In a particular implementation, the data decompression operation may be a start-run decompression operation. In other implementations, the data decompression operation may be a different decompression operation.

[0044] During operation, the data storage device 102 may receive commands from the access device 150. For example, the data storage device 102 may receive a first data request 152 from the access device 150. The first data request 152 may include an address associated with storage element(s) within the first group of storage elements 103 of the memory 104. For example, the first data request 152 may include a logical address, a physical address, a virtual address, or other identifier of one or more storage elements in the first group of storage elements 103 of the memory 104. The control unit 120 may generate the first request for data 130 based on the first data request 152 and may send the first request for data 130 to the memory 104.In response to receiving the first request for data 130, the read / write circuitry 140 may begin a sensing operation to read the first read data 132 from the first group of memory elements 103. Additionally, the selection module 144 may retrieve the first bitline defect information 134 from the dedicated portion 142 based on an address in the first request for data 130 that indicates a location in the first group of memory elements 103. In some implementations, the read / write circuitry 140 and the selection module 144 may operate concurrently (e.g., in parallel) or substantially concurrently. The control unit 120 may receive the first bitline defect information 134 and a representation of the first read data 132 in response to transmitting the first request for data 130.

[0045] The first bitline defect information 134 may be stored in the second memory 160 if the first group of storage elements 103 (e.g., a group of storage elements of the memory 104 corresponding to the first bitline defect information 134) is different from a previously accessed group of storage elements of the memory 104. If the first group of storage elements 103 is not different from the previously accessed group of storage elements, the first bitline defect information 134 is not saved in the second memory 160.

[0046] Additionally, the first bitline defect information 134 may be provided to the soft bit generator 170. In some implementations, the compression module 178 may receive the first bitline defect information and may decompress the first bitline defect information 134 before providing the decompressed first bitline defect information 134 to the soft bit generator 170. Any delay associated with the compression module 178 does not exceed the delay associated with the read / write circuitry 140 that provides the representation of the first read data 132 (and the additional sensed information) to the control unit 120, and thus does not introduce any additional delay to the decoding process.In response to receiving the first bitline defect information 134, the soft bit generator 170 may generate the first set of soft bits 172 based on the first bitline defect information 134 (and based on sensed data from the first group of memory elements 103, as described above). The first set of soft bits 172 may indicate probabilities that bits of the representation of the first read data 132 are correct (or erroneous).

[0047] The representation of the first read data 132 and the first set of soft bits 172 may be provided to the decoder 176, and the decoder 176 may generate the first decoded data 138 based on the representation of the first read data 132 and the first set of soft bits 172. For example, the decoder 176 may perform a decoding operation and one or more error correction operations on the representation of the first data 132 based on the first set of soft bits 172. In a particular implementation, the decoder 176 is an LPC decoder. In this implementation, because the first set of soft bits is more accurate (e.g.,If at least some bits are not erroneously identified as having a high probability of being erroneous, decoder 176 may converge more quickly than if decoder 176 decodes the representation of first read data 132 using soft bits based on bitline defect information for the entire memory 104. The first decoded data 138 may be provided by controller 120 to access device 150 in response to first data request 152.

[0048] The control unit 120 may also receive a second data request 154 from the access device 150. In response to the second data request 154, the control unit 120 may send the second request for data 131 to the memory 104. The read / write circuitry 140 may sense the second read data 133 in the second group of memory elements 105 and may provide a representation of the second read data 133 to the control unit 120. The selection module 144 may retrieve the second bitline defect information 135 and may provide the second bitline defect information 135 to the control unit 120. The control unit 120 may receive the second bitline defect information 135 and the representation of the second read data 133 in response to the second request for data 131.Because the second bit line defect information 135 corresponds to a different group of memory elements of the memory 104, the second bit line defect information 135 may be different from the first bit line defect information 134.

[0049] The soft bit generator 170 may generate the second set of soft bits 174 based on the second bitline defect information 135 and sensed information associated with the representation of the second read data 133. The decoder 176 may also generate the second decoded data 139 based on the second set of soft bits 174 and the representation of the second read data 133. Because the second set of soft bits 174 is more accurate (e.g., at least some bits are not erroneously identified as having a high probability of being erroneous), the decoder 176 may converge faster than if the decoder 176 decodes the representation of the second read data 133 using soft bits based on bitline defect information for the entire memory 104.The control unit 120 may provide the second decoded data 139 to the access device 150 based on the second data request 154.

[0050] Although one or more components of data storage device 102 have been described with reference to controller 120, in other implementations, specific components may be included in memory 104. For example, one or more of second memory 160, soft bit generator 170, decoder 176, and / or compression module 178 may be included in memory 104. Alternatively or additionally, some or more functions as described above with reference to controller 120 may be performed in or by memory 104. For example, one or more functions of second memory 160, soft bit generator 170, decoder 176, and / or compression module 178 may be performed by components and / or circuitry included in memory 104.Alternatively or additionally, one or more components of the data storage device 102 may be included in the access device 150. For example, one or more of the second memory 160, the soft bit generator 170, the decoder 176, and / or the compression module 178 may be included in the access device 150. Alternatively or additionally, some or more functions as described above with respect to the control unit 120 may be performed in or by the access device 150. As an illustrative, non-limiting example, the access device 150 may be configured to decode a representation of read data from the memory 104 based on bitline defect information (e.g., based on soft bits generated based on the bitline defect information).In some implementations, the components of the controller 120, the memory 104, and / or the access device 150 may include or correspond to dedicated circuitry, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) device, or other dedicated hardware configured to perform the operation of the corresponding component. In another implementation, the components may include or correspond to instructions executable by a processor or controller, as non-limiting examples, to perform the operations of the corresponding component.

[0051] Because the bitline defect information for each group of memory elements of memory 104 identifies bitlines having defects affecting the group of memory elements, the bitline defect information (e.g., the first bitline defect information 134, the second bitline defect information 135, etc.) for the group of memory elements may be more accurate than bitline defect information for the entire memory 104. Because the bitline defect information is more accurate, the number of bits indicated as being defective by soft bits generated based on the bitline defect information may be smaller than for soft bits generated based on the bitline defect information for the entire memory 104.By providing more accurate soft bits to decoder 176, the efficiency of decoder 176 is increased, thereby increasing the speed of the decoder and reducing its power consumption. Additionally, as data storage device 102 reaches the end of its useful life, memory elements begin to fail. The failure of memory elements can cause the number of errors in data read from memory 104 to increase, and other decoders may be unable to decode data that has an increased number of errors. However, because decoder 176 receives soft bits that do not erroneously identify at least some bits as having a high probability of being erroneous, decoder 176 is able to use the bits to decode the data with the increased number of errors, thereby extending the useful life of data storage device 102.

[0052] Referring to Fig. 2 illustrates a diagram 200 of several blocks of memory 104 of Fig. 1 and a plurality of bit lines having open defects. Diagram 200 illustrates an example of memory 104 including a plurality of blocks and is not limiting. A first block of the plurality of memory blocks may correspond to a first group of memory elements 103, and a second block of the plurality of memory blocks may correspond to the second group of memory elements 105. In other implementations, memory 104 may include more or fewer than the Fig. 2, and / or the memory 104 may contain other blocks (with other word lines and bit lines) than in Fig. 2 shown.

[0053] The memory 104 may include multiple blocks, such as a first block 202, an Nth block 204, an (N+1)th block 206, and a 2Nth block 208. The multiple blocks may include 2N blocks. In a particular implementation, 2N is one thousand. In other implementations, the number of blocks may be more or less than one thousand. Each block may include multiple transistors, and each transistor may be coupled to a word line of multiple word lines and a bit line of multiple bit lines. Each transistor may be a storage element of the memory 104 of Fig. 1 and may be configured to store an electrical charge representing a data value.

[0054] The plurality of bitlines may include a first bitline 210 (BL0), a second bitline 212 (BL1), a third bitline 214 (BL2), a fourth bitline 216 (BL3), a fifth bitline 218 (BL4), a sixth bitline 220 (BL5), and an M-th bitline 222 (BLM). In a particular implementation, the plurality of wordlines may include 218 wordlines. Fig. 2 contains an enlarged view 250 of the N-th block 204. The N-th block contains 128 word lines, M bit lines, and 128 * M transistors. Each transistor is coupled to a bit line and a word line, as shown in Fig. 2. Additionally, the bit lines may be coupled to a sense amplifier (SA) for use in reading data from the Nth block 204. Blocks 202 and 206-208 may have the same configuration as the Nth block 204.

[0055] One or more of the multiple bit lines of memory 104 may have a defect. In the illustrative example shown in Fig. 2, the first bit line 210, the second bit line 212, the fourth bit line 216, the fifth bit line 218, and the M-th bit line 222 may have open defects. To illustrate this, the first bit line 210 may have a break 230, the second bit line 212 may have a break 232, the fourth bit line 216 may have a break 234, the fifth bit line 218 may have a break 236, and the M-th bit line 222 may have a break 238. As described with reference to Fig. 1, memory elements coupled to word lines on one side of the break may have a high probability of storing faulty data, and memory elements coupled to word lines on the other side of the break may not have an increased probability of storing faulty data. Because breaks can occur at different locations in bit lines, a break that affects one memory block may not affect another memory block. As an example, the break 238 may be located on the Mth bit line 222 in the 2Nth block 208. Memory blocks above the 2Nth block 208 (e.g., the first block 202 - the Nth block 204) and the 2Nth block 208 may be affected by the break 238. Memory blocks below the fraction 238 (e.g., the (N+1)th block 206 to the (2N-1)th block) may not be affected by the fraction 238.Because the break 238 affects the first block 202 and not the (N+1)th block 206, bit line defect information corresponding to the first block 202 identifies the M-th bit line 222 as having a defect affecting the first block 202, and the bit line defect information corresponding to the (N+1)th block 206 does not identify the M-th bit line as having a defect affecting the (N+1)th block 206.

[0056] As with reference to Fig. 1, bitline defect information may be stored for each block of memory 104. For example, the first bitline defect information 134 may correspond to the first group of memory elements 103 (e.g., the first block 202), and the second bitline defect information 135 may correspond to the second group of memory elements 105 (e.g., a second block). Reliability information for the other blocks (e.g., blocks 3-2N) may also be stored in the dedicated section 142 of memory 104. The bitline defect information may include one or more identifiers of bitlines having defects affecting a block of memory 104 associated with the bitline defect information. For example, the first bitline defect information 134 may include a table containing one or more identifiers of the bitlines 210-222 that comprise the first block 202 (e.g.,the first group of memory elements 103 of . Fig. 1). Because the bitline defect information for blocks 202-208 identifies bitlines having defects that affect that corresponding block (and not bitlines having defects that do not affect the corresponding block), the bitline defect information associated with blocks 202-208 may be different from bitline defect information for the entire memory 104. For example, the bitline defect information for the entire memory 104 may include identifiers of the first bitline 210, the second bitline 212, the fourth bitline 216, the fifth bitline 218, and the M-th bitline 222 (and not the third bitline 214 and the fourth bitline 220), and the bitline defect information corresponding to one or more of blocks 202-208 may be different.

[0057] To illustrate this, bitline defect information corresponding to the first block 202 identifies the fifth bitline 218 and the M-th bitline 222 (as having defects affecting the first block 202), and not the bitlines 210-216 and 220. As another example, bitline defect information corresponding to the N-th block 204 identifies the fifth bitline 218 (as having a defect affecting the N-th block 204) and not the bitlines 210-216, 220, and 222. As another example, bitline defect information corresponding to the (N+1)-th block 206 identifies the first bitline 210, the second bitline 212, the fourth bitline 216, the fifth bitline 218, and the M-th bitline 222 (as having defects affecting the (N+1)-th block) and not the bit lines 214 and 220.As another example, the bitline defect information corresponding to the 2Nth block 208 identifies the fourth bitline 216, the fifth bitline 218, and the Mth bitline 222 (as having defects affecting the 2Nth block 208), rather than bitlines 210-214 and 220. In this way, the bitline defect information for each of the blocks of memory 104 identifies bitlines having defects affecting the corresponding block (e.g., a subset of the bitlines having defects), rather than each bitline having a defect (e.g., bitlines 210, 212, 216, 218, and 222). Providing the bitline defect information to the soft bit generator 170 of FIG. Fig. 1 enables the soft bit generator 170 to generate more accurate sets of soft bits, increasing the speed of the decoder 176 and reducing its power consumption while decoding data from the multiple blocks 202-208.

[0058] Referring to Fig. 3, a specific illustrative example of a method is depicted and generally designated 300. The method 300 may be performed in the data storage device 102, such as by the controller 120, the access device 150, or a combination thereof, as illustrative, non-limiting examples.

[0059] The method 300 may include receiving first bitline defect information from a memory at 302. The first bitline defect information may identify bitlines having defects affecting a first group of memory elements from among multiple memory elements of the memory. For example, the selection module 144 retrieves the first bitline defect information 134 indicating bitlines having defects affecting the first group of memory elements 103, such as closed defects and open defects affecting the first group of memory elements 103, but not open defects that do not affect the first group of memory elements 103. The control unit 120 receives the first bitline defect information 124 from the memory 104.

[0060] The method 300 may include generating a first set of soft bits based on the first bitline defect information at 304. For example, the soft bit generator 170 may generate the first set of soft bits 172 based on the first bitline defect information 134 and sensed information associated with the first read data 132, as described with reference to Fig. 1. The first set of soft bits 172 may be provided to the decoder 176.

[0061] The method may include, at 306, generating first decoded data based on the first read data and the first bitline defect information. For example, the decoder 176 of the control unit 120 generates the first decoded data 120 based on the representation of the first read data 132 and based on the first set of soft bits 172.

[0062] The method 300 may include receiving second bitline defect information from the memory at 308. The second bitline defect information may identify bitlines having defects affecting a second group of memory elements from the plurality of memory elements. For example, the selection module 144 retrieves the second bitline defect information 135 indicating bitlines having defects affecting the second group of memory elements 105, such as closed defects and open defects affecting the second group of memory elements 105, but not open defects that do not affect the second group of memory elements 105. The control unit 120 receives the second bitline defect information 135 from the memory 104.Because at least one defect affecting the first group of memory elements 103 may not affect the second group of memory elements 105, the first bit line defect information 134 and the second bit line defect information 135 may be different.

[0063] The method 300 may include generating a second set of soft bits based on the second bitline defect information at 310. For example, the soft bit generator 170 may generate the second set of soft bits 174 based on the second bitline defect information 135 and sensed information associated with the second read data 133, as described with reference to Fig. 1. The second set of soft bits 174 may be provided to the decoder 176.

[0064] The method 300 may include generating second decoded data based on the second read data and the second set of soft bits at 312. For example, the decoder 176 of the control unit 120 generates the second decoded data 139 based on the representation of the second read data 133 and based on the second set of soft bits 174.

[0065] In a particular implementation, the method 300 includes storing the first bitline defect information in a volatile memory of the control unit if an address associated with the first group of memory elements is different from an address associated with a group of previously accessed memory elements. For example, if a first address included in the first request for data 130 corresponds to memory element(s) within the first group of memory elements 103, the control unit may store the first bitline defect information 134 in the second memory 160. Additionally, the method 300 may include suppressing the storage of the additional bitline defect information in the volatile memory if a third group of memory elements associated with the additional bitline defect information is within the first group of memory elements.To illustrate this, control unit 120 may receive additional bitline defect information in response to a third request for data corresponding to a third group of memory elements. If the third group of memory elements is within the first group of memory elements 103, control unit 120 suppresses storing the additional bitline defect information in the second memory 160.

[0066] In a particular implementation, method 300 includes sending a request to retrieve first read data from the memory. The request to retrieve the first read data may include an address corresponding to the first group of memory elements. The request to retrieve the first read data may also include a request for bitline defect information associated with the address. For example, controller 120 sends the first request for data 130 to memory 104. The first request for data 130 may include a first address corresponding to memory element(s) within the first group of memory elements 103 of memory 104. The first request for data 130 may also include a request for bitline defect information associated with the first address.In this implementation, method 300 further includes, in response to sending the request to retrieve the first read data, receiving a representation of the first read data and the first bitline defect information from the memory. For example, in response to sending the first request for data 130, control unit 120 may receive the representation of the first read data 132 and the first bitline defect information 134.

[0067] Additionally, method 300 may include receiving a data request from a host device. The data request may include a second address. Method 300 may further include determining whether the second address corresponds to the first group of storage elements, and in response to determining that the second address corresponds to the first group of storage elements, sending a request to retrieve data stored at the second address to the memory. The request to retrieve the data stored at the second address may not include a request for bitline defect information. To illustrate, control unit 120 may receive a data request from access device 150 and may determine whether an address included in the data request corresponds to the first group of storage elements 103.In response to determining that the address corresponds to the first group of storage elements 103, the control unit 120 may send a third request for third read data to the memory 104. Because the first bit line defect information 134 (e.g., bit line defect information corresponding to the address specified by the data request) is already stored in the second memory 160, the control unit 120 may not include a request for bit line defect information in the third request.

[0068] In a particular implementation, method 300 may further include decompressing the first bitline defect information before generating the first set of soft bits. For example, compression module 178 may decompress first bitline defect information 134 before providing first bitline defect information 134 to decoder 176.

[0069] By using the bitline defect information for a specific group of memory elements of memory 104, which identifies bitlines having defects affecting the specific group of memory elements, in a decoding process, method 300 increases the speed and reduces the power consumption of the decoding process (e.g., generating the decoded bits) compared to using bitline defect information for the entire memory.

[0070] Referring to Fig. 4, a specific illustrative example of a method is depicted and generally designated 400. The method 400 may be executed in the data storage device 102, such as by a component in the memory 104. As an illustrative non-limiting example, the method 400 may be executed by the selection module 144 of Fig. 1 can be executed.

[0071] The method 400 may include, at 402, receiving a request for first data from a control unit. The request for the first data may include a first address of storage element(s) storing the first data. For example, the memory 104 may receive the first request for data 130 from the control unit 120. The first request for data 130 may include a first address of storage element(s) storing the first read data 132, and the storage element(s) may be within the first group of storage elements 103 of the memory 104. The method 400 may include, at 404, retrieving first bitline defect information from a dedicated portion of a memory in response to the first address corresponding to a first group of storage elements. The first bitline defect information may identify bitlines having defects related to the first group of storage elements.For example, the selection module 144 may retrieve the first bitline defect information 134 from the dedicated portion 142 of the memory 104 in response to the first address corresponding to one or more memory elements within the first group of memory elements 103. The first bitline defect information 134 identifies bitlines having defects that affect the first group of memory elements 103 and not bitlines having defects that do not affect the first group of memory elements 103. In one particular implementation, the dedicated portion 142 of the memory may include one or more read-only memory (ROM) fuses. In another particular implementation, the dedicated portion of the memory may include one or more single-level cell (SLC) memory elements.

[0072] The method 400 may include, at 406, receiving a request for second data from the control unit. The request for the second data may include a second address of storage element(s) storing the second data. For example, the memory 104 may receive the second request for data 131 from the control unit 120. The second request for data 131 may include a second address of storage element(s) storing the second read data 133, and the storage element(s) may be within the second group of storage elements 105 of the memory 104. The method 400 may include, at 408, retrieving second bitline defect information from the dedicated section in response to the second address corresponding to a second group of storage elements. The second bitline defect information may identify bitlines having defects related to the second group of storage elements.For example, the selection module 144 may retrieve the second bitline defect information 135 from the dedicated portion 142 of the memory 104 in response to the second address corresponding to the second group of storage elements 105 of the memory 104. The second bitline defect information 135 identifies bitlines having defects related to the second group of storage elements 105 and not bitlines having defects not related to the second group of storage elements 105.

[0073] Method 400 enables a data storage device to provide bitline defect information corresponding to different groups of storage elements of a memory of the data storage device. The bitline defect information for a specific group of storage elements identifies bitlines having defects that affect the specific group of storage elements, rather than bitlines having defects that do not affect the specific group of storage elements. The more accurate bitline defect information enables a decoder receiving the bitline defect information to operate at increased speed and with reduced power consumption when decoding data based on the bitline defect information.

[0074] The procedure 300 of Fig. 3 and / or the method 400 of Fig. 4 may be initiated or controlled by an application-specific integrated circuit (ASIC), a processing unit such as a central processing unit (CPU), a control unit, another hardware device, a firmware device, a field-programmable gate array (FPGA) device, or any combination thereof. As an example, the method 300 of Fig. 3 and / or the method 400 of Fig. 4 by one or more processors, such as one or more processors included in or coupled to a control unit, or a memory of the storage device 102 and / or the access device 150 of Fig. 1. As an example, one or more of the procedures of Fig. 3 and Fig. 4 individually or in combination by the control unit 120 of Fig. 1. To illustrate this, a section of one of the procedures of the Fig. 3 and Fig. 4 with a second stage of one of the procedures of Fig. 3 and Fig. 4. In addition, one or more operations related to the Fig. 3 and Fig. 4 may be optional, may be performed at least partially concurrently, and / or may be performed in a different order than shown or described.

[0075] In one illustrative example, a processor may be programmed to decode a representation of read data using bitline defect information that identifies bitlines having defects affecting a group of storage elements of a memory that store the read data. For example, the processor may execute instructions to receive first bitline defect information from a memory. The first bitline defect information may identify bitlines having defects affecting a first group of storage elements from among multiple storage elements of the memory. The processor may execute instructions to generate a first set of soft bits based on the first bitline defect information. The processor may further execute instructions to generate first decoded data based on the first set of soft bits and a representation of first read data.The first read data may be stored in the first group of memory elements.

[0076] Although various components of the data storage device 102 and / or the access device 150 of Fig. 1 are depicted here as block components and described in general terms, such components may include one or more microprocessors, state machines, or other circuits configured to enable the various components to perform operations described herein. One or more aspects of the various components may be implemented using a microprocessor or microcontroller programmed to perform operations described herein, such as one or more operations of the method 300 of Fig. 3 and / or the procedure of Fig. 4. In a particular implementation, each of the control unit 120, the memory 104, the second memory 160 and / or the access device 150 of Fig. 1 a processor that executes instructions stored in a memory, such as a non-volatile memory of the data storage device 102 or the access device 150 of Fig. 1. Alternatively or additionally, executable instructions executed by the processor may be stored in a separate memory location that is not part of the non-volatile memory, such as a read-only memory (ROM) of the data storage device 102 or the access device 150 of Fig. 1.

[0077] With reference to Fig. 1, the data storage device 102 may be attached to or embedded within one or more access devices, such as within a housing of a communications device (e.g., the access device 150). For example, the data storage device 102 may be integrated into a device such as a mobile phone, a computer (e.g., a laptop, a tablet, or a notebook computer), a music player, a video player, a gaming device or console, an electronic reading device, a personal digital assistant (PDA), a portable navigation device, or other device that uses non-volatile memory. However, in other embodiments, the data storage device 102 may be implemented in a portable device configured to be selectively coupled to one or more external access devices.In still other embodiments, the data storage device 102 may be a component (e.g., a solid-state drive (SSD)) of a network-accessible data storage system, such as an enterprise data system, a network-attached storage system, a cloud data storage system, etc.

[0078] To further illustrate this, the data storage device 102 may be configured to be coupled to the access device 150 as embedded storage, such as in connection with an embedded MultiMedia Card (eMMC®) (trademark of the JEDEC Solid State Technology Association, Arlington, Virginia) configuration as one illustrative example. The data storage device 102 may correspond to an eMMC device. As another example, the data storage device 102 may correspond to a memory card, such as a microSD card. B. a “Secure Digital” card (SD® card), a microSD® card, a miniSD™ card (trademark of SD-3C LLC, Wilmington, Delaware), a MultiMediaCard™ card (MMC™ card) (trademark of JEDEC Solid State Technology Association, Arlington, Virginia) or a CompactFlash® card (CF card) (trademark of SanDisk Corporation, Milpitas, California).The data storage device 102 may operate in accordance with a JEDEC industry specification. For example, the data storage device 102 may operate in accordance with a JEDEC eMMC specification, a JEDEC Universal Flash Memory (UFS) specification, one or more other specifications, or a combination thereof. In yet another particular implementation, the data storage device 102 is indirectly coupled to the access device 150, e.g., via a network. For example, the data storage device 102 may be a network-attached storage (NAS) device or a component (e.g., a solid-state drive (SSD) device) of a data center storage system, an enterprise storage system, or a storage area network.

[0079] The memory 104 and / or the second memory 160 of Fig. 1 may include resistive random access memory (ReRAM), three-dimensional (3D) memory, flash memory (e.g., NAND memory, NOR memory, single-level cell (SCL) flash memory, multi-level cell (MLC) flash memory, split-bit-line NOR (DINOR) memory, AND memory, high capacitive coupling ratio (HiCR) device, asymmetric contactless transistor (ACT) device, or another flash memory), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), read-only memory (ROM), one-time programmable memory (OTP), or a combination thereof. Alternatively or additionally, memory 104 and / or second memory 160 may include another type of memory. The memory 104 and / or the second memory 160 of Fig.1 may include a semiconductor memory device.

[0080] Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM"), non-volatile memory devices such as magnetoresistive random access memory ("MRAM"), resistive random access memory ("ReRAM"), electrically erasable programmable random access memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in a NAND or NOR configuration.

[0081] The memory devices may be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching memory element such as an anti-fuse, phase-change material, etc., and optionally a steering element such as a diode, etc. Further, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements including a charge storage region such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0082] Multiple storage elements may be configured to be connected in series or so that each element is individually accessible. As a non-limiting example, flash memory devices in a NAND (NAND memory) configuration typically include storage elements connected in series. A NAND memory array may be configured so that the array is composed of multiple chains of memory, where a chain is composed of multiple storage elements that share a single bit line and are accessed as a group. Alternatively, storage elements may be configured so that each element is individually accessible, such as a NOR memory array. NAND and NOR memory configurations are exemplary, and storage elements may be configured in other ways.

[0083] The semiconductor memory elements located within and / or above a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure. In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., in a plane in the xz direction) that extends substantially parallel to a major surface of a substrate supporting the memory elements. The substrate may be a wafer over or in which the layer of memory elements is formed, or it may be a carrier substrate that is attached to the memory elements after they have been formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

[0084] The memory elements can be arranged in an ordered array, such as multiple rows and / or columns, within the individual memory device levels. However, the memory elements can be arranged in non-regular or non-orthogonal configurations. The memory elements can each have two or more electrodes or contact lines, such as bit lines and word lines.

[0085] A three-dimensional memory array is arranged such that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the main surface of the substrate). As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device planes. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y direction), each column having multiple memory elements in each column. The columns may be arranged in a two-dimensional configuration, e.g.,The memory elements can be arranged in an xz plane, resulting in a three-dimensional array of memory elements with elements on multiple vertically stacked memory levels. Other configurations of memory elements in three dimensions can also form a three-dimensional memory array.

[0086] As a non-limiting example, in a three-dimensional NAND memory array, the storage elements may be coupled together to form a NAND chain within individual horizontal (e.g., xy) memory device planes. Alternatively, the storage elements may be coupled together to form a vertical NAND chain spanning multiple horizontal memory device planes. Other three-dimensional configurations are conceivable, with some NAND chains including storage elements in a single memory plane, while other chains include storage elements spanning multiple memory planes. Three-dimensional memory arrays may also be constructed in a NOR configuration and in a ReRAM configuration.

[0087] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may further comprise one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor material such as silicon. In a monolithic three-dimensional array, the layers forming each memory device level of the array are typically formed on top of the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or may have intermediate layers between memory device levels.

[0088] Alternatively, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates can be thinned or removed from the memory device levels before stacking, but because the memory device levels are initially formed over separate substrates, the resulting memory arrays are non-monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked-chip memory device.

[0089] Associated circuitry is typically used to operate the memory elements and to communicate with the memory elements. As non-limiting examples, memory devices may include circuitry used to control and drive memory elements to achieve functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0090] One skilled in the art will recognize that this disclosure is not limited to the described two-dimensional and three-dimensional illustrative structures, but rather covers all relevant memory structures within the scope of the disclosure as described herein and as understood by one skilled in the art. The explanations of the embodiments described herein are intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments. Those skilled in the art will recognize that such modifications are within the scope of the present disclosure.

[0091] The above-disclosed subject matter is to be considered as illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, improvements, and other embodiments that fall within the scope of the present disclosure. Thus, to the maximum extent permitted by law, the scope of the present disclosure is to be determined by the broadest possible interpretation of the following claims and their equivalents, and is not to be restricted or limited by the foregoing detailed description.

Claims

[1] A data storage device (102) comprising: a memory (104) containing a plurality of memory elements; and a control unit (120) coupled to the memory, the control unit being configured: receive first bit line defect information (134) from the memory, the first bit line defect information identifying bit lines affecting a first group of memory elements (103) of the plurality of memory elements; receive second bit line defect information (135) from the memory, the second bit line defect information identifying bit lines affecting a second group of memory elements (105) of the plurality of memory elements; generate a first group of soft bits (172) based on the first bit line defect information, wherein the first group of soft bits indicates a probability that a first group of bits corresponding to the first group of memory elements (103) is correct, and generate a second group of soft bits (174) based on the second bit line defect information, the second group of soft bits indicating a probability that a second group of bits corresponding to the second group of memory elements (105) is correct. [2] The data storage device of claim 1, wherein the control unit (120) is configured to send a request for first read data (132) to the memory (104) and receive a representation of the first read data and the first bit line defect information (134) in response to sending the request for the first read data. [3] The data storage device of claim 2, wherein the control unit (120) is configured to send a request for second read data (133) to the memory (104) and receive a representation of the second read data and the second bit line defect information (135) in response to sending the request for the second read data. [4] The data storage device of claim 1, wherein the control unit (120) includes a decoder (176) configured to generate first decoded data (138) based on a representation of the first read data and the first set of soft bits (172). [5] The data storage device of claim 1, wherein the control unit (120) includes a compression module (178) configured to perform a data decompression operation on the first bit line defect information (134), the second bit line defect information (135), or a combination thereof. [6] Procedure which includes: in a data storage device (102) including a memory (104) and a controller (120) coupled to the memory, the memory including a plurality of storage elements configured to store data, performing: Receiving (302) first bit line defect information (134) from the memory (104), wherein the first bit line defect information identifies bit lines having defects that affect a first group of memory elements (103) of the plurality of memory elements; and Generating (304) a first set of soft bits (172) based on the first bit line defect information (134), wherein the first set of soft bits (172) indicates a probability that a first group of bits corresponding to the first group of memory elements (103) is correct. [7] The method of claim 6, further comprising storing the first bit line defect information (134) in a volatile memory (160) of the control unit (120) if an address associated with the first group of memory elements (103) is different from an address associated with a group of previously accessed memory elements. [8] The method of claim 7, further comprising suppressing the storage of additional bit line defect information in the volatile memory (160) if a third group of memory elements associated with the additional bit line defect information is within the first group of memory elements (103). [9] The method of claim 6, further comprising generating (306) first decoded data (138) based on the first set of soft bits (172) and a representation of first read data, wherein the first read data (132) is stored in the first group of storage elements (103). [10] The method of claim 9, further comprising: Receiving (308) second bit line defect information (135) from the memory (104), the second bit line defect information identifying bit lines having defects that affect a second group of memory elements (105) of the plurality of memory elements; Generating (310) a second set of soft bits (174) based on the second bit line defect information (135), wherein the second set of soft bits indicates a probability that a second group of bits corresponding to the second group of memory elements (105) is correct; and Generating (312) second decoded data (139) based on the second set of soft bits (174) and a representation of second read data, wherein the second read data (133) is stored in the second group of storage elements (105). [11] The method of claim 9, further comprising: Sending a request to retrieve first read data (132) from the memory (104), wherein the request to retrieve the first read data includes an address corresponding to the first group of memory elements (103), and wherein the request to retrieve the first read data includes a request for bit line defect information associated with the address; and in response to sending the request to retrieve the first read data, receiving a representation of the first read data and the first bit line defect information (134) from the memory. [12] The method of claim 11, further comprising: Receiving from a host device a data request, the data request comprising a second address; Determining whether the second address corresponds to the first group of memory elements (103); and in response to determining that the second address corresponds to the first group of memory elements (103), sending a request to retrieve data stored at the second address to the memory (104), wherein the request to retrieve data stored at the second address does not include a request for bit line defect information.

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