Low-latency multiprotocol resynchronizer

Abstract

A multiprotocol resynchronization device and a method for using it are disclosed.In one embodiment, a device for performing a resynchronization between a first and a second device according to a plurality of protocols comprises the following: a receiver capable of receiving data, a transmitter capable of sending data, a first data path coupled to the receiver and the transmitter capable of transmitting data received by the receiver to the transmitter during protocol-specific training, wherein the first data path comprises a control switching system to control protocol-specific training of the transmitter and / or the receiver in response to a display of a protocol of the plurality of protocols, and a second data path coupled to the receiver and the transmitter, wherein the second data path has a lower latency than the first data path and is intended for use in transmitting data received by the receiver to the transmitter after the protocol-specific training.

Description

AREA OF INVENTION

[0001] Embodiments of the present invention relate to the field of interfaces for computer systems. In particular, embodiments of the present invention relate to resynchronizers that can be configured to transmit data according to several protocols. BACKGROUND OF THE INVENTION

[0002] As the prevalence of external interfaces in computer systems increases and channel improvement while maintaining backward compatibility remains moderate, the need for interface resynchronizers grows. For example, the 4th generation Peripheral Component Interface Express (PCIe), which operates at 16.0 GT / s, requires a resynchronizer for most server channels, which are typically 20" FR4 with two connectors. Universal Serial Bus (USB) version 3.1, operating at 10 GT / s, already requires a resynchronizer for most platforms. Other interfaces require some form of expansion device for some platforms operating at 10.4 GT / s.

[0003] Each of these interfaces presents various challenges. With cache coherence protocols such as Ultra Path Interconnect (UPI), an additional latency of approximately 30 ns per resynchronization hop renders it unusable due to the unacceptable performance degradation. Even with PCIe, latency is a problem for some storage applications, a problem that is expected to worsen with the next generation of non-volatile memory (NVM) technologies, which offer higher bandwidth and lower latency, thus closing the gap to synchronous dynamic random access memory with twice the data rate (DDR-SDRAM). With an analogous new driver, this latency problem does not exist.However, since it is not involved in the connection initialization and equalization phase, the analog re-driver, unlike the re-synchronizers, does not rebuild the transmitter equalization space and therefore has limited application, especially in systems with open slots / connectors.

[0004] Another challenge lies in supporting multiple protocols across different physical layers (PHYs), as found in a Type-C connector. While a separate resynchronizer with a physical multiplexer to isolate between the different PHYs can be a solution, it is expensive and can require valuable board space and higher power consumption.

[0005] A third difficulty is that several different resynchronizers need to be supported on certain platforms, as well as the associated validation, which causes difficulties in terms of interoperability.

[0006] EP 2 778 938 A2 discloses a system comprehensively in which, in response to a first component and a second component undergoing a link training and balancing procedure, a second component transmits a first data set to the first component via a first transmission logic on at least one channel of a communication link.

[0007] US 2005 / 0256984 A1 demonstrates the determination of connection integrity using information in an industry-standard interconnect protocol, such as the Peripheral Component Interconnect Express industry-standard system-level bus interconnect protocol.

[0008] The problem stated is solved according to the invention by the features of claim 1. Further embodiments of the invention are described in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more comprehensive understanding of the present invention is provided by the following detailed description and the accompanying drawings of various embodiments of the invention, which, however, are not to be understood as limiting the invention to the specific embodiments, but merely serve for explanation and understanding. Fig. 1A illustrates a connection without a resynchronizer. Fig. 1B illustrates a connection with one or more resynchronizers. Fig. 1C illustrates another element of a connection with multiple synchronizers. Fig. Figure 2 is a block diagram of an embodiment of a resynchronizer. Fig. Figure 3 is another block diagram of an embodiment of a resynchronizer, showing a data path for training use. Fig. Figure 4 is a flowchart of an embodiment of a process for transmitting data between two facilities using at least one resynchronizer. Fig. Figure 5 illustrates one embodiment of a system level diagram. DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0010] The following description provides numerous details to explain the present invention more precisely. However, a person skilled in the art understands that the present invention can also be implemented without these specific details. In other cases, generally known structures and devices are shown not in detail, but in block diagram form, to highlight the invention more clearly.

[0011] A multiprotocol-capable resynchronizer and a method for using it are disclosed. In one embodiment, a connection, such as a PCIe-compliant connection, can include one or more such resynchronizers or other expansion devices. The resynchronizer includes active electronic elements that receive and transmit (resynchronize) digital signals.

[0012] In one embodiment, the multiprotocol resynchronizer includes two data paths for each sub-connection. The first data path is a low-latency bypass path for normal data traffic. In one embodiment, this first data path is used in common-mode operation. The second data path has a higher latency than the first data path. In one embodiment, this second data path is used in non-common-mode operation or during training (e.g., link training and / or initialization). This is typically the case when latency is not critical.

[0013] In one embodiment, the multiprotocol resynchronizer employs a common data path along with a converged link training and state machine (LTSSM), which is essential for initialization and link training for multiple protocols for which the resynchronizer can be configured. In one embodiment, the LTSSM identifies the protocol running on the link at the beginning from the data rate and bit patterns. In one embodiment, this information can be represented by a sideband mechanism such as a strap or Joint Test Action Group (JTAG) or System Management Bus (SMBUS). In one embodiment, the training includes a link equalization procedure, such as the PCIe link equalization procedure.In one embodiment, the resynchronizer includes a bypass path for low-latency use after any necessary link training (e.g., an equalization process to generate transmitter and / or receiver equalization parameters (e.g., coefficients)) has been performed.

[0014] In one embodiment, the resynchronizer is able to switch between the two paths. In another embodiment, protocol enhancements during training ensure that the resynchronizer can switch back and forth between these two data paths. These protocol enhancements are described in more detail below.

[0015] In one embodiment, the resynchronizer with multiprotocol detection employs circuits to determine the PHY or protocol used for data transmission. In one embodiment, the circuits are coupled to receive a strap option or other sideband mechanism indicating the PHY. In another embodiment, the PHY is determined by detecting a training set modification on a training set used for link training.

[0016] The resynchronizer described here exhibits low latency and can be used across multiple intermediate connections. This represents a significant improvement over separate resynchronizers for separate intermediate connections with high latency.

[0017] Fig. Figure 1A illustrates a connection without a resynchronizer. According to Fig. 1A represents a device 1 and a device 2 connected via a connection A and a connection B. In contrast, this illustrates... Fig. 1B a connection with one or more resynchronizers. According to Fig. In 1B, device 1 and device 12 are coupled to one or more resynchronizers 101. The resynchronizer(s) 101 can be a single component for all lines of the connection or multiple resynchronizers, each responsible for its own set of lines in the connection. In one embodiment, there are multiple resynchronizers in a single connection, as for example in Fig. Figure 1C shows that, in the case of a single resynchronizer, the resynchronizer 101 is connected to facility 1 via a sub-connection A1 and a sub-connection B2, and to facility 2 via a sub-connection A2 and a sub-connection B1. These sub-connections follow a protocol, and the resynchronizer 101 is configurable to operate under this protocol (i.e., one from a variety of protocols), which the sub-connections follow to enable communication between facility 1 and facility 2.

[0018] Fig. Figure 2 is a block diagram of an embodiment of a resynchronizer. In one embodiment, the resynchronizer performs a resynchronization between two devices and is configurable for any (one at a time) of a plurality of protocols.

[0019] According to Fig. 2. A receiver 201 receives data from a first device for transmission to a second device via a sender 202. The receiver 201 and the sender 202 are coupled via a first data path 203, a second data path 204, and a multiplexer (Mux) 206. In one embodiment, the data path 204 is used to transmit data received by the receiver 201 to the sender 202 during protocol-specific training (e.g., link training). The protocol-specific training enables the sender 202 and the receiver 201 to transmit data between the two devices according to the protocol of the link between them. The data path 203 is used to transmit data between the receiver 201 and the sender 202 after the protocol-specific training has been completed. In one embodiment, the data path 203 has a lower latency than the data path 204.In one embodiment, data path 203 is used during common-mode operation, while data path 204 is intended for use during non-common-mode operation and during training.

[0020] In one embodiment, the data path 204 is coupled to the controller 205 (e.g., a control switching system). The controller 205 performs the protocol-specific training of the transmitter 202 and / or the receiver 201. In one embodiment, the protocol-specific training includes link training and initialization. In one embodiment, such link training includes performing an equalization procedure. In one embodiment, the equalization process generates transmitter equalization coefficients to control equalization performed by the transmitter 202, such as cursor coefficients to determine the level of post-equalization and pre-ringing. In one embodiment, the equalization process generates receiver equalization coefficients for receiver-side equalization in the form of continuous time-linear equalization (CTLE) and decision feedback equalization (DFE).It should be noted that in one embodiment, data path 204 is also used during the training of receiver 201.

[0021] In one embodiment, the data path 204 includes one or more connection training state machines for the plurality of protocols, wherein the one or more connection training state machines are executed by the controller 205 to perform connection training according to the protocol specified by the protocol display 210. In one embodiment, a state machine is capable of performing training (e.g., connection training) for multiple protocols. In another embodiment, there are separate state machines for each of the different protocols. In one embodiment, the connection training state machines comprise a connection training and status state machine (LTSSM). The state machine is stored in memory and accessed by the controller 205.In one embodiment, when executing LTSSM, the controller 205 generates ordered sets (OSs) for connection training that correspond to each of the multitude of protocols.

[0022] In one embodiment, the controller 205 responds to a protocol indicator 210 (e.g., one or more signals) that specifies a protocol (or several protocols) used to transmit data between the two devices. The protocol indicator 210 is provided by a protocol / PHY determiner 207 (e.g., a determiner circuit), which provides the protocol indicator 210 in response to a strap option and / or a sideband signal 212 and / or an indicator 213 of a training set modification received from the data path 204. The training set modification is typically specified by any protocol that has a defined training set modification specification for the resynchronizer.

[0023] In one embodiment, upon receiving a predefined training set, the system switches from using data path 203 to data path 204. In such a case, a training set modification indicator 213 can be sent from data path 204 to the protocol / PHY determiner 207, which provides the controller 205 with a protocol indicator 210 to specify that a new link training (e.g., equalization) procedure must be performed. It should be noted that such switching to use either data path 203 or data path 204 is partially implemented by the multiplexer 206. A data path selection signal 211 from the controller 205 causes either data from data path 203 or 204 to be output to the transmitter 202 for transmission.

[0024] Fig. Figure 3 is another block diagram of an embodiment of a resynchronizer, showing a data path for training use. It should be noted that the controller and its function are shown in Figure 3. Fig. 3 not shown, as this is in Fig. 2 happened. Nevertheless, a person skilled in the art understands that the controller fulfills the function of implementing the resynchronization process described herein.

[0025] According to Fig. 3. The resynchronizer comprises a receiver 301 (e.g., receiving circuits) and a transmitter 302 (e.g., transmitting circuits). In one embodiment, the receiver 301 performs continuous time-linear equalization (CTLE) or decision feedback equalization (DFE) in a manner known in the prior art. A clock and data recovery (CDR) circuit 340 is coupled to the receiver 301 and operates in a manner known in the prior art.

[0026] The resynchronizer includes two data paths between the receiver 301 and the transmitter 302. Both are connected to the output of the receiver 301 and two inputs of a multiplexer (Mux) 326, whose output is connected to an input of the transmitter 302. One of the data paths, namely data path 351, is intended for use during training, while the other data path, namely bypass path 350, is used after training.

[0027] Data path 351 includes several components. A serial-to-parallel (S2P) converter 320 converts data from serial to parallel. Since the receiver 301 operates analogously, the S2P converter converts the received data into a parallel format so that the data can be processed in digital format.

[0028] Based on the protocol associated with the data, the parallel data undergoes alignment, decoding, and drafting by the data processor 301, if necessary. Specifically, the data must be disentangled. This may be due to the speed at which the data is received. The bits may also need to be decoded. For example, the data may need to undergo 8b / 10b decoding or another type of decoding. Furthermore, the data may need to undergo alignment to determine where characters begin in the bitstream. These options are performed in a manner known in the prior art to capture the various supported protocols. It should be noted that if alignment, decoding, and / or drafting are not required, such functions are not used. The resulting data is stored in an elastic buffer 322.

[0029] In one embodiment, the elastic buffer 322 is a shared elastic buffer that can also function as a drift buffer for protocols (such as UPI, USB, Thunderbolt, etc.) that require it. The elastic buffer 322 also compensates for bitstreams that are transmitted according to clock cycles of a clock range that do not correspond to the clock cycles of the clock range to which the data is transferred.

[0030] The data from the elastic buffer 322 are sent to the staging buffer and multiplexer (Mux) 324 and the multiprotocol training control block 323.

[0031] In one embodiment, the multiprotocol training control block 323 includes a common set of link training and state machine (LTSSM) subsets required for each protocol, along with the associated bitstream capture / modification required for each protocol. For example, if one of the protocols is PCIe, then the PCIe LTSSM is included as a subset in the common set, and the multiprotocol training control block 323 is capable of performing PCIe standard bitstream capture, ordering (used during link training), and bitstream modification, which is generally known in the prior art. In one embodiment, the multiprotocol training control block 323 includes a common set of link training and state machine (LTSSM) subsets for USB, DisplayPort, Thunderbolt, and / or coherence protocols such as UPI.

[0032] Any data output by the multiprotocol training control block 323 for transmission by the transmitter 302, as well as data from the elastic buffer 322, are received by inputs of the staging buffer mux and the mux 324, which outputs one of the two depending on the control selection (e.g. signal) received by the mux.

[0033] Finally, data output from the staging buffer and the Mux 324 undergoes any scrambling and encoding specified by the protocol used for data transmission, as well as conversion into a serial format using the converter 325. The serial data is output to an input of the Mux 326, which provides the serial data or the data from the bypass path 350 to the transmitter 325.

[0034] It should be noted that in one embodiment the various analog control switching systems, such as those of receiver 301 and transmitter 302, can operate with all data rates of the supported protocols.

[0035] A phase-locked loop (PLL) or other clock generator 311 provides clock signals for the components of the resynchronizer.

[0036] The data path 351 thus has a common set of processing blocks, and the aforementioned common switching system has a common set and associated control switching system that can provide the protocol- and data-rate-related controls required for operation to transmit data according to more than one protocol. In one embodiment, the data path uses a strap or sideband signal to determine the PHY / protocol used. Alternatively, the logic layer can search for the initial training sets and determine which PHY or protocol is used. In one embodiment, this logic layer is located in the multiprotocol training control block 323.

[0037] Bypass path 350 is the second data path intended for use after connection training. In one embodiment, bypass path 350 is intended for low-latency bit transmission and is also enabled for regular bitstream transmission in common-mode operation.

[0038] In one embodiment, the logic layer in the regular path 351 also monitors data traffic in bypass mode to determine whether a bitstream needs to be modified. In one embodiment, the following mechanisms are used for transitions between path 351 and bypass path 350.

[0039] In one embodiment, during link training, path 351 participates in the Tx equalization mechanism on both sides, as specified by the corresponding PHY protocol specification. The Tx equalization setting persists for this speed until a re-equalization procedure occurs. It should be noted that in one embodiment, a re-equalization procedure can occur if a component detects, based on the error rate, that the previously performed equalization is not functioning correctly. In another embodiment, the re-equalization procedure can occur if software, based on similar metrics such as an error rate exceeding a threshold, instructs a link to re-equalize.

[0040] In one embodiment, the PHY specification uses one or more special training sets (TSs) which couple the devices (e.g., device 1 or device 2) described herein via the resynchronizers (or other extension devices). Fig. 1B) After completion of the Tx equalization, send to allow the resynchronizer(s) to switch to bypass mode, in which bypass path 350 is used. During the switchover, the resynchronizer(s) lose the bits that are currently being processed in the regular data path 351. Thus, the receiving device (e.g., device 2 of the Fig. 1B) a section of the bitstream. In one embodiment, this situation is addressed as follows.

[0041] The first single ordered set (OS) (referred to here as the "regular-to-bypass marker ordered set") instructs the resynchronizer(s) to switch the path from regular path 351 to bypass path 350 after the single ordered set has been transmitted, simultaneously signaling the device to reset the block / character boundary. In one embodiment, the switch occurs after a predetermined time, which all components follow. The resynchronizer ensures that the latency does not exceed this predetermined time to allow for the complete transmission of the "regular-to-bypass marker ordered set" without it being truncated or dropped.

[0042] Some time after the marked ordered set is sent, a subsequent ordered set is transmitted. In one embodiment, the elapsed time is longer than the maximum number of resynchronizers permitted on the path by the specification (typically 2) multiplied by the predetermined time after the resynchronizer switches to the bypass path 350. This is determined by the receiver device (e.g., device 2 of the Fig. 1B) used to reset its character / block boundary after missing some bits due to the switch.

[0043] For protocols such as PCI Express, such an ordered set is not necessary, as the ordered sets of TS1 and EIEOS are continued after the de-alignment process. The facility (e.g., facility 2) can easily retrain itself and obtain block alignment upon request through a specification modification.

[0044] Cases occur (such as re-equalization) where the resynchronizer must switch from bypass channel 350 to the normal channel 351. When this happens, a portion of the bitstream is repeated. This can occur because the same marked ordered set of training sets is followed by others, similar to what was described above.

[0045] In one embodiment, when a link needs to go into electrical idle, the sending of the indicating ordered set (e.g., electrical idle ordered set in PCIe) occurs some time before the link actually goes into electrical idle. It should be noted that in PCIe, the EIOS is long enough and can be identified after only a few initial characters, meaning that, depending on the encoding / speed, between 20 and 96 UI remain before the link goes into electrical idle. This indicating ordered set is followed by a valid bitstream that can be dropped. This allows the resynchronizer to respond to the ordered set (in the regular path 351) and send its Tx lines into electrical idle. In an alternative embodiment, no changes are made, and the setup page (e.g., setup 2 from) is expected to Fig. 1B) retrained after exiting electrical idle (which it does anyway after leaving L1).

[0046] Fig. Figure 4 is a flowchart of an embodiment of a process for transmitting data between two devices using at least one resynchronizer. In one embodiment, the process is carried out by processing logic that may include hardware (switching systems, specialized logic, etc.), software (such as that running on a general-purpose computer system or a specialized machine), firmware, or a combination of these three.

[0047] The process begins with processing logic determining the type (e.g., PCIe, USB, DisplayPort, etc.) of the physical layer (PHY) for transmitting data from the receiver to the transmitter (processing block 401). In one embodiment, determining the PHY type is based on a strap option. In another embodiment, determining the PHY type is based on a sideband signal. In yet another embodiment, determining the PHY type is based on monitoring the training set to tune the PHY type.

[0048] In response to the determination of the physical layer (PHY) type for transferring data from receiver to sender, processing logic then provides a protocol display of the protocol according to which the data is transferred (processing block 402).

[0049] In response to the protocol display, processing logic selectively configures either the transmit receiver and / or the receiver (processing block 403). The configuration may include training (e.g., link training). In one embodiment, the protocol-specific training includes performing an equalization process. In another embodiment, performing the equalization process includes generating transmitter equalization coefficients to control equalization performed by the transmitter.

[0050] Subsequently, processing logic with a receiver of a multiprotocol resynchronizer receives data, the data being transmitted according to one of a plurality of protocols (processing block 404), and transmits data between the receiver and the sender of the resynchronizer using a first data path coupled to the receiver and the sender if the transmission of the data received by the receiver occurs during or prior to protocol-specific training of the sender and / or receiver via a control switching system in response to a display of one of the plurality of protocols, or a second data path coupled to the receiver and the sender if the transmission of the data received by the receiver occurs after the protocol-specific training, the second data path having a lower latency than the first data path (processing block 405).

[0051] In one embodiment, using the first data path includes running a link-training state machine to perform link training according to the protocol specified by the display. In another embodiment, running a link-training state machine to perform link training includes generating ordered sets associated with a protocol for link training.

[0052] In one embodiment, the second data path is used during common-mode operation, and the first data path is reserved for use during non-common-mode operation and during protocol-specific training. In another embodiment, using either the first or second data path involves sending a control signal to a multiplexer that has a first input coupled to the first data path and a second input coupled to the second data path to generate an output coupled to the transmitter.

[0053] At a later time, in response to receiving a predefined training set, processing logic switches optionally from using the second data path to the first data path (processing block 406).

[0054] At Fig. Figure 5 is an embodiment of a system-level diagram 500 that may include the methods described above. For example, the methods described above may be integrated into an intermediate connection or interface in the system 500.

[0055] According to Fig. 5 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a mobile phone, a mobile data processing device, a smartphone, an internet-enabled device, or any other type of data processing device. In another embodiment, the System 500 implements the methods disclosed herein and may be a system-on-a-chip (SoC).

[0056] In one embodiment, the processor 510 has one or more processor cores 512 to 512N, where 512N represents the Nth processor core within the processor 510, and N is a positive integer. In another embodiment, the system 500 includes multiple processors, including the processors 510 and 505, wherein the processor 505 has similar or identical logic to the processor 510. In yet another embodiment, the system 500 includes multiple processors, including the processors 510 and 505, such that the processor 505 has logic that is completely independent of the logic of the processor 510. In such an embodiment, a multi-package system 500 is a heterogeneous multi-package system, since the processors 505 and 510 have different logic units.In one embodiment, the processing core 512 comprises, but is not limited to, pre-access logic for accessing instructions, decoding logic for decoding the instructions, execution logic for executing instructions, and the like. In one embodiment, the processor 510 has a cache memory 516 for storing instructions and / or data of the system 500 in the cache. In another embodiment of the invention, the cache memory 516 includes Level 1, Level 2, and Level 3 cache memory, or any other configuration of the cache memory within the processor 510.

[0057] In one embodiment, the processor 510 includes a Memory Control Hub (MCH) 514 capable of performing functions that allow the processor 510 to access and communicate with a memory 530, which includes volatile memory 532 and / or non-volatile memory 534. In one embodiment, the Memory Control Hub (MCH) 514 is positioned as an independent integrated circuit outside the processor 510.

[0058] In one embodiment, the processor 510 is operational and communicates with the memory 530 and a chipset 520. In such an embodiment, the SSD 580 executes the computer's executable instructions when the SSD 580 is booted up.

[0059] In one embodiment, the processor 510 is further coupled to a radio antenna 578 to communicate with any device configured to transmit and / or receive radio signals. In one embodiment, the interface of the radio antenna 578 operates, but is not limited to, in accordance with the IEEE 802.11 standard and its family, HomePlug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMAX, or any form of radio communication protocol.

[0060] In one embodiment, the volatile memory 532 includes, but is not limited to, a synchronous dynamic dial-access memory (SDRAM), dynamic dial-access memory (DRAM), dynamic RAMBUS dial-access memory (RDRAM), and / or any other type of dial-access memory device. The non-volatile memory 534 includes, but is not limited to, flash memory (e.g., NAND, NOR), phase-change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0061] Memory 530 stores information and instructions to be executed by processor 510. In one embodiment, chipset 520 is connected to processor 510 via point-to-point (PtP or PP) interfaces 517 and 522. In another embodiment, chipset 520 enables processor 510 to connect to other modules in system 500. In yet another embodiment, interfaces 517 and 522 operate according to a PtP communication protocol such as Intel QuickPath Interconnect (QPI) or the like.

[0062] In one embodiment, the chipset 520 is capable of communicating with the processor 510, 505, the display unit 540, and other units 572, 576, 574, 560, 562, 564, 566, 577, etc. In another embodiment, the chipset 520 is also coupled to a radio antenna 578 to communicate with any unit configured to transmit and / or receive radio signals.

[0063] In one embodiment, the chipset 520 is connected to a display device 540 via an interface 526. In one embodiment, the display device 540 includes, but is not limited to, a liquid crystal display (LCD), a plasma display, a cathode ray tube (CRT) display, or any other type of optical display device. Furthermore, the chipset 520 is connected to one or more buses 550 and 555, which connect various modules 574, 560, 562, 564, and 566. In one embodiment, the buses 550 and 555 can be interconnected via a bus bridge 572 if there is a discrepancy regarding the bus speed or the communication protocol.In one embodiment, the chipset 520, without being limited thereto, is connected via the interface 524 to a non-volatile memory 560, a mass storage device(s) 562, a keyboard / mouse 564 and a network interface 566, a smart TV 576, consumer electronics 577 etc.

[0064] In one embodiment, the mass storage device 562 includes, but is not limited to, a solid-state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, the network interface 566 is implemented by any type of a generally known network interface standard, including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect (PCI) Express interface, a radio interface, and / or any other interface type.

[0065] Although the in Fig.The 5 modules shown are represented as separate blocks within the System 500; however, the functions performed by some of these blocks may be integrated into a single semiconductor circuit or implemented using two or more separate integrated circuits.

[0066] In a first exemplary embodiment, a device for performing a resynchronization between a first and a second device according to a plurality of protocols comprises the following: a receiver capable of receiving data, a transmitter for sending data, a first data path coupled to the receiver and the transmitter capable of transmitting data received by the receiver to the transmitter during protocol-specific training, wherein the first data path comprises a control switching system to control protocol-specific training of the transmitter and / or the receiver in response to a display of a protocol of the plurality of protocols, and a second data path coupled to the receiver and the transmitter.where the second data path has a lower latency than the first data path and is intended for use when transmitting data received by the receiver to the sender after protocol-specific training.

[0067] In a further exemplary embodiment, the subject matter of the first exemplary embodiment may optionally include the protocol-specific training comprising the execution of an equalization process. In a further exemplary embodiment, the subject matter of this exemplary embodiment may optionally include the equalization process generating transmitter equalization coefficients to control equalization performed by the transmitter.

[0068] In a further exemplary embodiment, the subject matter of the first exemplary embodiment can optionally include the fact that the second data path is used during common-mode operation and the first data path is provided for use during non-common-mode operation and during training.

[0069] In another exemplary embodiment, the subject matter of the first exemplary embodiment can optionally include a switch from using the second data path to the first data path in response to receiving a predefined training set.

[0070] In a further exemplary embodiment, the subject matter of the first exemplary embodiment may optionally include a circuit to provide the display in response to a determination of the physical layer (PHY) for transmitting data from the receiver to the transmitter. In a further exemplary embodiment, the subject matter of this exemplary embodiment may optionally include the circuit being capable of determining the PHY based on a strap option, of determining the PHY based on a sideband signal, or of determining the PHY based on a training quantity modification.

[0071] In another exemplary embodiment, the subject matter of the first exemplary embodiment can optionally include a multiplexer having a first input coupled to the first data path, a second input coupled to the second data path, and an output coupled to the transmitter.

[0072] In a further exemplary embodiment, the subject matter of the first exemplary embodiment may optionally include that the first data path further comprises one or more connection training state machines for the plurality of protocols, wherein the one or more connection training state machines are used by the control switching system to perform connection training according to the protocol specified by the display. In a further exemplary embodiment, the subject matter of this exemplary embodiment may optionally include that the control switching system is capable of generating ordered sets associated with each of the plurality of protocols for connection training.

[0073] In a further exemplary embodiment, the subject matter of the first exemplary embodiment may optionally include the following in the first data path: a serial-to-parallel (S2P) converter coupled to convert first serial data received by the receiver into first parallel data; first logic coupled to the S2P converter to perform alignment, decoding, and design, if necessary; an elastic buffer coupled to the first logic to store data after any alignment, decoding, and design; a staging buffer circuitry coupled to the elastic buffer and the control circuitry, wherein the staging buffer circuitry comprises a multiplexer that responds to one or more control signals to provide the sender with data from the elastic buffer or training data.and a parallel-to-serial (P2S) converter, coupled and operational, to receive second parallel data from the staging buffer switching system and to convert the second parallel data into second serial data.

[0074] In a second exemplary embodiment, a method comprises receiving data with a receiver of a multiprotocol resynchronizer, wherein the data was transmitted according to one of a plurality of protocols, and transmitting data between the receiver and the sender of the resynchronizer using a first data path coupled to the receiver and the sender, if the transmission of the data received by the receiver occurs during or prior to protocol-specific training of the sender and / or receiver via a control switching system in response to a display of one of the plurality of protocols, or a second data path coupled to the receiver and the sender, if the transmission of the data received by the receiver occurs after the protocol-specific training, wherein the second data path has a lower latency than the first data path.

[0075] In a further exemplary embodiment, the subject matter of the second exemplary embodiment may optionally include the protocol-specific training comprising the execution of an equalization process. In a further exemplary embodiment, the subject matter of this exemplary embodiment may optionally include the execution of the equalization process comprising the generation of transmitter equalization coefficients in order to control equalization performed by the transmitter.

[0076] In a further exemplary embodiment, the subject matter of the second exemplary embodiment may optionally include the fact that the second data path is used during common-mode operation and the first data path is provided for use during non-common-mode operation and during protocol-specific training.

[0077] In another exemplary embodiment, the subject matter of the second exemplary embodiment can optionally include switching from the use of the second data path to the first data path in response to receiving a predefined training set.

[0078] In another exemplary embodiment, the subject matter of the second exemplary embodiment can optionally include providing the display in response to a determination of the physical layer (PHY) for transmitting data from the receiver to the transmitter. In a further exemplary embodiment, the subject matter of this exemplary embodiment can optionally include the determination of the PHY type being based on a strap option, a sideband signal, or a training amount modification.

[0079] In a further exemplary embodiment, the subject matter of the second exemplary embodiment may optionally include the selection of a control signal of a multiplexer having a first input coupled to the first data path and a second input coupled to the second data path in order to generate an output coupled to the transmitter.

[0080] In another exemplary embodiment, the subject matter of the second exemplary embodiment can optionally include running a link-training state machine to perform link training according to the protocol specified by the display. In a further exemplary embodiment, the subject matter of this exemplary embodiment can optionally include generating ordered sets associated with a protocol for link training.

[0081] In a further exemplary embodiment, the subject matter of the second exemplary embodiment may optionally include: storing data in an elastic buffer during training, and controlling an output of a multiplexer coupled to the elastic buffer to send data from the elastic buffer or training data generated during link training to the transmitter, wherein a parallel-to-serial (P2S) converter is coupled and operational to receive second parallel data from the staging buffer circuitry and to convert the second parallel data into second serial data.

[0082] In a third exemplary embodiment, a system comprises a pair of devices, a resynchronizer coupled between the pair of devices to provide a bidirectional data flow between the pair of devices, wherein the data flow in each direction is carried out by a receiver capable of receiving data, a transmitter to send data, a first data path coupled to the receiver and the transmitter capable of transmitting data received by the receiver to the transmitter during protocol-specific training, wherein the first data path comprises a control switching system to control protocol-specific training of the transmitter and / or the receiver in response to a display of a protocol of the plurality of protocols, and a second data path coupled to the receiver and the transmitter.wherein the second data path has a lower latency than the first data path and is intended for use in transmitting data received by the receiver to the sender after protocol-specific training. In a further exemplary embodiment, the subject matter of this exemplary embodiment may optionally include the protocol-specific training comprising the performance of an equalization process. In a further exemplary embodiment, the subject matter of this exemplary embodiment may optionally include the equalization process generating sender equalization coefficients to control equalization performed by the sender.

[0083] In a further exemplary embodiment, the subject matter of the second exemplary embodiment can optionally include the fact that the second data path is used during common-mode operation and the first data path is provided for use during non-common-mode operation and during training.

[0084] Some sections of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits in a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art in data processing to most effectively communicate the content of their work to another skilled person. An algorithm is understood here, as it is generally, as a coherent sequence of steps that leads to a desired result. These steps are those that require the physical manipulation of physical quantities. Usually, but not necessarily, these quantities are in the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated.At times, primarily for reasons of general use, it has proven useful to refer to these signals as bits, values, elements, symbols, characters, expressions, numbers, or the like.

[0085] However, it should be remembered that all these and similar expressions are to be assigned to the appropriate physical quantities and are merely convenient designations applied to these quantities.Unless expressly stated otherwise, as is evident from the following discussion, it is understood that throughout this description, discussions using terms such as "processing" or "data processing" or "calculating" or "determining" or "displaying" or the like refer to actions and processes of a computer system or similar electronic data processing device that manipulates data represented as physical (electronic) quantities within the registers and memories of the computer system and transforms them into other data represented in a similar manner as physical quantities within the memories or registers or other such information storage, transmission, or display devices of the computer system.

[0086] The present invention also relates to a device for carrying out the present work steps. This device may be specially designed for the required purposes or it may comprise a general-purpose computer which is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored on a computer-readable storage medium, for example, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic-optical disks, read-only memory (ROMs), random-access memory (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0087] The algorithms and displays presented herein do not inherently relate to any particular computer or other specific device. Various general-purpose systems with programs according to the present teachings can be used, or it may prove advantageous to construct more specialized devices to perform the necessary process steps. The required structure for a variety of such systems will become apparent from the following description. Furthermore, the present invention is not described with reference to any particular programming language. It is understood that a variety of programming languages ​​can be used to implement the teachings of the invention as described herein.

[0088] A machine-readable medium is any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). Examples of machine-readable media include read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory, etc.

[0089] For a person skilled in the art, after reading the foregoing description, many changes and modifications of the present invention are undoubtedly conceivable, and it is understood that certain embodiments shown and described for illustrative purposes are by no means to be considered limiting. References to details of various embodiments are therefore not intended to limit the scope of the claims, which in themselves only specify the features that are considered essential to the invention.

Claims

[1] Device for performing a resynchronization between a first and a second device (1,2) according to a plurality of protocols, wherein the device (1,2) comprises: a receiver (201, 301) that is operational and capable of receiving data, a transmitter, (202, 302) to send data, a first data path (203) coupled to the receiver (201, 301) and the transmitter (202, 302), which is operational, to transmit data received by the receiver (201, 301) to the transmitter (202, 302) during protocol-specific training, wherein the first data path (203) comprises a control switching system to control protocol-specific training of the transmitter (202, 302) and / or the receiver (201, 301) in response to a display of a protocol (210) of the plurality of protocols, and a second data path (204) coupled to the receiver (201, 301) and the sender (202, 302), wherein the second data path (204) has a lower latency than the first data path (203) and is intended for use in transmitting data received by the receiver (201, 301) to the sender (202, 302) after protocol-specific training. [2] Device according to claim 1, wherein the protocol-specific training comprises performing an equalization process. [3] Device according to claim 2, wherein the equalization process generates transmitter equalization coefficients to control an equalization performed by the transmitter (202, 302). [4] Device according to claim 1, wherein the second data path (204) is used during common-mode operation and the first data path (203) is provided for use during non-common-mode operation and during training. [5] Device according to claim 1, wherein in response to receiving a predefined training quantity, a switch is made from the use of the second data path (204) to the first data path (203). [6] Device according to claim 1, further comprising a circuit (207) to provide the display (210) in response to a determination of the physical layer (PHY) for transmitting data from the receiver (201, 301) to the transmitter (202, 302). [7] Device according to claim 6, wherein the circuit (207) is capable of determining the PHY based on a strap option, a sideband signal or a training quantity modification. [8] Device according to claim 1, further comprising a multiplexer (206, 324) having a first input coupled to the first data path (203) and a second input coupled to the second data path (204) and an output coupled to the transmitter (202, 302). [9] Device according to claim 1, wherein the first data path (203) further comprises one or more link training state machines for the plurality of protocols, wherein the one or more link training state machines are used by the control switching system to perform link training according to the protocol specified by the display (210). [10] Device according to claim 1, wherein the first data path (203) further comprises: a serial-to-parallel (S2P) converter (320) which is coupled to convert first serial data received by the receiver (201, 301) into first parallel data, first logic coupled to the S2P converter (320) to perform alignment, decoding and design if necessary, an elastic buffer coupled to the first logic to store data after any alignment, decoding and design, a staging buffer switching system coupled to the elastic buffer and the control switching system, wherein the staging buffer switching system comprises a multiplexer (206, 326) that responds to one or more control signals to provide the transmitter (202, 302) with data from the elastic buffer or training data, and a parallel-to-serial (P2S) converter (320) that is coupled and operational, to receive second parallel data from the staging buffer switching system and to convert the second parallel data into second serial data. [11] Procedure, encompassing: Receiving (404) data with a receiver (201, 301) of a multiprotocol resynchronizer (101), wherein the data was transmitted according to one of a variety of protocols, and Transfer (405) of data between the receiver (201, 301) and the sender (202, 302) of the resynchronizer (101) using a first data path (203) coupled to the receiver (201, 301) and the sender (202, 302), if the transmission of the data received by the receiver (201, 301) during or prior to protocol-specific training of the sender (202, 302) and / or receiver (201, 301) via a control switching system in response to a display (210) of a protocol of the plurality of protocols, or a second data path (203) coupled to the receiver (201, 301) and the sender (202, 302), if the transmission of the data received by the receiver (201, 301) takes place after protocol-specific training, wherein the second data path (204) has a lower latency than the first data path (203). [12] Method according to claim 11, wherein the protocol-specific training comprises performing an equalization process to generate transmitter equalization coefficients to control equalization performed by the transmitter (202, 302). [13] Method according to claim 11, wherein the second data path (204) is used during common-mode operation and the first data path (203) is provided for use during non-common-mode operation and during protocol-specific training. [14] Method according to claim 11, further comprising a switching (406) from the use of the second data path (204) to the first data path (203) in response to receiving a predefined training set. [15] Method according to claim 11, further comprising providing the display (210) in response to a determination of the physical layer (PHY) for transmitting data from the receiver (201, 301) to the sender (202, 302). [16] Method according to claim 15, wherein the determination of the PHY is based on a strap option, a lateral band signal or a training quantity modification. [17] Method according to claim 11, further comprising: Storing data in an elastic buffer during a training session and Controlling an output of a multiplexer (206, 324) coupled to the elastic buffer to send data from the elastic buffer or training data generated during link training to the transmitter (202, 302), wherein a parallel-to-serial (P2S) converter (320) is coupled and operational, to receive second parallel data from the staging buffer switching system and to convert the second parallel data into second serial data. [18] System, comprehensive, a pair of facilities (1, 2), a resynchronizer (101) coupled between the pair of facilities (1, 2) to provide a bidirectional data flow between the pair of facilities (1, 2), the data flow being carried out in each direction by a receiver (201, 301) that is operational and capable of receiving data, a transmitter (202, 302) to send data, a first data path (203) coupled to the receiver (201, 301) and the transmitter (202, 302), which is operational to transmit data received by the receiver (201, 301) to the transmitter (202, 302) during protocol-specific training, wherein the first data path (203) comprises a control switching system to control protocol-specific training of the transmitter (202, 302) and / or the receiver (201, 301) in response to a display (210) of a protocol of the plurality of protocols, and a second data path (203) coupled to the receiver (201, 301) and the sender (202, 302), wherein the second data path (204) has a lower latency than the first data path (203) and is intended for use in transmitting data received by the receiver (201, 301) to the sender (202, 302) after protocol-specific training. [19] System according to claim 18, wherein the protocol-specific training comprises performing an equalization process to generate transmitter equalization coefficients to control equalization performed by the transmitter (202, 302). [20] System according to claim 18, wherein the second data path (204) is used during common-mode operation and the first data path (203) is provided for use during non-common-mode operation and during training.

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