Semiconductor device

Abstract

Semiconductor device comprising the following: a multilayer wiring layer in which several interlayer films and several diffusion prevention films are stacked alternately and a wiring conductor is formed in the interlayer films; a contact via that penetrates a via insulation layer formed on a surface of the multilayer wiring layer and is electrically connected to the wiring conductor of the multilayer wiring layer; a through-hole that penetrates at least one of the interlayer wiring films and the diffusion prevention films from the other surface of the multilayer wiring layer on the opposite side from one surface of the multilayer wiring layer; and an air gap connected to the through-hole and formed in at least one of the intermediate layer films to expose the contact via, wherein a semiconductor substrate is further arranged on the other surface of the via insulation layer on the opposite side from a surface on which the multilayer wiring layer is formed, wherein a photodiode is arranged in the semiconductor substrate, and wherein The air gap is further formed in an area in contact with a TG control line, which is electrically connected to a gate of a transfer transistor that controls a reading of a signal charge from the photodiode.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor device. STATE OF THE ART

[0002] As semiconductor devices become increasingly smaller, wiring delays, which reduce the operating speed of semiconductor devices, have increased. Specifically, in a semiconductor device, wiring resistance increases due to a decrease in the cross-sectional area of ​​the wiring leads, and therefore a delay increases proportionally to the product of the wiring resistance and the capacitance between the wiring leads (this delay is also known as RC delay).

[0003] To reduce such wiring delays, investigations were carried out to lower the dielectric constant of an interlayer film between wiring conductors. However, no interlayer film material has yet been found that achieves a sufficiently low dielectric constant.

[0004] In view of this, a method for further reducing the dielectric constant between wiring leads by removing the material between the wiring leads and forming a hollow layer (also known as an air gap) with a relative dielectric constant of 1 between the wiring leads was considered.

[0005] For example, German patent application JP 2006-19401A discloses the provision of a structure that does not damage the wiring leads when an insulating film between the wiring leads is removed to form an air gap structure. German patent application DE 11 2017 004 206 T5 discloses a semiconductor device in which mechanical strength and reliability are maintained while inter-wiring capacitance is reduced by means of a gap.

[0006] Publication US 2008 / 0179750A1 shows an integrated electronic circuit comprising stacked insulating layers and metal elements distributed within the insulating layers. Brief description of the invention; problems to be solved by the invention

[0007] According to the technology disclosed in JP 2006-19401A, a thin film with low mechanical strength protrudes into a space where an air gap is formed, and therefore there is a possibility that the thin film protruding into the air gap will collapse. Furthermore, according to the technology disclosed in JP 2006-19401A, if the distance between wiring leads is long, the mechanical strength of the entire semiconductor device is lower due to the air gaps, and therefore there is a possibility that the reliability of the semiconductor device will decrease.

[0008] In light of the above, the present disclosure proposes a new and improved semiconductor device capable of reducing the capacitance between wiring leads while maintaining mechanical strength and reliability. SOLUTIONS TO THE PROBLEMS

[0009] According to a first aspect, the present disclosure provides a semiconductor device according to claim 1. Further aspects will become apparent from the dependent claims, the drawings, and the following description.The present disclosure is intended to provide a semiconductor device comprising: a multilayer wiring layer in which several interlayer films and several diffusion-inhibiting films are stacked alternately and a wiring conductor is formed in the interlayer films; a contact via that penetrates a via insulation layer formed on one surface of the multilayer wiring layer and is electrically connected to the wiring conductor of the multilayer wiring layer; a through-hole that penetrates at least one of the interlayer films and the diffusion-inhibiting films from the other surface of the multilayer wiring layer on the opposite side from the one surface; and an air gap connected to the through-hole that is formed in at least one of the interlayer films to expose the contact via.

[0010] According to the present disclosure, an intermediate layer film is removed in a predetermined region in the stacking direction and the plane-internal direction, so that an air gap can be formed in a region around a contact via which connects a semiconductor substrate to a wiring line. EFFECTS OF INVENTION

[0011] As described above, according to the present disclosure it is possible to reduce the capacitance between wiring leads while maintaining the mechanical strength and reliability of a semiconductor device.

[0012] It is noted that the effect described above is not necessarily limiting and it is possible to achieve any of the effects described in this patent specification together with or instead of the effect mentioned above, or it is possible to achieve other effects that are apparent from this patent specification. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure in the stacking direction. Fig. Figure 2A is a cross-sectional view illustrating a step in a method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 2B is a cross-sectional view illustrating a step in the process for manufacturing the semiconductor device according to the embodiment. Fig. Figure 2C is a cross-sectional view illustrating a step in the process for manufacturing the semiconductor device according to the embodiment. Fig. 2D is a cross-sectional view illustrating a step in the process for manufacturing the semiconductor device according to the embodiment. Fig. Figure 2E is a cross-sectional view illustrating a step in the process for manufacturing the semiconductor device according to the embodiment. Fig. Figure 2F is a cross-sectional view illustrating a step in the process for manufacturing the semiconductor device according to the embodiment. Fig. Figure 2G is a cross-sectional view illustrating a step in the process for manufacturing the semiconductor device according to the embodiment. Fig. Figure 3 is a cross-sectional view of a semiconductor device according to a first modification of the embodiment in the stacking direction. Fig. Figure 4 is a cross-sectional view of a semiconductor device according to a second modification of the embodiment in the stacking direction. Fig. Figure 5A is a cross-sectional view of a semiconductor device according to a third modification of the embodiment in the stacking direction. Fig. Figure 5B is a cross-sectional view of a semiconductor device according to the third modification of the embodiment in the stacking direction. Fig. 5C is a cross-sectional view of a semiconductor device according to the third modification of the embodiment in the stacking direction. Fig. Figure 6 is a cross-sectional view of a semiconductor device according to a fourth modification of the embodiment in the stacking direction. Fig. Figure 7 is a cross-sectional view of a semiconductor device according to a second embodiment of the present disclosure in the stacking direction. Fig. Figure 8A is a cross-sectional view illustrating a step in a method for manufacturing the semiconductor device according to the embodiment. Fig. Figure 8B is a cross-sectional view illustrating a step in the process for manufacturing the semiconductor device according to the embodiment. Fig. Figure 8C is a cross-sectional view illustrating a step in the process for manufacturing the semiconductor device according to the embodiment. Fig. Figure 8D is a cross-sectional view illustrating a step in the process for manufacturing the semiconductor device according to the embodiment. Fig. Figure 8E is a cross-sectional view illustrating a step in the process for manufacturing the semiconductor device according to the embodiment. Fig. Figure 9 is a cross-sectional view of a semiconductor device according to a modification of the embodiment in the stacking direction. Fig. Figure 10 is a cross-sectional view of a semiconductor device according to a third embodiment of the present disclosure in the stacking direction. Fig. Figure 11 is a schematic diagram showing the stacking structure of each wiring line of the semiconductor device according to the embodiment. Fig. Figure 12 is a schematic diagram showing the stacking structure of each wiring line of the semiconductor device according to the embodiment. Fig. 13A is a cross-sectional view showing a cross-section along the Fig. Line A-AA is shown in section 11. Fig. 13B is a cross-sectional view showing a cross-section along the Fig. Line B-BB is shown in section 11. Fig. 13C is a cross-sectional view showing a cross-section along the in Fig. Line C-CC is shown in section 12. Fig. Figure 14 is a diagram that schematically shows an example configuration of an endoscopic surgical system. Fig. Figure 15 is a block diagram showing an example of the functional configurations of a camera head and a CCU. Fig. Figure 16 is a block diagram that schematically shows an example configuration of an in-vivo information acquisition system. Fig. Figure 17 is a block diagram that schematically shows an example configuration of a vehicle control system. Fig. Figure 18 is an explanatory diagram showing an example of installation positions for external information detectors and imaging units. METHODS OF IMPLEMENTATION OF THE INVENTION

[0013] The following is a detailed description of preferred embodiments of the present disclosure with reference to the accompanying drawings. It should be noted that in this patent specification and the drawings, components with substantially the same functional configurations are designated by the same reference numerals, and their explanation is not repeated.

[0014] In the drawings referenced below, the sizes of some components are sometimes shown larger than they actually are for the sake of clarity. Therefore, the relative sizes of the components shown in the drawings do not always accurately represent the size relationship between the actual components. Furthermore, the direction in which substrates or layers are stacked is sometimes referred to as the upward direction in the description below.

[0015] Please note that the explanation will follow the order below. 1. First embodiment 1.1. Example configuration 1.2. Manufacturing process 1.3. Modifications 2. Second embodiment 2.1. Example configuration 2.2. Manufacturing process 2.3. Modifications 3. Third embodiment 4. Example applications 4.1. First application 4.2. Second application 4.3. Third Application <1. First embodiment>(1.1. Example configuration)

[0016] First, with reference to Fig. 1 describes the configuration of a semiconductor device according to a first embodiment of the present disclosure. Fig. Figure 1 is a cross-sectional view of a semiconductor device according to this embodiment in the stacking direction. It is noted that Fig. 1 shows a part of a cross-section of a semiconductor device 1 according to this embodiment and the semiconductor device 1 naturally extends into areas not shown in the drawing.

[0017] As in Fig. As shown in Figure 1, the semiconductor device 1 includes a via insulation layer 600 and a multilayer wiring layer 101 in which a first to third intermediate layer film 110, 120 and 130 and a first to fourth diffusion prevention film 210, 220, 230 and 240 are stacked alternately.

[0018] Contact vias 610 and a zero-level wiring line 620 are formed in the via insulation layer 600, and the first to third wiring lines 310, 320, and 330 are formed in the first to third intermediate layer films 110, 120, and 130, respectively. The first to third wiring lines 310, 320, and 330 are electrically connected to each other by a second and third through-via 420 and 430.

[0019] Hereinafter, the first to third interlayer films 110, 120, and 130 are also collectively referred to as the interlayer films 100, and the first to fourth diffusion-prevention films 210, 220, 230, and 240 are also collectively referred to as the diffusion-prevention films 200. Furthermore, the first to third wiring lines 310, 320, and 330 are also collectively referred to as the wiring lines 300, and the second and third through-vias 420 and 430 are also collectively referred to as the through-vias 400.

[0020] That is, the semiconductor device 1 includes the multilayer wiring layer 101 in which the interlayer films 100 including the wiring lines 300 and the through-vias 400 and the diffusion prevention films 200 are stacked alternately.

[0021] It is noted that in Fig. 1. The multilayer wiring layer 101 has a structure in which the first to third interlayer films 110, 120, and 130 and the first to fourth diffusion-prevention films 210, 220, 230, and 240 are stacked alternately. However, the technology according to the present disclosure is not limited to such an example. The multilayer wiring layer 101 can, for example, include four or five or more interlayer films 100. Furthermore, the multilayer wiring layer 101 can be formed with interlayer films 100 and diffusion-prevention films 200 present in equal numbers.

[0022] The interlayer films 100 electrically insulate the wiring leads 300 from one another and are the main layer elements that form the semiconductor device 1. The interlayer films 100 are formed with an insulating material that is easily etched (in particular, etching is easier than on the diffusion-inhibiting films 200 described later) and can be formed with an insulating material such as SiO2. Alternatively, the interlayer films 100 can be formed with an organic resin, a low-k material such as carbon-doped SiO2 or porous silicon dioxide, or the like.

[0023] The diffusion-inhibiting films 200 are arranged to sandwich the respective intermediate layer films 100, preventing surface diffusion of the metal forming the wiring conductors 300 and acting as a stopper when the layers are processed on top of them. Specifically, the diffusion-inhibiting films 200 are formed with an insulating material having a higher etch resistance (for example, etch resistance with respect to a fluorine compound) than the intermediate layer films 100 and can be combined with an insulating material such as SiN. x , SiCN, SiON or SiC, may be formed.

[0024] It is noted that the materials forming the interlayer films 100 and the diffusion-inhibiting films 200 only need to be selected to increase the etch selectivity of the interlayer films 100 relative to the diffusion-inhibiting films 200, and various combinations are possible. Therefore, the materials forming the interlayer films 100 and the diffusion-inhibiting films 200 are not limited to those described above, and a combination of other materials can be used.

[0025] The wiring leads 300 transmit current or voltage between active or passive elements provided in the semiconductor device 1. The wiring leads 300 are formed with a conductive material and can be formed with a first metal, an alloy of the first metal, or the like. The first metal is, for example, an easy-to-process metal with low resistance, such as copper (Cu), aluminum (Al), cobalt (Co), or an alloy of these metals (such as CoWB). If the wiring leads 300 are formed with Cu, they can be easily formed by using a Damascene technique or the like. If the wiring leads 300 are formed with Al, they can also be easily formed by dry etching with a halogen gas.

[0026] The through-vias 400 electrically connect the wiring lines 300 formed in the different interlayer films 100. Specifically, the second through-via 420 electrically connects the first wiring lines 310 and the second wiring lines 320, and the third through-via 430 electrically connects the second wiring lines 320 and the third wiring lines 330. The through-vias 400 are formed with a conductive material and can be formed with a first metal or an alloy of the first metal, such as the wiring lines 300. For example, the through-vias 400 can be formed with copper (Cu), aluminum (Al), cobalt (Co), an alloy of these metals (such as CoWB), or the like.

[0027] The via insulation layer 600 is formed with an insulating material on a surface of the multilayer wiring layer 101 and electrically insulates each of the contact vias 610 from one another. Like the interlayer films 100, the via insulation layer 600 can be formed with an insulating material on which etching can be carried out relatively easily (in particular, on which etching can be carried out more easily than on the diffusion-inhibiting films 200). The via insulation layer 600 can be formed with an insulating material such as SiO2, or it can be formed with an organic resin, a low-k material such as carbon-doped SiO2 or porous silicon dioxide, or the like.

[0028] The contact vias 610 penetrate the via insulating layer 600 and the first diffusion-prevention film 210, are formed such that they project into the first interlayer film 110, and electrically connect the (not shown) semiconductor substrate to the first wiring leads 310. In particular, the contact vias 610 electrically connect the first wiring leads 310 to the (not shown) semiconductor substrate formed on the other surface of the via insulating layer 600 on which the multilayer wiring layer 101 is formed, or to electrodes or the like formed on the semiconductor substrate. For example, the contact vias 610 can be formed with a conductive material and can be formed with a second metal or an alloy of the second metal, which is different from the first metal forming the wiring leads 300, and the like.The second metal is one that exhibits characteristics such as lower diffusion of metal atoms into the semiconductor substrate, stronger burying properties at the time of contact via 610 formation, and higher heat resistance. This metal could be, for example, tungsten (W) or a similar alloy.

[0029] It is noted that the contact vias 610 can be formed in a potential-free state in the via insulation layer 600 and the first interlayer film 110 to ensure the mechanical strength of the semiconductor device 1. In such a case, the contact vias 610 act as column-like elements that provide support between the layers of the semiconductor device 1.

[0030] The zero-point wiring line 620 is formed within the first interlayer film 110 and on the first diffusion-prevention film 210 and electrically connects active or passive elements provided in the semiconductor device 1 to the contact vias 610. The zero-point wiring line 620 is formed with a conductive material and can be formed with a second metal or an alloy of the second metal, such as the contact vias 610. For example, the zero-point wiring line 620 can be formed with tungsten (W), a tungsten alloy, or the like.

[0031] Since the contact vias 610 and the zero-point wiring line 620 are located closer to the semiconductor substrate than the wiring lines 300, they can be formed with the second metal, which has a lesser influence on the semiconductor substrate than the first metal. If the contact vias 610 and the zero-point wiring line 620 are formed with the second metal, a barrier metal layer, formed with a metal exhibiting strong barrier properties against atoms, can be created on the surfaces of the contact vias 610 and the zero-point wiring line 620. The barrier metal layer can be formed with a metal such as tantalum (Ta), titanium (Ti), ruthenium (Ru), cobalt (Co), or manganese (Mn), or with a nitride or oxide of these metals.

[0032] However, the barrier metal layer can be damaged during the etching process to form the air gap 530, which is described later. Therefore, if the barrier metal layer is formed on the surfaces of the contact vias 610 and the zero-point wiring line 620, a protective film formed with a material similar to that of the diffusion-inhibiting films 200 can be provided to cover the barrier metal layer.

[0033] The semiconductor device 1 according to this embodiment further comprises a through-hole 510, a protective side wall 520, and an air gap 530. The air gap 530 is formed in the first interlayer film 110 and the second interlayer film 120, so that the contact vias 610 are exposed. The through-hole 510 is formed such that it penetrates the fourth diffusion-inhibiting film 240, the third interlayer film 130, and the third diffusion-inhibiting film 230, and connects the air gap 530 to the outside. The protective side wall 520 is formed on the side surface within the through-hole 510.

[0034] It is noted that, although this in Fig. (Not shown in Figure 1) a sealing layer for covering the opening formed by the through-hole 510 can be arranged on the fourth diffusion-prevention film 240. The sealing layer can be made, for example, of an inorganic insulating material such as SiO₂. x , SiN x , SiCN, SiON or SiC, or an organic resin and can prevent the ingress of moisture and the like into the through hole 510 and the air gap 530.

[0035] The through-hole 510 is formed such that it penetrates the interlayer films 100, which are located on the other surface of the multilayer wiring layer 101 opposite the surface provided with the via insulation layer 600, and the diffusion-prevention films 200, which sandwich the interlayer films 100. In particular, the through-hole 510 is formed such that it penetrates the third interlayer film 130 and the third and fourth diffusion-prevention films 230 and 240, which sandwich the third interlayer film 130. The opening of the through-hole 510 can be formed in any planar shape. For example, the opening of the through-hole 510 can be formed in a substantially square shape with a side of at least 50 nm to 300 nm or in a substantially circular shape with a diameter of at least 50 nm to 300 nm.

[0036] The protective sidewall 520 is formed on the side surface within the through-hole 510 and protects the side surface of the third interlayer film 130, which is exposed through the through-hole 510. The protective sidewalls 520 are formed, for example, with an insulating material having a higher etch resistance (for example, etch resistance with respect to a fluorine compound) than the interlayer films 100 and can be made with an insulating material such as SiN xThe protective sidewall 520 may be formed with SiCN, SiON, SiOC, or SiC. Alternatively, it may be formed with a high-k material such as aluminum oxide (Al₂O₃), titanium oxide (TiO₂), dititanium pentoxide (Ta₂O₅), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), or lanthanum oxide (La₂O₃), or it may be formed with a metallic material. It should be noted that if the protective sidewall 520 is formed with a metallic material, it is constructed in a potential-free state.

[0037] The protective sidewall 520 protects the third interlayer film 130 from etching when the air gap 530 is formed. Specifically, the air gap 530 is formed by introducing an etching solution or etching vapor through the through-hole 510 and performing etching (wet or vapor etching) on ​​the first interlayer film 110 and the second interlayer film 120. At this point, the protective sidewall 520 protects the third interlayer film 130 from etching by the etching solution or etching vapor. Since the through-hole 510 on the inner wall surface is covered by the protective sidewall 520, as described above, the semiconductor device 1 can form the air gap 530 in the interlayer films 100 within the multilayer wiring layer 101. It is noted that the protective sidewall 520, for example, can be a thin film with a thickness of 5 nm to 30 nm.

[0038] The air gap 530 is formed in at least one of the interlayer films 100 of the multilayer wiring layer 101, so that the contact vias 610 are exposed, and the space between the respective contact vias 610 or the respective wiring leads 300 is a hollow space with a relative dielectric constant of 1. In particular, the air gap 530 is formed in the first interlayer film 110 and the second interlayer film 120, and each space between a portion of the contact vias 610, the first wiring leads 310, and the second wiring leads 320 is a hollow space. With this arrangement, the air gap 530 can reduce the parasitic capacitance formed between the respective contact vias 610 or the respective wiring leads 300.

[0039] In the semiconductor device 1 according to this embodiment, the air gap 530 is formed in the first interlayer film 110 to expose at least the contact vias 610. With this configuration, the semiconductor device 1 can reduce the capacitance between the wiring leads in the area near the semiconductor substrate on which transistors and the like are formed. Accordingly, the basic performance of the semiconductor device 1, such as signal conversion efficiency and switching characteristics, can be improved.

[0040] It is noted that the air gap 530 can be formed, for example, by introducing an etching solution or etching vapor through the through-hole 510 and performing an etching on the first intermediate layer film 110 and the second intermediate layer film 120 using wet etching or steam etching.

[0041] In this phase, the area in which the air gap 530 is formed is limited, in the stacking direction of the multilayer wiring layer 101, to the area surrounded by the diffusion-inhibiting films 200. This is because the diffusion-inhibiting films 200 have a higher etch resistance than the interlayer films 100, and the etching process is minimal. Furthermore, the area in which the air gap 530 is formed is controlled in the plane-internal direction of the multilayer wiring layer 101 by the degree of etching. In particular, the etching solution or etching vapor introduced through the through-hole 510 distributes isotropically from directly below the through-hole 510, so that etching is carried out on the interlayer films 100. Accordingly, the area in the plane-internal direction of the air gap 530 can be controlled by the degree of etching.

[0042] It is noted that the etching of the interlayer films 100 is carried out under the condition that the etching is not performed on the contact vias 610, the through-vias 400, and the wiring leads 300. Therefore, if the contact vias 610, the through-vias 400, or the wiring leads 300 are present in the area where the air gap 530 is to be formed, these components can remain in the air gap 530 without any modification. Furthermore, if the interlayer films 100 are spatially divided by the contact vias 610, the through-vias 400, or the wiring leads 300, the entry of the etching solution or etching vapor through these components is blocked, and the area in which the air gap 530 is to be formed is limited.

[0043] If the air gap 530 is formed across several interlayer films 100, an opening is created in the diffusion-prevention films 200 within the multiple interlayer films 100. Specifically, if the air gap 530 is formed between the first interlayer film 110 and the second interlayer film 120, an opening is created in the second diffusion-prevention film 220 between the first interlayer film 110 and the second interlayer film 120. When the etching solution or etching vapor is introduced through the through-hole 510, the etching solution or etching vapor spreads from the second interlayer film 120 through the opening to the first interlayer film 110. Accordingly, the air gap 530 is formed across the multiple interlayer films 100.

[0044] In this phase, the opening in the diffusion-prevention films 200 is formed such that it protrudes into the air gap 530 and does not extend beyond the area without the hole on the wiring lines 300. Accordingly, the diffusion-prevention films 200, which protrude into the air gap 530, are prevented from collapsing after the air gap 530 has been formed.

[0045] Although Fig. Figure 1 shows a case in which only one through-hole 510 is formed; the technology according to the present disclosure is not limited to the example described above. For example, several through-holes 510 can be formed. In such a case, the several through-holes 510 can form the same air gap 530, or each of the through-holes 510 can form different air gaps 530 from one another.

[0046] In the semiconductor device 1 described above, each space between the wiring leads 300 can be made hollow with an air gap 530, and accordingly, the capacitance between the wiring leads can be reduced. Therefore, the semiconductor device 1 can achieve higher speed and lower power consumption by reducing delays in the wiring leads 300. Furthermore, in the semiconductor device 1, no diffusion-inhibiting films 200 protrude into the air gap 530. Therefore, the collapse of the diffusion-inhibiting films 200, which have low mechanical strength, is prevented. (1.2. Manufacturing process)

[0047] With reference to Fig. Sections 2A to 2G now describe a method for manufacturing the semiconductor device 1 according to this embodiment. Fig. Figures 2A to 2G are cross-sectional views, each illustrating a step in the process for manufacturing the semiconductor device 1 according to this embodiment.

[0048] First, as in Fig. Figure 2A shows the via insulation layer 600, the first diffusion barrier film 210, the first interlayer film 110, and the second diffusion barrier film 220 being sequentially stacked on a semiconductor substrate (not shown) by chemical vapor deposition (CVD). Furthermore, the contact vias 610 are formed in the via insulation layer 600, and the zeroth wiring line 620 and the first wiring lines 310 are formed in the first interlayer film 110.

[0049] In particular, the via insulation layer 600 is first formed by CVD on a (not shown) semiconductor substrate containing silicon (Si) or the like. Next, after the first diffusion inhibitor film 210 is formed by CVD on the via insulation layer 600, the via insulation layer 600 and the first diffusion inhibitor film 210 are removed by etching in predetermined areas. After a barrier metal layer, such as a titanium nitride (TiN) layer, is formed by sputtering in the openings created by the etching, tungsten (W) is buried in the openings to form the contact vias 610 and the zero-point wiring line 620.

[0050] After the first interlayer film 110 has been formed by CVD on the first diffusion-inhibiting film 210, the first interlayer film 110 is removed in predetermined areas by etching, and the resulting openings are filled with copper (Cu) or the like using a Damascene technique, thus forming the first wiring traces 310. Subsequently, the second diffusion-inhibiting film 220 is formed by CVD on the entire surface of the first interlayer film 110 and over the first wiring traces 310.

[0051] It is noted that the via insulation layer 600 and the first intermediate layer film 110 contain SiO₂ xor the like can be formed on which etching with hydrofluoric acid can be easily carried out, and the first diffusion prevention film 210 and the second diffusion prevention film 220 can be formed with SiC or the like with a high etch resistance to hydrofluoric acid.

[0052] Next, as in Fig. Figure 2B shows that a portion of the second diffusion-inhibiting film 220 is removed by a photolithographic technique or the like, creating an opening 530A. The opening 530A serves as the opening for introducing an etching solution from the second intermediate film 120 to the first intermediate film 110 during the formation of the air gap 530 in a later stage.

[0053] As in Fig. As shown in Figure 2C, the second interlayer film 120, the third diffusion-prevention film 230, the third interlayer film 130, and the fourth diffusion-prevention film 240 are sequentially stacked onto the second diffusion-prevention film 220 by CVD. Furthermore, the second wiring leads 320 and the second through-via 420 are formed in the second interlayer film 120, and the third wiring leads 330 and the third through-via 430 are formed in the third interlayer film 130.

[0054] After the second interlayer film 120 has been formed by CVD on the second diffusion-inhibiting film 220, the second interlayer film 120 is removed in predetermined areas by etching, and the resulting openings are filled with copper (Cu) or the like using a damascene technique, thus forming the second wiring leads 320 and the second through-via 420. Similarly, the third diffusion-inhibiting film 230 and the third interlayer film 130 are formed by CVD on the second wiring leads 320 and the second interlayer film 120. The third interlayer film 130 is then removed in predetermined areas by etching, and the resulting openings are filled with copper (Cu) or the like using a damascene technique, thus forming the third wiring leads 330 and the third through-via 430.The fourth diffusion prevention film 240 is then formed by CVD on the third wiring lines 330 and the third intermediate layer film 130.

[0055] It is noted that the second interlayer film contains 120 and the third interlayer film contains 130 SiO₂. x or the like can be formed on which etching with hydrofluoric acid can be easily carried out, and the third diffusion prevention film 230 and the fourth diffusion prevention film 240 can be formed with SiC or the like with a high etch resistance to hydrofluoric acid.

[0056] Next, as in Fig. As shown in 2D, the fourth diffusion-inhibiting film 240 and the third interlayer film 130 are removed in a region by etching or the like, so that the through-hole 510 is formed to expose the third diffusion-inhibiting film 230. It is noted that the region in which the through-hole 510 is formed is, for example, the region in which the second wiring lines 320 and the third wiring lines 330 are not formed. The planar shape of the opening of the through-hole 510 can, for example, be a square with a side length of 50 nm to 300 nm. It is noted that, of course, multiple through-holes 510 can be formed.

[0057] As in Fig. As shown in Figure 2E, a protective film 520A is then formed by atomic layer deposition (ALD) on the fourth diffusion-inhibiting film 240 and on the side surface in the through-hole 510. The protective film 520A can be formed with SiC or the like, which exhibits high etch resistance to hydrofluoric acid and is capable of ensuring, for example, sufficient etch selectivity with respect to the intermediate films 100. The protective film 520A can have a thickness of 5 nm to 30 nm. It is noted that the protective film 520A formed by ALD is uniformly (conformally) formed on the fourth diffusion-inhibiting film 240 and on the side surface in the through-hole 510.

[0058] Next, as in Fig. 2F shows that a back-etching was carried out on the entire surface of the protective film 520A, so that the protective film 520A, which is formed on the fourth diffusion prevention film 240 and the third diffusion prevention film 230, is removed, and the fourth diffusion prevention film 240 and the second intermediate layer film 120 are exposed.

[0059] The full-surface back-etch is a high-perpendicular anisotropy etching process used to remove the protective film 520A formed on the fourth diffusion-inhibiting film 240 and the third diffusion-inhibiting film 230, while retaining the protective film 520A formed inside the through-hole 510. As a result, the protective sidewall 520 is formed, covering the inner surface of the through-hole 510. If the fourth diffusion-inhibiting film 240 forms on the third intermediate layer film 130, the protective sidewall 520 can be formed without causing any damage to the third intermediate layer film 130 through the full-surface back-etch.

[0060] As in Fig. As shown in Figure 2G, the etching is then carried out by introducing a solution or vapor of dilute hydrofluoric acid through the through-hole 510 into the second interlayer film 120 and the first interlayer film 110. Accordingly, the air gap 530 is formed.

[0061] Since the protective sidewall 520 and the first to fourth diffusion-prevention films 210, 220, 230, and 240 are formed with SiC or the like, exhibiting high resistance to hydrofluoric acid, etching barely progresses in this phase. Furthermore, the contact vias 610, the zero-level wiring line 620, the first and second wiring lines 310 and 320, and the second through-via 420 are formed with a metallic material, such as copper (Cu) or tungsten (W), and also exhibit high resistance to hydrofluoric acid. Accordingly, etching barely progresses. Therefore, only the first interlayer film 110 and the second interlayer film 120 can be removed by etching, and the air gap 530 can be formed.

[0062] Therefore, the area in which the air gap 530 is to be formed is limited, in the stacking direction of the semiconductor device 1, to the area sandwiched between the first diffusion-prevention film 220 and the third diffusion-prevention film 230. Furthermore, the area in which the air gap 530 is to be formed is controlled, in the in-plane direction of the semiconductor device 1, by the etching extent. However, if the contact vias 610, the zero-level wiring line 620, the first and second wiring lines 310 and 320, and the second through-via 420 are formed like walls surrounding a predetermined area, the area in which the air gap 530 is to be formed can be limited to the predetermined area surrounded by these components. In this way, the semiconductor device 1 can have the air gap 530, which is formed only in the area where the capacitance between wiring leads is to be reduced.

[0063] It is noted that the second diffusion-prevention film 220 is formed in the region that has its end in a region containing a first wiring line 310, and does not protrude into the air gap 530. Accordingly, in the semiconductor device 1, it is possible to prevent the second diffusion-prevention film 220 from collapsing after the air gap 530 has been formed.

[0064] The semiconductor device 1 can be manufactured according to this embodiment by the above steps. It is noted that, in order to prevent the ingress of moisture and the like into the air gap 530, a sealing layer formed with an insulating material can be formed on the fourth diffusion-prevention film 240 near the opening of the through-hole 510.

[0065] In the manufacturing process described above, hydrofluoric acid is used during etching, and the interlayer films are 100 with SiO₂. x The diffusion-inhibiting films 200 are formed from a material that readily accepts hydrofluoric acid etching, and they are formed from SiC, which exhibits higher etch resistance to hydrofluoric acid. However, the technology according to the present disclosure is not limited to the example described above. The combination of materials to be used for the interlayer films 100 and the diffusion-inhibiting films 200 can be any suitable combination, as long as sufficient etch selectivity with respect to the diffusion-inhibiting films 200 can be ensured for the interlayer films 100. (1.3. Modifications)

[0066] Next, modifications of the semiconductor device 1 according to this embodiment will be described with reference to Fig. 3, Fig. 4, Fig. 5 to Fig. 6 described. Fig. Figure 3 is a cross-sectional view of a semiconductor device 11 according to a first modification in the stacking direction. Fig. Figure 4 is a cross-sectional view of a semiconductor device 12 according to a second modification in the stacking direction. Fig. Figures 5A to 5C are cross-sectional views of semiconductor devices 13A to 13C according to a third modification in the stacking direction. Fig. Figure 6 is a cross-sectional view of a semiconductor device 14 according to a fourth modification in the stacking direction. It is noted that Fig. 3, Fig. 4, Fig. 5 to Fig. Figure 6 shows a portion of a cross-section of a semiconductor device, and the semiconductor device naturally extends into areas not shown in the drawings. (First modification)

[0067] As in Fig. As shown in Figure 3, a protective film 540 can be formed on the surface of the semiconductor device 11 according to the first modification, which is exposed by the air gap 530. In particular, the protective film 540 can be formed on the respective surfaces of the contact vias 610, the zero-point wiring line 620, the interlayer films 100, the diffusion-prevention films 200, the wiring lines 300, and the through-vias 400, which are exposed by the air gap 530. It is noted that the other components are the same as those referred to in Figure 3. Fig. They are described in point 1, and therefore no explanation of them is given here.

[0068] The protective film 540, for example, is formed with any suitable insulating material and can be combined with an insulating material such as SiO₂. x , SiN x , SiCN, SiON, SiOC or SiC, can be formed. The thickness of the protective film 540 can be, for example, 2 nm to 50 nm. The protective film 540 can improve wiring reliability by preventing electromigration or time-dependent dielectric breakdown (TDDB) in the wiring leads 300 and the through-passages 400. It is possible to form such a protective film 540, for example, by introducing a source gas through the through-hole 510 into the air gap 530 and passing an ALD through it. (Second modification)

[0069] Next, as in Fig. As shown in Figure 4, in the semiconductor device 12 according to the second modification, the interlayer films 100 can be formed with several different materials. In particular, the via insulation layer 600, the first interlayer film 110, and the second interlayer film 120 can be formed with a first material, and a third interlayer film 131 can be formed with a second material different from the first. For example, the via insulation layer 600, the first interlayer film 110, and the second interlayer film 120 can be formed with a first material such as SiO₂. x , can be formed, and the third interlayer film 131 can be combined with a second material having a lower relative dielectric constant than SiO xof the first material (this second material is a so-called low-k material as described above). It is noted that the other components are the same as those described with reference to Fig. They are described in point 1, and therefore no explanation of them is given here.

[0070] The air gap 530 is formed in the interlayer films 100, which are formed with the first material having a higher relative dielectric constant than the second material, so that the parasitic capacitance formed between the wiring leads 300 can be effectively reduced. However, it is self-evident that the air gap 530 in the interlayer film(s) 100 can also be formed with a second material having a higher relative dielectric constant than the first material.

[0071] Furthermore, if a combination of the first and second materials is selected such that the etch selectivity of the first material is higher with respect to the second material (the so-called low-k material described above), the air gap 530 can be formed even if the protective sidewall 520 is not formed. In particular, since no etching is carried out on the third intermediate layer film 131, which is formed with the second material, during the etching to form the air gap 530, it becomes possible to form the air gap 530 without forming the protective sidewall 520. (Third modification)

[0072] Next, as in Fig. 5A to 5C shown, in the semiconductor devices 13A to 13C according to the third modification, four or more interlayer films 100 and four or more diffusion prevention films 200 are stacked and the air gap 530 can be formed in one to three interlayer films 100.

[0073] Here, a fourth intermediate layer film 140 can be formed with a material similar to that of the first to third intermediate layer films 110, 120, and 130. A fifth diffusion-prevention film 250 can be formed with a material similar to that of the first to fourth diffusion-prevention films 210, 220, 230, and 240. Fourth wiring lines 340 can be formed with a material similar to that of the first to third wiring lines 310, 320, and 330. A fourth through-via 440 can be formed with a material similar to that of the second and third through-vias 420 and 430. Furthermore, the other components are the same as those referred to in Fig. As described in point 1, and therefore no explanation from them is given here.

[0074] As in Fig. As shown in Figure 5A, the air gap 530 can be formed in a single interlayer film 100. In particular, the air gap 530 can be formed in the first interlayer film 110. In such a case, the through-hole 510 is formed such that it penetrates the second to fifth diffusion-prevention films 220, 230, 240 and 250 and the second to fourth interlayer films 120, 130 and 140.

[0075] Alternatively, as in Fig. As shown in Figure 5B, the air gap 530 is formed in two intermediate layer films 100. In particular, the air gap 530 can be formed in the first intermediate layer film 110 and the second intermediate layer film 120. In such a case, the through-hole 510 is formed such that it penetrates the third to fifth diffusion-prevention films 230, 240 and 250 and the third and fourth intermediate layer films 130 and 140.

[0076] Furthermore, as in Fig. As shown in Figure 5C, the air gap 530 can be formed in three intermediate layer films 100. In particular, the air gap 530 can be formed in the first intermediate layer film 110, the second intermediate layer film 120, and the third intermediate layer film 130. In such a case, the through-hole 510 is formed such that it penetrates the fourth and fifth diffusion-prevention films 240 and 250 and the fourth intermediate layer film 140.

[0077] However, in each case, with semiconductor devices 13A to 13C according to this modification, the air gap 530 is formed at least in the first interlayer film 110 to expose the contact vias 610 and the zero-point wiring line 620. With this configuration, semiconductor devices 13A to 13C can reduce the capacitance between the wiring lines in the area near the semiconductor substrate on which transistors and the like are formed. Accordingly, the basic performance of the semiconductor device 1, such as signal conversion efficiency and switching characteristics, can be improved.

[0078] It is noted that the number of stacked layers, which are the interlayer films 100 and the diffusion-prevention films 200, in the semiconductor device 1 according to this embodiment is not limited to a specific number. That is, the multilayer wiring layer 101 can be formed by stacking six or more interlayer films 100 and six or more diffusion-prevention films 200. The greater the number of interlayer films 100 in which the air gap 530 is formed, the more the capacitance between wiring leads in the entire semiconductor device 1 can be reduced. Conversely, the smaller the number of interlayer films 100 in which the air gap 530 is formed, the more the mechanical strength in the entire semiconductor device 1 can be maintained.Therefore, the number of interlayer films 100 in which the air gap 530 is to be formed can be adjusted if necessary, taking into account the balance between the interwire capacitance and the mechanical strength. (Fourth modification)

[0079] Furthermore, as in Fig. Figure 6 shows that in the semiconductor device 14 according to the fourth modification, a diffusion-inhibiting film 211 is formed in the first interlayer film 110. In particular, the diffusion-inhibiting film 211 can also be formed between the first wiring lines 310 and the contact vias 610 in the first interlayer film 110.

[0080] It is noted that the diffusion-inhibiting film 211 can be formed with a material similar to that of the first to fourth diffusion-inhibiting films 210, 220, 230 and 240. Furthermore, the other components are the same as those referred to in Fig. As described in point 1, and therefore no explanation from them is given here.

[0081] In this configuration, the area in which the air gap 530 is to be formed can be controlled more precisely using the diffusion-prevention film 211. For example, it is possible to change the planar area in which the air gap 530 is to be formed between the first wiring leads 310 and the contact vias 610. <2. Second embodiment>(2.1. Example configuration)

[0082] Now, with reference to Fig. 7 describes the configuration of a semiconductor device 2 according to a second embodiment of the present disclosure. Fig. Figure 7 is a cross-sectional view of a semiconductor device according to this embodiment in the stacking direction. It is noted that Fig. Figure 7 shows a part of a cross-section of the semiconductor device 2 according to this embodiment, and the semiconductor device 2 naturally extends into areas not shown in the drawing.

[0083] As in Fig. As shown in Figure 7, in the semiconductor device 2 a multilayer wiring layer 101, in which insulating films 100 and diffusion prevention films 200 are stacked alternately, lies between a pair of substrates 710 and 720 and a via hole 510 is formed to create the substrate 710 and a via insulating layer 600.

[0084] Here, a fourth intermediate layer film 140 can be formed with a material similar to that of the first to third intermediate layer films 110, 120, and 130. Furthermore, the other components are the same as those referred to in Fig. As described in point 1, and therefore no explanation from them is given here.

[0085] In the semiconductor device 2 according to this embodiment, the multilayer wiring layer 101, in which the interlayer films 100 and the diffusion prevention films 200 are stacked alternately, is located between the pair of substrates 710 and 720, so that the mechanical strength of the entire semiconductor device 2 can be increased.

[0086] Substrate 710 is a semiconductor substrate and can, for example, be a silicon (Si) substrate. Specifically, substrate 710 is a substrate in which various passive or active elements are arranged to implement the main functions of the semiconductor device 1. For example, a memory circuit, a logic circuit, an amplifier circuit, a color sensor, or the like can be arranged in substrate 710.

[0087] Any substrate made of any material can be used as substrate 720, as long as it can be joined to the multilayer wiring layer 101, in which the interlayer films 100 and the diffusion-prevention films 200 are stacked alternately. Substrate 720 can, for example, be a glass substrate such as quartz, a resin substrate such as polyimide or polyester, or a semiconductor substrate such as silicon (Si).

[0088] Furthermore, the substrates 710 and 720 can be thinned by chemical-mechanical polishing (CMP) or the like. The semiconductor device 2 according to this embodiment can maintain its overall mechanical strength even when the air gap 530 is formed. Accordingly, sufficient mechanical strength can be maintained even when the substrates 710 and 720 are thinned.

[0089] As shown in the semiconductor device 2 according to this embodiment, the through-holes 510 can be formed from any of the surfaces of the multilayer wiring layer 101, in which the interlayer films 100 and the diffusion-prevention films 200 are stacked alternately. That is, the through-hole 510 can be formed from the side of the fourth interlayer film 140 or from the side of the first interlayer film 110 (which is the side of the via insulation layer 600). In both cases, in the semiconductor device 2, the air gap 530, which exposes the contact vias 610 or the zero-point wiring line 620, can be formed in the multilayer wiring layer 101 via the through-hole 510, as in the first embodiment. (2.2. Manufacturing process)

[0090] Now, with reference to Fig. Sections 8A to 8E describe a method for manufacturing the semiconductor device 2 according to this embodiment. Fig. Figures 8A to 8E are cross-sectional views, each illustrating a step in the process for manufacturing the semiconductor device 2 according to this embodiment.

[0091] First, as in Fig. Figure 8A shows the via insulation layer 600, the first diffusion prevention film 210, the first interlayer film 110, and the second diffusion prevention film 220 being sequentially stacked by CVD. Furthermore, the contact vias 610 are formed in the via insulation layer 600, and the zeroth wiring line 620 and the first wiring lines 310 are formed in the first interlayer film 110.

[0092] In particular, the via insulation layer 600 is first formed by CVD. Next, after the first diffusion inhibitor film 210 is formed on the via insulation layer 600 by CVD, the via insulation layer 600 and the first diffusion inhibitor film 210 are removed by etching in predetermined areas. A barrier metal layer, such as a titanium nitride (TiN) layer, is then formed by sputtering in the openings created by the etching, and tungsten (W) is subsequently buried in the openings to form the contact vias 610 and the zero-point wiring conductor 620.

[0093] After the first interlayer film 110 has been formed by CVD on the first diffusion-inhibiting film 210, the first interlayer film 110 is removed in predetermined areas by etching, and the resulting openings are filled with copper (Cu) or the like using a Damascene technique, thus forming the first wiring traces 310. Subsequently, the second diffusion-inhibiting film 220 is formed by CVD on the entire surfaces of the first interlayer film 110 and the first wiring traces 310.

[0094] It is noted that the via insulation layer 600 and the first intermediate layer film 110 contain SiO₂ x or the like can be formed on which etching with hydrofluoric acid can be easily carried out, and the first diffusion prevention film 210 and the second diffusion prevention film 220 can be formed with SiC or the like with a high etch resistance to hydrofluoric acid.

[0095] Next, as in Fig. Figure 8B shows that a portion of the second diffusion-inhibiting film 220 is removed by a photolithographic technique or the like, so that an opening 530A is formed. The opening 530A serves as the opening for introducing an etching solution from the second intermediate film 120 to the first intermediate film 110 in the process of forming the air gap 530 in a later stage.

[0096] As in Fig. As shown in Figure 8C, the second interlayer film 120, the third diffusion-prevention film 230, the third interlayer film 130, and the fourth diffusion-prevention film 240 are sequentially stacked onto the second diffusion-prevention film 220 by CVD. Furthermore, the second wiring leads 320 and the second through-via 420 are formed in the second interlayer film 120, and the third wiring leads 330 and the third through-via 430 are formed in the third interlayer film 130.

[0097] After the second interlayer film 120 has been formed by CVD on the second diffusion-inhibiting film 220, the second interlayer film 120 is removed in predetermined areas by etching, and the resulting openings are filled with copper (Cu) or the like using a damascene technique, thus forming the second wiring leads 320 and the second through-via 420. Similarly, the third diffusion-inhibiting film 230 and the third interlayer film 130 are formed by CVD on the second wiring leads 320 and the second interlayer film 120. The third interlayer film 130 is then removed in predetermined areas by etching, and the resulting openings are filled with copper (Cu) or the like using a damascene technique, thus forming the third wiring leads 330 and the third through-via 430.The fourth diffusion prevention film 240 is then formed by CVD on the third wiring lines 330 and the third intermediate layer film 130.

[0098] It is noted that the second interlayer film contains 120 and the third interlayer film contains 130 SiO₂. x or the like can be formed on which etching with hydrofluoric acid can be easily carried out, and the third diffusion prevention film 230 and the fourth diffusion prevention film 240 can be formed with SiC or the like with a high etch resistance to hydrofluoric acid.

[0099] Next, as in Fig. Figure 8D shows that after the fourth interlayer film 140 is stacked onto the fourth diffusion-prevention film 240 by CVD, the substrate 720 is connected to the surface of the fourth interlayer film 140, and the substrate 710 is also connected to the side of the via insulation layer 600. As a result, the multilayer wiring layer 101 is located between the substrates 710 and 720. Subsequently, the through-hole 510 and the protective film 521 are formed on the side of the substrate 710.

[0100] The fourth interlayer film 140 can be used with SiO xor the like, on which etching with hydrofluoric acid is easily carried out. The fifth diffusion-inhibiting film 250 can be formed with SiC or the like, exhibiting high etch resistance to hydrofluoric acid. Furthermore, substrates 710 and 720 can be silicon(Si) substrates. Substrates 710 and 720 can be thinned with CMP or the like after the multilayer wiring layer 101 has been joined to them.

[0101] The through-hole 510 is formed by etching away certain areas of the substrate 710 and the via insulation layer 600. Furthermore, the protective film 520A is uniformly (conformally) formed on the substrate 710 and within the through-hole 510 by ALD. It is noted that the planar shape of the opening of the through-hole 510 can be a square with a side length of 50 nm to 300 nm. The protective film 520A can be formed with SiC or similar materials with high etch resistance to hydrofluoric acid and is designed to have, for example, a thickness of 5 nm to 30 nm.

[0102] Next, as in Fig. Figure 8E shows that a back-etch is performed on the entire surface to remove the protective film 520A on the substrate 710 and the protective film 520A and the first diffusion-prevention film 210 on the first interlayer film 110. An etching solution or vapor is then introduced through the through-hole 510, thus etching the first interlayer film 110 and the second interlayer film 120 to form the air gap 530. It is noted that the back-etch can be performed on the entire surface, for example, by performing a high perpendicular anisotropy etch.

[0103] Here, etching of the first interlayer film 110 and the second interlayer film 120 can be carried out by wet etching or steam etching using dilute hydrofluoric acid. Since the protective sidewall 520 and the first to third diffusion-prevention films 210, 220, and 230 are formed with SiC or the like, which has high etch resistance to hydrofluoric acid, etching in this phase hardly progresses. Furthermore, the contact vias 610, the zero-point wiring line 620, the first wiring lines 310, the second wiring lines 320, and a first through-via 410 are formed with a metallic material, such as copper (Cu) or tungsten (W), and exhibit high etch resistance to hydrofluoric acid. Accordingly, etching in these areas hardly progresses.With this arrangement in the semiconductor device 2, selective etching can be carried out on the first interlayer film 110 and the second interlayer film 120 to form the air gap 530.

[0104] The semiconductor device 2 can be manufactured according to this embodiment by the above steps. It is noted that, in order to prevent the ingress of moisture and the like into the air gap 530, a sealing layer formed with an insulating material can be formed on the substrate 710 near the opening of the through-hole 510.

[0105] By the method for manufacturing the semiconductor device 2 according to this embodiment, the air gap 530 can be formed after the substrates 710 and 720 have been thinned by CMP. Accordingly, the semiconductor device 2 can reduce the formation of cracks and the like due to the air gap 530 in the CMP step in which a mechanical load is applied to the semiconductor device 2. (2.3. Modification)

[0106] Furthermore, a modification of the semiconductor device 2 according to this embodiment is described with reference to Fig. 9 described. Fig. Figure 9 is a cross-sectional view of a semiconductor device 21 according to this modification in the stacking direction. It is noted that Fig. Figure 9 shows part of a cross-section of the semiconductor device, and the semiconductor device naturally extends into areas not shown in the drawing.

[0107] As in Fig. As shown in Figure 9, in the semiconductor device 21 according to this modification, the interlayer films 100 can be formed with several different materials. In particular, the via insulation layer 600 and part of the first interlayer film 110 are formed with a first material, and the remaining part 111 of the first interlayer film, a second interlayer film 121, and a third interlayer film 131 are formed with a second material different from the first material. For example, the via insulation layer 600 and part of the first interlayer film 110 can be formed with a first material such as SiO₂. x , can be formed, and the remaining part 111 of the first interlayer film, the second interlayer film 121 and the third interlayer film 131 can be combined with a second material having a lower relative dielectric constant than SiO xof the first material (this second material is a so-called low-k material as described above). It is noted that the other components are the same as those described with reference to Fig. The 7 described above are therefore not explained here.

[0108] The air gap 530 is formed in the interlayer films 100, which are formed with the first material having a higher relative dielectric constant than the second material, so that the capacitance between the wiring leads 300 can be effectively reduced. However, it is self-evident that the air gap 530 in the interlayer film(s) 100 can also be formed with a second material having a higher relative dielectric constant than the first material.

[0109] Furthermore, if a combination of the first and second materials is selected such that the etch selectivity of the first material is higher with respect to the second material, the air gap 530 can be formed only in the interlayer film(s) 100 formed with the first material. In particular, the air gap 530 can be formed by etching only in that part of the first interlayer film 110 that is formed with the first material. In such a case, the region in which the air gap 530 is to be formed can be more easily controlled in the semiconductor device 21. <3. Third embodiment>

[0110] Now, with reference to Fig. Sections 10 to 13C describe the configuration of a semiconductor device 3 according to a third embodiment of the present disclosure. Fig. Figure 10 is a cross-sectional view of a semiconductor device according to this embodiment in the stacking direction.

[0111] As in Fig. As shown in Figure 10, the semiconductor device 3 is a stacked solid-state imaging device formed by stacking a first substrate 1100 and a second substrate 1200. The dashed line in Fig. 10 indicates the bonding plane between the first substrate 1100 and the second substrate 1200.

[0112] The first substrate 1100 is a pixel substrate in which a pixel unit is arranged, and the second substrate 1200 is a logic substrate in which, for example, circuits for performing various types of signal processing with respect to the operation of the semiconductor device 3 are arranged. The semiconductor device 3 photoelectrically converts light entering the pixel unit from a surface of the first substrate 1100 and converts the photoelectrically converted signal charges into pixel signals in the second substrate 1200. The semiconductor device 3 can be a so-called back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor.

[0113] The first substrate 1100 is primarily formed with a semiconductor substrate 1170, which contains, for example, silicon (Si), and a multilayer interconnect layer 1101 formed on the semiconductor substrate 1170. A pixel unit, in which pixels are arranged in a predetermined array, and a pixel signal processing circuit for processing pixel signals are arranged in the semiconductor substrate 1170. A pixel primarily consists of a photodiode (PD), which receives light (observation light) from an observation target and performs a photoelectric conversion, and a drive circuit, which includes a transistor and the like, for reading a pixel signal corresponding to the observation light detected by the PD. In the pixel signal processing circuit, various types of signal processing, such as analog-to-digital conversion (AD conversion), are performed on the read pixel signal.

[0114] The interlayer films 1110 and the diffusion-prevention films 1120 are stacked alternately on a surface of the semiconductor substrate 1170, in which the pixel unit and the pixel signal processing circuit are formed. The wiring lines 1130 for transmitting various types of signals, such as a control signal for driving the transistor of a control circuit and a pixel signal, are formed in the interlayer films 1110. In this way, the multilayer wiring layer 1101 is formed. The wiring lines in the lowest layer (the layer closest to the side of the semiconductor substrate 1170) of the multilayer wiring layer 1101 are electrically connected by contact vias 1160, formed for example with tungsten (W) or the like, to electrodes 1180 or the like, which extract signals from the pixel unit or the pixel signal processing circuit.In the semiconductor device 3 according to this embodiment, air gaps 1153 and through holes 1151 are formed to create the air gaps 1153 in the areas to which the contact vias 1160 are exposed.

[0115] The second substrate 1200 is primarily formed with a semiconductor substrate 1270, which, for example, contains silicon, and a multilayer wiring layer 1201 formed on the semiconductor substrate 1270. A logic circuit, which performs various types of signal processing with respect to the operation of the semiconductor device 3, is formed in the semiconductor substrate 1270. For example, the logic circuit can perform control of a control signal for driving the pixel unit of the first substrate 1100 (which is a control of the pixel unit) and control of a signal exchange with the outside.

[0116] The interlayer films 1210 and the diffusion-inhibiting films 1220 are stacked alternately on a surface of the semiconductor substrate 1270, in which the logic circuit is formed. The wiring layers 1230 for transmitting various types of signals related to the operation of the logic circuit are formed in the interlayer films 1210. In this way, the multilayer wiring layer 1201 is formed. The wiring lines in the bottom layer (the layer closest to the side of the semiconductor substrate 1270) of the multilayer wiring layer 1201 are electrically connected by contact vias 1260, formed, for example, with tungsten (W) or the like, to electrodes 1280 or the like, which extract signals from the logic circuit.

[0117] It is noted that pads 1290, which function as external input / output (I / O) units for exchanging various types of signals with the outside world, can be formed in the multilayer wiring layer 1201. The pads 1290 can be formed, for example, with aluminum (Al) or similar materials.

[0118] Here, electrodes are formed in the top layer (the layer furthest from the semiconductor substrate 1170) of the multilayer wiring layer 1101, so that a metal surface is exposed through the interlayer films 1110. Electrodes are also formed in the top layer (the layer furthest from the semiconductor substrate 1270) of the multilayer wiring layer 1201, so that a metal surface is exposed in a similar manner through the interlayer films 1210. These electrodes form an electrode union structure 1340 for electrically connecting signal lines, ground lines, and power supply lines formed in the respective substrates when the first substrate 1100 and the second substrate 1200 are bonded together.

[0119] In such a stacked structure consisting of the first substrate 1100 and the second substrate 1200, a color filter layer 1310 and a microlens array 1330 are arranged via an insulating film or the like on the other surface of the semiconductor substrate 1170 on the opposite side from the surface on which the multilayer wiring layer 1101 is arranged.

[0120] The color filter layer 1310 is formed with several color filters arranged to correspond to pixels. The microlens array 1330 is formed with several microlenses arranged to correspond to pixels. The color filter layer 1310 and the microlens array 1330 are formed immediately above the pixel unit, and one color filter and one microlens are provided for the PD of a pixel. It is noted that the pixels are separated from each other by a light-blocking pixel definition film 1320.

[0121] Each color filter in the 1310 color filter layer, for example, has a red, green, or blue color. Observation light passing through a color filter enters the photodiode of the pixel, and a pixel signal is detected. Accordingly, pixel signals of the respective color components of the observation target are detected. It should be noted that a pixel corresponding to a color filter can function as a subpixel, and a pixel can be formed from multiple subpixels. For example, four color subpixels—a red pixel with a red color filter, a green pixel with a green color filter, a blue pixel with a blue color filter, and a white pixel without a color filter—can form a single pixel.

[0122] The microlens array 1330 is configured such that the individual microlenses are located directly above the respective color filters. When the microlens array 1330 is deployed, the observation light collected by the microlenses passes through the color filters and into the photodiodes of the pixels. Accordingly, the microlens array 1330 can improve the light-gathering efficiency of the observation light and increase the sensitivity of the solid-state imaging device.

[0123] Now, with reference to Fig. Sections 11 to 13C describe special positions where the air gaps 1153 are formed in the semiconductor device 3, which is a solid-state imaging device as described above. Fig. 11 and Fig. Figure 12 are schematic diagrams showing the stacking structures formed with the respective wiring leads of the semiconductor device 3, which is a solid-state imaging device. It is noted that in Fig. 11 and Fig. 12 the opposite side of the drawing is the side of the semiconductor substrate 1170 and the one in Fig. 12 planar configurations shown on the in Fig. It is arranged in the planar configuration shown in 11.

[0124] Furthermore, Fig. 13A a cross-sectional view showing a cross-section along the in Fig. Line A-AA is shown in section 11. Fig. 13B is a cross-sectional view showing a cross-section along the Fig. Line B-BB is shown in section 11. Fig. 13C is a cross-sectional view showing a cross-section along the in Fig. Line C-CC is shown in section 12.

[0125] As in Fig. As shown in Figure 11, a photodiode PD is provided for each pixel in the semiconductor substrate 1170. A gain transistor AMP, a selection transistor SEL, and a (not shown) reset transistor are also provided for each predetermined number of pixels in the semiconductor substrate 1170, and the signal charges, which are photoelectrically converted by the photodiodes PD, are converted into pixel signals.

[0126] In particular, a transfer gate 3080 is arranged on each photodiode PD. The transfer gate 3080 transfers the signal charge, which is photoelectrically converted by the photodiode PD, to a floating diffusion (FD) region 3083. The signal charge transferred to the floating diffusion (FD) region 3083 is further transferred to an FD wiring line 3033 and controls the gate voltage of the gain transistor AMP in a later stage. It is noted that the transfer gate 3080 acts as the gate electrode of a vertical transistor, and the turning on and off of the transfer gate 3080 is controlled by a TG control line 3032 via a via 3061, a wiring line 3031, and a via 3062.

[0127] The amplification transistor AMP includes a gate electrode 3081, whose on and off states are controlled by the signal charge accumulated in the FD wiring line 3033. The amplification transistor AMP converts the signal charge stored in the FD wiring line 3033 into a current that flows between the source and the drain. The converted current is distributed, for example, via a wiring line 3034, a via 3064, a wiring line 3035, and a via 3065 to a vertical signal line or a power supply line 3036, which is connected to Fig. 12 is shown, transferred.

[0128] The selection transistor SEL includes a gate electrode 3082, whose on and off states are controlled by a signal from a signal line to select each pixel. The selection transistor SEL is connected in series with the gain transistor AMP and controls the current flowing between the source and drain of the gain transistor AMP. The signal for the gate electrode 3082 of the selection transistor SEL is transmitted, for example, via a wiring line 3038, a via 3067, a wiring line 3037, and a via 3066.

[0129] Here, as in Fig. As shown in Figure 13A, the air gap 1153 is formed around the FD wiring line 3033, to which the signal charge is transferred and photoelectrically converted by the photodiode PD. In such a case, the air gap 1153 can also be formed around the via 3061, which controls the on and off states of the transfer gate 3080. If the air gap 1153 is formed in such a region, the inter-wire capacitance of the FD wiring line 3033 is reduced, and consequently, the semiconductor device 3 can increase the conversion efficiency when converting signal charges into pixel signals.

[0130] Furthermore, as in Fig. Figure 13B shows that the air gap 1153 is formed around the TG control line 3032, which controls the on and off states of the transfer gate 3080. When each air gap 1153 is formed in such a region, the inter-wire capacitance of the TG control line 3032 is reduced, and accordingly, the semiconductor device 3 can increase the rate of an analog signal transmission.

[0131] Furthermore, as in Fig. Figure 13C shows that the air gap 1153 is formed around the vertical signal line or the power supply line 3036, which is connected to the respective pixels. When the air gap 1153 is formed in such areas, the inter-wire capacitance of the vertical signal line or the power supply line 3036 is reduced, and accordingly, the semiconductor device 3 can increase the rate of an analog signal transmission.

[0132] It is noted that the air gaps 1153 are formed at least in the regions that expose the contact vias, which electrically connect to the semiconductor substrate 1170 or to the electrodes arranged on the semiconductor substrate 1170. At this stage, the contact vias exposed opposite the air gaps 1153 can be multiple contact vias for transmitting the same signal. That is, the contact vias can include dummy contact vias provided for redundancy. Since the regions where the air gaps 1153 are formed have lower mechanical strength than the other regions, a greater number of contact vias can be arranged in such regions than in the other regions, so that the contact vias act as support elements, bolstering spaces between layers.Examples of such areas include, for example, the areas around the FD wiring lines 3033, the areas connected to the transfer gates 3080, and the like. <4. Example Applications>(4.1. First Application)

[0133] The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgical system.

[0134] Fig. Figure 14 is a diagram schematically showing an example configuration of an endoscopic surgical system to which the technology (the present technology) can be applied according to the present disclosure.

[0135] Fig. Figure 15 shows a situation in which a surgeon (doctor) 11131 performs an operation on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the drawing, the endoscopic surgical system 11000 includes an endoscope 11100 and other surgical instruments 11110, such as a pneumoperitoneum tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various types of devices for an endoscopic operation are mounted.

[0136] The endoscope 11100 includes a lens tube 11101, which has a section of predetermined length from its upper end that is to be inserted into a body cavity of the patient 11132, and a camera head 11102, which is connected to the base end of the lens tube 11101. In the example shown in the drawing, the endoscope 11100 is designed as a so-called rigid endoscope with a rigid lens tube 11101. However, the endoscope 11100 can also be designed as a so-called flexible endoscope with a flexible lens tube.

[0137] An opening is provided at the upper end of the lens tube 11101, into which an objective lens is inserted. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the upper end of the lens tube by a light guide extending inside the lens tube 11101 and is emitted by the objective lens toward the current observation target in the body cavity of the patient 11132. It should be noted that the endoscope 11100 can be a forward-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0138] An optical system and an imaging device are provided within the camera head 11102. Light reflected from the current observation target (observation light) is focused by the optical system onto the imaging device. The observation light is photoelectrically converted by the imaging device, generating an electrical signal corresponding to the observation light and an image signal corresponding to the observation image. The image signal is transmitted as RAW data to a camera control unit (CCU) 11201.

[0139] The CCU 11201 is comprised of a central processing unit (CPU), a graphics processing unit (GPU), or the like, and collectively controls the operations of the endoscope 11100 and a display unit 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and subjects the image signal to various types of image processing, such as a demosaicing process, in order to display an image based on the image signal.

[0140] The display device 11202 displays an image based on the image signal that has been subjected to image processing by the CCU 11201, under the control of the CCU 11201.

[0141] The light source device 11203 is formed with a light source, such as a light-emitting diode (LED), and supplies the endoscope 11100 with illumination light for the imaging of the surgical site or the like.

[0142] An input device 11204 is an input interface to the endoscopic surgical system 11000. The user can input various types of information and instructions into the endoscopic surgical system 11000 via the input device 11204. For example, the user can enter instructions to change imaging conditions (such as the type of illumination, magnification, and focal length) for the endoscope 11100.

[0143] A treatment tool control device 11205 controls a control unit for the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, or the like. A pneumoperitoneum device 11206 injects gas through the pneumoperitoneum tube 11111 into a body cavity of the patient 11132 to inflate the body cavity, ensuring the field of view of the endoscope 11100 and the working space for the surgeon. A recording device 11207 is a device capable of recording various types of information about the operation. A printer 11208 is a device capable of printing various types of information relating to the operation in different formats, such as text, images, graphics, and the like.

[0144] It is noted that the light source device 11203, which supplies the endoscope 11100 with illumination for imaging the surgical site, can be formed, for example, with an LED, a laser light source, or a white light source that is a combination of an LED and a laser light source. If a white light source is formed with a combination of RGB laser light sources, the output intensity and timing of each color (wavelength) can be controlled with high precision. Accordingly, the white balance of an image captured by the light source device 11203 can be adjusted. Alternatively, in this case, laser light from each of the RGB laser light sources can be emitted onto the current observation target in a time-split manner, and the imaging device of the camera head 11102 can be controlled in synchronization with the timing of the light emission.Accordingly, images corresponding to the respective RGB colors can be captured in a time-split manner. According to this method, a color image can be obtained without any color filter being provided in the imaging device.

[0145] Furthermore, the control of the light source device 11203 can also be controlled such that the intensity of the emitted light is changed at predetermined time intervals. The control of the imaging device of the camera head 11102 is synchronized with the timing of the change in light intensity, and images are captured in a time-split manner and then combined. Accordingly, a high dynamic range image can be generated that has no black areas and no white spots.

[0146] Furthermore, the light source device 11203 can also be designed to provide light of a predetermined wavelength band compatible with special-light imaging. In special-light imaging, light with a narrower band than the illumination light (or white light) emitted during normal observation is used, for example, to exploit the wavelength dependence of light absorption in body tissue. As a result, so-called narrowband imaging is performed to image a predetermined tissue, such as a blood vessel in a mucosal surface layer or the like, with high contrast. Alternatively, special-light imaging can be used to perform fluorescence imaging to obtain an image with fluorescence generated by the emission of excitation light.In fluorescence observation, excitation light is emitted to the body tissue so that the fluorescence of the tissue can be observed (autofluorescence observation). Alternatively, a reagent, such as indocyanine green (ICG), is injected locally into the body tissue, and excitation light corresponding to the fluorescence wavelength of the reagent is emitted to the tissue, allowing a fluorescence image to be obtained. The light source device 11203 can be designed to provide narrowband light and / or excitation light compatible with such specialized light observation.

[0147] Fig. Figure 15 is a block diagram that shows an example of the functional configurations of the camera head 11102 and the CCU 11201, which are in Fig. The 14 figures shown are shown.

[0148] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a communication-capable transmission cable 11400.

[0149] The lens unit 11401 is an optical system provided at the connecting part with the lens tube 11101. Observation light captured by the upper end of the lens tube 11101 is directed to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 consists of a combination of several lenses, including a zoom lens and a focusing lens.

[0150] The imaging unit 11402 can be formed with a single imaging device (a so-called single-plate type) or with multiple imaging devices (a so-called multi-plate type). If the imaging unit 11402 is a multi-plate type, for example, imaging signals corresponding to the respective RGB colors can be generated by the individual imaging devices and then combined to obtain a color image. Alternatively, the imaging unit 11402 can be designed to include a pair of imaging devices for capturing image signals for the right eye and image signals for the left eye, compatible with a three-dimensional (3D) display. When the 3D display is performed, the surgeon 11131 can more accurately determine the depth of body tissue at the surgical site.It should be noted that if the imaging unit 11402 is of a multi-plate type, several lens units 11401 are provided for the respective imaging devices.

[0151] Furthermore, the imaging unit 11402 is not necessarily provided in the camera head 11102. For example, the imaging unit 11402 can be provided directly behind the objective lens in the lens tube 11101.

[0152] The drive unit 11403 is formed with an actuator and moves the zoom lens and the focus lens of the lens unit 11401 by a certain distance along the optical axis under control by the camera head control unit 11405. With this arrangement, the magnification and the focus point of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0153] The communication unit 11404 is equipped with a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal received as RAW data from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400.

[0154] Furthermore, the communication unit 11404 also receives a control signal from the CCU 11201 to control the camera head 11102 and delivers the control signal to the camera head control unit 11405. The control signal contains information about the image acquisition conditions, such as information to specify the frame rate of captured images, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus point of captured images.

[0155] It is noted that the above imaging conditions, such as the frame rate, exposure value, magnification, and focus point, can be appropriately specified by the user or automatically set by the 11413 control unit of the CCU 11201 based on a captured image signal. In the latter case, the 11100 endoscope features an auto exposure (AE) function, an autofocus (AF) function, and an auto white balance (AWB) function.

[0156] The camera head control unit 11405 controls the operation of the camera head 11102 based on a control signal received by the CCU 11201 via the communication unit 11404.

[0157] The communication unit 11411 is formed with a communication device for transmitting and receiving various types of information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted by the camera head 11102 via the transmission cable 11400.

[0158] Furthermore, the communication unit 11411 also transmits a control signal to the camera head 11102 for controlling its operation. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0159] The image processing unit 11412 performs various types of image processing on an image signal consisting of RAW data transmitted by the camera head 11102.

[0160] The control unit 11413 performs various types of control with regard to the display of an image of the surgical area or the like, captured by the endoscope 11100, and of a captured image obtained through imaging of the surgical site or the like. For example, the control unit 11413 generates a control signal to control the operation of the camera head 11102.

[0161] Furthermore, the control unit 11413 also causes the display device 11202 to display a captured image showing the surgical site or the like, based on the image signal that has undergone image processing by the image processing unit 11412. This allows the control unit 11413 to recognize the respective objects shown in the captured image using various image recognition techniques. For example, the control unit 11413 can detect the shape, color, and other characteristics of the edges of an object shown in the captured image in order to identify the surgical instrument, such as forceps, a specific body part, bleeding, nebulization at the time of using the energy treatment instrument 11112, or the like.When the display device 11202 is caused to display the captured image, the control unit 11413 can cause the display device 11202 to overlay and display various types of surgical aid information on the image of the surgical site on the display, using the recognition result. When the surgical aid information is overlaid and displayed, and accordingly presented to the surgeon 11131, it becomes possible to reduce the surgeon's workload and enable the surgeon 11131 to proceed with the operation reliably.

[0162] The transmission cable 11400, which connects the camera head 11102 and the CCU 11201, is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable made of these.

[0163] In the example shown in the drawing, communication is carried out in a wired manner using the transmission cable 11400. However, communication between the camera head 11102 and the CCU 11201 can be carried out wirelessly.

[0164] An example of an endoscopic surgical system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can, for example, be applied to the imaging unit 11402 of the camera head 11102 and the like in the configuration described above. In particular, the semiconductor device (a solid-state imaging device) according to the third embodiment of the present disclosure can be applied to the imaging unit 11402 of the camera head 11102 and the like. When the technology according to the present disclosure is applied to the imaging unit 11402 of the camera head 11102, it is possible to obtain a clearer image of the surgical site with less noise. Accordingly, the surgeon can verify the surgical site without failure.Furthermore, since the surgical site image is obtained with lower latency, it is possible for the surgeon to perform a treatment with a sensation similar to that in a case where the surgeon touches and observes the surgical site.

[0165] It is noted that the endoscopic surgical system has been described here as an example, but the technology according to the present disclosure can be applied to, for example, a microscopic surgical system or the like. (4.2. Second Application)

[0166] The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgical system.

[0167] Fig. Figure 16 is a block diagram schematically showing an example configuration for an in vivo information acquisition system for a patient using a capsule endoscope to which the technology (the present technology) can be applied according to the present disclosure.

[0168] An in-vivo information acquisition system 10001 includes a capsule endoscope 10100 and an external control device 10200.

[0169] The capsule endoscope 10100 is swallowed by the patient during the examination. The capsule endoscope 10100 features an imaging function and a wireless communication function. Before being naturally excreted by the patient, the capsule endoscope 10100 moves within the internal organs, such as the stomach and intestines, through peristaltic movement or similar motions, sequentially acquiring images of the interior of the internal organs (these images are subsequently referred to as in vivo images) at predetermined intervals and sequentially transmitting information about the in vivo images wirelessly to the external control device 10200 outside the body.

[0170] The external control device 10200 controls the overall operation of the in-vivo information acquisition system 10001. The external control device 10200 also receives information about the in-vivo images transmitted by the capsule endoscope 10100 and generates image data for displaying the in-vivo images on a (not shown) display based on the received in-vivo information.

[0171] In this way, the in-vivo information acquisition system can capture 10001 in-vivo images showing the internal conditions of the patient's body at any suitable time until the swallowed capsule endoscope 10100 is excreted.

[0172] The configurations and functions of the 10100 capsule endoscope and the 10200 external control device are now described in more detail.

[0173] The capsule endoscope 10100 has a capsule-like housing 10101 and the housing 10101 contains a light source unit 10111, an imaging unit 10112, an image processing unit 10113, a wireless communication unit 10114, a power supply unit 10115, a power supply unit 10116 and a control unit 10117.

[0174] The light source unit 10111 is formed with a light source, such as a light-emitting diode (LED), and emits light to the imaging field of view of the imaging unit 10112.

[0175] The imaging unit 10112 comprises an imaging device and an optical system including several lenses positioned in front of the imaging device. Reflected light from the light emitted towards body tissue as the current observation target (this reflected light is hereinafter referred to as the observation light) is collected by the optical system and enters the imaging device. Within the imaging unit 10112, the observation light incident on the imaging device is photoelectrically converted, and an imaging signal corresponding to the observation light is generated. The image signal generated by the imaging unit 10112 is then supplied to the image processing unit 10113.

[0176] The image processing unit 10113 is comprised of a processor, such as a central processing unit (CPU) or a graphics processing unit (GPU), and performs various types of signal processing on the image signal generated by the imaging unit 10112. The image processing unit 10113 delivers the processed image signal as RAW data to the wireless communication unit 10114.

[0177] The wireless communication unit 10114 further performs predetermined processing, such as modulation processing, on the image signal, which is subjected to signal processing by the image processing unit 10113, and transmits the image signal to the external control device 10200 via an antenna 10114A. The wireless communication unit 10114 also receives a control signal for controlling the operation of the capsule endoscope 10100 from the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 delivers the control signal received from the external control device 10200 to the control unit 10117.

[0178] The 10115 power supply unit includes an antenna coil for power reception, a power regeneration circuit that regenerates power from the current generated in the antenna coil, a booster circuit, and similar components. Electrical power is generated in the 10115 power supply unit according to a so-called contactless charging principle.

[0179] The power supply unit 10116 is formed with a secondary battery and stores the electrical power generated by the power input unit 10115. To avoid complicating the drawing, in Fig. Figure 16 does not show an arrow or the like indicating the destination of the power supply from the power supply unit 10116. However, the electrical power stored in the power supply unit 10116 is supplied to the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the control unit 10117 and can be used to control these components.

[0180] The control unit 10117 is formed with a processor, such as a CPU, and controls the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114 and the power supply unit 10115 as appropriate according to a control signal transmitted by the external control device 10200.

[0181] The external control device 10200 comprises a processor, such as a CPU, GPU, or microcomputer, a control board, or the like, on which a processor and a storage element, such as a memory, are mounted together. The external control device 10200 controls the operation of the capsule endoscope 10100 by transmitting a control signal via an antenna 10200A to the control unit 10117 of the capsule endoscope 10100. Within the capsule endoscope 10100, the conditions for emitting light to the current observation target in the light source unit 10111 can be changed, for example, according to the control signal from the external control device 10200. Furthermore, the imaging conditions (such as the frame rate and exposure value in the imaging unit 10112) can also be changed according to the control signal from the external control device 10200.Furthermore, the contents of the processing in the image processing unit 10113 and the conditions (such as the transmission intervals and the number of images to be transmitted) for the wireless communication unit 10114 for transmitting image signals according to the control signal from the external control device 10200 can be changed.

[0182] Furthermore, the external control device 10200 also performs various types of image processing on the image signal transmitted by the capsule endoscope 10100 and generates image data for displaying a captured in-vivo image on the display device. Examples of image processing include various types of signal processing, such as a development process (a demosaicing process), an image quality enhancement process (a band enhancement process, a super-resolution process, a noise reduction (NR) process, a camera shake correction process, and / or the like), and / or a magnification process (an electronic zoom process). The external control device 10200 controls the operation of the display device to cause it to display a captured in-vivo image based on the generated image data.Alternatively, the external control device 10200 can cause a recording device (not shown) to record the generated image data, or cause a printing device (not shown) to print the generated image data.

[0183] An example of an in vivo information acquisition system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 10112 in the configuration described above. In particular, the semiconductor device (a solid-state imaging device) according to the third embodiment of the present disclosure can be applied to the imaging unit 10112 and the like. When the technology according to the present disclosure is applied to the imaging unit 10112, a clearer surgical site image can be obtained, and consequently, the accuracy of an examination is increased. (4.3. Third Application)

[0184] The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device mounted on any type of moving object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an aircraft, a drone, a ship, and a robot.

[0185] Fig. Figure 17 is a block diagram that schematically illustrates an example configuration of a vehicle control system, which is an example of a motion object control system to which the technology according to the present disclosure can be applied.

[0186] A vehicle control system 12000 comprises several electronic control units connected via a communication network 12001. In the case of the Fig. In the example shown, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal vehicle information detection unit 12040, and an overall control unit 12050. Furthermore, a microcomputer 12051, an audio / video output unit 12052, and an internal vehicle network interface (SST) 12053 are also shown as functional components of the overall control unit 12050.

[0187] The 12010 vehicle system control unit controls the processes of the devices related to the vehicle's driving system according to various programs. For example, the 12010 vehicle system control unit functions as control devices such as a drive power generation device to generate driving force for the vehicle, such as an internal combustion engine or a drive motor, a drive power transmission mechanism to transfer the driving force to the wheels, a steering mechanism to adjust the vehicle's steering angle, and a braking device to generate braking force for the vehicle.

[0188] The 12020 body control unit (BCU) controls the operations of various devices mounted on the vehicle body according to different programs. For example, the 12020 BCU functions as a keyless entry system, a smart key system, an electric window regulator, or a control unit for various lights, such as headlights, taillights, brake lights, turn signals, fog lights, and the like. In this case, the 12020 BCU can receive radio waves transmitted by a portable device that replaces a key or signals from various switches. The 12020 BCU receives these radio wave or signal inputs and controls the door locking mechanism, the electric window regulator, the lights, and the like of the vehicle.

[0189] The external information detection unit 12030 detects information outside the vehicle, which is equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle's exterior and receives the captured image. Based on the received image, the external information detection unit 12030 can perform an object detection process to detect a person, vehicle, obstacle, sign, symbol on the road surface, or the like, or it can perform a distance processing process.

[0190] The 12031 imaging unit is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The 12031 imaging unit can output an electrical signal as an image or as distance measurement information. Furthermore, the light received by the 12031 imaging unit can be visible light or invisible light, such as infrared radiation.

[0191] The vehicle interior information detection unit 12040 detects information about the vehicle's interior. For example, a driver condition detector 12041, which detects the driver's condition, is connected to the vehicle interior information detection unit 12040. The driver condition detector 12041 includes, for example, a camera that captures an image of the driver, and the vehicle interior information detection unit 12040 can, based on the detected information input from the driver condition detector 12041, calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0192] Based on external / internal information acquired by the external information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control setpoint for the drive power generation device, steering mechanism, or braking device and issue a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to achieve the functions of a driver assistance system (DAS), including vehicle collision avoidance or impact mitigation, distance-based following, speed maintenance, vehicle collision warning, lane departure warning, or similar functions.

[0193] Furthermore, the microcomputer 12051 can also perform cooperative control to carry out automated driving or the like, so that the vehicle is operated autonomously without dependence on the operation of the driver by controlling the drive force generating device, the steering mechanism, the braking device or the like based on information about the vehicle's environment, the information being acquired by the external information detection unit 12030 or the vehicle internal information detection unit 12040.

[0194] Furthermore, the microcomputer 12051 can also issue a control command to the body control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 controls the headlight according to the position of the vehicle ahead or the oncoming vehicle detected by the external information detection unit 12030, and performs cooperative control to achieve an anti-glare effect by switching from high beam to low beam or the like.

[0195] The 12052 audio / video output unit transmits an audio output signal and / or a video output signal to an output device capable of visually or audibly notifying the vehicle's occupant(s) or the exterior of the vehicle of information. In the case of the Fig. The example shown in Figure 17 comprises an audio loudspeaker 12061, a display unit 12062, and an instrument panel 12063 as an output device. The display unit 12062 can, for example, include an on-board display and / or a head-up display.

[0196] Fig. Figure 18 is a diagram showing an example of installation positions for the imaging units 12031.

[0197] In Fig. 18 include the imaging units 12101, 12102, 12103, 12104 and 12105 as the imaging unit 12031.

[0198] Imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, provided in the following locations: the front edge of a vehicle 12100, a side mirror, the rear bumper, a tailgate, the upper portion of the front windshield inside the vehicle, and the like. Imaging unit 12101, provided on the front edge, and imaging unit 12105, provided on the upper portion of the front windshield inside the vehicle, primarily capture images in front of the vehicle 12100. Imaging units 12102 and 12103, provided on the side mirrors, primarily capture images on the sides of the vehicle 12100. Imaging unit 12104, provided on the rear bumper or a tailgate, primarily captures images behind the vehicle 12100.The imaging unit 12105, which is provided on the upper part of the front windscreen inside the vehicle, is mainly used to detect a vehicle ahead of the vehicle, a pedestrian, an obstacle, a traffic signal, a road sign, a roadway or the like.

[0199] It is noted that Fig.Figure 18 shows an example of the imaging areas of imaging units 12101 to 12104. An imaging area 12111 specifies the imaging area of ​​imaging unit 12101, which is provided at the front edge; imaging areas 12112 and 12113 specify the imaging areas of imaging units 12102 and 12103, which are provided at the respective side mirrors; and an imaging area 12114 specifies the imaging area of ​​imaging unit 12104, which is provided at the rear bumper or a tailgate. For example, image data acquired by imaging units 12101 to 12104 are superimposed to obtain an overhead image of the vehicle 12100, as seen from above.

[0200] At least one of the imaging units 12101 to 12104 can have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 can be a stereo camera including multiple imaging devices or can be an imaging device with pixels for phase difference detection.

[0201] For example, based on distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 calculates the distances to the respective three-dimensional objects within the imaging areas 12111 to 12114 and changes in distance over time (the speeds relative to the vehicle 12100). In this way, the three-dimensional object that is the nearest three-dimensional object on the path of motion of the vehicle 12100 and is moving at a predetermined speed (for example, 0 km / h or more) in essentially the same direction as the vehicle 12100 can be extracted as the vehicle that is ahead of the vehicle 12100.Furthermore, the microcomputer 12051 can preset a minimum distance to be maintained between vehicles ahead of the vehicle 12100 and can perform automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), and the like. In this way, it is possible to implement cooperative control for executing automated driving or similar functions, enabling autonomous driving independent of driver input.

[0202] For example, based on distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can extract three-dimensional object data relating to three-dimensional objects in the categories of two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, utility poles, and the like, and use this three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 classifies obstacles near vehicle 12100 into obstacles visible to the driver of vehicle 12100 and obstacles that are difficult to detect visually. The microcomputer 12051 then determines collision risks, indicating the likelihood of a collision with the respective obstacles.If the risk of collision is equal to or higher than a specified value and there is a possibility of a collision, the microcomputer 12051 can issue a warning to the driver via the audio speaker 12061 and the display unit 12062, or it can provide driving assistance to avoid a collision by performing a forced deceleration or evasive steering via the driving system control unit 12010.

[0203] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared radiation. For example, the microcomputer 12051 can detect a pedestrian by determining whether or not a pedestrian exists in images captured by the imaging units 12101 to 12104. Such pedestrian detection is performed, for example, by a process of extracting feature points from the images captured by the imaging units 12101 to 12104 acting as infrared cameras, and a process of performing a pattern match on the series of feature points that define the outlines of objects, and determining whether or not a pedestrian is present.If the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104, and detects a pedestrian, the audio / video output unit 12052 controls the display unit 12062 to overlay a rectangular outline to highlight the detected pedestrian. Furthermore, the audio / video output unit 12052 can also control the display unit 12062 to display a symbol or the like indicating the pedestrian's position.

[0204] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 and the like in the configuration described above. In particular, the semiconductor device (a solid-state imaging device) according to the third embodiment of the present disclosure can be applied to the imaging unit 12031. When the technology according to the present disclosure is applied to the imaging unit 12031, a captured image that is easier to view can be obtained, and consequently, driver fatigue can be reduced. Furthermore, since the captured image is obtained with lower latency, the vehicle can be driven with a feeling similar to that in a case where the driver directly views the surroundings.

[0205] Although preferred embodiments of the present disclosure have been described above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to these examples. It is obvious that a person skilled in the art in the field of the present disclosure may make various changes or modifications within the scope of the technical idea claimed herein, and it is understood that such changes or modifications are within the technical scope of the present disclosure. REFERENCE MARK LIST 1, 2, 3, 11, 12, 13A, 13B, 13C, 14, 21 Semiconductor device 100 Interlayer film 101 Multilayer wiring layer 200 diffusion-prevention film 300 wiring leads 400 through-vias 510 Through hole 520 Protective side wall 530 air gap 600 Via insulation layer 610 Contact-Via 620 Zeroth wiring line 710, 720 substrate

Claims

[1] Semiconductor device comprising the following: a multilayer wiring layer in which several interlayer films and several diffusion prevention films are stacked alternately and a wiring conductor is formed in the interlayer films; a contact via that penetrates a via insulation layer formed on a surface of the multilayer wiring layer and is electrically connected to the wiring conductor of the multilayer wiring layer; a through-hole that penetrates at least one of the interlayer wiring films and the diffusion prevention films from the other surface of the multilayer wiring layer on the opposite side from one surface of the multilayer wiring layer; and an air gap connected to the through-hole and formed in at least one of the intermediate layer films to expose the contact via, wherein a semiconductor substrate is further arranged on the other surface of the via insulation layer on the opposite side from a surface on which the multilayer wiring layer is formed, wherein a photodiode is arranged in the semiconductor substrate, and wherein The air gap is further formed in an area in contact with a TG control line, which is electrically connected to a gate of a transfer transistor that controls a reading of a signal charge from the photodiode. [2] Semiconductor device according to claim 1, wherein the air gap is formed in an area in contact with an FD wiring line which stores a signal charge read by the photodiode. [3] Semiconductor device according to claim 1, wherein the contact via is electronically connected to the gate of the transfer transistor. [4] Semiconductor device according to claim 1, wherein the air gap is further formed in an area in contact with a vertical signal line or a power supply line which is connected to a pixel circuit which converts a signal charge read by the photodiode into a pixel signal. [5] Semiconductor device according to claim 1, wherein a substrate is further arranged opposite the semiconductor substrate on one side of the other surface of the multilayer wiring layer. [6] Semiconductor device according to claim 1, wherein the contact via is formed such that it protrudes into the interlayer film which is arranged on one side of the via insulation layer of the multilayer wiring layer. [7] Semiconductor device according to claim 1, wherein the air gap is further formed in at least one of the interlayer films. [8] Semiconductor device according to claim 7, wherein the air gap is also formed in several of the intermediate layer films, and an opening is formed in a part of the diffusion prevention film between the interlayer films, in which the air gap is formed. [9] Semiconductor device according to claim 8, wherein each of the interlayer films is formed with a first material or a second material having a lower relative dielectric constant than the first material, wherein several interlayer films are formed with the first material and at least one interlayer film is formed with the second material, and the air gap is formed in the intermediate layer films that are formed with the first material. [10] Semiconductor device according to claim 1, wherein the wiring line is formed with a first metal and the contact via is formed with a second metal different from the first metal. [11] Semiconductor device according to claim 10, wherein a wiring line connected to the contact via and formed with the second metal is further formed in the interlayer films. [12] Semiconductor device according to claim 10, wherein the first metal is copper and the second metal is tungsten. [13] Semiconductor device according to claim 11, wherein surfaces of the contact via and the wiring line formed with the second metal are covered with a protective layer. [14] Semiconductor device according to claim 1, wherein a protective side wall is further formed within the through-hole. [15] Semiconductor device according to claim 14, wherein the diffusion prevention films and the protective sidewall are each formed with a material having a higher etch resistance to a fluorine compound than the interlayer films.

Images