semiconductor component

Abstract

Semiconductor component (5), comprising: a semiconductor chip (41) having a main surface (42); an insulating layer (51) formed on the main surface (42); a functional component formed in at least one of the semiconductor chip (41) and the insulating layer (51); a low-potential terminal (11) formed on the insulating layer (51) and electrically connected to the functional component; a high-potential terminal (12) formed on the insulating layer (51) at a distance from the low-potential terminal (11) and electrically connected to the functional component; and a sealing conductor (61) embedded as a wall in the insulating layer (51) to delimit, in a top view, a region containing the functional component, the low-potential terminal (11), and the high-potential terminal (12) from another region, and which is electrically isolated from the semiconductor chip (41), the functional component,the low-potential terminal (11) and the high-potential terminal (12), wherein the functional component includes a low-potential pattern (22, 193) formed inside the insulating layer (51) and a high-potential pattern (23, 194) formed inside the insulating layer (51) such that it is perpendicular to the main surface (42) opposite the low-potential pattern (22, 193), wherein the low-potential terminal (11) is connected to the low-potential pattern (22, 193), wherein the high-potential terminal (12) is electrically connected to the high-potential pattern (23, 194), and wherein the semiconductor component (5) has a dummy pattern (85) embedded in a periphery of the high-potential pattern (23, 194) inside the insulating layer (51) and which, in a sectional view, is wider than the high-potential pattern (23, 194). is.,

Description

Technical area

[0001] The present invention concerns one -helmer component that has a winning manager or sealing manager ("Seal Conductor"). State of the art

[0002] Patent literature 1 reveals a semiconductor component that has a semiconductor substrate, an active element, a variety of intermediate layers, a variety of metal electrodes and a moisture protection ring (victory conductor). The active element is formed in the semiconductor substrate. The large number of intermediate shift layers are laminated on the semiconductor substrate. The variety of metal electrodes are formed on a top intermediate layer layer. The moisture protection ring is so embedded in the variety of intermediate shifts layers in such a way that it surrounds the active element and the variety of metal electrodes in a top view. The moisture protection ring is grounded or placed on mass, namely to the semiconductor substrate. Quote list patient literature

[0003] Patent literature 1: Japanese patent application with the publication number 2006-261613 Overview of the invention technology problem

[0004] With the semiconductor component in accordance with the patent literature 1, due to the structure in which the victory conductor is grounded to the semiconductor substrate, there is a possibility that an undesirable line ("change") occurs between the large number of metal electrodes and the victory manager, and when a tension is created to the large number of metal electrodes. A stand -up voltage ("with" with volume ") of the semiconductor component decreases due to this type of management. Examples of types of undesirable line include an electrical leak and electrical unloading, etc.

[0005] A preferred embodiment of the present invention provides a semiconductor component, in which a standing voltage can be improved in a structure that includes a winning ladder. Solution to the problem

[0006] A preferred embodiment of the present invention provides a semiconductor component, with a semiconductor chip that has a main area, an insulating layer formed on the main area, a functional component that is formed in the semiconductor chip and / or in the insulating layer, a low -potential mineral that is formed on the insulating layer and electrically connected with the functional component, a high potential term which is formed on the insulating layer with a distance ("interval") of the low -potential terminal and electrically connected to the functional component, and a victory conductor or delimitation manager or sealing manager or encapsulation manager ("Seal Conductor"), which is embedded as a wall in the insulating layer, a region that the functional component and the low potential High potential terminal includes to differentiate from another region in a top view, and that is electrically separated or isolated from the semiconductor chip, the functional component, the low -potential terminal and the high potential terminal.

[0007] According to this semiconductor component, an undesirable line ("Conduction") can be suppressed between the high potential terminal and the victory conductor if a tension is created on the low -potential terminal and the high potential terminal. Furthermore, an undesirable line between the low -potential terminal and the victory conductor can be suppressed. Furthermore, an undesirable line between the functional component and the victory manager can be suppressed. A standing voltage can therefore be improved.

[0008] A preferred embodiment of the present invention provides a semiconductor component, with a semiconductor chip that has a main area, an insulating layer formed on the main area, a low potential pattern that is formed inside the insulating layer, a high potential pattern that is formed inside the insulating layer, in such a way that it is in a normal direction ("normal direction") The main area is opposite the low potential pattern, a dummy pattern that is formed inside the insulating layer in a periphery of the high potential pattern, which contains a ladder and which shields an electric field between the low potential pattern and the high potential pattern, a low-potential terminal that is formed on the insulating layer and the electrically with the Low potential pattern is connected, a high potential terminal that is formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the high potential pattern, and a victory ladder that is embedded as a wall in the insulating layer, a region that the low potential pattern, the high potential pattern, the dummy pattern, the Low-potential terminal and The High Potential Maline includes to differentiate from another region in a top view, and that is separated or isolated from the semiconductor chip, the low potential pattern, the dummy pattern, the low-potential terminal and the high-potential terminal.

[0009] According to this semiconductor component, an electrical field concentration with regard to the high potential pattern can be suppressed, by the dummy pattern if a tension is created to the low-potential terminal and the high potential terminal. Furthermore, according to this semiconductor component, an undesirable line between the high potential pattern (high -potential terminal) and the victory conductor can be suppressed if a tension is created on the low potential terminal and the high -potential terminal. Furthermore, an undesirable line between the low potential pattern (low -potential terminal) and the winner can be suppressed. Furthermore, an undesirable line between the dummy pattern and the winner can be suppressed. A standing voltage can therefore be improved.

[0010] The above tasks, characteristics and effects of the present invention result from the following description of the preferred embodiment with reference to the attached drawings. Figure list Fig. 1 is a top view of a semiconductor module that contains a semiconductor component according to a first preferred embodiment of the present invention. Fig. 2 is a diagram to describe an operation of the in Fig. 1 semi -conductor module shown. Fig. 3 is a voltage waveform diagram that is described when describing the Fig. 2 is used. Fig. 4 is a perspective view of the in Fig. 1 semiconductor component shown. Fig. 5 is a top view of the in Fig. 4 semiconductor components shown. Fig. 6 is a top view of a layer of the in Fig. 4 semiconductor components shown in which low potential coils are formed. Fig. 7 is a top view of a layer of the in Fig. 4 semiconductor components shown in which high potential coils are formed. Fig. 8 is a cutting view along a line VIII-VIII that in Fig. 7 is shown. Fig. 9 is a cutting view along a line IX-X, which is in Fig. 7 is shown. 10] Fig. 10 is an enlarged view of a region X, which in Fig. 7 is shown. Fig. 11 is an enlarged view of a region XI that is in Fig. 7 is shown. Fig. 12 is an enlarged view of a region XII that in Fig. 7 is shown. Fig. 13 is an enlarged view of a region of XIII that in Fig. 8 is shown, and is a diagram that shows a separation structure according to a first configuration example. Fig. 14a is an enlarged view of the XIII region, which in Fig.8 is shown, and is a diagram that shows a separation structure according to a second configuration example. Fig. 14b is an enlarged view of the XIII region, which in Fig. 8 is shown, and is a diagram that shows the separation structure according to a third configuration example. Fig. 14c is an enlarged view of the XIII region, which in Fig. 8 is shown and is a diagram that shows the separation structure according to a fourth configuration example. Fig. 14D is an enlarged view of the XIII region, which in Fig. 8 is shown, and is a diagram that shows the separation structure according to a fifth configuration example. Fig. 15 is a graph of medium current delay ("Average instantaneous") dielectric throat or breakthrough tension. Fig. 16 is a diagram that is obtained by examining an electrical field distribution near a high potential coil using a simulation. Fig. 17 is a diagram that is obtained by examining an electrical field distribution of a first high potential dummy pattern by means of a simulation. Fig. 18 is a diagram that is obtained by examining an electrical field distribution of a floating dummy pattern by means of a simulation. Fig. 19 is a top view accordingly Fig. 7 and is a top view of a semiconductor component according to a second preferred embodiment of the present invention. Fig. 20 is a cutting view along a line XX-XX that is in Fig. 19 is shown. Fig. 21 is a cut view of a region accordingly Fig. 8 And is a cut view of a semiconductor component according to a third party preferred embodiment of the present invention. Description of embodiment

[0011] Fig. 1 is a top view of a semiconductor module 1, which contains a semiconductor component 5 according to a first preferred embodiment of the present invention. In Fig. 1 is a central section of a housing body 2 to clarify an internal structure transparently.

[0012] With reference to Fig. 1 The semiconductor module 1 of this embodiment is constructed from an SOP housing ("Small Outline Package"). The semiconductor module 1 is not restricted to a SOP housing and can be structured from a QFN housing ("Quad for non-lead package"), a DFP housing ("Dual Flat Package"), a dip housing ("Dual Inline Package"), a QFP case ("quad flat pack"), a SIP case ("single Inline package ”) or a soy housing (“ Small Outline J-Leaded Package ”), or from any different housings that refer to them.

[0013] With this embodiment, the semiconductor module 1 is a module from the composite type ("Composite Type Module"), which includes a variety of components. The semiconductor module 1 includes the main housing body 2, a variety of DIE PADS 3, a variety of connection terminals 4, the semiconductor component 5, a controller IC 6, a regulatory interior ic ("Driver IC") 7 and a variety of connection wires 17 to 20.

[0014] The semiconductor component 5 is a transformer chip that has an electrical signal that has been entered ("boosts"). The Controller IC 6 is an IC chip that controls the semiconductor component 5 ("Drives") and controls ("Controls"). The control system is an IC chip that generates an electrical signal in accordance with the electrical signal from the semiconductor component 5 to control and control a load (for example a manual component, etc.). The controller IC 6 is a low-potential component in terms of semiconductor component 5. The control IC 7 is a high-potential component in relation to which the semiconductor component 5.

[0015] The housing body 2 includes a cast resin. The cast resin can contain an epoxy resin. The housing body 2 is formed in a rectangular parallel epiped shape. The housing body 2 has an assembly-free surface ("Non-Mounting Surface") 8 on one page, an assembly area 9 on a different page and side walls 10a to 10d, which connect the assembly-free area 8 and the assembly area 9. The assembly -free surface 8 and the assembly area 9 are formed in a top view from a normal direction z on four -sided forms. The assembly area 9 is an area or surface that is opposite a connection object ("Connection Object") in a state in which the semiconductor module 1 is mounted on the connection object. Examples of the connection object include a circuit board such as a printed circuit board ("PCB, Printed Circuit Board").

[0016] The side walls 10a up to 10d include a first side wall 10a, a second side wall 10b, a third side wall 10C and a fourth side wall 10d. The first side wall 10a and the second side wall 10b extend in a first direction X and lie in a second direction Y, the orthogonal is the first direction X. The third side wall 10c and the fourth side wall 10d extend in the second direction Y and are opposite each other in the first direction X.

[0017] The variety of DIE PADS 3 are arranged inside the housing body 2. With this embodiment, the variety of DIE PADS 3 are each formed in a rectangular parallel epiped shape. The multitude of Pads 3 include the first PAD 3A and a second DIE PAD 3B. The first DIE PAD 3A is arranged on the side of the first side wall 10a. The second DIE PAD 3B is arranged on the second side wall 10b side, at a distance from the first DIE PAD 3A.

[0018] The variety of connection terminals 4 are arranged on the side of the first side wall 10a and on the side of the second side wall 10b of the case 2. Each connection terminal 4 has an end section that is positioned inside the housing body 2, and another end section that is positioned outside the case 2. The other end section of each connection terminal 4 is formed as an external connecting section connected to the connection object.

[0019] The semiconductor component 5 is arranged on the first PAD 3A inside the case 2. With this embodiment, the semiconductor component 5 is formed in a top view in a rectangular shape. The semiconductor component 5 is arranged on the first DIE PAD 3A in an orientation that is chosen in such a way that its long sides of the first side wall 10a (the second side wall 10b) are opposite.

[0020] The semiconductor component 5 contains a variety of low potential dates 11 and a variety of high potential terminals 12. The variety of low potential terminals 11 are arranged on the first side wall 10a along the long side of the semiconductor component 5. The multitude of high potential terminals 12 are arranged on the side of the second side wall 10b along the long side of the semiconductor component 5 with distances.

[0021] The Controller IC 6 is arranged on the first PAD 3A inside the case 2. More precisely, the controller IC 6 on the first DIE PAD 3A on the side of the first side wall 10a is arranged with a distance from the semiconductor component 5. With this embodiment, the controller IC 6 is formed in a rectangular shape in a top view. The Controller IC 6 is arranged on the first DIE PAD 3A in an orientation that is chosen in such a way that its long sides of the first side wall 10a (the second side wall 10b) are opposite.

[0022] The Controller IC 6 includes a variety of first entrance pads 13 and a variety of first output pads 14. The large number of first entrance pads 13 are arranged on the first side wall 10a along the long side of the Controller IC 6. The multitude of first output pads 14 are arranged on the side of the second side wall 10b along the long side of the Controller IC 6.

[0023] The control IC 7 is arranged on the second PAD 3B inside the case 2. With this embodiment, the control facility IC 7 is formed in a top view in a rectangular form. The control IC 7 is arranged on the second DIE PAD 3B in an orientation that is chosen in such a way that its long sides of the first side wall 10a (the second side wall 10b) are compared.

[0024] The control facility IC 7 includes a variety of second input pads 15 and a variety of second output pads 16. The large number of second input pads 15 are arranged on the first side wall 10a along the long side of the control facility ic. The multitude of second output pads 16 are arranged on the side of the second side wall 10b along the long side of the control facility IC 7.

[0025] The multitude of connection wires 17 to 20 selectively combine the multitude of connection terminals 4, the semiconductor component 5, the controller IC 6 and the control facility ic 7 inside the case of housing 2. The large number of connecting wires 17 to 20 are each constructed or formed from a bond wire. The multitude of connection wires 17 to 20 contain at least one wire from a copper wire, a gold wire and an aluminum wire.

[0026] The multitude of connection wires 17 to 20 contain the first connection wires 17, second connection wires 18, third connection wires 19 and fourth connecting wires 20. The first connection wires 17 are connected to the connection terminals 4 on the first side wall 10a and the first input pads 13 of the Controller IC 6. The second connecting wires 18 are connected to the low-potential terminals 11 of the semiconductor component 5 and the first output pad 14 of the Controller IC 6. The third connection wires 19 are connected to the high-potential terminals 12 of the semiconductor component 5 and the second input pad 15 of the control facility IC 7. The fourth connecting wires 20 are connected to the second output pads 16 of the control facility IC 7 and the connection terminals 4 on the second side wall 10b side.

[0027] Fig. 2 is a diagram to describe an operation of the in Fig. 1 semiconductor module shown 1. Fig. 3 is a voltage waveform diagram that is described when describing the Fig. 2 is used.

[0028] With reference to Fig. 2 includes the semiconductor component 5 a transformer 21. The transformer 21 contains a low potential coat 22 (low-potential pattern) on a primary side and a high potential coil 23 (high potential pattern), which are opposite each other in an upward / downward direction. The high potential coil 23 is arranged on one upper side with regard to the low potential coil 22 and is compared to the low potential coil 22.

[0029] The high potential coil 23 is via a magnetic coupling with the low potential coil 22 AC connected ("AC Connected") and is also direct current isolated compared to the low potential coil 22. This means that the control facility IC 7 is interconnected with the controller IC 6, via the semiconductor component 5, and is also direct current compared to the Controller IC 6, namely using the semiconductor component 5.

[0030] The low -potential coil 22 includes a first inner terminal end 24, a first external term 25 and a first spiral section 26, which is laid in a spiral between the first internal end of the term 24 and the first external term 25 ("Routed"). The high potential coil 23 includes a second inner terminal end 27, a second external term 28 and a second spiral section 29, which is laid in a spiral between the second internal end of the term 27 and the second external terminal end.

[0031] The semiconductor component 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33 and a second high potential wiring 34. The first low potential wire 31 combines the first internal terminal end 24 of the low potential coil 11. Low potential wiring 32 connects the first external termination 25 of the low potential coil 22 with the corresponding low potential terminal 11. The first high potential wiring 33 combines the second internal term 27 of the high potential coil 12. High potential coil 23 with the corresponding high potential terminal 12.

[0032] The Controller IC 6 includes a first wiring 35 and a second wiring 36. The first wiring 35 is connected to the first input pad 13 and the first output pad 14 that correspond to each other. The second wiring 36 is connected to the first input pad 13 and the first output pad 14 that correspond to each other. The Controller IC 6 also includes a first switching component SW1 and a second switching component SW2. The first switching component SW1 and the second switching component SW2 are built up from a transistor.

[0033] The first switching component SW1 is intermediate in the first wiring 35. The first switching component SW1 controls and the interruption of an electrical signal that is transmitted to the first wiring 35. The second switching component SW2 is intermediate in the second wiring 36. The second switching component SW2 controls and the interruption of an electrical signal that is transmitted to the second wiring 36.

[0034] The first input pad 13 on the first wiring 35 is connected to mass via a first connection wire 17. The first output pad 14 on the first wiring 35 is connected electrically to the low-potential terminal 11, on the side of the first internal term 24 via a second wiring 18. The first input pad 13 on the second wiring 36 is electrically connected to a power supply 3 via a first connection wire 17. The power supply 37, for example, creates a voltage of 5 V to the Controller IC 6. The first output pad 14 on the second wiring 36 is electrically connected to the low-potential terminal 11, namely via a second wiring 18 on the side of the first external term 25.

[0035] The control IC 7 is electrically connected to the semiconductor component 5 via a variety of third parties 19. More precisely, a second input pad 15 of the control facility ic 7 is connected electrically to the high potential terminal 12 on the side of the second inner terminal end 27, namely via a third connection wire 19. Furthermore, a second input pad 15 of the control facility IC 7 is electrically connected to the high potential terminal on the page of the second external term, and via a third-party jewelry 19.

[0036] A reference voltage performance supply 38, a performance supply 39 and an SIC-MISFET (metall isolator-helter-field effect transistor) as an example of the load are connected to the control facility IC 7. The reference voltage power supply 38 is a reference voltage from Eg 1200 V to the regulator furnishing IC 7. This reference voltage is also created on the high potential coil 23, namely via the control facility IC 7. The power supply 39 lies, for example, a voltage of 15 V to the control facility IC 7. The control IC 7 controls the SIC-MISFET ("Drives") and controls it ("Controls"), namely using the 1200 V as a reference voltage.

[0037] With reference to Fig. 3 If the Controller IC 6 carries out an ON / AUS control ("ON / OFF Control") of the first switch component SW1 and the second switch component SW2 in a predetermined switching pattern to create a pulsignal PS. In this example, the predetermined switching pattern includes a first application state (SW1: a ("on"), SW2: from ("off")) and a second application state (SW1: from ("off"), SW2: an ("on")). Fig. 3 shows an example in which the powder signal PS of 5 V with 0 V (mass potential) is generated as a reference.

[0038] The pulse signal PS created by the Controller IC 6 is entered in the semiconductor component 5. The semiconductor component 5 transmits the pulses sign from the low potential coil 22 to the high potential coil 23. The pulse signal PS is increased by this, exactly by one or according to an amount that corresponds to a winding ratio (transformation ratio) of the low potential coil and the high potential coil 23. An example in which the pulse signal PS is reinforced to 15 V is in Fig. 3 shown.

[0039] The reinforced ("Boosted") pulse signal PS is entered in the control facility IC 7. The control system IC 7 generates an electrical signal according to the reinforced pulse signal PS to control and control the SIC-MISFET. The numerical values ​​that in Fig. 2 and Fig. 3 are all given, all are only one example. For example, the reference voltage on the secondary side (high potential side) may not be smaller than 500 V and possibly not larger than 4000 V.

[0040] Fig. 4 is a perspective view of the in Fig. 1 semiconductor component shown 5. Fig. 5 is a top view of the in Fig. 4 semiconductor components shown 5. Fig. 6 is a top view of a layer of the in Fig. 4 semiconductor component shown 5, within which low potential coils 22 are formed. Fig. 7 is a top view of a layer of the in Fig. 4 semiconductor components shown 5, within which high potential coils 23 are formed. Fig. 8 is a cutting view along a line VIII-VIII that in Fig. 7 is shown. Fig. 9 is a cutting view along a line IX-X, which is in Fig. 7 is shown. Fig. 10 is an enlarged view of a region X, which in Fig. 7 is shown. Fig. 11 is an enlarged view of a region XI that is in Fig. 7 is shown. Fig. 12 is an enlarged view of a region XII that in Fig. 7 is shown. Fig. 13 is an enlarged view of a region of XIII that in Fig. 8 is shown and is a diagram that shows a separation structure 130 according to a first configuration example.

[0041] With reference to Fig. 4 to Fig. 8, the semiconductor component 5 includes a semiconductor chip 41 with a rectangular parallel epiped shape. The semiconductor chip 41 contains at least one of silicon, a semiconductor with a wide band gap and a composite-hal writer ("Compound Semiconductor").

[0042] The semiconductor with a wide band gap ("Wide Bandgap Semiconductor") is built up from a semiconductor that exceeds the band gap (about 1.12 eV) from silicon. The band gap of the semiconductor with a wide band gap is preferably not less than 2.0 Ev. The semiconductor with a wide band gap can be sic (silicon carbid). The composite hauler can be a group of group III-V. The composite necker can contain at least one of Aln (aluminum nitrid), Inn (indium nitrid), Gan (Galliumnitrid) and Gaas (gallium arsenide).

[0043] With this embodiment, the semiconductor chip 41 includes a semiconductor substrate that is made of silicon. The semiconductor chip 41 can be an epitaxial substrate with a laminated structure that includes a semiconductor substrate made from silicon and an epitaxial layer made from silicon. A type of conductivity of the semiconductor substrate can be an N type or a P-type. The epitaxial layer can be of an N type or a P-type.

[0044] The semiconductor chip 41 shows a first main area 42 on one side, a second main area 43 on a different side and chip side walls 44a to 44d, which connect the first main area 42 and the second main area 43. The first main area 42 and the second main area 43 are formed in a top view from a normal direction z (hereinafter simply referred to as a "top view") in four -sided forms (rectangular shapes in this embodiment).

[0045] The chip side walls 44a up to 44D include a first chip page wall 44a, a second chip page wall 44b, a third chip page wall 44c and a fourth chip pages wall 44d. The first chip side wall 44a and the second chip pages wall 44b form long sides of the semiconductor chip 41. The first chip pages wall 44a and the second chip pages wall 44b extend in the first direction X and are opposite each other in the second direction. The third chip side wall 44c and the fourth chip pages 44d form short sides of the semiconductor chip 41. The third chip pages wall 44c and the fourth chip pages wall 44d extend in the second direction Y and are facing each other in the first direction. The chip side walls 44a to 44d are made up of sanded surfaces ("ground surfaces").

[0046] The semiconductor component 5 also includes an insulating layer 51, which is formed on the first main area 42 of the semiconductor chip 41. The insulating layer 51 has an insulating area 52 and insulating side walls 53a up to 53d. The insulating area 52 is formed in a top view into a four -sided form (rectangular shape in this embodiment), which matches the first main area 42. The insulating area 52 extends parallel to the first main area 42.

[0047] The insulating side walls 53a up to 53D include a first insulating side wall 53a, a second insulating side wall 53b, a third insulating side wall 53c and a fourth isolating side wall 53d. The insulating side walls 53a up to 53d extend from the circumference edge of the insulating area 52 to the semiconductor chip 41 and continuously ("Are Continuous") transferred to the chip side walls to 44D. More precisely, the insulating side walls 53a up to 53d are flush with the chip side walls 44a to 44d. The insulating side walls 53a up to 53d form polished surfaces that are flush with the chip side walls 44a up to 44D.

[0048] The insulating layer 51 is built from a multi -layered insulating laminate structure, which includes a lowest insulating layer 55, a top insulating layer 56 and a variety (eleven with this embodiment) of intermediate layers 57. The lowest insulating layer 55 is an insulating layer that directly covers the first main area 42. The top insulating layer 56 is an insulating layer that forms the insulating area 52. The variety of intermediate shifting layers 57 are insulating layers that are arranged between the lowest insulating layer 55 and the top insulating layer 56. With this embodiment, the lowest insulating layer 55 has a single layer structure that contains silicon oxide. With this embodiment, the top insulating layer 56 has a single layer structure that contains silicon oxide. A thickness of the lowest insulating layer 55 and a thickness of the top insulating layer 56 may not be smaller than 1 µm and not larger than 3 µm (e.g. about 2 µm).

[0049] The multitude of intermediate shifting layers 57 each have a laminated structure, which includes a first insulating layer 58 on the side of the lowest insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 can contain silicon nitride. The first insulating layer 58 is formed as a caustic stop layer in relation to the second insulating layer 59. A thickness of the first insulating layer 58 may not be less than 0.1 µm and not larger than 1 µm (e.g. about 0.3 µm).

[0050] The second insulating layer 59 is formed on the first insulating layer 58. The second insulating layer 59 includes an insulating material that differs from that of the first insulating layer 58. The second insulating layer 59 can contain silicon oxide. A thickness of the second insulating layer 59 may not be less than 1 µm and not larger than 3 µm (e.g. about 2 µm). The thickness of the second insulating layer 59 preferably exceeds the thickness of the first insulating layer 58.

[0051] A total thickness of the insulating layer 51 may not be less than 5 µm and not larger than 50 µm. The total thickness of the insulating layer 51 and the number of laminated layers of the intermediate layersolier layers 57 are arbitrary and are set according to a dielectric standing tension to be implemented (dielectric penalty resistance, "Dielectric Breakdown Resistance"). Furthermore, the insulating materials of the lowest insulating layer 55, the top insulating layer 56 and the intermediate layered layers 57 are arbitrary and are not restricted to specific insulating materials.

[0052] The semiconductor component 5 includes a first functional component 45, which is formed in the insulating layer 51. The first functional component 45 includes one or a variety of transformers 21. This means that the semiconductor component 5 is structured from a component of the multi -channel type, which contains the large number of transformers 21. The variety of transformers 21 are formed in an inner section of the insulating layer 51, with intervals from the insulating side walls 53a to 53d. The large number of transformers 21 are formed with intervals ("intervals") in the first direction X.

[0053] More precisely, the multitude of transformers 21 includes a first transformer 21a, a second transformer 21b, a third transformer 21c and a fourth transformer 21d, which are formed in a top view from the side of the insulating side wall 53c to the side of the insulating side wall 53D in this order. The large number of transformers 21a to 21d each have the same structure. The structure of the first transformer 21a is described below as an example. A description of the structures of the second transformer 21b, the third transformer 21c and the fourth transformer 21d is omitted, since the description of the first transformer 21a can be applied.

[0054] With reference to Fig. 6 to Fig.9 includes the first transformer 21a a low potential coil 22 and a high potential coil 23. The low potential coil 22 is formed inside the insulating layer 51. The high potential coil 23 is formed inside the insulating layer 51, in such a way that it is opposite the low potential coil 22 in the normal direction Z. In this embodiment, the low potential coil 22 and the high potential coil 23 are formed in a region, which is arranged in a sandwich between the lowest insulating layer 55 and the top insulating layer 56 (that is, in the large number of intermediate layers 57).

[0055] The low potential coil 22 is formed inside the insulating layer 51 on the side of the bottom insulating layer 55 (of the semiconductor chip 41), and the high potential coil 23 is formed inside the insulating layer 51 with regard to the low potential coil 22 on the top of the top insulation layer 52). This means that the high potential coil 23 is offset by the semiconductor chip 41 over the low potential coil 22. Places of the arrangement of the low potential coil 22 and the high potential coil 23 are arbitrary. It is also sufficient if the high potential coil 23 of the low potential coil 22 is opposite one or more intermediate layers.

[0056] A distance (i.e. the number of laminated layers from intermediate layersolier layers 57) between the low potential coat 22 and the high potential coil 23 is adapted to them. The third intermediate layer layer 57 formed, counting from the side of the lowest insulating layer 55. With this embodiment, the high potential coil 23 is formed in the first intermediate laying layer 57, and counted based on the side of the top isolation layer 56.

[0057] The low potential coil 22 is embedded in an intermediate layer layer 57, in such a way that it penetrates the first insulating layer 58 and the second insulating layer 59. The low potential coil 22 includes a first inner terminal end 24, a first external term 25 and a first spiral section 26, which is laid in a spiral between the first inner term 24 and the first external term 25. The first spiral section 26 is laid in a spiral that extends in an exception of an elliptical form (oval form). A section of the first spiral section 26, which forms an innermost circumference, distinguishes a first inner region 66 with an elliptical form in one point.

[0058] The number of turns of the first spiral section 26 may not be less than 5 and not greater than 30. The width of the first spiral section 26 is preferably not less than 1 µm and not larger than 3 µm. The width of the first spiral section 26 is defined perpendicular to a spiral direction by a width in one direction. A first turning distance ("First Winding Pitch") of the first spiral section 26 may not be less than 0.1 µm and not larger than 5 µm. The first turning distance is preferably not less than 1 µm and not larger than 3 µm. The first wind distance defined by a distance between two sections of the first spiral section 26, which are in the direction of orthogonal to the spiral direction.

[0059] A formation form of the first spiral section 26 and a layer form of the first inner region 66 are arbitrary and are not on the in Fig. 6 implemented embodiment, etc. restricted. The first spiral section 26 can be wrapped or wound in a top view of a polygonal shape like a triangular shape, a four -sided shape, etc. or in a circular shape. In a top view, the first inner region 66 can be differentiated into a polygonal shape in accordance with the turning form of the first spiral section 26 such as a triangular shape, a four -sided form, etc. or in a circular form.

[0060] The low potential coil 22 can contain at least one material of titanium, titanium nitride, copper, aluminum and tungsten. The low potential coil 22 can have a laminated structure that contains a barrier layer and a main body layer. The barrier layer distinguishes an reception room inside the intermediate layer layer 57. The main body layer is embedded in the recess area, which is delimited by the barrier layer. The barrier layer can at least contain a material from Titan and Titannitrid. The main body layer can at least contain a material of copper, aluminum and tungsten.

[0061] The high potential coil 23 is embedded in an intermediate layered layer 57, in such a way that it penetrates the first insulating layer 58 and the second insulating layer 59. The high potential coil 23 includes a second inner terminal end 27, a second external term 28 and a second spiral section 29, which is laid between the second internal end of the term 27 and the second external terminal end in a spiral. The second spiral section 29 is laid in a spiral that extends in a top view in an elliptical form (oval form). In this embodiment, a section of the second spiral section 29, which forms an innermost circumferential edge, distinguishes a second inner region 67 with an elliptical form. The second inner region 67 of the second spiral section 29 is offset by the first inner region 66 of the first spiral section 26 in the normal direction z.

[0062] The number of turns of the second spiral section 29 may not be less than 5 and not greater than 30. The number of turns of the second spiral section 29 is set in terms of the number of turns of the first spiral section 26 according to a "to be boosted") voltage value. The number of turns of the second spiral section 29 preferably crosses the number of turns of the first spiral section 26. It goes without saying that the number of turns of the second spiral section 29 can be smaller than the number of turns of the first spiral section 26 or equal to the number of turns of the first spiral section 26.

[0063] A width of the second spiral section 29 may not be less than 0.1 µm and not larger than 5 µm. The width of the second spiral section 29 is preferably not less than 1 µm and not larger than 3 µm. The width of the second spiral section 29 is defined by a width in one direction, the orthogonal is the spiral direction. The width of the second spiral section 29 is preferably equal to the width of the first spiral section 26.

[0064] A second turning distance of the second spiral section 29 may not be less than 0.1 µm and not larger than 5 µm. The second turning distance is preferably not less than 1 µm and not larger than 3 µm. The second wind distance is defined by a distance between two sections of the second spiral section 29, which are adjacent to the spiral direction in the direction of orthogonal. The second turning distance is preferably the first turning distance of the first spiral section 26.

[0065] A formation of the second spiral section 29 and a layer form of the second inner region 67 are arbitrary and are not on the in Fig. 7 Exclined embodiment, etc. The second spiral section 29 can be wrapped in a polygonal shape like a triangular shape, a four -sided shape, etc. or in a circular shape. In a top view, the second inner region 67 can be delimited in a top view in accordance with the turn of the second spiral section 29 in a polygonal form such as a triangular shape, a four -sided form, etc. or in a circular shape.

[0066] The high potential coil 23 is preferably made from the same conductive materials as the low potential coil 22. This means that, as with the low potential coil 22, the high potential coil 23 preferably includes a barrier layer and a main body layer.

[0067] With reference to Fig.5 includes the semiconductor component 5 The large number (twelve with this embodiment) of the low potential terminals 11 and the large number (twelve with this embodiment) of the high potential dates 12. The variety of low potential minals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21a to 21d. The large number of high potential terminals 12 are electrically connected to the high potential coil 23 of the corresponding transformers 21a to 21d.

[0068] The variety of low potential terminals 11 are formed on the insulating main area 52 of the insulating layer 51. More precisely, the variety of low potential terminals 11 are formed in a region on the side of the insulating side wall 53b, with intervals in the second direction Y from the multitude of transformers 21a to 21d, and are aligned or lined up in the first direction X.

[0069] The multitude of low potential dates 11 include the first low -potential dates 11a, second low -potential dinals 11b, third low potential terminals 11c, fourth low -potential terminals 11d, fifth low -potential terminals 11e and sixth low -potential minals 11f. In this embodiment, two of each of the variety of low potential dates 11a to 11f are formed. The number of each of the multitude of low potential dates 11a to 11f is arbitrary.

[0070] The first low -potential terminals 11a are opposed to the first transformer 21a in the second direction Y in a top view. The second low -potential terminals 11b are opposite the second transformer 21b in the second direction Y in a top view. The third low -potential terminals 11c are opposed to the third transformer 21c in the second direction Y in a top view. The fourth low -potential terminals 11d are opposite the fourth transformer 21d in the second direction Y in a top view. The fifth low -potential terminals 11E are formed in a top view in a region between the first low potential terminals 11a and the second low -potential terminals 11b. The sixth low -potential terminals 11F are formed in a top view in a region between the third low -potential terminals 11c and the fourth low potential terminals 11D.

[0071] The first low potential dates 11a are electrically connected to the first internal term 24 of the first transformer 21a (low potential coil 22). The second low -potential dates 11b are electrically connected to the first internal term 24 of the second transformer 21b (low potential coil 22). The third low -potential dates 11c are electrically connected to the first internal term 24 of the third transformer 21C (low potential coil 22). The fourth low -potential terminals 11D are electrically connected to the first internal term 24 of the fourth transformer 21D (low potential coil 22).

[0072] The fifth low -potential terminals 11E are electrically connected with the first external term 25 of the first transformer 21a (low potential coil 22) and with the first external termination 25 of the second transformer 21b (low potential coil 22). The sixth low -potential terminals 11F are electrically connected to the first external term 25 of the third transformer 21C (low potential coil 22) and with the first external term 25 of the fourth transformer 21D (low potential coil 22).

[0073] The variety of high potential terminals 12 are formed on the insulating main area 52 of the insulating layer 51 with distances from the variety of low -potential terminals 11. To be more precise, the variety of high potential terminals 12 in a region on the side of the insulating side wall 53a with intervals in the second direction Y from the large number of low potential terminals 11 are formed and are aligned or lined up in the first direction X.

[0074] The large number of high potential terminals 12 are formed in a top view in regions in the neighborhood of the corresponding transformers 21a to 21d. The fact that the high -potential terminals 12 are located in the neighborhood of transformers 21a to 21d means that the distances or distance between the high -potential terminals 12 and the respective transformer 21 are smaller than the distances between the low -potential terminals 11 and the high -potential terminals 12, in a top view.

[0075] More precisely, the variety of high potential terminals 12 along the first direction X are formed with distances, in such a way that they are opposite the variety of transformers 21a to 21d along the first direction X. More precisely, the variety of high potential terminals 12 with distances along the first direction X are formed in such a way that they are positioned in the second inner regions 67 of the high potential coil 23 and in regions between neighboring high potential coil 23, seen in a top view. The variety of high potential terminals 12 with the variety of transformers 21a to 21d are aligned or lined up in a single series in a top view, in the first direction X.

[0076] The multitude of high potential terminals 12 contain the first high potential terminals 12a, second high -potential minals 12b, third high -potential terminals 12C, fourth high -potential minals 12D, fifth high -potential minals 12e and sixth high -potential minals 12f. With this embodiment, two of each of the large number of high potential dates 12a to 12f are formed. The number of each of the multitude of high potential dates 12a to 12f is arbitrary.

[0077] The first high -potentials 12A are formed in a top view in the second inner region 67 of the first transformer 21a (high potential coil 23). The second high potential dates 12b are formed in a top view in the second inner region 67 of the second transformer 21b (high potential coil 23). The third high -potential terminals 12C are formed in a top view in the second inner region 67 of the third transformer 21C (high potential coil 23). The fourth high -potential terminals 12D are formed in a top view in the second inner region 67 of the fourth transformer 21d (high potential coil 23). The fifth high -potential terminals 12E are formed in a view in a region between the first transformer 21a and the second transformer 21b. The sixth high -potential terminals 12f are formed in a top view in a region between the third transformer 21c and the fourth transformer 21d.

[0078] The first high -potentials 12A are electrically connected to the second inner terminal end 27 of the first transformer 21a (high potential coil 23). The second high potential dates 12b are electrically connected to the second inner terminal end 27 of the second transformer 21b (high potential coil 23). The third high -potential dates 12C are electrically connected to the second inner terminal end of the third transformer 21C (high potential coil 23). The fourth high -potential terminals 12D are electrically connected to the second internal term 27 of the fourth transformer 21D (high potential coil 23).

[0079] The fifth high -potential terminals 12E are electrically connected to the second external term 28 of the first transformer 21a (high potential coil 23) and the second external terminal end of the second transformer 21b (high potential coil 23). The sixth high -potential terminals 12F are electrically connected to the second external terminal end of the third transformer 21C (high potential coil 23) and the second external term 28 of the fourth transformer 21D (high potential coil 23).

[0080] With reference to Fig. 6 to Fig.9 includes the semiconductor component 5 first low potential wires 31, second low potential wires 32, first high potential wires 33 and second high potential wires 34, which are formed inside the insulating layer 51. With this embodiment, a variety of low potential wires 31, a variety of the second low potential wires 32, a variety of the first high potential wires 33 and a variety of second high potential wires 34 are formed.

[0081] Initial potential wires 31 and a second low potential wiring 32 define the low potential coil 22 of the first transformer 21a and the low potential coil 22 of the second transformer 21b on the same potential. Furthermore, the first low potential wires 31 and a second low potential wiring 32 set the low potential coil 22 of the third transformer 21C and the low potential coil 22 of the fourth transformer 21D on the same potential. With this embodiment, the first low potential wires 31 and the second low potential wires 32 determine the low potential coil 22 of all transformers 21a to 21d to the same potential.

[0082] First high potential wiring 33 and a second high potential wiring 34, the high potential coil 23 of the first transformer 21a and the high potential coil 23 of the second transformer 21b determine the same potential. Furthermore, the first high potential wiring 33 and a second high potential wiring 34 The high potential coil 23 of the third transformer 21c and the high potential coil 23 of the fourth transformer 21D set the same potential. With this embodiment, the first high potential wires 33 and the second high potential wires 34 set the high potential coil 23 from all transformers 21a to 21d to the same potential.

[0083] The large number of first low potential wires 31 are connected electrically with the corresponding low potential terminals 11a to 11d and the first internal terminal ends 24 of the corresponding transformers 21a to 21d (low potential coil 22). The multitude of first low potential wires 31 have the same structure. In the following, the structure of the first low potential wiring 31, which is connected to the first low -potential terminals 11a and the first transformer 21a, is described as an example. A description of the structures of the other first low potential wires 31 is omitted, since the description of the first low potential wiring 31, which is connected to the first transformer 21a, can be applied to this.

[0084] The first low potential wiring 31 includes a penetration wiring 71, a low potential connection wiring 72, a guide wiring 73, a first connecting plug electrode 74 ("First Connection Plug Electrode"), a second connecting plug electrode 75, one or a variety of PAD stuffing electrodes 76 as well as one or a variety of substrate plug electrodes 77.

[0085] The penetration wiring 71, the low-potential connection wiring 72, the outlet wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the PAD plug electrodes 76 and substrate plug electrodes 77 are preferably formed from the same conductive materials as the low potential coils, etc. Like the low potential coils 22, etc., each includes the penetration wiring 71, the low potential connection wiring 72, the outlet wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the PAD plug electrodes 76 and the substrate plug electrodes 77 preferably a barrier layer and one Main body layer.

[0086] The penetration wiring 71 penetrates a variety of intermediate shifts 57 and extends as a pillar that extends in the insulating layer 51 along the normal direction. In this embodiment, the penetration wiring 71 is formed in a region of the insulating layer 51 between the lowest insulating layer 55 and the top insulating layer 56. The penetration wiring 71 has an upper end section on the side of the top insulation layer 56 and a lower end section on the side of the lowest insulating layer 55. The upper end section of the penetration wiring 71 is formed in the same intermediate layer layer 57 as the high potential coils 23 and is covered by the top insulating layer 56. The lower end section of penetration wiring 71 is formed in the same intermediate layer layer 57 as the low potential coil 22.

[0087] With this embodiment, the penetration wiring 71 includes a first electrode layer 78, a second electrode layer 79 and a variety of wiring stuffing steke ("Wiring plug electrodes") 80. In the case of penetration wiring 71, the first electrode layer 78, the second electrical layer 79 and the wiring stuffing steeper 80 each from the same conductive materials formed like the low potential coil 22, etc. This means, as with the low potential coil 22, etc., each includes a barrier layer and a main body layer.

[0088] The first electrode layer 78 forms the upper end section of the penetration wiring 71. The second electrode layer 79 forms the lower end section of the penetration wiring 71. The first electrode layer 78 is formed as an island and is contrasted with low -potential terminals 11 (the first low -potential terminal 11a) in the normal direction Z. The second electrode layer 79 is formed as an island and is compared to the first electrode layer 78 in the normal direction z.

[0089] The variety of wiring plug lectures 80 are embedded in the variety of intermediate shifting layers 57, which are positioned in a region between the first electrode layer 78 and the second electrode layer 79. The variety of wiring plug lectures 80 are laminated from the lowest insulating layer 55 to the top insulating layer 56 in such a way that they are electrically connected and the first electrode layer 78 and the second electrode layer 79 connect electrically. Each of the variety of wiring plugs 80 has an area in the level or a layer area ("Planar Area"), which is smaller than a level surface of the first electrode layer 78 and a level surface of the second electrode layer 79.

[0090] The number of laminated layers of the multitude of wiring plug lectrodes 80 matches the number of laminated layers of the multitude of intermediate laying stories 57. Although in this embodiment six wiring stuffing steeping 80 are embedded in each intermediate layer slect 57, the number of wiring stuffing steels is 80, which is 80, which is embedded in each Intermediate layer layer 57 are embedded, arbitrary. It goes without saying that one or a variety of wiring plug lectrodes 80 can be formed, which penetrate a variety of intermediate layers.

[0091] The low potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21a (low potential coil 22) inside the same intermediate layer layer 57 as the low potential coil 22. The low -potential connection wiring 72 is formed as an island and is offset by high -potential terminals 12 (the first high -potential minals 12a) in the normal direction z. The low -potential connection wiring 72 preferably has a layer area that exceeds the layer area of ​​the wiring plug steering rod 80. The low potential connection wiring 72 is electrically connected to the first internal term 24 of the low potential coat 22.

[0092] The wire wiring 73 is formed in a region inside the intermediate layer layers 57 between the semiconductor chip 41 and the penetration wiring 71. With this embodiment, the wire wiring 73 is formed inside the first intermediate layer layer 57, and counted from the lowest insulating layer 55. The first final section of the wiring 73 is positioned in a region between the semiconductor chip 41 and the lower end section of the penetration wiring 71. The second end section of the outlet wiring 73 is positioned in a region between the semiconductor chip 41 and the low potential connection wiring 72. The wiring section extends along the first main area 42 of the semiconductor chip 41 and extends as a band in a region between the first end section and the second section.

[0093] The first connecting plug electrode 74 is formed in a region inside the intermediate laying layers 57 between penetration wiring 71 and the outlet wiring 73 and is electrically connected to the penetration wiring 71 and the first final section of the outlet wiring 73. The second connecting plug electrode 75 is formed in a region inside the intermediate layer layers 57 between the low potential connection wiring 72 and the outlet wiring 73 and is electrically connected to the low potential connection wiring 72 and the second final section of the outer wiring 73.

[0094] The variety of PAD plug electrodes 76 are formed in a region inside the top insulating layer 56 between the low potential dates 11 (first low potential terminals 11a) and the penetration wiring 71 and each are connected electrically with the low-potential terminals 11 and the upper final section of the penetration wiring 71. The variety of substrate plug electrodes 77 are formed in a region inside the lowest insulating layer 55 between the semiconductor chip 41 and the wire wiring 73. With this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first end section of the wire wiring 73 and are each electrically connected to the semiconductor chip 41 and the first final section of the outlet wiring 73.

[0095] With reference to Fig. 9 are connected to the large number of second low potential wires 32 electrically with the corresponding low potential terminals 11e and 11f and the first external terminal ends 25 of the low potential coil 22 of the corresponding transformers 21a to 21d. The multitude of second low potential wires 32 each have the same structure. The structure of the second low potential wiring 32 is described below, which is connected to the fifth low -potential terminals 11E and the first transformer 21a (second transformer 21b). A description of the structure of the other second low potential wiring 32 is omitted, since the description of the second low potential wiring 32, which is connected to the first transformer 21a (second transformer 21b), can be applied.

[0096] As with the first low potential wiring 31, the second low-potential wiring 32 includes penetration wiring 71, a low potential connection wiring 72, a outlet wiring 73, a first connecting plug electrode 75, PAD plug electrodes 76 and substrate electrodes 77. The second low potential wiring 32 has the same structure as the first low potential wiring 31, with the exception that the low potential connection wiring 72 electrically connected to the first external term 25 of the first transformer 21a (low potential coil 22) and the first external terminal end 25 of the second transformer 21b (low potential coil 22).

[0097] The low potential connection wiring 72 The second low potential wiring 32 is formed in an circumferential range of low potential coil 22 inside the same intermediate layer layer 57 as the low potential coil 22. More specifically, the low -potential connection wiring 72 is formed in a top view in a region between two low potential coils 22, which are neighboring. The PAD plug electrodes 76 are formed in a region inside the top isolation layer 56 between low potential terminals 11 (fifth low-potential dinals 11E) and the low potential connection wiring 72 and are connected electrically with the low-potential terminals 11 and low-potential connection wiring 72.

[0098] With reference to Fig. 8 are connected to the multitude of first high potential wires 33 electrically with the corresponding high -potential terminals 12a to 12d and the second internal terminal ends 27 of the corresponding transformers 21a to 21d (high potential coil 23). The multitude of first high potential wires 33 each have the same structure. The structure of the first high potential wiring 33 is described below, which is connected to the first high -potential terminals 12a and the first transformer 21a. A description of the structures of the other first high potential wires 33 is omitted, since the description of the first high potential wiring 33, which is connected to the first transformer 21a, can be applied to this.

[0099] The first high potential wiring 33 includes a high potential connection wiring 81 and one or a variety (a large number of PAD plug electrodes 82. In the case of low potential coils 22, etc., each of the high potential connection wiring 81 and the PAD plug electrodes 82 preferably a barrier layer and a main body layer.

[0100] The high potential connection wiring 81 is formed in the second inner region 67 of the high potential coil 23 inside the same intermediate layer layer 57 as the high potential coil 23. The high potential connection wiring 81 is formed as an island and is offset by high potential terminals 12 (the first high -potential minals 12a) in the normal direction z. The high potential connection wiring 81 is electrically connected to the second internal term 27 of the high potential coil 23. The high potential connection wiring 81 is formed in a top view at a distance ("interval") of the low potential connection wiring 72 and is not offset by the low potential connection wiring 72 in the normal direction Z. This increases an isolation distance between the low potential connection wiring 72 and the high potential connection wiring 81 and a dielectric standing voltage of the insulating layer 51 is increased.

[0101] The variety of PAD plug electrodes 82 are formed in a region inside the top insulation layer 56 between the high potential dates 12 (first high-potential dinals 12a) and the high potential connection wiring 81 and are each connected electrically with the high-potential minals 12 and the high-potential connection wiring 81. The multitude of PAD plug electrodes 82 each have a level surface ("Planar Area"), which is smaller than a level surface of the high potential connection wiring 81, in the top view.

[0102] With reference to Fig.9 are connected to the multitude of second high potential wires 34 electrically with the corresponding high -potential terminals 12e and 12f and the second external terminal ends 28 of the corresponding transformers 21a to 21d (high potential coil 23). The multitude of second high potential wires 34 each have the same structure. The structure of the second high potential wiring 34, which is connected to the fifth high -potential terminals 12E and the first transformer 21a (second transformer 21b), is described below. A description of the structure of the other second high potential wiring 34 is omitted, since the description of the second high potential wiring 34, which is connected to the first transformer 21a (second transformer 21b), can be applied to this.

[0103] As with the first high potential wiring 33, the second high potential wiring 34 includes a high potential connection 81 and PAD plug electrodes 82. The second high potential wiring 34 has the same structure as the first high potential wiring 33, with the exception that the high-potential connection 81 electrically with the second external Terminal end of the first transformer 21a (high potential coil 23) and the second external terminal end 28 of the second transformer 21b (high potential coil 23).

[0104] The high potential connection wiring 81 of the second high potential wiring 34 is formed in a periphery or a circumferential range of high potential coil 23 inside the same intermediate layer layer 57 as the high potential coil 23. The high potential connection wiring 81 is formed in a region between two high potential coil 23, which are neighboring in a top view, and is opposite high potential terminals (the fifth high -potential terminals 12e) in the normal direction. The high potential connection wiring 81 is formed in a view at a distance from the low potential connection wiring 72 and is not offset by low potential connection wiring 72 in the normal direction Z.

[0105] The variety of PAD plug electrodes 82 are formed in a region inside the top insulating layer 56 between the high potential terminals 12 (fifth high-potential dinals 12e) and the high potential connection wiring 81 and are electrically connected to the high-potential minals 12 and the high-potential connection wiring 81.

[0106] With reference to Fig. 8 and Fig. 9 A distance between the low -potential terminals 11 and the high potential terminals 12 preferably exceeds a distance between the low potential coil 22 and the high potential coil 23 (D2 <D1). The distance D1 preferably exceeds the total thickness of the multitude of intermediate layersolier layers 57 (dt <d1). A ratio D2 / D1 of distance D2 in relation to distance D1 may not be less than 0.01 and not larger than 0.1. The distance D1 is preferably not less than 100 µm. And not larger than 500 µm. The distance D2 may not be less than 1 µm. And not larger than 50 µm. The distance D2 is preferably not less than 5 µm and not larger than 25 µm. The values ​​of the distance D1 and distance D2 are arbitrary and are expediently set according to the dielectric standing tension to be implemented.

[0107] With reference to Fig. 7 to Fig. 12 includes the semiconductor component 5 a dummy pattern 85, which is embedded inside the insulating layer 51, in such a way that it is positioned in a view in peripheral or circumference areas of the transformers 21a to 21d. In Fig. 10 to Fig. 12 is the dummy pattern or the dummy structure ("dummy pattern") 85 shown by a hatch. The dummy pattern 85 includes a ladder ("Conductor"). The dummy pattern 85 is preferably formed from the same conductive materials as the low potential coil 22, etc. This means, as with low potential coil 22 etc., the dummy pattern 85 preferably includes a barrier layer and a main body layer

[0108] The dummy pattern 85 is formed from a pattern (discontinuous pattern), which differs from the high potential coil 23 and the low potential coil 22 and which is independent from the transformers 21a to 21d. This means that the dummy pattern 85 does not work as the transformers 21a to 21d or does not contribute to their function. The dummy pattern 85 is formed as a shielding guide layer, the electrical fields between the low potential coil 22 and the high potential coil 23 shields in transformers 21a to 21d and suppresses an electrical field concentration with regard to the high potential coil 23.

[0109] With this embodiment, the dummy pattern 85 is rerped or laid in a form of dense lines ("Dense Lines"), in such a way that it partially covers a region of periphery from one or a variety of high potential coil 23 in a top view and partially exposed. In this embodiment, the dummy pattern 85 is laid with a line density, which is the same as a line density ("line density") of the high potential coils 23 per unit area ("perit area"). The fact that the linie density of the dummy pattern 85 is equal to the linie density of the high potential coil 23 means that the linie density of the dummy pattern 85 falls into an area of ​​± 20% of the linie density of high potential coil 23 or in an area of ​​the line density of the high potential coil 23 ± 20%.

[0110] The dummy pattern 85 is preferably formed in regions, which are in a top view of the high potential coils 23 than the low potentials 11. The fact that the dummy pattern 85 is in a top view in a neighborhood to the high potential coils 23 means that a distance between the dummy pattern 85 and a high potential coil is smaller than a distance Between the dummy pattern 85 and a low potential terminal 11.

[0111] A deep position of the dummy pattern 85 in an inside of the insulating layer 51 is arbitrary and is set in accordance with the relaxing ("to be relaxed") electrical field strengths. The dummy pattern 85 is preferably formed in regions in regions in a closer or closer neighborhood to the high potential coil 23 than the low potential coils 22, namely when considering in the normal direction, the fact that the dummy pattern 85 is located with a view to the normal direction of the high potential coils 23, means that zeine distance between the normal direction between the dummy pattern is 85 and a high potential coil 23 is smaller than a distance between the dummy pattern 85 and a low potential coil 22.

[0112] In this case, the electrical field concentration with regard to the high potential coil 23 can be suppressed. The more the distance between the dummy pattern 85 and the high potential coil 23 with regard to the normal direction Z, the more the electrical field concentration can be suppressed in terms of high potential coil 23. The dummy pattern 85 is preferably formed inside the same intermediate shift layer 57 as the high potential coil 23. In this case, the electrical field concentration with regard to the high potential coil 23 can be suppressed even more easily.

[0113] The dummy pattern 85 is preferably formed in the peripherals of the multitude of high potential coil 23, in such a way that it is arranged in a top view in regions between neighboring the multitude of high potential coil 23 ("interposed"). In this case, the undesirable electrical field concentration in relation to the variety of high potential coils 23 using the regions between neighboring the large number of high potential coils can be suppressed.

[0114] The dummy pattern 85 is preferably arranged in regions between the low-potential terminals 11 and the high potential coil 23, in the top view. In this case, an undesirable line ("Conduction") between the low potential terminals 11 and the high potential coil 23 can be suppressed on the high potential coil 23 due to the electrical field concentration. The dummy pattern 85 is preferably arranged in regions between the low-potential terminals 11 and the high potential terminals 12 in between. In this case, an undesirable line between the low -potential terminals 11 and the high potential terminals 12 can be suppressed on the high potential coil 23 due to the electrical field concentration.

[0115] With this embodiment, the dummy pattern 85 along the large number of high potential coils 23 is formed and is arranged in the regions between neighboring high potential coil 23. Furthermore, the dummy pattern 85 completely surrounds a region that includes the large number of high potential coil 23 and the large number of high potential terminals 12. Furthermore, the dummy pattern 85 is arranged in the regions between the multitude of low-potential terminals 11a to 11f and the large number of high potential coil 23. Furthermore, the dummy pattern 85 is arranged in the regions between the multitude of low-potential terminals 11a to 11f and the large number of high-potential minals 12A to 12F.

[0116] With reference to Fig. 7 to Fig. 12 includes the dummy pattern 85 a variety of dummy patterns that differ in terms of the electrical state ("electrical state"). The dummy pattern 85 includes a high potential dummy pattern 86. The high potential dummy pattern 86 is formed inside the insulating layer 51 in such a way that it is positioned in the peripheries of transformers 21a to 21d. The high potential dummy pattern 86 is made from a pattern (discontinuous pattern) that differs from the high potential coil 23 and the low potential coils 22 and which is independent of transformers 21a to 21d. This means that the high potential dummy pattern 86 does not work as the transformers 21a to 21d.

[0117] With this embodiment, the high potential dummy pattern 86 is laid or rated in a form of dense lines in order to partially cover and partially uncover regions of the peripheries of high potential coil 23. In this embodiment, the high potential dummy pattern 86 is laid or roucted with a linie density, which is equally the line density of the high potential coil 23, namely per unit area ("unit area"). The fact that the line density of the high potential dummy pattern 86 is equal to the line density of the high potential coil 23 means that the line density of the high potential dummy pattern 86 falls into an area of ​​± 20% of the linia density of the high potential coils.

[0118] The high potential dummy pattern 86 shields the electrical fields between the low potential coil 22 and the high potential coil 23 in the transformers 21a to 21d and suppresses the electrical field concentration with regard to the high potential coats 23. High potential coils 23 in order to let electric fields emerge from the high potential coil 23 ("Leaking out"). An electrical field concentration on the high potential coil 23 due to the electrical fields that escape towards the upper sides of the high potential coil 23 is suppressed.

[0119] A voltage is created on the high potential dummy pattern 86 that exceeds a voltage that is created on the low potential coil 22. Voltage waste ("Voltage Drops") between the high potential coil 23 and the high potential dummy pattern 86 can be suppressed, and therefore the electrical field concentration can be suppressed in relation to the high potential coil 23. The voltage that is placed on the high potential coils 23 is preferably the one that is placed on the high potential dummy pattern 86. This means that the high potential dummy pattern 86 is preferably set to the same potential as the high potential coil 23.

[0120] A deep position of the high potential dummy pattern 86 in the interior of the insulating layer 51 is arbitrary and is set according to the electrical field strengths to be relaxed. The high-potential dummy pattern 86 is preferably formed in regions in a closer neighborhood to the high potential coil 23 as the low potential coil 22, with regard to the normal direction Z. The fact that the high-potential dummy pattern 86 is in neighborhood to the high potential coils, in terms of normal direction z, means that a distance in terms of normal direction, Between the high potential dummy pattern 86 and a high potential coil 23 is smaller than a distance between the high potential dummy pattern 86 and a low potential coil 22.

[0121] In this case, the electrical field concentration with regard to the high potential coils 23 can be supposedly suppressed. The more the distance between the high potential dummy pattern 86 and the high potential coil 23 with regard to the normal direction z, the more the electrical field concentration can be suppressed in relation to the high potential coil 23. The high potential dummy pattern 86 is preferably formed inside the same intermediate layer layer 57 as the high potential coil 23. In this case, the electrical field concentration with regard to the high potential coils can be suppressed even more easily.

[0122] In the top view, the high potential dummy pattern 86 is preferably formed in regions in a narrow neighborhood for high potential coil 23 than the low-potential terminals 11. The fact that the high potential dummy pattern 86 is in the neighborhood for high potential coil 23, in the top view, means that a distance between the high potential dummy pattern 86 and a high potential coil 23 is smaller than a distance between the high-potential dummy pattern 86 and a low-potential terminal 11.

[0123] The high potential dummy pattern 86 is preferably formed in the peripherals of the large number of high potential coil 23, in such a way that it is arranged in the view in the regions between neighboring the multitude of high potential coil 23. In this case, the undesirable electrical field concentration in relation to the variety of high potential coils 23 using the regions between neighboring the large number of high potential coils can be suppressed.

[0124] The high potential dummy pattern 86 is preferably arranged in the top view in the regions between the low-potential terminals 11 and the high potential coil 23. In this case, an undesirable line between the low potential terminals 11 and the high potential coil 23 can be suppressed on the high potential coil 23 due to the electrical field concentration. The high potential dummy pattern 86 is preferably arranged in a top view in regions between the low-potential terminals 11 and the high-potential minals 12. In this case, an undesirable line between the low -potential terminals 11 and the high potential terminals 12 can be suppressed on the high potential coil 23 due to the electrical field concentration.

[0125] With this embodiment, the high potential dummy pattern 86 along the variety of high potential coils 23 is formed and is arranged in the regions between neighboring high potential coil 23. Furthermore, the high potential dummy pattern 86 surrounds the region, which contains the large number of high potential coil 23 and the large number of high potential dates 12, completely in the top view. Furthermore, the high potential dummy pattern 86 is arranged in the regions between the multitude of low potential dates 11a to 11f and the variety of high potential coil 23. Furthermore, the high potential dummy pattern 86 is arranged in the regions between the multitude of low potential dates 11a to 11f and the variety of high potential terminals 12A to 12F.

[0126] In the regions between neighboring the multitude of high potential coil 23, in the top view, the high potential dummy pattern 86 around peripheral of the high-potential ratios 12e and 12f is laid around regions directly below the high-potential terminals 12e and 12f. Sections of the high potential dummy pattern 86 can be compared to the high-potential terminals 12a to 12f in the normal direction z. In this case, the high-potentials 12e and 12f shield as well as the high potential dummy pattern 86 the electrical fields to suppress the electrical fields to the top of the high potential coils 23. This means that the high-potentials 12e and 12f are formed as shielding conductor layers, which together with the high potential dummy pattern 86 suppress the electrical field concentration with regard to the high potential coil 23.

[0127] The high potential dummy pattern 86 is preferably formed in a form with ends. In this case, the formation of a loop circuit (closed circuit) for electricity or a current loop ("Loop Circuit of Current") can be suppressed in the high potential dummy pattern 86. A noise due to a stream that flows through the high potential dummy pattern 86 is suppressed. As a result, an undesirable electrical field concentration can be suppressed due to the noise, and at the same time fluctuations can be suppressed with regard to electrical characteristics of the transformers 21a to 21d.

[0128] To be more precise, the high potential dummy pattern 86 includes a first high potential dummy pattern 87 and a second high potential dummy pattern 88. The first high potential dummy pattern 87 is formed in regions between neighboring 21A to 21d (variety of high potential spools 23). The second high potential dummy pattern 88 is formed in a view in a region outside the regions between neighboring the large number of transformers 21a to 21d (large number of high potential coil 23).

[0129] A region between the first transformer 21a (high potential coil 23) and the second transformer 21b (high potential coil 23), which are neighboring, is called the first region 89. Furthermore, a region between the second transformer 21b (high potential coil 23) and the third transformer 21C (high potential coil 23) is called the second region 90. Furthermore, a region between the third transformer 21C (high potential coil 23) and the fourth transformer 21d (high potential coil 23) is called the third region 91.

[0130] With this embodiment, the first high potential dummy pattern 87 is electrically connected to high potential terminals 12 (the fifth high-potential 12E) via the second high potential wiring 34. More specifically, the first high potential dummy pattern 87 includes a first connecting section 92, which is connected to the second high potential wiring 34. The position of the first connecting section 92 is arbitrary. The first high potential dummy pattern 87 is thus set to the same potential as the large number of high potential coil 23.

[0131] To be more precise, the first high potential dummy pattern 87 includes a first pattern 93, which is formed in the first region 89, a second pattern 94 that is formed in the second region 90, and a third pattern 95 that is formed in third region 91. The first high-potential dummy pattern 87 This suppresses the electrical fields that escape to the upper sides of the high potential coil 23, and suppresses the electrical field concentration in relation to the neighboring of the multitude of high potential coils 23 in the first region 89, second region 90 and third region 91.

[0132] With this embodiment, the first pattern 93, the second pattern 94 and the third pattern 95 integral or one piece are formed and the same potential is set. The first pattern 93, the second pattern 94 and the third pattern 95 can be separated from each other as long as the patterns are set to the same potential.

[0133] With reference to Fig. 7 and Fig. 10, the first pattern 93 is connected to the second high potential wiring 34 via the first connecting section 92. The first pattern 93 is laid in a form of dense lines to cover and hide a region of a section of the first region 89 in a top view ("Cover and Hide"). The first pattern 93 is formed in a top view in the first region 89 with intervals ("intervals") of the high potential terminals 12 (fifth high -potential terminals 12e) and is not offset by the high -potential terminals in the normal direction Z. Furthermore, the first pattern 93 has been formed in a top view with distances from the low potential connection wires 72 and is not compared to the low potential connection wires 72 in the normal direction Z. This can increase an insulation distance between the first pattern 93 and the low potential connection wires 72 and the dielectric standing voltage of the insulating layer 51 is increased.

[0134] The first pattern 93 includes a first external scope 96, a second exterior range 97 and a variety of initial interim lines 98. The first external scope 96 extends as a volume along the periphery of the high potential coil 23 of the first transformer 21a. With this embodiment, the first external scope 96 is formed in a top view of a ring shape with an open end in the first region 89. A width of the open end of the first external circumference 96 is smaller than a width along the second direction Y of the high potential coil 23.

[0135] A width of the first external circumference 96 may not be less than 0.1 µm and not larger than 5 µm. The width of the first external circumference 96 is preferably not less than 1 µm and not larger than 3 µm. The width of the first external circumference 96 is defined by a width in one direction orthogonal to a direction in which the first external scope 96 extends. The width of the first external circumference 96 is preferably the same as the width of the high potential coil 23. The fact that the width of the first external scope 96 is equal to the width of the high potential coil 23 means that the width of the first external scope 96 falls into a range of ± 20% of the width of the high potential coil 23.

[0136] A first distance ("pitch") between the first external scope of 96 and the high potential coil 23 (first transformer 21a) is not less than 0.1 µm and not larger than 5 µm. The first distance is preferably not less than 1 µm and not larger than 3 µm. The first distance is preferably equal to the second turning distance ("Second Winding Pitch") of the high potential coil 23. The fact that the first distance is equal to the first turning distance means that the first distance falls into an area of ​​± 20% of the first turning distance.

[0137] The second external circumference 97 extends as a band along the periphery of the high potential coil 23 of the second transformer 21b. With this embodiment, the second external scope 97 is formed in a top view of a ring shape with an open end in the first region 89. A width of the open end of the second exterior circumference 97 is smaller than the width of the high potential coil 23 along the second direction Y. The open end of the second external scope 97 is opposite the open end of the first external scope 96 along the first direction X.

[0138] A width of the second exterior range 97 may not be less than 0.1 µm and not larger than 5 µm. The width of the second exterior range 97 is preferably not less than 1 µm and not larger than 3 µm. The width of the second outdoor exterior line 97 is defined by a width in one direction orthogonal to a direction in which the second external scope 97 extends. The width of the second external circumference 97 is preferably equal to the width of the high potential coil 23. The fact that the width of the second exterior scope 97 is equal to the width of the high potential coil 23 means that the width of the second exterior scope 97 falls into a range of ± 20% of the width of the high potential coil 23.

[0139] A second distance ("Pitch") between the second external circumference management 97 and the high potential coil 23 (the second transformer 21b) may not be less than 0.1 µm and not larger than 5 µm. The second distance is preferably not less than 1 µm and not larger than 3 µm. The second distance is preferably equal to the second turning distance of the high potential coil 23. The fact that the second distance is equal to the second turning distance means that the second distance falls into an area of ​​± 20% of the second turning distance.

[0140] The large number of first intermediate lines 98 extend as ligaments in a region of the first region 89 between the first external scope 96 and the second external scope 97. The multitude of first intermediate lines 98 contain at least one (one with this execution) first connecting line 99, which electrically connected the first external scope 96 and the second external scope 97.

[0141] From the point of view of preventing the formation of forming a current loop, the variety of first intermediate lines 98 preferably contains exactly one first connecting line 99. The position of the first connecting line 99 is arbitrary. A slot 100 that interrupts a current loop is formed in at least one of the variety of first intermediate lines 98. The position of the slot 100 is set according to expediency by the construction or the design of the multitude of first intermediate lines 98.

[0142] The large number of first intermediate lines 98 are preferably formed as ligaments that extend along a direction, so that they are compared to the large number of high potential coil 23. In this embodiment, the multitude of first intermediate lines 98 each are formed as ligaments that extend in the first direction X and are formed from each other in the second direction. The multitude of first intermediate lines 98 are formed as stripes that extend in a top view in the first direction X.

[0143] To be more precise, the multitude of first intermediate lines 98 include a variety of first first sections ("lead-out portions") 101 and a large number of second output sections 102. The large number of first lead section 101 are brought out as stripes from the first external scope 96 towards the second external management 97 ("LED out"). Top or end sections of the multitude of first output sections 101 are formed from the first external scope 96 with intervals to the side of the second external scope 97.

[0144] The multitude of second section 102 are led as stripes based on the second external scope 97 to the first external scope 96. Final sections of the multitude of second output sections 102 are formed from the second external scope 97 with intervals to the side of the first external scope 96. With this embodiment, the multitude of second output sections 102 Alternating with and with distances from the variety of first first sections 101 in the second direction y are formed, in a design in which a first outlet section 101 is recorded.

[0145] The multitude of second section 102 can record the multitude of first leads 101. Furthermore, a group that contains the large number of the second sections 102 can be formed in such a way that it is neighboring a group that contains the multitude of first leading sections 101. The slot 100, the multitude of first leads 101 and the multitude of second output sections 102 suppress the formation of a current loop in the first pattern 93.

[0146] A width of every first intermediate line 98 in the second direction Y is not less than 0.1 µm. And not larger than 5 µm. The width of the first intermediate line 98 is preferably not less than 1 µm and not larger than 3 µm. The width of the first intermediate line 98 is preferably equal to the width of every high potential coil 23. The fact that the width of the first intermediate line 98 is equal to the width of every high potential coil 23 means that the width of the first intermediate line 98 falls into a range of ± 20% of the width of any high potential coil 23.

[0147] Third distances ("Pitches") between two neighboring first intermediate lines 98 may not be less than 0.1 µm and not larger than 5 µm. The third distances are preferably not less than 1 µm and not larger than 3 µm. Each third distance is defined by a distance between neighboring the multitude of first intermediate lines 98 with regard to the second direction Y. The third distances are preferably the same. The fact that the third distances to each other is the same means that the third distances fall into an area of ​​± 20% of the third distances. The third distances are preferably equal to the second turning distance of the high potential coil 23. The fact that the third distances are equal to the second turning distance means that the third distances fall into an area of ​​± 20% of the second turning distance.

[0148] With reference to Fig. 7 and Fig. 11, the second pattern 94 is electrically connected to high potential terminals 12 via the first high potential wiring 33. In this embodiment, the second pattern 94 is electrically connected to the second high potential wiring 34 (fifth high -potential terminals 12e) via the second external scope 97 of the first pattern 93. The second pattern 94 is laid in a form of dense lines or lines to cover and hide the second region 90 ("Cover and Hide").

[0149] The second pattern 94 includes the second outdoor range 97 described above, a third external circumference 103 and a variety of second interim lines 104. The third external circumference 103 extends as a volume along the periphery of the high potential coil 23 of the third transformer 21c. With this embodiment, the third exterior scope 103 is formed in a top view of a ring shape with an open end in the third region 91. A width of the open end of the third exterior circumference 103 is smaller than a width along the second direction Y of the high potential coil 23 of the third transformer 21c.

[0150] A width of the third exterior circumference 103 may not be less than 0.1 µm and not larger than 5 µm. The width of the third exterior circumference 103 is preferably not less than 1 µm and not larger than 3 µm. The width of the third exterior circumference 103 is defined by a width in one direction orthogonal to a direction in which the third external scope of 103 extends. The width of the third external circumference 103 is preferably equal to the width of the high potential coil 23. The fact that the width of the third external scope 103 is equal to the width of the high potential coil 23 means that the width of the third external scope 103 falls into an area of ​​± 20% of the width of the high potential coil 23.

[0151] A fourth distance ("Pitch") between the third external scope 103 and the high potential coil 23 (the third transformer 21C) is not less than 0.1 µm and not larger than 5 µm. The fourth distance is preferably not less than 1 µm and not larger than 3 µm. The fourth distance is preferably equal to the second turning distance of the high potential coil 23. The fact that the fourth distance is equal to the second turning distance means that the fourth distance falls into a range of ± 20% of the second turning distance.

[0152] The multitude of second intermediate lines 104 extends as ligaments in a region of the second region 90 between the second exterior scope 97 and the third exterior scope 103. The large number of second intermediate lines 104 contain at least one (one with this execution form) second connecting line 105, which electrically connects the second external scope 97 and the third external scope 103.

[0153] From the point of view of preventing the formation of forming a current loop, the multitude of second intermediate lines 104 preferably contains exactly one second connecting line 105. The second connecting line 105 can have a width, which is larger than a width of the other second intermediate lines 104. The position of the second connecting line is arbitrarily. A slit 106 that interrupts a current loop is formed in at least one of the variety of second intermediate lines 104. The position of slit 106 is set according to the design of the multitude of second intermediate lines 104.

[0154] The variety of second intermediate lines 104 are preferably formed as ligaments that stretch along a direction, so that they are compared to the variety of high potential coil 23. With this embodiment, the variety of second intermediate lines 104 each are formed as ligaments that extend in the first direction X and are formed with intervals in the second direction y. The large number of second intermediate lines 104 are formed as stripes that extend in a top view in the first direction X.

[0155] To be more precise, the multitude of second intermediate lines 104 include a variety of third parties 107 and a variety of fourth sections 108. The multitude of third parties 107 are removed from the second external scope 97 to the third external scope 103 as stripes. Final sections of the multitude of third parties 107 are formed with intervals ("intervals") starting from the third external scope 103 to the side of the second external scope 97.

[0156] The multitude of fourth output sections 108 are led as stripes from the third external circumference 103 to the second exterior scope 97. End sections of the multitude of fourth output sections 108 are formed from the second external scope 97 with intervals ("intervals") to the side of the third external scope 103. With this embodiment, the variety of fourth output sections 108 Alternating with and at intervals from the multitude of third parties are formed in the second direction y, in a design in which a third section 107 is recorded.

[0157] The large number of fourth sections 108 can absorb the multitude of third parties 107. Furthermore, a group that contains the large number of fourth sections 108 can be formed in such a way that it is neighboring to a group that contains the large number of third parties. The slot 106, the multitude of third parties out and the large number of fourth output sections 108 suppress the formation of a current loop in the second pattern 94.

[0158] The width of each second intermediate line 104 in the second direction Y is not less than 0.1 µm. And not larger than 5 µm. The width of the second intermediate line 104 is preferably not less than 1 µm and not larger than 3 µm. The width of the second intermediate line 104 is preferably equal to the width of every high potential coil 23. The fact that the width of the second intermediate line is 104 is equal to the width of each high potential coil 23, means that the width of the second intermediate line is 104 in a range of ± 20% of the width of any high potential coil 23.

[0159] Fifth distances ("Pitches") between two neighboring second intermediate lines 104 may not be less than 0.1 µm and not larger than 5 µm. The fifth distances are preferably not less than 1 µm and not larger than 3 µm. Each fifth distance is defined by a distance between neighboring the multitude of second intermediate lines 104 in the second direction Y. The fifth distances are preferably the same. The fact that the fifth distances to each other are the same means that the fifth distances fall into an area of ​​± 20% of the fifth distances. The fifth distances are preferably equal to the second turning distance of the high potential coil 23. The fact that the fifth distances are equal to the second turning distance means that the fifth distances fall into a range of ± 20% of the second turning distance.

[0160] With reference to Fig. 7 and Fig. 12 is the third pattern 95 electrically connected to the second high potential wiring 34. With this embodiment, the third pattern 95 is electrically connected to the second high potential wiring 34 via the second pattern 94 and the first pattern 93. The third pattern 95 is laid or ruined in the form of dense lines or lines to cover and hide a region of a section of the third region 91. The third pattern 95 is formed in third parties 91 in a top view with distances ("intervals") of high potential terminals 12 (the sixth high -potential terminals 12f) and is not offset by the high -potential terminals in the normal direction Z.

[0161] The third pattern 95 is formed in a top view of the low potential connection wires 72 and is not offset by the low potential connection wires 72 in the normal direction Z. This increases an insulation distance between the third pattern 95 and the low potential connection wires 72 in the normal direction Z, and the dielectric standing tension of the insulation layer 51 is increased.

[0162] The third pattern 95 includes the third external circumference 103, which has been described above, a fourth outdoor scope 109 and a variety of third parties 110. With this embodiment, the fourth outdoor scope 109 is formed in a top view of a ring shape with an open end in the third region 91. A width of the open end of the fourth exterior circumference 109 is smaller than the width in the second direction Y of the high potential coil 23 of the fourth transformer 21d. The open end of the fourth exterior circumference 109 is opposed to the open end of the third external scope 103 in the first direction X.

[0163] A width of the fourth exterior circumference 109 may not be less than 0.1 µm and not larger than 5 µm. The width of the fourth exterior circumference 109 is preferably not less than 1 µm and not larger than 3 µm. The width of the fourth exterior circumference 109 is defined by a width in one direction orthogonal to a direction in which the fourth outdoor scope of 109 extends. The width of the fourth exterior circumference 109 is preferably equal to the width of the high potential coil 23. The fact that the width of the fourth exterior scope 109 is equal to the width of the high potential coil 23 means that the width of the fourth outdoor scope of the outdoor scope of 109 falls into an area of ​​± 20% of the width of the high potential coil 23.

[0164] A sixth distance ("Pitch") between the fourth exterior scope 109 and the high potential coil 23 (fourth transformer 21d) may not be less than 0.1 µm and not larger than 5 µm. The sixth distance is preferably not less than 1 µm and not larger than 3 µm. The sixth distance is preferably equal to the second turning distance of the high potential coil 23. The fact that the sixth distance is equal to the second turning distance means that the sixth distance falls into an area of ​​± 20% of the second turning distance.

[0165] The multitude of third parties 110 extend as ligaments in a region of third region 91 between the third external circumference 103 and the fourth exterior circumference 109. The large number of third parties 110 include at least one (one with this execution) third connection line 111, which combines the third external scope 103 and the fourth outdoor reaching 109 electrically.

[0166] From a point of view of preventing the formation of forming a current loop, the variety of third parties 110 preferably contains exactly one third connecting line 111. The position of third parties 111 is arbitrary. A slot 112 that interrupts a current loop is formed in at least one of the large number of third parties 110. The position of slit 112 is set according to expediency by designing the multitude of third parties 110.

[0167] The multitude of third parties 110 are preferably formed as ligaments that stretch along a direction, so that they are compared to the variety of high potential coil 23. In this embodiment, the multitude of third parties 110 are formed as ligaments that extend in the first direction X and are formed in the second direction Y with distances. The multitude of third parties 110 are formed in one top view as stripes.

[0168] With this embodiment, the multitude of third parties 110 include a variety of fifth sections 113 and a variety of sixth output sections 114. The multitude of fifth leaders 113 are led as stripes starting from the third external scope 103 to the fourth exterior management 109 ("LED out"). Final sections of the multitude of fifth sections 113 are formed from the fourth exterior scope 109 with intervals to the side of the third external scope 103.

[0169] The large number of sixth output sections 114 are led as stripes based on the fourth exterior scope 109 to the third external scope 103. Final sections of the multitude of sixth output sections 114 are formed from the third external scope 103 with intervals to the side of the fourth exterior scope 109. With this embodiment, the multitude of sixth output sections 114 Alternating with and with distances from the multitude of fifth leadership section 113 in the second direction Y are formed, in a design in which a fifth outlet section 113 is absorbed.

[0170] The large number of sixth output sections 114 can absorb the multitude of fifth leadership sections 113. Furthermore, a group that contains the large number of sixth output sections 114 can be formed in such a way that it is neighboring to a group that contains the multitude of fifth sections 113. The slot 112, the multitude of fifth leads 113 and the multitude of sixth output section 114 suppress the formation of a current loop in the third pattern 95.

[0171] A width of every third intermediate line 110 in the second direction Y is not less than 0.1 µm and not larger than 5 µm. The width of the third intermediate line 110 is preferably not less than 1 µm and not larger than 3 µm. The width of the third intermediate line 110 is preferably equal to the width of every high potential coil 23. The fact that the width of the third intermediate line 110 is the width of each high potential coil 23 means that the width of the third intermediate line 110 falls into a range of ± 20% of the width of any high potential coil 23.

[0172] Seventh distances ("Pitches") between two neighboring third intermediate lines 110 may not be less than 0.1 µm and not larger than 5 µm. The seventh distances are preferably not less than 1 µm and not larger than 3 µm. Each seventh distance is defined by a distance between neighboring the multitude of third parties 110 in the second direction Y. The seventh distances are preferably the same. The fact that the seventh distances are the same means that the seventh distances fall into an area of ​​± 20% of the seventh distances. The seventh distances are preferably equal to the second wind spacing of each high potential coil 23. The fact that the seventh distances are equal to the second turning distance means that the seventh distances fall into an area of ​​± 20% of the second turning distance.

[0173] With reference to Fig. 7 to Fig. With this embodiment, the second high potential dummy pattern 88 is electrically connected to the high potential dates 12 via the first high potential dummy pattern 87. To be more precise, the second high potential dummy pattern 88 includes a second connecting section 115, which is connected to the first high potential dummy pattern 87. The position of the second connecting section 115 is arbitrary. The second high potential dummy pattern 88 is thus set to the same potential as the large number of high potential coil 23.

[0174] The second high potential dummy pattern 88 suppresses the electrical fields that step out to the upper sides of the high potential coils 23 ("Leaking out"), and suppresses the electrical field concentration with regard to the large number of high potential trains 23 in a region outside the first region 90 and third region 91. High potential dummy pattern 88 The region completely that contains the variety of high potential coil 23 and the variety of high potential minals 12a to 12f, in one top view. With this embodiment, the second high potential dummy pattern 88 is formed in an oval ring shape (elliptical ring shape), in a top view.

[0175] The second high-potential dummy pattern 88 is arranged in a top view in the regions between the large number of low potential terminals 11a to 11f and the large number of high potential coil 23. Furthermore, the second high potential dummy pattern 88 is arranged in a top view in the regions between the multitude of low-potential minals 11a to 11f and the variety of high potential dates 12a to 12f.

[0176] The second high potential dummy pattern 88 includes a variety of (six with this embodiment) of high potential lines 116a, 116b, 116c, 116d, 116e and 116f. The number of high potential lines is set according to the electrical fields to be relaxed. The large number of high potential lines 116a to 116f are formed in the order in directions in directions away from the large number of high potential coil 23.

[0177] The large number of high potential lines 116a to 116f surround the large number of high potential coil 23 in a top view. More precisely, the region is surrounded by the multitude of high potential lines 116a to 116f that contains the region, which contains the large number of high potential coil 23 and the large number of high potential terminals 12a to 12f. In this embodiment, the large number of high potential lines 116a up to 116f are formed in a top view of oval ring shapes (elliptical ring shapes).

[0178] The large number of high potential lines 116a to 116f each have a slit 117, which is formed in it and which interrupts a current loop. The positions of the slots 117 are set according to the design of the multitude of high potential lines 116a to 116f.

[0179] A width of each of the high potential lines 116a to 116f may not be less than 0.1 µm and not larger than 5 µm. The width of each of the high potential lines 116a to 116f is preferably not less than 1 µm and not larger than 3 µm. The width of each of the high potential lines 116a to 116f is defined by a width in one direction orthogonal to a direction in which the high potential lines 116a extend to 116f. The width of each of the high potential lines 116a to 116f is preferably the width of every high potential coat 23. The fact that the width of each of the high potential lines 116a to 116f is equal to the width of every high potential coil 23 means that the width of each of the high potential lines 116a to 116f in an area of ​​± 20% of the width of everyone High potential coil 23 falls.

[0180] Eighth distances ("Pitches") between two neighboring the high potential lines 116a to 116f may not be less than 0.1 µm and not larger than 5 µm. The eighth distances are preferably not less than 1 µm. And not larger than 3 µm. The eighth distances are preferably the same. The fact that the eighth distances to each other are the same means that the eighth distances fall into an area of ​​± 20% of the eighth distances.

[0181] A ninth distance ("Pitch") between the first high potential dummy pattern 87 and the second high potential dummy pattern 88, which are neighboring, is not less than 0.1 µm and not larger than 5 µm. The ninth distance is preferably not less than 1 µm and not larger than 3 µm. The ninth distances are preferably equal to the second wind spacing of the high potential coil 23. The fact that the ninth distances are equal to the second turning distance means that the ninth distances fall into an area of ​​± 20% of the second turning distance. The number, the width, the distances, etc., the multitude of high potential lines 116a to 116f are arbitrary and are set in accordance with the electrical fields to be relaxed.

[0182] With reference to Fig. 7 to Fig. 12 includes the dummy pattern 85 A floating dummy pattern 121, which is formed in an electrically floating ("floating") state inside the insulating layer 51 in such a way that it is positioned in a top view in the peripheral or circumference of the transformers to 21d. The floating dummy pattern 121 is formed from a pattern (discontinuous pattern), which differs from the high potential coil 23 and the low potential coil 22 and is independent of transformers 21a to 21d. This means that the floating dummy pattern 121 does not work as the transformers 21a to 21d.

[0183] In this embodiment, the floating dummy pattern 121 is laid or roucted in a form of dense lines in order to partially cover and partially cover the regions of the peripheries of high potential coil 23. The floating dummy pattern 121 can be formed in a shape with ends or in an endless shape.

[0184] The floating dummy pattern 121 is laid with a line density that is equal to the line density of the high potential coil 23, namely per unit area. The fact that the line density of the floating dummy pattern 121 is equal to the line density of the high potential coil 23 means that the linie density of the floating dummy pattern 121 falls into an area of ​​± 20% of the linie density of the high potential coils 23.

[0185] Furthermore, the floating dummy pattern 121 is laid with a line of lines that is equal to the line density of the high potential dummy pattern 86, namely per unit area. The fact that the line density of the floating dummy pattern 121 is equal to the line density of the high potential dummy pattern 86 means that the linie density of the floating dummy pattern 121 falls into an area of ​​± 20% of the linial density of the high potential dummy pattern 86.

[0186] The floating dummy pattern 121 shields the electrical fields between the low potential coil 22 and the high potential coil 23 in transformers 21a to 21d and suppresses the electrical field concentration with regard to the high potential coils 23. 121 In direction away from the high potential coil 23 scattered ("dispersed"). The electrical field concentration with regard to the high potential coil 23 can be suppressed.

[0187] Furthermore, electrical fields that emerge towards an upper side of the high potential dummy pattern 86 are scattered in a periphery of the high potential dummy pattern 86, through the floating dummy pattern 121 in directions away from the high potential coils 23 and the high potential dummy pattern 86. This allows an electrical field concentration to be suppressed in relation to the high potential dummy pattern 86, and at the same time the electrical field concentration with regard to the high potential coil 23 can be suppressed.

[0188] A deep position of the floating dummy pattern 121 in the inside of the insulating layer 51 is arbitrary and is set according to the electrical field strengths to be relaxed. The floating dummy pattern 121 is preferably formed in regions in a narrow neighborhood to the high potential coil 23 as the low potential coil 22 in the normal direction z. The fact that the floating dummy pattern 121 is in the neighborhood to the high potential coil 23 in the normal direction Z means that in the normal direction Z is a distance between the floating dummy pattern 121 and a high potential coil 23 than a distance between the floating dummy pattern 121 and a low potential coil 22.

[0189] In this case, the electrical field concentration with regard to the high potential coil 23 can be suppressed. The further distance between the floating dummy patterns 121 and the high potential coil 23 in the normal direction z, the more the electrical field concentration can be suppressed in relation to the high potential coil 23. The floating dummy pattern 121 is preferably formed inside the same intermediate shift layer 57 as the high potential coil 23. In this case, the electrical field concentration with regard to high potential coil 23 can be suppressed even more expedient.

[0190] The floating dummy pattern 121 is preferably arranged in a top view in the regions between the low-potential terminals 11 and the high potential coil 23. In this case, an undesirable line between the low potential terminals 11 and the high potential coil 23 can be suppressed on the high potential coil 23 due to the electrical field concentration. The floating dummy pattern 121 is preferably arranged in a top view in a region between the low-potential terminals 11 and the high-potential terminals 12. In this case, an undesirable line between the low -potential terminals 11 and the high potential terminals 12 can be suppressed on the high potential coil 23 due to the electrical field concentration.

[0191] With this embodiment, the floating dummy pattern 121 is formed in a top view along the large number of high potential coil 23. More precisely, the floating dummy pattern 121 completely surrounds the region in a top view, which contains the large number of high potential coil 23 and the large number of high potential terminals 12. With this embodiment, the floating dummy pattern 121 completely surrounds the region that contains the large number of high potential coil 23 and the variety of high potential minals 12, namely via the high potential dummy pattern 86 (second high-potential dummy pattern 88).

[0192] As a result, the floating dummy pattern 121 is arranged in a top view in a region between the large number of low potential dates 11a to 11f and the variety of high potential coil 23. Furthermore, the floating dummy pattern 121 is arranged in a top view in a region between the large number of low potential dates 11a to 11f and the variety of high potential terminals 12A to 12F.

[0193] The number of floating lines is arbitrary and is set in accordance with the electrical fields to be relaxed. With this embodiment, the floating dummy pattern 121 includes a variety of (six with this embodiment) of floating lines 122a, 122c, 122d, 122e and 122f. The multitude of floating lines 122a to 122f in the order in directions away from the large number of high potential coil 23 with intervals ("intervals").

[0194] The large number of floating lines 122a to 122f surround the variety of high potential coil 23 in a top view. To be more precise, the multitude of floating lines 122a up to 122f surrounds the region that contains the large number of high potential coil 23 and the large number of high potential minals 12a to 12f, via the high potential dummy pattern 86. With this embodiment, the variety of floating lines 122a up to 122f are formed in a top view of oval ring shapes (elliptical ring shapes).

[0195] A width of each of the floating lines 122a to 122f may not be less than 0.1 µm and not larger than 5 µm. The width of each of the floating lines 122a to 122f is preferably not less than 1 µm and not larger than 3 µm. The width of each of the floating lines 122a to 122f is defined by a width in one direction orthogonal to a direction in which the floating lines 122a to 122f extend.

[0196] Tenth distances ("Pitches") between two neighboring floating lines 122a to 122f may not be less than 0.1 µm and not larger than 5 µm. The tenth distances are preferably not less than 1 µm and not larger than 3 µm. The width of each of the floating lines 122a to 122f is preferably equal to the width of any high potential coil 23. The fact that the width of each of the floating lines is 122a to 122f is the width of every high potential coil 23, the width of each of the floating lines to 122f in an area of ​​± 20% of the width of Every high potential coil 23 falls.

[0197] Eleven distances ("Pitches") between the floating dummy pattern 121 and the high potential dummy pattern 86 (second high potential dummy pattern 88) are not less than 0.1 µm and not larger than 5 µm. The eleventh distances are preferably not less than 1 µm. And not larger than 3 µm. The eleventh distances are preferably the same. The fact that the eleventh distances are the same means that the eleventh distances fall into an area of ​​± 20% of the eleventh distances.

[0198] The eleventh distances are preferably equal to the second wind spacing of the high potential coil 23. The fact that the eleventh distances between the floating lines 122a until 122f are equal to the second turning distance means that the eleventh distances fall into an area of ​​± 20% of the second turning distance. In Fig. 10 to Fig. 12 is shown an example for reasons of clarity, in which the eleventh distances are larger are the second turning distance.

[0199] A twelfth distance ("Pitch") between the floating dummy pattern 121 and the high potential dummy pattern 86 is preferably the second turning distance. The fact that the twelfth distance is equal to the second turning distance means that the twelfth distance falls into a range of ± 20% of the second turning distance. The number, the width, the distances, etc., the multitude of floating lines 122a to 122f are set in accordance with the electrical fields to be relaxed and are not restricted to certain values.

[0200] With reference to Fig. 8 and Fig. 9 includes the semiconductor component 5 a second functional component 60, which is formed in the first main area 42 of the semiconductor chip 41 in a component region 62. The second functional component 60 is formed using a surface layer section ("Surface Layer Portion") of the first main area 42 of the semiconductor chip 41 and / or a region on the first main area 42 of the semiconductor chip 41 and is covered by the insulating layer 51 (the bottom insulating 55). In Fig. 8 and in Fig. 9 is shown the second functional component 60 in a simplified manner by dashed lines that are shown in the surface layer section of the first main area 42.

[0201] The second functional component 60 is electrically connected to the low -potential terminals 11, namely via low potential wires, and is electrically connected to the high -potential terminals 12, namely via high potential wires. With the exception that they are laid inside the insulating layer 51, in such a way that they are connected to the second functional component 60, those low potential wires have the same structure as the first low potential wires 31 (second low potential wires 32). With the exception that they are laid inside the insulating layer 51, in such a way that they are connected to the second functional component 60, those high potential wires have the same structure as the first high potential wires 33 (second high potential wires 34). A precise description of the low potential wires and the high potential wires relating to the second functional component 60 is omitted.

[0202] The second functional component 60 can contain at least one of a passive component, an equal site semiconductor component and a switching semiconductor component. The passive component or the second functional component 60 can contain a circuit network, in which any two or more types of components from the passive component, the equivalent semiconductor component and the switching semiconductor component are selectively combined. The circuit network can form a section of an integrated circuit or an entire integrated circuit.

[0203] The passive component can contain a passive semiconductor component. The passive component can either contain a resistance and a capacitor or both. The equivalent semiconductor component can contain at least one from a PN transition diode, a PIN diode, a Zener diode, a Schottky barrier diode and a fast diode ("Fast Recovery Diode"). The switching semiconductor component can at least contain one of a BJT (transistor with bipolar crossing, "Bipolar junction transistor"), a Misfet (metall isolator field effect transistor), an IGBT (bipolar transition transistor with isolated gate) and a JFET (transition field effect transistor, "Junction Field Effect Transistor").

[0204] With reference to Fig. 8 and Fig. 9 includes the semiconductor component 5 also a victory manager ("Seal Conductor") 61, which is embedded inside the insulating layer 51. The victory ladder 61 is embedded as a wall inside the insulating layer 51, in the top view with intervals from the insulating side walls 53a to 53d, and divided the insulation layer 51 into component region 62 and an external region 63. The victory conductor 61 suppresses the penetration of moisture and penetration of breaks into component region 62 out of the external region 63.

[0205] Component region 62 is a region that is the first functional component 45 (large number of transformers 21), the second functional component 60, the multitude of low potential dates 11, the multitude of high potential minals 12, the first low potential wires 31, the second low potential wiring 3, the first high -potential wiring 33, the second, the second High potential wiring 34 and the dummy pattern 85 includes. The outer region 63 is a region outside the component region 62.

[0206] The winner 61 is electrically separated from component region 62. More precisely, the winner 61 is electrically from the first functional component 45 (large number of transformers 21), the second functional component 60, the multitude of low potentials 11, the multitude of high potential minals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second, the second High potential wires 34 and the dummy pattern 85 separated. More precisely, the winner 61 is defined in an electrically floating state ("floating state"). The winner 61 does not form a power path that is connected to the component region 62.

[0207] The winner 61 is formed in a top view as a band along the insulating side walls 53a up to 53d. With this embodiment, the winner 61 is formed in a top view of a four -sided ring form (more precisely, a rectangular ring shape). The winner 61 therefore borders component region 62 in a top view as a four -sided form (more precisely, a rectangular shape). Furthermore, the victory ladder 61 defines the outer region 63 with a four -sided ring shape (more precisely, a rectangular ring shape), which surrounds the component region 62 in a top view.

[0208] More specifically, the winner 61 has an upper end section on the side of the insulating area 52, a lower end section on the side of the semiconductor chip 41 and a wall section that extends as a wall between the upper end section and the lower end section. With this embodiment, the upper end section of the victory conductor 61 is formed from the insulating main area 52 to the side of the semiconductor chip 41 and is positioned inside the insulating layer 51. With this embodiment, the upper end section of the victory conductor 61 is covered by the highest insulating layer 56. The upper end section of the victory manager 61 can be covered by one or a variety of intermediate layers. The upper end section of the winner 61 can be uncovered compared to the highest insulating layer 56. The lower end section of the victory conductor 61 is formed with a distance from the semiconductor chip 41 to the side of the upper end section.

[0209] The winner 61 is therefore embedded inside the insulating layer 51, in such a way that it is positioned with this embodiment on the side of the semiconductor chip 41 with regard to the variety of low potential terminals 11 and the large number of high potential terminals 12. Furthermore, the winner 61 is located inside the insulating layer 51 the first functional component 45 (large number of transformers 21), the first low potential wires 31, the second low potential wires 32, the first high potential wires 33, the second high potential wiring 34 and the dummy pattern 85, in direction parallel to the directions Insulating area 52. Inside the insulating layer 51, the victory ladder 61 can also be compared to a section of the second functional component 60, in direction parallel to the insulation area 52.

[0210] The winner 61 includes a variety of seal stag leaders 64 and one or a variety of (a large number of this embodiment) Siegelbütkontekungsleiter 65. The number of siegelbecontactation leaders 65 is arbitrary. The top seal stop conductor 64 of the multitude of seal stipes 64 forms the upper end section of the victory conductor 61. The multitude of siegelbetzkontaktungsreiten 65 each form the lower final section of the winning manager 61. The seal stuff conductor 64 and the winning -through contact manager 65 are preferably formed from the same conductive materials as the low -potential spools 22. This means that, as with the low potential coil 22, etc., the seal stipes 64 and the winning translation manager 65 each prefer a barrier layer and a main body layer.

[0211] The large number of seal stipes 64 are embedded in the variety of intermediate shifts 57 and are each formed in a four -sided ring form (more precisely, a rectangular ring shape), which surrounds the component region 62 in one view. The variety of seal stipes 64 are based on the lowest insulating layer 55 to the top insulating layer 56 laminated in such a way that they are connected. The number of laminated layers of the large number of seal stag leaders 64 agrees with the number of laminated layers of the multitude of intermediate shifting layers 57. It goes without saying that one or a variety of seal stag leaders 64 can or can be formed, which penetrates the multitude of intermediate layers 57.

[0212] If a ring -shaped victory ladder 61 is formed by an arrangement from the large number of seal stipes 64, not all of the large number of seal stipes 64 must be formed in a ring form. For example, at least one of the large number of seal stipes 64 can be formed in a form with ends. Furthermore, at least one of the large number of seal stipes 64 can be divided into a variety of band -shaped sections with ends. With regard to the risk of penetrating moisture and breaks ("cracks") into component region 62, the large number of seal stipes 64 are preferably formed in endless forms (ring forms).

[0213] The large number of siegelbintellation leaders 65 are formed in a region in the lowest insulating layer 55 between the semiconductor chip 41 and a seal stop manager 64. The multitude of siegelbecontactation managers 65 are each formed with intervals of the semiconductor chip 41 and are connected to the seal stop manager 64. The multitude of siegelkmontaktungsleiter 65 each have a layer area ("planar area"), which is smaller than a level surface of the seal stop manager 64. If a single siegelkontaktungs manager 65 is formed, the individual siegelbetzkontaktungs manager 65 can have a layer area that is not smaller than a level area of ​​the sealing head 64.

[0214] A width of the winner 61 may not be less than 0.1 µm and not larger than 10 µm. The width of the winner 61 is preferably not less than 1 µm and not larger than 5 µm. The width of the winner 61 is defined by a width in one direction orthogonal to a direction in which the victory conductor 61 extends.

[0215] With reference to Fig. 8, 8, Fig. 9 and Fig. 13, the semiconductor component 5 also includes the separation structure 130, which is arranged between the semiconductor chip 41 and the winner 61 and which electrically separates the winner 61 from the semiconductor chip 41. The separation structure 130 prefers to contain an insulator. In this embodiment, the separation structure 130 is built from a field insulating film 131, which is formed in the first main area 42 of the semiconductor chip 41.

[0216] The field insulating film 131 contains at least one of an oxid film (silicon oxide film) and a nitrid film (silicon nitrid film). The field insulating film 131 is preferably built from a locos ("Local Oxidation of Silicon) film, as an example of an oxide film, which is formed by oxidation of the first main area 42 of the semiconductor chip 41. A thickness of the field insulating film 131 is arbitrary as long as it can isolate the semiconductor chip 41 and the winner 61. The thickness of the field insulating film 131 may not be less than 0.1 µm and not larger than 5 µm.

[0217] The separation structure 130 is formed in the first main area 42 of the semiconductor chip 41 and extends in a top view as a band along the winning conductor 61. With this embodiment, the separation structure 130 is formed in a top view of a four -sided ring shape (more precisely, a rectangular ring shape). The separation structure 130 has connecting sections 132, with which the lower end section (winning declaration manager 65) of the victory manager 61 is connected. The connecting sections 132 can form anchor sections with which the lower end section (winning penalty manager 65) of the victory conductor 61 is wedged or wedged or jammed ("wedged"), to the side of the semiconductor chip 41. It goes without saying that the connecting sections 132 can be formed flush with a main area of ​​the separation structure.

[0218] The separation structure 130 contains an inner end section 130a on the side of component region 62, an external final section 130b on the side of the outer region 63 and a main body section 130c between the inner end section 130a and the outer end section 130b. In a top view, the inner end section 130a distinguishes the region (that is, component region 62), in which the second functional component 60 is formed. The inner end section 130a can be integrally or one piece with an insulating film (not shown), which is formed on the first main area 42 of the semiconductor chip 41.

[0219] The external end section 130b is uncovered compared to the chip side walls 44a up to 44D of the semiconductor chip 41 and is continuously trained with the chip side walls 44a up to 44d of the semiconductor chip 41. The outer end section 130b is formed flush with the chip pages 44a of the semiconductor chip 41. The external end section 130b forms blissful ground surfaces ("Flush Ground Surfaces") with the chip side walls 44a to 44d of the semiconductor chip 41 and the insulating side walls 53a to 53d of the insulating layer 51. Intervals from the chip side walls 44a to 44d.

[0220] The main body section 130c has a flat surface, which extends essentially parallel to the first main area 42 of the semiconductor chip 41. The main body section 130c has the connecting sections 132, with which the lower end section (winning permission manager 65) of the victory manager 61 is connected. The connecting sections 132 are formed on sections of the main body section 130c with distances from the inner end section 130a and the outer end section 130b. In addition to the field insulating film 131, the separation structure 130 can adopt any of different configurations, such as those in the Fig. 14a to Fig. 14D are shown.

[0221] Fig. 14a is an enlarged view of the XIII region, which in Fig. 8 is shown, and is a diagram that shows a separation structure 130 according to a second configuration example. With reference to Fig. 14a can have the separation structure 130 a laminated structure that is an insulating film 133, which is formed on the first main area 42, and includes a conductor film 134 that is formed on the insulating film 133. In this case, the insulating film 133 and / or the ladder film 134 can be uncovered compared to the chip side walls 44a to 44d.

[0222] The insulating film 133 can contain silicon oxide or silicon nitride. The insulating film 133 can be the field insulating film 131. A thickness of the insulating film 133 may not be less than 0.1 µm and not larger than 5 µm. The ladder film 134 includes polysilicon or metal and is formed in an electrically floating state. A thickness of the ladder film 134 may not be less than 0.1 µm and not larger than 5 µm. The connecting sections 132 with the winner 61 are formed in the head film 134.

[0223] Fig. 14b is an enlarged view of the XIII region, which in Fig. 8 is shown, and is a diagram that shows the separation structure 130 according to a third configuration example. With reference to Fig. 14b includes the separation structure 130 a ditch 135, which is formed in the first main area 42, and a embedded body 136, which is embedded in the ditch 135. In this case, the ditch is 135 and the embedded body 136 is free compared to the chip side walls 44a up to 44d. The embedded body 136 is so embedded in the ditch 135 that it is electrically separated from the semiconductor chip 41. More precisely, the embedded body 136 in the ditch 135 is so embedded that it is in an electrically floating state.

[0224] In this configuration example, the embedded body 136 is built from an insulator 137. This means that the separation structure 130 is built from a trench insulation structure. The trench insulation structure can be a STI (flat trench insulation, "Shallow trench isolation"). A depth of the trench 135 may not be less than 0.1 µm and not larger than 5 µm. The embedded body 136 can contain silicon oxide or silicon nitride. The embedded body 136 can have a main area that continues as the first main area 42. The embedded body 136 can have a main area that is further positioned towards one side of a floor wall of the trench 135 than the first main area 42. The embedded body 136 can have a main area that is continuously formed with the first main area 132 with the winner 61 embedded body 136 formed.

[0225] Fig. 14c is an enlarged view of the XIII region, which in Fig. 8 is shown, and is a diagram that shows the separation structure 130 according to a fourth configuration example. With reference to Fig. 14c includes the separation structure 130 the Graben 135, which is formed in the first main area 42, and the embedded body 136, which is embedded in the ditch 135. In this case, the ditch is 135 and the embedded body 136 is free compared to the chip side walls 44a up to 44d. The embedded body 136 is so embedded in the ditch 135 that it is electrically separated from the semiconductor chip 41. More precisely, the embedded body 136 in the ditch 135 is so embedded that it is in an electrically floating state.

[0226] In this configuration example, the embedded body 136 includes an insulating film 138, which is formed on a wall surface of the trench 135, and a ladder 139, via which isolating film 138 is embedded in the Graben 135. The head ("Conductor") 139 is electrically isolated compared to the semiconductor chip 41, namely by the insulating film 138, and is embedded in the electrically floating state. This means that the separation structure 130 is built from a trench insulation structure. The trench insulation structure can be a STI structure.

[0227] A depth of the trench 135 may not be less than 0.1 µm and not larger than 5 µm. The insulating film 138 can contain silicon oxide or silicon nitride. A thickness of the insulating film 138 may not be less than 0.1 µm and not larger than 2 µm. The ladder 139 contains polysilicon or metal and is embedded in the electrically floating state. The conductor 139 can have a main area that continues as the first main area 42. The conductor 139 can have a main area that is still positioned towards one side of a floor wall of the trench 135 than the first main area 42. The conductor 139 can have a main area that is continuously formed with the first main area 42. The connecting sections 132 with the winner 61 are formed in the head 139.

[0228] Fig. 14D is an enlarged view of the XIII region, which in Fig. 8 is shown, and is a diagram that shows the separation structure 130 according to a fifth configuration example. With reference to Fig. 14D the separation structure 130 is built from a section of the insulating layer 51. The separation structure 130 can contain the lowest insulating layer 55 and one or a variety of intermediate shifting layers 57. In this configuration example, the separation structure 130 from the lowest insulating layer 55 is built. In this configuration example, the winning ladder 61 does not have the Siegelbeskontachungs director 65 and has a lower final section that is built up from a seal stop manager 64. Connection section 132 of the separation structure 130 is built from a connecting section of the insulating layer 51 (the bottom insulating layer 55) and the lower end section (seal stuff conductor 64) of the victory manager 61.

[0229] With reference to Fig. 8 and Fig. 9 also includes the semiconductor component 5 an inorganic insulating layer 140 or an inorganic insulating film, which is formed on the insulating main area 52 of the insulating layer 51 to cover the winner 61. The inorganic insulating layer 140 can be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main area 52.

[0230] In this embodiment, the inorganic insulating layer 140 has a laminated structure that contains a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 can contain silicon oxide. The first inorganic insulating layer 141 prefers to include USG (non -endowed silicat glass), which is a silicon oxide that is not endowed with contamination. A thickness of the first inorganic insulating layer 141 may not be less than 50 Nm and not larger than 5000 Nm. The second inorganic insulating layer 142 can contain silicon nitride. A thickness of the second inorganic insulating layer 142 may not be less than 500 Nm and not greater than 5000 Nm. By increasing a total thickness of the inorganic insulating layer 140, a dielectric standing voltage on the high potential coils 23 can be increased.

[0231] If the first inorganic insulating layer 141 is structured from USG and the second inorganic insulating layer 142 from silicon nitride is structured, a dielectric penetration voltage or breakthrough voltage ("Dielectric Breakdown Voltage") (V / cm) of USG exceeds the dielectric penetration voltage (v / cm) from silicon nitride. Therefore, if the inorganic insulating layer has to be designed 140 thicker, it is preferred to form the first inorganic insulating layer 141, which is thicker than the second inorganic insulating layer 142.

[0232] The first inorganic insulating layer 141 can contain at least one material from BPSG (boron-doped phosphorus silicat glass) and PSG (phosphorus silicat glass) as an example of silicon oxide. In this case, however, contamination (boron or phosphorus) is contained inside the silicon oxide, and consequently it is preferred with regard to increasing the dielectric standing voltage at the high potential coil 23, especially if the first inorganic insulating layer 141 is formed from USG. It goes without saying that the inorganic insulating layer 140 can have a single layer structure that is built up either from the first inorganic insulating layer 141 or from the second inorganic insulating layer 142.

[0233] The inorganic insulating layer 140 covers an entire area of ​​the victory conductor 61 and has a variety of low potential pad openings 143 and a variety of high-potential pad openings 144, which are formed in a region outside or within the victory manager 61. The variety of low potential pad openings 143 each free the large number of low-potential terminals 11. The large number of high potential pad openings 144 each free the large number of high potential terminals 12. The inorganic insulating layer 140 can have overlap sections that sit on the circumference edge sections of the low potential terminals 11 ("Riding"). The inorganic insulating layer 140 can have overlap sections that sit on the circumference edge sections of the high potential terminals 12.

[0234] The semiconductor component 5 also includes an organic insulating layer 145, which is formed on the inorganic insulating layer 140. The organic insulating layer 145 can contain a light sensitive resin. The organic insulating layer 145 can contain at least one material from a polyimide, a polyamide and a polybenzoxazole. With this embodiment, the organic insulating layer 145 includes a polyimide. A thickness of the organic insulating layer 145 may not be less than 1 µm and not larger than 50 µm.

[0235] A thickness of the organic insulating layer 145 preferably crosses the total thickness of the inorganic insulating layer 140. Furthermore, a total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 preferably not smaller than the distance D2 between the low potential coils 22 and the high potential coils 23. In this case, the total thickness of the inorganic insulation layer is 140 preferably not less than 2 µm and not larger than 10 µm. Furthermore, the thickness of the organic insulating layer 145 is preferably not less than 5 µm and not larger than 50 µm. These structures can be suppressed that inorganic insulating layer 140 and the organic insulating layer 145 thicker, and at the same time the dielectric standing voltage on the high potential coils can be increased, namely by a laminated film from the inorganic insulating layer 140 and the organic insulating layer 145.

[0236] The organic insulating layer 145 includes a first section 146, which covers a region on a low potential side and a second section 147 that covers a region on a high potential side. The first section 146 covers the winner 61, namely via the inorganic insulating layer 140. The first section 146 has a variety of low-potential terminal openings 148, the respective of the large number of low-potential minals 11 (low-potential pad openings 143) in the region outside the victory manager 61. The first section 146 can have an overlap section that sits on the edge of the circumference (overlap section) of the low potential pad openings 143.

[0237] The second section 147 is formed with a distance ("interval") of the first section 146 and releases the inorganic insulating layer 140 between itself and the first section 146. The second section 147 has a variety of high-potential minals 149, which expose the respective of the large number of high potential terminals 12 (high potential pad openings 144). The second section 147 can have overlap sections that sit on the part of the circumference (overlap section) of the high potential pad openings 144.

[0238] The second section 147 completely covers the transformers 21a to 21d and the dummy pattern 85. In particular, the second section 147 covers the multitude of high potential coil 23, the multitude of high potentials 12, the first high potential dummy pattern 87, the second high-potential dummy pattern 88 and the floating dummy pattern 121.

[0239] If the organic insulating layer 145 is not formed, the variety of high potential coil 23, the large number of high potential terminals 12, the winner 61, the first high potential dummy pattern 87, the second high potential dummy pattern 88 and the floating dummy pattern 121 damage due to a filler ("Filler") Housing body 2 (cast resin) is included. This type of damage is referred to as a filler or filling agent attack ("Filler Attack").

[0240] The organic insulating layer 145 protects the multitude of high potential coil 23, the multitude of high potential dinals 12, the winner 61, the first high potential dummy pattern 87, the second high potential dummy pattern 88 and the floating dummy pattern 121, which contains in the case resin 2 (cast resin) is. A slit between the first section 146 and second section 147 acts as an anchor section in relation to the main case 2 (cast resin, "Molded resin").

[0241] A section of the case of the housing body 2 (cast resin) joins the slot between the first section 146 and the second section 147 and is connected to the inorganic insulating layer 140. An adhesion or adhesion ("adhesion force") of the case of the housing body 2 (cast resin) at the semiconductor component 5 is increased. It goes without saying that the first section 146 and the second section 147 can be trained. Furthermore, the organic insulating layer 145 may only contain the first section 146 or second section 147. In this case, however, a filling agent attack ("Filler Attack") must be taken into account.

[0242] Fig. 15 is a graph of medium current dielectric thirsty tension ("Average instantaneous dielectric breakdown voltages"). In Fig. 15 The ordinate specifies the medium current dielectric penetration voltage [KV · RMS], and the abscissa indicates the object. A higher average current dielectric penetration tension means that the standing tension of the insulating layer is 51 higher. A first beam G1, a second bar G2, a third bar G3 and a fourth bar G4 are in Fig. 15 shown.

[0243] The first beam G1 shows the mean current dielectric penetration voltage of the semiconductor component 5 according to a first structure. In the semiconductor component 5 according to the first structure, the dummy pattern 85 is not formed. The second beam G2 shows the mean current dielectric penetration voltage of the semiconductor component 5 according to a second structure. In the semiconductor component 5 according to the second structure, the dummy pattern 85, which only contains the second high potential dummy pattern 88, is formed.

[0244] The third beam G3 shows the middle current dielectric penetration voltage of the semiconductor component 5 according to a third structure. In the semiconductor component 5 according to the third structure, the dummy pattern 85 is formed, which only contains the floating dummy pattern 121 and the second high potential dummy pattern 88. The fourth beam G4 shows the middle current dielectric fault voltage of the semiconductor component 5 according to a fourth structure. In the semiconductor component 5 according to the fourth structure, the dummy pattern 85 is formed, which includes the first high potential dummy pattern 87, the second high potential dummy pattern 88 and the floating dummy pattern 121.

[0245] With reference to the first beam G1 and the second bar G2, the average current dielectric penetration voltage is increased by 11.2%, namely by forming the second high potential dummy pattern 88. With reference to the second bar G2 and the third bar G3, the average current dielectric penetration voltage is increased by 13.2% Floating dummy pattern 121 In addition to the second high potential dummy pattern 88.

[0246] With reference to the third bar G3 and the fourth bar G4, the mean current dielectric penetration voltage is increased by 6.2%, namely by forming the first high-potential dummy pattern 87 in addition to the second high potential dummy pattern 88 and the floating dummy pattern 121. Current dielectric penetration tension increased by 13.37% by forming the first high potential dummy pattern 87, the second high potential dummy pattern 88 and the floating dummy pattern 121.

[0247] Fig. 16 is a diagram that is obtained by examining equipotial lines (electrical field distribution) near a high potential coil 23, namely by simulation. The electrical field distribution of the semiconductor component 5 according to the first structure described above is in Fig. 16 shown. With reference to Fig. 16, surround ("Wrap") In the case of the semiconductor component 5 according to the first structure, the equipotial lines an upper side of the high -potential coil 23 or wrap them and concentrate on a circumferential edge of the high potential coil 23. The average current dielectric penetration tension is reduced by this type of electrical field concentration.

[0248] Fig. 17 is a diagram that is obtained by examining equipotial lines (electrical field distribution) in a neighborhood or closeness of the first high potential dummy pattern 87, namely by simulation. The electrical field distribution of the semiconductor component 5 according to the fourth structure described above is in Fig. 17 shown. With reference to Fig. 17 Calculate ("bypass") in the case of the semiconductor component 5 according to the fourth structure The equipotial lines the high potential coil 23 and the first high potential dummy pattern 87 and emerge towards the top of the first high potential dummy pattern 87. This means that in the case of the semiconductor component 5 according to the fourth structure, the electrical field is not concentrated on the high potential coil 23. The average current dielectric penetration voltage can be increased.

[0249] Although a special presentation is omitted, the second high potential dummy pattern 88 shows the same effect as the first high potential dummy pattern 87. That means in a neighborhood of the second high potential dummy pattern 88 the equipotial lines 23 and the second high-potential dummy pattern 88 and occur to an upper side of the second High potential dummy pattern 88. The electrical field concentration with regard to the high potential coil 23 can be suppressed, and the average current dielectric penetration tension can be increased.

[0250] Fig. 18 is a diagram that is obtained by examining an electrical field distribution near the floating dummy pattern 121, namely by simulation. The electrical field distribution of the semiconductor component 5 according to the fourth structure described above is in Fig. 18 shown. With reference to Fig. 18 In the case of the semiconductor component 5, according to the fourth structure, the equipotial lines towards the upper side of the high potential coil 23, namely from regions between neighboring sections of the floating dummy pattern 121. This means, in the case of the semiconductor component 5 according to the fourth structure, the electrical field, the electrical field, the upper side of the high potential coil 23 Exit, thinned out by the floating dummy pattern 121 ("Thinned Out"). The electrical field concentration with regard to the high potential coil 23 can be suppressed, and the average current dielectric penetration voltage can therefore be increased.

[0251] More precisely, the equipotial lines start from the regions between neighboring sections of the floating dummy pattern 121 towards an upper side of the high potential dummy pattern 86. This means that in the case of the semiconductor component 5 according to the fourth structure, the electrical field, which exits the upper side of the high potential dummy pattern 86, is thinned out by the floating dummy pattern 121.

[0252] In the dummy pattern 85, which contains the high potential dummy pattern 86 and the floating dummy pattern 121, the high potential dummy pattern 86 keeps the electrical field that exit to the upper side of the high potential coil 23. Floating dummy pattern 121 in a region that is separated from the high potential coil 23, the electrical field, which ends towards the upper side of the high potential dummy pattern 86, in directions away from the high potential coil 23 and the high potential dummy pattern 86. This can be supposedly suppressed, and the average current dielectric penetration voltage can therefore be increasingly increased.

[0253] It was therefore found that the electrical field concentration in relation to the high potential coil can be suppressed and the average current dielectric penetration tension can be increased, namely by forming the dummy pattern 85, which contains the first high-potential dummy pattern 87, the second high-potential dummy pattern 88 and the floating dummy pattern. It was also found out from the results of the Fig. 16, the Fig. 17 And the Fig. 18 that it is sufficient if the dummy pattern 85 contains at least one of the first high potential dummy pattern 87, the floating dummy pattern 121 and the second high potential dummy pattern 88.

[0254] As described above, the semiconductor component 5 includes the semiconductor chip 41, the insulating layer 51, the first functional component 45, the low -potential terminals 11, the high -potential minals 12 and the winner 61. The insulating layer 51 is formed on the first main area 42 of the semiconductor chip 41. The first functional component 45 is formed inside the insulating layer 51. The low -potential terminals 11 are formed on the insulating layer 51 and are electrically connected to the first functional component 45.

[0255] The high -potential terminals 12 are formed on the insulating layer 51, with distances from the low -potential terminals 11, and are electrically connected to the first functional component 45. The winner 61 is embedded as a wall in the insulating layer 51 to differentiate a region that contains the first functional component 45, the low -potential terminals 11 and the high -potential terminals 12, and is electrically separated from another region, and is electrically separated or isolated from the semiconductor chip 41, the first functional component 45, the low -potential terminals 11 and the High potential terminals 12.

[0256] This structure can suppress an undesirable line ("Conduction") between the high potential terminals 12 and the winner 61 if a voltage is created to the low -potential terminals 11 and the high potential terminals 12. Furthermore, an undesirable line between the low -potential terminals 11 and the winner 61 can also be suppressed. An undesirable line between the first functional component 45 and the winner 61 can also be suppressed. A standing voltage can therefore be improved.

[0257] In this structure, the winner 61 is preferably defined in the electrically floating state. With this structure, it can be reliably suppressed that the winner 61 forms a power path. An undesirable management of the victory conductor 61 can thus be supposedly suppressed.

[0258] The winner 61 is preferably embedded in the insulating layer 51 with a distance ("interval") in the normal direction Z from the first main area 42 of the semiconductor chip 41. Due to this structure, the victory conductor 61 can be electrically expediently separated or separated from the semiconductor chip 41. A mutual line between the semiconductor chip 41 and the winner 61 can therefore be supposedly suppressed.

[0259] The semiconductor component 5 also prefers to include the separation structure 130, which is arranged between the semiconductor chip 41 and the winner 61 and which electrically separates the semiconductor chip 41 from the victory conductor 61. Due to this structure, the victory conductor 61 can be electrically expediently separated from the semiconductor chip 41, namely by the separation structure 130.

[0260] The separation structure 130 can include the field insulating film 131, which is formed in the first main area 42 of the semiconductor chip 41. The separation structure 130 can include the ditch 135, which is formed in the first main area 42, and contain the embedded body 136, which is embedded in the ditch 135. The embedded body 136 is so embedded in the ditch 135 that it is electrically separated from the semiconductor chip 41. To be more precise, the embedded body 136 in the ditch 135 is so embedded that it is in the electrically floating state. The separation structure 130 can be formed using a section of the insulating layer 51.

[0261] The separation structure 130 is preferably free on the chip side walls 44a up to 44d of the semiconductor chip 41. Even if the winner 61 is formed in such a way that it is transferred to the pages of the chip side walls 44a up to 44d, the victory ladder 61 can be advised by this structure with the separation structure 130, since the separation structure, which is exposed on the chip pages 44a to 44d, is formed on the circumference of the first main area 42.

[0262] The insulating side walls 53a up to 53D of the insulating layer 51 are preferably continuously trained with the chip pages 44a up to 44d of the semiconductor chip 41. Furthermore, the insulating layer 51 is preferably continuously trained with the external final section 130b of the separation structure. Insulating layer 51 and the separation structure 130.

[0263] The winner 61 is preferably formed in a ring shape, which in a top view surrounds the first functional component 45, the low -potential terminals 11 and the high potential terminals 12. This structure can be used to protect the first functional component 45, the low -potential d are 11 and the high -potential terminals 12 using the victory conductor 61.

[0264] The semiconductor component 5 includes the inorganic insulating layer 140, which covers the winner 61 on the insulating layer 51. The inorganic insulating layer 140 has the low potential pad openings 143 and the high potential pad openings 144, which are formed in the region outside ("outside") of the winning manager 61. The low-potential pad openings 143 release the low-potential terminals 11, and the high potential pad openings 144 freely lay the high potential terminals. This structure can be protected by this structure 61, and an insulating property of the victory conductor 61 with regard to the outer environment can be increased at the same time using the inorganic insulating layer 140.

[0265] The semiconductor component 5 also includes the organic insulating layer 145, which is formed on the inorganic insulating layer 140, in such a way that it covers the victory conductor 61 across the inorganic insulating layer 140. This structure can be protected by this structure 61 and the insulating property of the victory conductor 61 with regard to the outer environment can also be increased by the organic insulating layer 145.

[0266] The first functional component 45 can contain transformers 21 (passive components), which are formed inside the insulating layer 51. The transformers 21 include the low potential coils 22 (low potential pattern), which are formed inside the insulating layer 51, and the high potential coil 23 (high potential pattern), which are formed in this way inside the insulating layer 51 in such a way that they are compared to the low potential coil 22 in the normal direction. The high potential coil 23 are opposite the semiconductor chip 41 over the low potential coils 22. The low potential coil 22 are electrically connected to the low -potential terminals 11, and the high potential coil 23 are electrically connected to the high -potential terminals 12.

[0267] With this structure, an undesirable line between the high -potential terminals 12 and the victory conductor 61 can be suppressed if a voltage to transformers 21 is created via the low -potential terminals 11 and the high potential terminals 12. Furthermore, an undesirable line between the low -potential terminals 11 and the victory conductor 61 can be suppressed if a voltage to transformers 21 is created via the low -potential terminals 11 and the high potential terminals 12. Furthermore, an undesirable management between transformers 21 and the winner 61 can be suppressed if a voltage to transformers 21 is created via the low -potential terminals 11 and the high potential terminals 12.

[0268] The semiconductor component 5 also includes the second functional component 60, which is formed on the first main area 42 of the semiconductor chip 41. The insulating layer 51 covers the second functional component 60. The low -potential terminals 11 and the high potential terminals 12 are electrically connected to the second functional component 60. The winner 61 borders a region that contains the second functional component 60, from another region in a top view and is electrically separated from the second functional component 60.

[0269] With this structure, an undesirable line between the second functional component 60 and the victory conductor 61 can be suppressed if a voltage is created to the low -potential terminals 11 and the high -potential terminals 12. Therefore, 5 effects can be used by the semiconductor component, which are the same effects that have been shown between the first functional component 45 and the winner 61, also between the second functional component 60 and the victory manager 61.

[0270] Furthermore, the semiconductor component 5 includes the dummy pattern 85, which is formed inside the insulating layer 51 so that it is positioned in the perspective in the peripheries of high potential coil 23. The dummy pattern 85 shields the electrical fields, which are formed between the low potential coil 22 and the high potential coil 23, and suppresses an electrical field concentration with regard to the high potential coil 23. As a result, the electrical field concentration with regard to the high potential coils can be suppressed, and the wicker stagger Throughout tension) can be improved. Furthermore, with the semiconductor component 5, an undesirable line between the dummy pattern 85 and the winner 61 can be suppressed if a voltage is created to the low-potential terminals 11 and the high potential terminals 12. An improvement effect regarding the standing voltage can therefore be implemented using the dummy pattern 85 and the winner 61.

[0271] With this embodiment, the dummy pattern 85 is arranged in the regions between neighboring the multitude of high potential coil 23, seen in a top view. The electrical field concentration in relation to the variety of high potential coil 23 can be suppressed, using the regions between neighboring the multitude of high potential coil 23.

[0272] With this embodiment, the dummy pattern 85 is arranged in the region between the low-potential minals 11 and the high potential coil 23, seen in the top view. An undesirable line between the low -potential terminals 11 and the high potential coil 23 due to the electrical field concentration on the high potential coil 23 can be suppressed.

[0273] With this embodiment, the dummy pattern 85 is arranged in a top view in the region between the low-potential terminals 11 and the high potential terminals 12. An undesirable line between the low -potential terminals 11 and the high potential terminals 12 due to the electrical field concentration on the high potential coil 23 can be suppressed.

[0274] With this embodiment, the dummy pattern 85 is arranged in a top view in a region between the winner 61 and the high potential coil 23. An undesirable line between the winner 61 and the high potential coil 23 due to the electrical field concentration on the high potential coil 23 can be suppressed.

[0275] With this embodiment, the dummy pattern 85 is arranged in a top view in a region between the winner 61 and the high potential terminals 12. An undesirable line between the winner 61 and the high potential terminals 12 due to the electrical field concentration on the high potential coil 23 can be suppressed.

[0276] With this embodiment, the dummy pattern 85 includes the high potential dummy pattern 86, which is formed in a top view in the peripheries of high potential coil 23. The high potential dummy pattern 86 suppresses that in the region of the peripheral of the high potential coils 23 electrical fields to the upper sides of the high potential coils 23 sprinkle out ("Leaking out"). The electrical field concentration in relation to high potential coil 23 can thus be properly suppressed in the region of the peripheries of high potential coil 23.

[0277] The dummy pattern 85 includes the first high potential dummy pattern 87, which is arranged in a top view in the regions between neighboring the multitude of high potential coil 23. The first high-potential dummy pattern 87 suppresses that in the regions between neighboring the large number of high potential coils 23 electrical fields to the upper sides of the multitude of high potential coil 23. The electrical field concentration in relation to the large number of high potential coil 23 can thus be supposedly suppressed in the regions between neighboring the large number of high potential coil 23.

[0278] Furthermore, the dummy pattern 85 includes the second high potential dummy pattern 88, which is positioned in a top view in the region outside the regions between neighboring the large potential coil 23. The second high-potential dummy pattern 88 suppresses that in the region outside the regions between neighboring the large number of high potential coils, 23 electrical fields sprinkle out towards the upper sides of the large number of high potential coils 23. The electrical field concentration in relation to the large number of high potential coil 23 can thus be supposedly suppressed in the region outside the regions between neighboring the large number of high potential coil 23.

[0279] Furthermore, the dummy pattern 85 includes the floating dummy pattern 121, which is formed in the electrically floating state in the peripheries of high potential coil 23. The floating dummy pattern 121 shields the electrical fields between the low potential coil 22 and the high potential coil 23 in order to dispel the electrical fields that step out towards the upper sides of the high potential coil 23 ("disperse"). An electrical field concentration with regard to high potential coil 23 can be suppressed.

[0280] Furthermore, the floating dummy pattern 121 in the periphery of the high potential dummy pattern 86 is scattered the electrical fields that emerge towards the upper side of the high potential dummy pattern 86. As a result, the electrical field concentration with regard to the high potential dummy pattern 86 can be suppressed, and at the same time the electrical field concentration can be supposedly suppressed in terms of high potential coils 23. In this structure, it is preferred if the winner 61 is formed, which is in the electrically floating state. In this case, the victory ladder 61 does not cause a voltage drop in relation to the floating dummy pattern 121. An undesirable line between the dummy pattern 85 and the winner 61 can therefore be supposedly suppressed.

[0281] How off Fig. 16, the dummy pattern 85 preferably includes all patterns or structures from the first high potential dummy pattern 87, the floating dummy pattern 121 and the second high potential dummy pattern 88. However, the average current dielectric penetration voltage can be improved even with a dummy pattern 85, which is only one or two of the first High potential dummy pattern 87, the floating dummy pattern 121 and the second high potential dummy pattern 88 include.

[0282] This means that a dummy pattern 85 can be used that only has the first high potential dummy pattern 87. A dummy pattern 85 can also be used, which only has the second high potential dummy pattern 88. A dummy pattern 85 can also be used, which only has the floating dummy pattern 121.

[0283] A dummy pattern 85 can also be used, which only has the first high potential dummy pattern 87 and the second high potential dummy pattern 88. A dummy pattern 85 can also be used, which only has the first high potential dummy pattern 87 and the floating dummy pattern 121. A dummy pattern 85 can also be used, which only has the second high potential dummy pattern 88 and the floating dummy pattern 121.

[0284] Furthermore, the first high potential dummy pattern 87 can be changed to a floating dummy pattern 121. The first high potential dummy pattern 87 and the second high potential dummy pattern 88 can also be changed in floating dummy pattern 121.

[0285] Such floating dummy patterns 121 are formed by the first high potential dummy pattern 87 and the second high potential dummy pattern 88 from the high potential connection wires 81 (high potential dinals 12a to 12f) ("Disconnecting"). In the floating dummy pattern 121, voltage waste in relation to the high potential coil 23 is not formed, because of this because it is formed in the electrically floating state. Therefore, with the floating dummy pattern 121, the electrical field concentration with regard to the high potential coils 23 can be suppressed, while an increase in the electrical field strength in relation to high potential coils 23 is suppressed. In the case of the floating dummy pattern 121, however, the presence of electrical fields should be taken into account, which leads to the top side of the high potential coil 23.

[0286] Furthermore, the floating dummy pattern 121 can be changed to a second high potential dummy pattern 88. In this case, however, the electrical field strengths between the low-potential terminals 11 (winning ladder 61) and the second high potential dummy pattern 88 increase, as a result that distances between the low potential minals 11 (victory manager 61) and the second high potential dummy pattern 88 become narrow or close. One possibility that an undesirable electrical field concentration on the high potential coils 23 and the second high potential dummy pattern 88 can occur if the electrical field strengths increase should be taken into account.

[0287] Fig. 19 is a top view accordingly Fig. 7 And is a top view of a semiconductor component 161 according to a second preferred embodiment of the present invention. Fig. 20 is a cutting view along a line XX-XX that is in Fig.19 is shown. The following are structures below that correspond to the structures described in relation to the semiconductor component 5, and a description of this is omitted. In Fig. 20 is shown an example in which the separation structure 130 (field insulating film 131) is realized according to the first configuration example (see also Fig. 13). With the semiconductor component 161 according to the second preferred embodiment, however, any of the separation structures 130 can be formed according to the second to fifth configuration examples instead of the separation structure 130 in accordance with the first configuration example (see also Fig. 14a to Fig. 14D).

[0288] With reference to Fig. 19 and 19 Fig. 20 includes the dummy pattern 85 of the semiconductor component 161 Furthermore, a low potential dummy pattern 162. In Fig. 19 is shown the low-potential dummy pattern 162 by thick lines. The low-potential dummy pattern 162 is preferably formed from the same conductive materials as the low potential coil 22, etc. This means that, as with the low potential coil 22, etc.

[0289] The low-potential dummy pattern 162 is formed from a pattern (discontinuous pattern), differs from the high potential coil 23 and the low potential coil 22 and which is independent of the transformers 21a to 21d. This means that the low-potential dummy pattern 162 does not work as the transformers 21a to 21d or does not contribute to their function. A tension that is smaller than the voltage set to the high potential terminals 12 is placed on the low-potential dummy pattern 162. The voltage set to the low-potential terminals 11 (that is, the reference voltage) is preferably created to the low-potential dummy pattern 162. This means that the low-potential dummy pattern 162 is preferably set to the same potential as the low potential dates 11. The low potential dummy pattern 162 contains a connecting section 163, which is connected to any second or first electrode layer 79 and 78.

[0290] The low-potential dummy pattern 162 is formed in a top view of peripheral of low-potential terminals 11. More precisely, the low-potential dummy pattern 162 is formed in a top view in regions in a narrow neighborhood or closeness to the low-potential minals 11 than the or ZZ the high potential coil 23 (high-potential minals 12). The fact that the low-potential dummy pattern 162 is in the neighborhood for the low potential dates 11, in a top view, means that a distance between the low-potential dummy pattern 162 and a low-potential terminal 11 is smaller than a distance between the low potential dummy pattern and a high potential coil (High potential terminal 12).

[0291] A deep position of the low-potential dummy pattern 162 in the inside of the insulating layer 51 is arbitrary and is set according to the electrical field strengths to be relaxed. The low-potential dummy pattern 162 is preferably formed in the normal direction z in regions inside the insulating layer 51 in a closer neighborhood to the low potential terminals 11 than the low potential coil 22. The fact that the low-potential dummy pattern 162 is located in the normal direction z near or neighborhood of low-potential minals 11 means that a distance between the low-potential dummy pattern 162 and a low-potential minals is smaller than a distance between the low-potential dummy pattern 162 and one Low potential coil 22. The low potential dummy pattern 162 is preferably formed within the same intermediate layer layer 57 as the high potential coil 23.

[0292] The low-potential dummy pattern 162 is preferably arranged in a top view in regions between the low-potential terminals 11 and the high potential coil 23. The low-potential dummy pattern 162 is preferably arranged in a top view in the regions between the low-potential terminals 11 and the high-potential minals 12.

[0293] In this embodiment, the low-potential dummy pattern 162 is laid with a line density that is equal to the line density of the high potential coil 23, namely per unit area ("perit area"). The fact that the line density of the low-potential dummy pattern 162 is equal to the line density of the high potential coil 23 means that the linie density of the low-potential dummy pattern 162 falls into an area of ​​± 20% of the linial density of high potential coils 23.

[0294] The low-potential dummy pattern 162 is preferably formed in a form with ends. Due to this structure, the formation of a current loop in which low potential dummy pattern 162 can be supposedly suppressed. A noise due to a current that flows through the low-potential dummy pattern 162 can be suppressed, and therefore an undesirable electrical field concentration can be suppressed due to the noise, and at the same time fluctuations of the electrical characteristics of the transformers to 21a can be supposedly suppressed.

[0295] With this embodiment, the low potential dummy pattern 162 is formed as a band that extends in the first direction X. The low-potential dummy pattern 162 crosses or crosses the large number of low potential dates 11a to 11f in a top view or runs by. The low-potential dummy pattern 162 is arranged in a top view in the regions between the low-potential terminals 11a to 11f and the variety of high potential coil 23. Furthermore, the low-potential dummy pattern 162 is arranged in a top view in the regions between the low potential terminals 11a to 11f and the high-potential minals 12A to 12F.

[0296] With this embodiment, the low-potential dummy pattern 162 includes a variety of (three with this embodiment) of low potential podium lines 164a, 164b and 164c. The large number of low potential lines 164a to 164c are formed with intervals ("intervals"), in this order based on the side of the low -potential terminals 11a to 11f to the side of the high potential minals up to 12f. The variety of low potential lines 164a to 164C are electrically connected to any low potential connection wiring 72.

[0297] The large number of low potential podium lines 164a to 164c are formed as ligaments that extend in a top view in the first direction X. This means that the large number of low potential lines 164a to 164c are formed in one top view as stripes that extend in the first direction X.

[0298] A width of each of the low potential podium lines 164a to 164c may not be less than 0.1 µm and not larger than 5 µm. The width of each of the low potential lines 164a to 164c is preferably not less than 1 µm and not larger than 3 µm. The width of each of the low potential lines 164a to 164c is defined by a width in one direction orthogonal towards the direction in which the low potential lines 164a to 164c extend. The width of each of the low potential lines 164a to 164c is preferably equal to the width of any high potential coil 23. The fact that the width of each of the low potential lines 164a to 164c is the width of every high potential coil 23 means that the width of each of the low potential lines 164a to 164c in an area of ​​± 20% of the width of Every high potential coil 23 falls.

[0299] Thirteenth distances ("pitches") between two neighboring the low potential lines 164a to 164c may not be less than 0.1 µm and not larger than 5 µm. The thirteenth distances are preferably not less than 1 µm and not larger than 3 µm. The thirteenth distances are preferably the same. The fact that the thirteenth distances are the same means that the thirteenth distances fall into an area of ​​± 20% of the thirteenth distances. Due to these structures, the imbalance in the electrical fields can be suppressed in the insulating layer 51 and consequently an undesirable electrical field concentration can be suppressed. The number, the width and distances of the low potential lines 164a up to 164c are set according to the electrical fields to be relaxed and are not restricted to specific values.

[0300] The semiconductor component 161 also includes a main area insulating layer 165, which covers the insulating area 52 of the insulating layer 51. On the insulating main area 52, the main area insulating layer 165 completely covered the low -potential terminals 11a to 11f, the high -potential minals 12a to 12f, the organic insulating layer 145, the inorganic insulating layer 140 (second inorganic insulating layer 142), etc.

[0301] The main area insulating layer 165 has a second dielectric pacification resistance BS2, which is not larger than a first dielectric pacification strength BS1 of the insulating layer 51 (BS2 ≤ BS1). More precisely, the second dielectric pacification strength BS2 is smaller than the first dielectric pacification resistance BS1 (BS2 <BS1).

[0302] To be more precise, the insulating layer includes 51 silicon oxide and / or silicon nitride and has the first dielectric pacification strength BS1 of no less than 1 mv / cm and no more than 15 mv / cm. The first dielectric pacification strength BS1 is preferably not less than 5 mv / cm and not larger than 15 mv / cm. As long as the insulating layer 51 has the first dielectric pacification strength BS1 of no less than 1 mv / cm, the insulating layer 51 can contain an insulating material next to or except silicon oxide and silicon nitride. On the other hand, the second dielectric impact strength BS2 may not be less than 0.1 mv / cm and not larger than 1 mv / cm. The second dielectric pacification strength BS2 may not be less than 0.1 mv / cm and not larger than 0.5 mv / cm.

[0303] With this embodiment, the main area insulating layer 165 is built from a layer of resin. The main area insulating layer 165 can contain at least one of an epoxy resin layer, a polyimide resin layer and a polybenzoxazol resin layer. The main area insulating layer 165 can be formed by a section of the cast resin. If the main area insulating layer 165 is formed by a section of the cast resin, the main area insulating layer 165 can be formed by a section of the case 2. This means that in a state in which it is sealed or sealed by the main case 2, the main area insulating layer 165 can include a section of the case of the housing body 2, which covers the insulating area 52 of the insulating layer 51.

[0304] Electrical field strengths between the low potential dates 11a to 11f and the high potential dummy pattern 86 are influenced or significantly influenced by a distance between the low potential dummy pattern 162 and the high potential dummy pattern 86 ("governed"). Therefore, in the insulating layer 51, the electrical field strengths between the low-potential dates 11a to 11f and the high potential dummy pattern 86 are increased due to the low potential dummy pattern 162.

[0305] On the other hand, due to the increase in the electrical field strengths in the insulating layer 51, the electrical field strengths in the main area insulation layer 165 decrease. This means that the low-potential dummy pattern 162 deliberately increases the electrical field thicknesses in the insulating layer 51 with the comparatively high first dielectric impact strength BS1, and at the same time reduces the electrical field strengths in the main area insulation layer 165, which has the comparatively low second dielectric fault strength BS2. This means that the dielectric standing voltage of the main area insulating layer 165 can be improved relatively.

[0306] In the semiconductor component 161 described above, the same effects can be shown as the effects described for the semiconductor component 5. Furthermore, the low-potential dummy pattern 162 is included in the semiconductor component 161. The dielectric standing voltage of the main area insulating layer 165 can be improved. Furthermore, the winner 61 borders the region in the semiconductor component 161, which contains the low-potential dummy pattern 162, from another region in a top view and is electrically separated from the low potential dummy pattern. With this structure, an undesirable line between the low-potential dummy pattern 162 and the winner 61 can be suppressed if a voltage is created to the low-potential terminals 11 and the high potential terminals 12. The standing voltage can therefore be increased.

[0307] Fig. 21 is a cut view of a region accordingly Fig. 8 And is a cut view of a semiconductor component 191 according to a third party preferred embodiment of the present invention. The following are structures below that correspond to the structures described in relation to the semiconductor component 5, with the same reference signs and a description of this is omitted. In Fig. 21 is shown an example in which the separation structure 130 (field insulating film 131) is realized according to the first configuration example (see also Fig. 13). In the semiconductor component 191 according to the third party preferred embodiment, however, any of the separation structures 130 can be formed according to the second to fifth configuration examples instead of the separation structure 130 in accordance with the first configuration example (see also Fig. 14a to Fig. 14D).

[0308] The semiconductor component 5 according to the first preferred embodiment has the variety of transformers 21a to 21d, each with a low potential coil 22 and a high potential coil 23. On the other hand, the semiconductor component 191 includes a large number of capacitors 192 instead of the large number of transformers 21a to 21d. The positioning of the large number of capacitors 192 is the same as the positioning of the large number of transformers 21a to 21d. In Fig. 21 is only shown a single capacitor 192.

[0309] Instead of a low potential coil 22 and a high potential coil 23, the capacitors 192 each contain a low potential electrode 193 (low potential pattern) with a flat plate shape and a high potential electrode 194 (high potential pattern) with a flat plate shape. The low-potential electrode 193 is electrically connected to the low potential terminals 11, namely via a first low potential wiring 31.

[0310] A level shape ("Planar Shape") of the low potential electrode 193 is arbitrary. The low-potential electrode 193 can be formed in a top view of a polygonal shape like a triangular shape, a four-sided form, etc., or in a circular form or an elliptical shape. The low potential electrode 193 is electrically connected to the corresponding low potential dates 11 via the corresponding first low potential wiring 31.

[0311] The high potential electrode 194 is the low potential electrode 193 in the normal direction z and accumulates a load together with the low potential electrode 193. The high potential electrode 194 is electrically connected to high potential terminals 12 via a first high potential wiring 33. The high potential electrode 194 is electrically connected to the high-potential terminals 12 via PAD plug electrode 82.

[0312] A level shape of the high potential electrode 194 is arbitrary. In a top view of a polygonal shape, the high potential electrode 194 can be formed like a triangular shape, a four-way shape, etc., or in a circular shape or an elliptical shape. The high potential electrode 194 is electrically connected to the corresponding high-potential terminals 12 via the corresponding first high potential wiring 33.

[0313] In the semiconductor component 191, which was described above, the same effects as those effects that have been described for semiconductor components 5 can be shown. The semiconductor component 191 can also contain the low potential dummy pattern 162 in accordance with the second preferred embodiment.

[0314] The preferred embodiment of the present invention can be implemented in further embodiment.

[0315] In each of the preferred embodiment described above, the semiconductor component 5, 161 or 191 can have the separation structure 130 with a structure, in which at least two from the separation structures 130 are combined in any form in accordance with the first to fifth configuration examples.

[0316] In each of the preferred embodiment described above, an example was described in which the first functional component 45 and the second functional component 60 are formed. However, a configuration can be used, which does not have the first functional component 45 and has only the second functional component 60. In this case, the dummy pattern 85 can be removed. This structure shows the same effects as those effects that have been described in the first preferred embodiment in relation to the second functional component 60 (exclusively the effects relating to the dummy pattern 85).

[0317] This means that the undesirable management between the high potential dates 12 and the winner 61 can be suppressed if a voltage to the second functional component 60 is created via the low potential terminals 11 and the high potential minals 12. Furthermore, the undesirable management between the low -potential terminals 11 and the victory conductor 61 can be suppressed if a voltage via the low -potential terminals 11 and the high -potential terminals 12 is created to the second functional component 60.

[0318] Furthermore, an example in which the second functional component 60 is formed was described for each of the preferred embodiment described above. However, the second functional component 60 is not necessarily necessary and can be omitted.

[0319] Furthermore, an example was described in each of the preferred embodiment described above, in which the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily necessary and can be omitted.

[0320] Furthermore, an example was described for each of the preferred embodiment described above, in which the first functional component 45 is structured from the component of the multi -channel type, which contains the variety of transformers 21. However, a first functional component 45 can be used, which is made of a single sewer type that contains a single transformer 21.

[0321] Examples of characteristics that can be extracted from the present description and drawings are specified below. The following elements [A1] to [A19] each provide a semiconductor component, in which a standing voltage can be improved in a structure that contains a victory conductor ("Seal Conductor").

[0322] [A1] semiconductor component with a semiconductor chip that has a main area, an insulating layer formed on the main area, a functional component that is formed in at least one element of the semiconductor chip and the insulating layer, a low potential terminal that is formed on the insulating layer and the electrically connected to the functional component, a high -potential terminal that is on the insulating layer a distance from the low -potential terminal and which is electrically connected to the functional component, and with a victory ladder that is embedded as a wall in the insulating layer in order to separate a region that contains the functional component, the low potential terminal and the high -potential mineral, from a different region, and the electrically from the semiconductor chip, the functional component, the functional component Low potential terminal and the high potential terminal is separated.

[0323] According to this semiconductor component, an undesirable line ("Conduction") can be suppressed between the high potential terminal and the victory conductor if a tension is created on the low potential terminal and the high potential terminal. Furthermore, an undesirable line between the low -potential terminal and the victory conductor can be suppressed. Furthermore, an undesirable line between the functional component and the victory manager can be suppressed. The standing voltage can therefore be improved.

[0324] [A2] semiconductor component according to A1, with the victory manager being defined in an electrically floating or potential -free state.

[0325] [A3] semiconductor component according to A1 or A2, whereby the victory ladder is embedded in the insulating layer at a distance from the semiconductor chip in a normal direction.

[0326] [A4] semiconductor component according to any from A1 to A3, also with a separation structure that is arranged between the semiconductor chip and the victory manager and which electrically separates the victory manager from the semiconductor chip.

[0327] [A5] semiconductor component according to A4, whereby the separation structure contains an insulating film that is formed on the main area of ​​the semiconductor chip.

[0328] [A6] semiconductor component according to A4, whereby the separation structure includes a ditch that is formed in the main area, and includes a embedded body that is embedded in the ditch to be electrically separated from the semiconductor chip.

[0329] [A7] semiconductor component according to A4, whereby the separation structure is built up from a section of the insulating layer.

[0330] [A8] semiconductor component according to any of A4 to A7, the separation structure exposed on a side wall of the semiconductor chip.

[0331] [A9] semiconductor component according to any from A1 to A8, whereby the insulating layer has an insulating side wall that is continuously trained with the side wall of the semiconductor chip.

[0332] [A10] semiconductor component according to any from A1 to A9, whereby the victory ladder is formed in a top view into a ring shape that surrounds the functional component, the low -potential terminal and the high -potential terminal.

[0333] [A11] semiconductor component according to any from A1 to A10, also with an inorganic insulating layer that covers the victory ladder on the insulating layer and which has a variety of PAD openings, each exposing the low-potential terminal or the high potential terminal.

[0334] [A12] Shalk ladder component according to A11, also with an organic insulating layer that is formed on the inorganic insulating layer to cover the winner over the inorganic insulating layer.

[0335] [A13] semiconductor component according to any from A1 to A12, whereby the functional component is a low potential pattern that is formed inside the insulating layer and includes a high potential pattern that is formed inside the insulating layer, so that in a normal direction it is opposite the low potential pattern, where Low potential pattern is connected and the high potential terminal is electrically connected to the high potential pattern.

[0336] [A14] semiconductor component according to A13, whereby the high potential pattern is opposite the semiconductor chip over the low potential pattern.

[0337] [A15] Halfcase component according to A13 or A14, whereby the functional component is a transformer that includes a low potential coil as the low potential pattern and a high potential coil as the high potential pattern.

[0338] [A16] semiconductor component according to A13 or A14, whereby the functional component is a capacitor that contains a low potential electrode than the low potential pattern and a high potential electrode as the high potential pattern.

[0339] [A17] semiconductor component according to any from A1 to A12, whereby the functional component contains at least one component of a passive component, a semi -layer component and an switching semiconductor component and is formed in the main area of ​​the semiconductor chip.

[0340] [A18] semiconductor component according to any from A1 to A12, whereby the functional component is a first functional component that is formed in the insulating layer and contains a second functional component that is formed in the semiconductor chip.

[0341] [A19] semiconductor component with a semiconductor chip that has a main area, an insulating layer formed on the main area, a low potential pattern that is formed inside the insulating layer, a high potential pattern that is formed inside the insulating layer, so that in a normal direction it is opposite the low-potential pattern, a dummy pattern that is a periphery of the high potential pattern inside the insulating layer is formed, which contains a ladder and which shields an electrical field between the low potential pattern and the high potential pattern, a low -potential minal that is formed on the insulating layer and connected electrically to the low -potential pattern, a high -potential minal on the insulating layer with a distance from the low-potential terminal is formed and which is electrically connected to the high potential pattern, and with a winner that is embedded as a wall in the insulating layer to include a region that includes the low potential pattern, the high potential pattern, the dummy pattern, the low-potential terminal and the high-potential minals, and from another region, and from another region, and to be distinguished from another region, and The electrical is separated from the semiconductor chip, the low potential pattern, the high potential pattern, the dummy pattern, the low-potential terminal and the high potential terminal.

[0342] According to this semiconductor component, an electrical field concentration with regard to the high potential pattern can be suppressed using the dummy pattern if a voltage is created to the low potential terminal and the high-potential terminal. Furthermore, according to this semiconductor component, an undesirable line between the high potential pattern (high -potential terminal) and the victory conductor can be suppressed if a tension is created on the low potential terminal and the high -potential terminal. Furthermore, an undesirable line between the low potential pattern (low -potential terminal) and the winner can be suppressed. An undesirable line between the dummy pattern and the winner can also be suppressed. The standing voltage can therefore be improved.

[0343] The present registration corresponds to the Japanese patent application with the No. 2019-217565, which was registered on November 19, 2019 at the Japanese Patent Office and whose total disclosure is included in the present case by reference. Although preferred embodiment of the present invention has been described in detail, these are only special examples that are used to illustrate the technical content of the present invention, and the present invention should not be interpreted in such a way that it is restricted to these specific examples, and the area of ​​protection of the present invention is limited by the attached claims. Reference sign list 11 Low potential terminal 12 high potential terminal 21 transformer 22 Low potential coil 23 high potential coil 41 semiconductor chip 42 First main area 43 second main area 44a first chip pages wall 44b second chip pages wall 44c third chip pages wall 44d fourth chip pages wall 45 first functional component 51 insulating layer 53a first isolating side wall 53b second insulating side wall 53c third insulation side wall 53d fourth insulating side wall 60 second functional component 61 Siegelleiter ("Seal Conductor") 85 dummy pattern 130 separation structure 131 field insulating film 135 ditch 136 embedded body 140 inorganic insulating film 145 organic insulating film 161 semiconductor component 191 semiconductor component 192 capacitor 193 Low potential electrode 194 High potential electrode Quotes contain in the description

[0000] This list of documents listed by the applicant was automatically created and is only included in the reader's better information. The list is not part of the German patent or utility model registration. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2006261613

[0003] JP 2019217565

[0343]

Claims

[1] Semiconductor component, with: a semiconductor chip that has a main area; an insulating layer formed on the main surface; a functional component formed in at least one of the semiconductor chip and the insulating layer; a low-potential terminal formed on the insulating layer and electrically connected to the functional component; a high-potential terminal formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the functional component; and with a sealing conductor embedded as a wall in the insulating layer to separate, in a top view, a region containing the functional component, the low-potential terminal and the high-potential terminal from another region, and which is electrically separated from the semiconductor chip, the functional component, the low-potential terminal and the high-potential terminal. [2] Semiconductor component according to claim 1, wherein the sealing conductor is fixed in an electrically suspended state. [3] Semiconductor component according to claim 1 or 2, wherein the sealing conductor is embedded in the insulating layer at a distance from the semiconductor chip in a normal direction to the main surface. [4] Semiconductor component according to any one of claims 1 to 3, further comprising: a separating structure that is positioned between the semiconductor chip and the sealing conductor and that electrically separates the sealing conductor from the semiconductor chip. [5] Semiconductor component according to claim 4, wherein the separation structure includes an insulating film formed on the main surface of the semiconductor chip. [6] Semiconductor component according to claim 4, wherein the separation structure includes a trench formed in the main surface and an embedded body embedded in the trench to be electrically separated from the semiconductor chip. [7] Semiconductor component according to claim 4, wherein the separation structure is composed of a section of the insulating layer. [8] Semiconductor component according to any one of claims 4 to 7, wherein the separation structure is exposed on a side wall of the semiconductor chip. [9] Semiconductor component according to any one of claims 1 to 8, wherein the insulating layer has an insulating sidewall which is continuous with the sidewall of the semiconductor chip. [10] Semiconductor component according to any one of claims 1 to 9, wherein the sealing conductor is formed in a top view into a ring shape surrounding the functional component, the low potential terminal and the high potential terminal. [11] Semiconductor component according to any one of claims 1 to 10, further comprising: an inorganic insulating layer covering the sealing conductor on the insulating layer and having a multitude of pad openings, each exposing the low potential terminal and the high potential terminal. [12] Semiconductor component according to claim 11, further comprising: an organic insulating layer formed on top of the inorganic insulating layer to cover the sealing conductor over the inorganic insulating layer. [13] Semiconductor component according to any one of claims 1 to 12, wherein the functional component includes a low-potential pattern formed inside the insulating layer and a high-potential pattern formed inside the insulating layer such that it is opposite the low-potential pattern in a normal direction to the main surface, wherein the low-potential terminal is connected to the low-potential pattern, and wherein the high-potential terminal is electrically connected to the high-potential pattern. [14] Semiconductor component according to claim 13, wherein the high potential pattern is opposite the semiconductor chip across the low potential pattern. [15] Semiconductor component according to claim 13 or 14, wherein the functional component is a transformer comprising a low-potential coil as the low-potential pattern and a high-potential coil as the high-potential pattern. [16] Semiconductor component according to claim 13 or 14, wherein the functional component is a capacitor comprising a low-potential electrode as the low-potential pattern and a high-potential electrode as the high-potential pattern. [17] Semiconductor component according to any one of claims 1 to 12, wherein the functional component comprises at least one of a passive component, a rectifying semiconductor component and a switching semiconductor component and is formed in the main area of ​​the semiconductor chip. [18] Semiconductor component according to any one of claims 1 to 12, wherein the functional component comprises a first functional component formed in the insulating layer and a second functional component formed in the semiconductor chip. [19] Semiconductor component, with: a semiconductor chip that has a main area; an insulating layer formed on the main surface; a low-potential pattern formed inside the insulating layer; a high-potential pattern formed inside the insulating layer, such that it is opposite the low-potential pattern in a normal direction to the main surface; a dummy pattern formed in a periphery of the high-potential pattern inside the insulating layer, which includes a conductor and shields an electric field between the low-potential pattern and the high-potential pattern; a low-potential terminal formed on the insulating layer and electrically connected to the low-potential pattern; a high-potential terminal formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the high-potential pattern; and a sealing conductor embedded as a wall in the insulating layer to separate, in a top view, a region containing the low-potential pattern, the high-potential pattern, the dummy pattern, the low-potential terminal and the high-potential terminal from another region, and which is electrically separated from the semiconductor chip, the low-potential pattern, the high-potential pattern, the dummy pattern, the low-potential terminal and the high-potential terminal.