Symbol filtering on a phy side of a phy-mac interface

Abstract

Disclosed examples include a method. The method includes: communicating symbols from a PHY to a MAC via a PHY side of a PHY-MAC interface and filtering one or more symbols at an input of a PHY side of an interface wrapper of the PHY side of the PHY-MAC interface. Disclosed examples include an apparatus. The apparatus includes: a PHY side of a PHY-MAC interface and logic circuitry provided on the PHY side of a PHY-MAC interface, the logic circuitry comprising a symbol filter for filtering one or more symbols communicated via the PHY side of a PHY-MAC interface.

Description

PRIORITY CLAIM

[0001] This application claims the benefit of the filing date of Chinese Patent Application No. 202210950844.7 filed on August 9, 2022 for “SYMBOL FILTERING AT A PHY-SIDE OF PHY-MAC INTERFACE,” the disclosure of which is hereby incorporated by reference in its entirety. AREA

[0002] One or more examples relate to physical layer (PHY)-media access control (MAC) interfaces, and more specifically, one or more examples relate to PHY-side PHY-MAC interfaces and PHY-side interface wrappers with symbol-filtered inputs. BACKGROUND

[0003] Interconnects are widely used to support communication between a network's devices, subsystems, and systems. Generally speaking, electrical signals are transmitted on a physical medium (such as, but not limited to, a bus, coaxial cable, or twisted pair cable—commonly referred to simply as a "wire" or "bus") from the devices coupled to the physical medium.

[0004] Ethernet-based computer networking technologies, according to the Open Systems Interconnection (OSI) model, use baseband transmission (i.e., electrical signals are discrete electrical pulses) to carry data packets and, ultimately, messages communicated between network devices. According to the OSI model, specialized circuitry called a physical layer device or controller (PHY device or controller) is used to interface between an analog domain of a wire (the physical medium) and a digital domain of a data link layer (also referred to herein simply as the "link layer"), which operates according to packet signaling.While the data link layer may include one or more sublayers, in Ethernet-based computer networking, a data link layer typically includes at least a media access control (MAC) layer, which provides a physical layer control abstraction. As a non-limiting example, when transmitting data to another device on a network, a MAC controller may prepare frames for the physical medium, add error correction elements, and implement collision avoidance. Additionally, when receiving data from another device, a MAC controller may ensure the integrity of received data and prepare frames for higher layers.

[0005] There are various network topologies that implement physical layers and link layers (and may include, but are not limited to, other layers). The Peripheral Component Interconnect (PCI) standard and the Parallel Advanced Technology Attachment (Parallel ATA) standard, both in use since the early 1990s, can implement a multi-drop bus topology. The trend since the early 2000s has been to use point-to-point bus topologies; for example, the PCI Express (PCIe) standard and the Serial ATA (SATA) standard implement point-to-point topologies.

[0006] A typical point-to-point bus topology can implement circuits between each device (e.g., dedicated point-to-point, without limitation) or circuits between devices and switches (e.g., switched point-to-point, without limitation). In a multi-drop topology, a physical transmission medium is a shared bus, and each network device is coupled to the shared bus, for example, via a circuit selected based on the type of physical medium (e.g., coaxial or twisted pair, without limitation).

[0007] Point-to-point bus topologies, such as a dedicated point-to-point topology or a switched point-to-point topology, require more wires and thus more expensive material than multi-drop topologies, partly due to the larger number of links between devices. In certain applications, such as automotive applications, physical constraints may exist that make it difficult to connect devices directly, so a topology that requires no or fewer direct connections (e.g., a multi-drop topology, without limitation) in a network or subnetwork may be less susceptible to or hindered by such constraints.

[0008] Devices located in a baseband network (e.g., but not limited to, a multidrop network) use the same physical transmission medium ("shared transmission medium") and typically use the entire bandwidth of that medium for transmissions (in other words, a signal used in baseband transmission occupies the entire bandwidth of the media). As a result, only one device can transmit in a baseband network at a given time. Therefore, media access control techniques are sometimes used to manage contention for a shared transmission medium. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To easily identify the discussion of a specified element or particular action, the main numeral(s) in a reference number refer to the figure number in which that element is first introduced. Fig. 1 is a block diagram of a device for filtering symbols transmitted from a PHY toward a MAC via a PHY side of a PHY-MAC interface. Fig. 2 is a block diagram of a PHY side of a PHY-MAC interface including symbol filtering, according to one or more examples. Fig. 3 is a block diagram of a PHY side of a PHY-MAC interface including symbol filtering, according to one or more examples. Fig. 4 is a block diagram illustrating a symbol filter to filter based at least in part on detecting: a predetermined symbol, an indication of valid data, and an indication of out-of-band data, according to one or more examples. Fig. 5 is a block diagram illustrating a symbol filter to filter based at least in part on detecting: a predetermined symbol, according to one or more examples. Fig. 6 is a block diagram illustrating a symbol filter to filter based at least in part on an indication of valid data and an indication of out-of-band data, according to one or more examples. Fig. 7 is a flowchart illustrating a process for filtering symbols on a PHY side of a PHY-MAC interface according to one or more examples. Fig. 8 is a flowchart illustrating a process for filtering a symbol on a PHY side of a PHY-MAC interface based at least in part on detecting a predetermined symbol. Fig. 9 is a flowchart illustrating a process for filtering a symbol on a PHY side of a PHY-MAC interface based at least in part on an indication of out-of-band data, according to one or more examples. Fig. 10 is a flowchart illustrating a process for filtering a symbol on a PHY side of a PHY-MAC interface based at least in part on an indication of valid data and an indication of out-of-band data, according to one or more examples. Fig. 11 is a flowchart illustrating a process for filtering a symbol on a PHY side of a PHY-MAC interface based at least in part on an indication of valid data, according to one or more examples. Fig. 12 is a flowchart illustrating a process for filtering a symbol on a PHY side of a PHY-MAC interface based at least in part on detecting a predetermined symbol, an indication of valid data, and an indication of out-of-band data, according to one or more examples. Fig. 13 illustrates a timing diagram of signals according to one or more examples. Fig. 14 illustrates a timing diagram of signals according to one or more examples. Fig. 15 illustrates a timing diagram of signals according to one or more examples. Fig. 16 is a block diagram of circuit logic that may be used in some examples to implement various functions, operations, acts, processes, and / or methods disclosed herein. MODE(S) FOR CARRYING OUT THE INVENTION

[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which is shown by way of illustration specific examples of embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other embodiments may be utilized, and changes in structure, material, and process may be made without departing from the scope of the disclosure.

[0011] The illustrations presented herein are not intended to be actual views of any particular method or system, device, or structure, but are merely idealized representations used to describe embodiments of the present disclosure. The drawings presented herein are not necessarily to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not imply that the structures or components are necessarily identical in size, composition, configuration, or any other characteristic.

[0012] The following description may include examples to enable one of ordinary skill in the art to practice the disclosed embodiments. The use of the terms "exemplary," "as an example," and "for example" means that the accompanying description is illustrative, and while the scope of the disclosure is intended to include examples and their legal equivalents, the use of such terms is not intended to limit the scope of any embodiment or this disclosure to the specified components, steps, features, functions, or the like.

[0013] It should be understood that the components of the embodiments, as generally described herein and illustrated in the drawings, may be arranged and configured in a variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While the various aspects of the embodiments may be illustrated in drawings, the drawings are not necessarily drawn to scale unless expressly indicated.

[0014] Furthermore, the specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Elements, circuits, and functions may be shown in block diagram form in order not to obscure the present disclosure with unnecessary detail. Conversely, specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Furthermore, block definitions and the partitioning of logic between various blocks are exemplary of a specific implementation. It will be readily apparent to those skilled in the art that the present disclosure may be practiced using numerous other partitioning solutions.Details of timing considerations and the like have largely been omitted to the extent that such details are not necessary for a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0015] Those skilled in the art would understand that information and signals may be represented using a variety of different technologies and techniques. Some drawings may illustrate signals as a single signal for clarity of illustration and description. Those skilled in the art will understand that the signal may represent a bus of signals, where the bus may have a variety of bit widths, and the present disclosure may be implemented with any number of data signals, including a single data signal.

[0016] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof configured to perform the functions described herein.A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, it may be any conventional processor, control unit, microcontroller, or state machine. A processor may also be implemented as a combination of data processing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, while the general-purpose computer is configured to execute computational instructions (e.g., software code) related to embodiments of the present disclosure.

[0017] Embodiments may be described with respect to a process represented as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different order, in parallel, or substantially concurrently. Furthermore, the order of the acts may be changed. A process may correspond, without limitation, to a method, a thread, a function, a procedure, a subroutine, or a subprogram. Further, the methods disclosed herein may be implemented in hardware, software, or both. When implemented in software, the functions may be stored or broadcast as one or more instructions or as code on computer-readable media.Computer-readable media includes both computer storage media and communications media, including any media that supports the transfer of a computer program from one location to another.

[0018] Any reference herein to an element using a label such as "first," "second," etc., does not limit the quantity or order of those elements unless such a limitation is expressly stated. Rather, these labels may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to a first and a second element does not imply that only two elements may be employed or that the first element must precede the second element in any way. Furthermore, unless otherwise stated, a set of elements may include one or more elements.

[0019] As used herein, the term "substantially" with respect to a given parameter, property, or condition means, and includes, to an extent understood by one skilled in the art, that the given parameter, property, or condition is satisfied with a small degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the specified parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be at least 90% satisfied, at least 95% satisfied, or even at least 99% satisfied.

[0020] In this description, the term "coupled" and derivatives thereof may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. Conversely, when an element is described as being "directly coupled" to another element, no intervening elements or layers are present. The terms "to" and "connected" may be used interchangeably with the term "coupled" in this description and have the same meaning unless expressly stated otherwise or the context would indicate otherwise to a person skilled in the art.

[0021] As used herein, the term “pin” means “electrical terminal” and is understood to include any structure or device capable of forming at least a portion of an electrical connection, such as, but not limited to, an electrical contact, an electromechanical device, or a circuit.

[0022] As used herein, the terms “enable,” “deactivate,” and derivatives thereof, when used with respect to a pin, mean to enable or disable a signal associated with the pin (e.g., a signal specifically assigned to the pin or a signal to which the pin is specifically assigned, without limitation).

[0023] A vehicle, such as an automobile, truck, bus, ship, and / or aircraft, may include a vehicle communications network. Depending on the number of electronic devices within the network, the complexity of the vehicle communications network can vary. For example, a modern vehicle communications network may include various control modules, as non-limiting examples, for engine control, transmission control, safety control (e.g., anti-lock braking system), and emissions control. To support these modules, various communication protocols are used in the automotive industry.

[0024] 10SPE (i.e., 10 Mbps Single Pair Ethernet) is a networking technology currently under the IEEE 802.3cg™ specification, available from IEEE, Piscataway, New Jersey. 10SPE can be used to provide collision-free, deterministic transmission of symbols in a multidrop network. The 10SPE specification includes an optional physical-level collision avoidance (PLCA) cancellation sublayer for collision-free transmission.

[0025] In addition to symbols that are part of the "payload," a physical layer (PHY) device may receive symbols that are not part of the payload. Payload is defined as the entirety of a data frame presented by a media access controller (MAC) to a PHY for transmission, such as preamble data, frame data, and integrity data. Payload is also referred to herein as "in-band data" and, with respect to symbols, as "in-band symbols." Data other than in-band data is also referred to herein as "out-of-band data" and, with respect to symbols, as "out-of-band symbols." As a non-limiting example, a PLCA PHY, such as some 10SPE PHYs, that transmits may include symbols used for collision avoidance, such as, but not limited to, beacon and commit symbols.

[0026] A media-independent interface (MII) can be used to couple a MAC to different types of PHYs (i.e., PHYs for connecting to different types of physical media (e.g., but not limited to, coaxial or twisted pair) for a transmission medium). An MII typically includes a receive data validity signal ("RX Data Valid"), which typically indicates symbols of valid received data (in-band data) in the receive data ("RX Data"), and a carrier sense signal, which typically indicates a detected state (e.g., but not limited to, active or inactive) of a carrier on the transmission medium. A MAC can use the RX Data Valid and Carrier Sense signals to infer which symbols, if any, in the RX data are in-band data.

[0027] An MII typically includes a receive error signal ("RX Error Signal") to indicate, along with the RX Data Valid Signal, that certain symbols included in the RX data correspond to out-of-band data. According to 10SPE, when both the RX Error Signal and the RX Data Valid Signal are abrogated, this indicates that special PLCA symbols are present in the RX data. In the case of a carrier sense multiple access MAC (CSMA MAC) or a CSMA collision detection MAC (CSMACD MAC), the special PLCA symbols are processed by a PLCA abrogation sublayer in response to signaling by the RX Error Signal and the RX Data Valid Signal.

[0028] An interface wrapper is logic circuitry that can modify (for example, reduce or increase, but are not limited to) the signaling or hardware connections of an interface. Interface wrappers are sometimes used to modify the signaling or hardware interface between a PHY and a MAC to, as a non-limiting example, reduce the number of connections used to couple a PHY and a MAC. As a non-limiting example, a Reduced Media Independent Interface (RMII) wrapper can be used to encapsulate an MII and reduce the number of pins (i.e., hardware connections) and signals on the RMII compared to an MII.

[0029] A typical RMII wrapper assumes that the carrier sense and RX data valid signals are essentially identical and multiplexes the RX data valid and carrier sense signals to a single output (which may also be referred to as the non-exclusive signaling of carrier sense and RX data valid signals, or "CRS-DV" output). A typical RMII does not include an RX error signal. In a case where the internal MII carrier sense signal is asserted, the internal MII RX data valid signal is deasserted, and the internal MII RX error signal is asserted, a typical RMII wrapper asserts the CRS-DV signal based on at least one of the carrier sense and RX data valid signals being asserted. Therefore, an RMII wrapper may inadvertently indicate that symbols are in-band data when they are actually out-of-band data.In the same case, when the MAC receives the asserted CRS-DV signal, as a non-limiting example, it may merge symbols of in-band data and out-of-band data, resulting in corrupted data, lost data, or unusable data.

[0030] The inventors of this disclosure recognize that it may be advantageous to include symbol filtering in an interface wrapper (e.g., but not limited to, an RMII wrapper) to, as a non-limiting example, increase the accurate communication of in-band data (e.g., but not limited to, payload data) or out-of-band data (e.g., but not limited to, PLCA symbols) over a wrapped interface. The use of the terms "filter," "filtering," or derivatives thereof herein is not intended to imply that blocking, masking, or non-forwarding of symbols is required, or that circuitry that performs blocking, masking, or non-forwarding of symbols is required.Unless expressly stated otherwise or would be understood otherwise by one of ordinary skill in the art based on the context, the terms "filter", "filtering", or derivatives thereof should be understood to encompass a variety of techniques, including, but not limited to, forwarding symbols and altering or suppressing signals that affect how a downstream user interprets (e.g., as, but not limited to, in-band symbols or out-of-band symbols), uses, or recognizes in-band or out-of-band symbols, as well as blocking, masking, or not forwarding symbol data.

[0031] Fig. 1 is a block diagram of a device 100 for filtering symbols transmitted from a PHY to a MAC over a PHY-MAC interface. The device 100 may also be referred to as an "interface section 100." The device 100 includes a PHY side of the PHY-MAC interface 102. The PHY side of the PHY-MAC interface 102 includes logic circuitry 104 including a symbol filter 106.

[0032] The PHY side of PHY-MAC interface 102 is the PHY portion of an interface intended to support the communication of data (e.g., but not limited to, data frames) between a PHY and a MAC. As a non-limiting example, a PHY-MAC interface of the PHY side of PHY-MAC interface 102 may be an Ethernet PHY-MAC interface.

[0033] The symbol filter 106 of logic circuit 104 is used to filter one or more symbols transmitted over the PHY side of the PHY-MAC interface 102. In one or more examples, filtered symbols may be predetermined symbols, symbols identified via particular signaling, or both. Non-limiting examples of predetermined symbols include PLCA symbols, such as beacon or commit symbols, or more generally, out-of-band symbols. Non-limiting examples of suppressing communication include deleting predetermined symbols from a data frame or stream, providing signals to indicate the presence of predetermined symbols or generally invalid data (which may include providing signals to indicate the absence of data or valid data), or combinations thereof.Filtering symbols that are not out-of-band data does not exceed the scope of this disclosure. Any "symbol to be ignored" may be filtered according to examples disclosed herein, including, in one or more examples, in-band data.

[0034] Fig. 2 is a block diagram of a PHY side of the PHY-MAC interface 200 including symbol filtering according to one or more examples. The PHY side of the PHY-MAC interface 200 is a non-limiting example of the PHY side of the PHY-MAC interface 102 of Fig. 1.

[0035] The PHY side of PHY-MAC interface 200 includes interface 204, which may be a PHY side of an MII, interface wrapper 206, which may be a PHY side of an RMII wrapper, and symbol filter 208, which together form a PHY side of wrapped interface 202. Symbol filter 208 is provided at input 216 of interface wrapper 206. Input 216 is generally for receiving state signaling, such as emulated state signaling 214 (which may be identical to or different from state signaling 212), generated by symbol filter 208.

[0036] Various connections (not shown) may carry signaling and data, including a data stream 210 and state signaling 212. The data stream 210 is a data stream of symbols ("symbol data") received by a PHY from a physical transmission medium. The state signaling 212 includes one or more signals for indicating one or more of: a state of a carrier on a physical transmission medium (e.g., the state is "active" (i.e., carrying transmission data, such as, but not limited to, in-band data or out-of-band data)) or is "inactive" (i.e., not carrying transmission data, such as, but not limited to, in-band data or out-of-band data) or a state of symbol data of the data stream 210 (e.g., the symbol is, but not limited to, in-band data or out-of-band data).As discussed above, downstream users of the emulated state signaling 214 may distinguish between in-band symbols and out-of-band symbols of a data stream (e.g., in the data stream 210, but not limited to).

[0037] The symbol filter 208 generates emulated state signaling 214 and provides it to the interface wrapper 206. The symbol filter 208 may generate the emulated state signaling 214 at least in part in response to one or more of the data streams 210 and / or the state signaling 212, as discussed herein. In one or more examples, the symbol filter 208 may influence how a downstream user distinguishes between in-band data and out-of-band data in a data stream 210 by implementing differences between instances of the emulated state signaling 214 and the state signaling 212.

[0038] Fig. 3 is a block diagram of an interface section 300 including symbol filtering, according to one or more examples. Interface section 300 is an example PHY side of a PHY-MAC interface. Fig. 3 illustrates, among other things, a PHY side of the RMII wrapper 306 having symbol-filtered inputs, according to one or more examples. The interface portion 300 is a non-limiting example of a PHY side of the PHY-MAC interface 102 of Fig. 1 or a PHY side of the PHY-MAC interface 200 of Fig. 2.

[0039] The interface section 300 includes a PHY side of an MII 304, a PHY side of an RMII wrapper 306, and a symbol filter 308, which together form a PHY side of an RMII 302. Several connections couple the PHY side of the MII 304 to the PHY side of the RMII wrapper 306, including internal connections for signals provided on a receive path 320 (i.e., a PHY-to-MAC data path) of the PHY side of the RMII 302. The signals provided on the receive path 320 include, but are not limited to, RX data 310, RX data validity 312, RX error 314, and carrier sense 316.

[0040] The RX data 310 is associated with receive data ("RX data") received by a PHY from a shared transmission medium and transmitted by a PHY toward a MAC, and carries a data stream of symbols ("symbol data"). The RX data validity 312 is associated with an indication of the presence of valid data (i.e., symbols that are in-band data) in the RX data 310, i.e., valid data on the internal links carrying the RX data 310.The timing is linked to the setting / unsetting of the RX Data Valid signal 312 such that when the RX Data Valid signal 312 is set, this indicates a time at which valid data is present on the internal links carrying the RX data 310, and when the RX Data Valid signal 312 is deasserted, this indicates a time at which no valid data is present on the internal links carrying the RX data 310.

[0041] The RX Error 314 is associated with an indication of the presence of out-of-band data (e.g., predetermined symbols for communicating a state of a link partner or carrier on a cable, but not limited to) on the internal links carrying the RX data 310. Timing is associated with the assertion / assertion of the RX Error 314 signal, such that when the RX Error 314 signal is asserted, it indicates a time when out-of-band data is present on the internal links carrying the RX data 310, and when the RX Error 314 signal is asserted, it indicates a time when no out-of-band data is present on the internal links carrying the RX data 310.

[0042] Carrier detection 316 is associated with a detected state of a carrier on a physical medium (e.g., a cable such as, but not limited to, a coaxial cable or a twisted pair cable). Non-limiting examples of states of a carrier include "active" and "inactive," as discussed above.

[0043] The symbol filter 308 is disposed between the PHY side of the MII 304 and inputs 322 of the PHY side of the RMII wrapper 306 to receive the RX data 310, RX data valid 312, RX error 314, and carrier sense 316 signals. In one or more examples, the symbol filter 308 may provide (e.g., propagate or forward, but not be limited to) some or all of the RX data 310, RX data valid 312, RX error 314, and carrier sense 316 signals toward the inputs 322 of the PHY side of the RMII wrapper 306 associated with these signals. The symbol filter 308 may, as discussed herein, generate an emulated carrier sense 318 at least in part in response to one or more of the RX data 310, RX data validity 312, or RX error 314 signals.By implementing differences between the received carrier sense signal 316 and the output emulated carrier sense signal 318, the symbol filter 308 can influence how a downstream user (e.g., but not limited to, a MAC) distinguishes between in-band data and out-of-band data in a data stream on the internal links carrying the RX data 310. Influencing how the downstream user distinguishes between in-band data and out-of-band data in a data stream is referred to herein as symbol filtering.

[0044] Fig. 4, Fig. 5 and Fig. 6 are block diagrams illustrating configurations of symbol filters that are non-limiting examples of the symbol filter 208 of Fig. 2, of the symbol filter 308 of Fig. 3 or the symbol filter 106 of the logic circuit 104 of Fig. 1 are.

[0045] Fig. 4 is a block diagram illustrating a symbol filter 400 to filter based at least in part on detecting: a predetermined symbol, an indication of valid data, and an indication of out-of-band data, according to one or more examples.

[0046] Symbol filter 400 includes matching logic 402, detection logic 406, and suppression logic 408. Matching logic 402 receives a data stream 410. Detection logic 406 and suppression logic 408 each receive at least some component signals of status signaling 414. The component signals of status signaling 414 received by detection logic 406 include RX error signal 416 and optionally valid RX data 418. The component signal of status signaling 414 received by suppression logic 408 includes a carrier sense 420.

[0047] The matching logic 402 detects that one or more symbols 412 of the data stream 410 match one or more predetermined symbols 404. As a non-limiting example, the predetermined symbols 404 may include, but are not limited to, predetermined symbols associated with out-of-band data (e.g., predetermined symbols of bits or symbols associated with out-of-band data stored in or accessible by the matching logic 402), such as, but not limited to, commit symbols, PLCA symbols, or beacon symbols. In response to detecting that one or more symbols 412 match one or more predetermined symbols 404, the matching logic 402 sets the out-of-band symbol indication 422.Setting the out-of-band symbol indication 422 indicates the presence of one or more predetermined symbols 404 in the data stream 410, and clearing the out-of-band symbol indication 422 indicates the absence of one or more predetermined symbols 404 in the data stream 410.

[0048] As a non-limiting example, the matching logic 402 may be a combinational logic circuit that performs a bit-by-bit comparison of the predetermined symbols 404 and the symbols 412, generating the out-of-band symbol indication 422 having a first logic level, which may be a high voltage level, in response to the comparison indicating that the bits (or an appropriate number of the bits) are the same, and a second logic level, which may be a low voltage level, in response to the comparison indicating that the bits (or an appropriate number of the bits) are different.

[0049] Detection logic 406 detects that status signaling 414 indicates the presence of out-of-band data in data stream 410. As discussed above with respect to RX error 314, assertion of RX error signal 416 indicates that out-of-band data is present in data stream 410. As discussed above with respect to RX data validity 312, deassertion of RX data validity 312 indicates that no valid data is present in data stream 410. Detection logic 406 asserts out-of-band data signaling indication 426 at least in part in response to detecting both: assertion of RX error signal 416 and deassertion of RX data valid signal 418.As a non-limiting example, the detection logic 406 may be a combinational logic circuit including an AND gate having an input coupled to receive the RX error signal 416 and an input coupled to receive the RX data valid signal 418. In a contemplated operation, the AND gate outputs an out-of-band data signaling indication 426 having a logic high voltage level in response to one or both of the RX error signal 416 and the RX data valid signal 418 having a logic high voltage (in a case where a logic high voltage level corresponds to "asserted" and a logic low voltage level corresponds to "unasserted") and otherwise having a logic low voltage level. The suppression logic 408 generates an emulated carrier sense 424 to provide a downstream user (e.g.,a MAC, but is not limited to) to indicate whether or not one or more symbols of the data stream 410 correspond to out-of-band data. The suppression logic 408 generates an emulated carrier sense 424, which may include signaling to indicate that one or more symbols of the data stream 410 correspond to out-of-band data, at least in part in response to detecting both: setting an out-of-band symbol indication 422 (indicating that one or more symbols 412 match one or more predetermined symbols 404) and setting an out-of-band data signaling indication 426 (indicating that the state signaling 414 indicates the presence of out-of-band data in the data stream 410). In particular, portions of the emulated carrier detection 424 may differ from the carrier detection 420, but other portions remain substantially the same (i.e.unchanged).

[0050] As a non-limiting example, the suppression logic 408 may be a combinational logic circuit including an AND gate having an input coupled to the output of the alignment logic 402 to receive an out-of-band symbol indication 422 and an input coupled to the output of the detection logic 406 to receive an out-of-band data signaling indication 426, and a NAND gate having an input coupled to the output of the AND gate and an input coupled to receive the carrier sense 420. In a contemplated operation, the AND gate outputs a signal having a logic high voltage level in response to the out-of-band data signaling indication 426 and / or the out-of-band symbol indication 422 being logic high.Further, the NAND gate outputs the emulated carrier sense 424 having a logic low voltage level in response to the carrier sense 420 having a logic high voltage level and the output of the AND gate having a logic high voltage level.

[0051] Fig. 5 is a block diagram illustrating a symbol filter 500 to filter based at least in part on detecting a predetermined symbol, according to one or more examples.

[0052] Symbol filter 500 includes matching logic 502 and suppression logic 506. Matching logic 502 is coupled to receive data stream 518. A component signal of state signaling 510 received by suppression logic 506 includes carrier detection 512.

[0053] The matching logic 502 detects that one or more symbols 508 of the data stream 518 match one or more predetermined symbols 504. As a non-limiting example, one or more predetermined symbols 504 may include, but are not limited to, predetermined out-of-band data, such as PLCA symbols (e.g., beacon symbols or commit symbols). In response to detecting that one or more symbols 508 match one or more predetermined symbols 504, the matching logic 502 sets the out-of-band symbol indication 514, where the setting indicates the presence of out-of-band data in the data stream 518.

[0054] As a non-limiting example, the matching logic 502 may be a combinational logic circuit that performs a bit-by-bit comparison of the predetermined symbols 504 with the symbols 508 and outputs an out-of-band symbol indication 514 having a logic high voltage level in response to the comparison indicating that the bits (or an appropriate number of bits) are the same, and a logic low voltage level in response to the comparison indicating that the bits (or an appropriate number of bits) are different.

[0055] The suppression logic 506 generates an emulated carrier sense 516 to indicate to a downstream user (e.g., but not limited to, a MAC) that one or more symbols of the data stream 518 correspond to out-of-band data. The suppression logic 506 generates the emulated carrier sense 516, including signaling to indicate that one or more symbols of the data stream 518 correspond to out-of-band data, at least in part in response to detecting the setting of the out-of-band symbol indication 514 indicating that one or more symbols 508 match one or more predetermined symbols 504. In particular, in various use cases, portions of the emulated carrier sense 516 may differ from the carrier sense 512, but other portions may be substantially the same (i.e., unchanged).

[0056] As a non-limiting example, the suppression logic 506 may be a combinational logic circuit including a NAND gate having an input coupled to the output of the equalization logic 502 and an input coupled to receive the carrier sense 512. In a contemplated operation, the NAND gate outputs the emulated carrier sense 516 having a logic low voltage level in response to both the out-of-band data signaling indication 426 and the carrier sense 512 having a logic high voltage level.

[0057] Fig. 6 is a block diagram illustrating a symbol filter 600 to filter based at least in part on an indication of valid data and an indication of out-of-band data, according to one or more examples.

[0058] The symbol filter 600 includes a detection logic 602 and a suppression logic 604. The data stream 606 is Fig. 6, but is optional because the suppression logic 604 relies on the out-of-band data signaling indication 616 from the detection logic 602, but not on direct symbol matching (e.g., the matching logic 402 or the matching logic 502, but not limited to) to generate the emulated carrier sense 618, as discussed herein.

[0059] The detection logic 602 and the suppression logic 604 each receive some of the component signals of the state signaling 608. The component signals of the state signaling 608 received by the detection logic 602 include an RX error 610 and optionally valid RX data 612. The component signal of the state signaling 608 received by the suppression logic 604 includes the carrier sense 614.

[0060] Detection logic 602 detects that status signaling 608 indicates the presence of out-of-band data in data stream 606 and sets or deasserts out-of-band data signaling indication 616, at least in part in response thereto. As discussed above with respect to RX error 314, setting RX error 610 indicates that out-of-band data is present in data stream 606. As discussed above with respect to RX data validity 312, deasserting valid RX data 612 indicates that no valid data is present in data stream 606. The detection logic 602 sets the out-of-band data signaling indication 616 at least in part in response to detecting the setting of the RX error 610 and the de-assertion of the valid RX data 612.As a non-limiting example, the detection logic 602 may be a combinational logic circuit including an AND gate having an input coupled to receive the RX error 610 and an input coupled to receive an inverted version of the valid RX data 612. The AND gate outputs the out-of-band data signaling indication 426 having a logic high voltage level in response to both the RX error 610 having a logic high voltage and the inverted version of the valid RX data signal 418 having a logic low voltage, and otherwise outputs the out-of-band data signaling indication 426 having a logic low level.

[0061] The suppression logic 604 generates the emulated carrier sense 618 to indicate to a downstream user (e.g., but not limited to, a MAC) that one or more symbols of the data stream 606 correspond to out-of-band data. The suppression logic 604 generates the emulated carrier sense 618, including signaling to indicate that one or more symbols of the data stream 606 correspond to out-of-band data, at least in part in response to detecting the assertion of the out-of-band data signaling indication 616. In particular, portions of the emulated CRS 618 may differ from the carrier sense 614, but other portions remain substantially the same (i.e., unchanged).As a non-limiting example, the suppression logic 604 may be a combinational logic circuit including a NAND gate having an input coupled to the output of the detection logic 602 and an input coupled to receive the carrier sense 614. In a contemplated operation, the NAND gate outputs a logic low voltage level in response to both the out-of-band data signaling indication 616 and the carrier sense 614 having a logic high voltage level, and a logic high voltage level otherwise.

[0062] Fig. 7 is a flowchart illustrating a process 700 for filtering symbols on a PHY side of a PHY-MAC interface according to one or more examples. The process 700 may be performed, as a non-limiting example, by the device 100 of Fig. 1 should be carried out.

[0063] In operation 702, process 700 transmits symbols from a PHY toward a MAC via a PHY side of a PHY-MAC interface. At least some transmitted symbols are out-of-band data or in-band data. Some of the transmitted symbols may be symbols to be ignored.

[0064] In operation 704, process 700 filters one or more symbols at an input of an interface wrapper of the PHY side of a PHY-MAC interface. The interface wrapper may be an RMII wrapper, and the PHY side of a PHY-MAC interface may be a wrapped interface, such as, but not limited to, an MII wrapped by an RMII.

[0065] Fig. 8, Fig. 9, Fig. 11, Fig. 10 and Fig. 12 are flow diagrams each illustrating suppression of signaling on a PHY side of a PHY-MAC interface for filtering symbols according to one or more examples.

[0066] Fig. 8 is a flowchart illustrating a process 800 for filtering a symbol on a PHY side of a PHY-MAC interface based at least in part on detecting a predetermined symbol. The process 800 may be performed by symbol filters 500 on a PHY side of PHY-MAC interface 200 or a PHY side of PHY-MAC interface 102, as a non-limiting example.

[0067] In operation 802, process 800 detects one or more symbols that correspond to a predetermined symbol. The match between the one or more symbols and the predetermined symbols may be detected at an input to a PHY side of an interface wrapper of a PHY side of a PHY-MAC interface.

[0068] In operation 804, the predetermined symbol is optionally associated with out-of-band data (e.g., predetermined symbols of bits or symbols associated with commit symbols, PLCA symbols, beacon symbols, or other out-of-band data stored in or accessible to the matching logic 502). In operation 806, the predetermined symbol is optionally associated with a Physical Layer Collision Avoidance (PLCA).

[0069] In operation 808, process 800 suppresses signaling to the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface, the signaling being associated with the one or more symbols. As a non-limiting example, signaling to the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface may be suppressed during the same time period that associated symbols are provided to the PHY side of the interface wrapper of the PHY side of a PHY-MAC interface.

[0070] In operation 810, the suppressed signaling is optionally associated with a state of a bearer of a shared transmission medium.

[0071] Fig. 9 is a flowchart illustrating a process 900 for filtering a symbol on a PHY side of a PHY MAC interface based at least in part on an indication of out-of-band data, such as the setting of an RX error 610 from Fig. 6, according to one or more examples.

[0072] In operation 902, process 900 detects a setting of an indication of out-of-band data, e.g., by setting the out-of-band data signaling indication 616. The setting may be detected in response to the indication that out-of-band data changes its status from "suspended" to "set."

[0073] At operation 904, process 900 begins by suppressing signaling to a PHY-side input of a PHY-side interface wrapper of the PHY-MAC interface, at least in part in response to detecting the assertion of an indication of out-of-band data. Suppressing signaling may include providing signaling to indicate the presence of predetermined symbols or, more generally, invalid data (which may include providing signaling to indicate the absence of data or valid data), or combinations thereof.

[0074] In operation 906, process 900 detects a de-assertion of out-of-band data. The de-assertion may be detected in response to the out-of-band data indication changing its status from "set" to "de-asserted."

[0075] In operation 908, process 900 stops suppressing signaling to a PHY-side input of a PHY-side interface wrapper of a PHY MAC interface in response at least in part to detecting the despecification of out-of-band data.

[0076] Fig. 10 is a flowchart illustrating a process 1000 for filtering a symbol on a PHY side of a PHY-MAC interface based at least in part on an indication of valid data, such as the valid RX data 612 of Fig. 6, and an indication of out-of-band data, such as the RX error 610 from Fig. 6, according to one or more examples.

[0077] In operation 1002, the process 1000 detects at least one of: a revocation of an indication of valid data (e.g., a revocation of the valid RX data 612 from Fig. 6, without being limited thereto) or setting an indication of out-of-band data (e.g. setting RX error 610 of Fig. 6). Deasserting valid data may be detected in response to an indication that valid data (e.g., but not limited to, valid RX data 612) changes its state from "asserted" to "deasserted," and setting an indication of out-of-band data (e.g., but not limited to, RX error 610) may be detected in response to an indication that out-of-band data changes its state from "deasserted" to "set."

[0078] In operation 1004, the process 1000 begins by suppressing a signaling (e.g., the carrier detection 614 of Fig. 6, but not limited to) at an input of the PHY side of the interface wrapper of the PHY side of the PHY MAC interface, at least in part in response to detecting at least one of: deasserting an indication of valid data or asserting an indication of out-of-band data.

[0079] In operation 1006, process 1000 detects at least one of: setting the indication of valid data or de-setting out-of-band data. Setting an indication of valid data may be detected in response to the indication that valid data changes its state from de-set to set, and de-setting an indication of out-of-band data may be detected in response to the indication that out-of-band data changes its state from set to de-set.

[0080] In operation 1008, process 1000 terminates suppressing signaling to an input of the PHY side of an interface wrapper of the PHY side of a PHY MAC interface in response at least in part to detecting at least one of: setting an indication of valid data or de-indication of out-of-band data.

[0081] Fig. 11 is a flowchart illustrating a process 1100 for filtering a symbol on a PHY side of a PHY-MAC interface based at least in part on an indication of valid data, such as the valid RX data 612 of Fig. 6, according to one or more examples.

[0082] In operation 1102, process 1100 detects a deassertion of valid data. The deassertion may be detected in response to the indication that valid data changes state from "set" to "deasserted."

[0083] In operation 1104, process 1100 begins by suppressing signaling on the PHY side of a PHY MAC interface at least in part in response to detecting a de-indication of valid data.

[0084] In operation 1106, process 1100 detects a valid data indication assertion on the PHY side of a PHY-MAC interface. The assertion may be detected in response to the valid data indication changing its state from "unasserted" to "asserted."

[0085] In operation 1108, process 1100 terminates suppressing signaling on the PHY side of a PHY MAC interface at least in part in response to detecting the assertion of an indication of valid data.

[0086] Fig. 12 is a flowchart illustrating a process 1200 for filtering a symbol on a PHY side of a PHY-MAC interface based at least in part on detecting a predetermined symbol (e.g., but not limited to, the predetermined symbol 404), an indication of valid data (e.g., the valid RX data 418 of Fig. 4, without being limited thereto) and an indication of out-of-band data (e.g., the RX error signal 416 from Fig. 4, without limitation) according to one or more examples.

[0087] In operation 1202, process 1200 detects a symbol that corresponds to a predetermined symbol.

[0088] In operation 1204, process 1200 detects at least one of: an unindication of valid data or an indication of out-of-band data. Unindication may be detected in response to the indication that valid data changes its state from "indicated" to "unindicated," and setting may be detected in response to the indication that out-of-band data changes its state from "indicated" to "indicated."

[0089] In operation 1206, suppressing signaling at an input of the PHY side of an interface wrapper of the PHY side of a PHY MAC interface corresponding to the detected symbol begins, at least in part, in response to detecting the symbol corresponding to the predetermined symbol and detecting at least one of: deasserting an indication of valid data or asserting an indication of out-of-band data.

[0090] In operation 1208, at least one of: setting an indication of valid data or de-setting an indication of out-of-band data is detected. Setting may be detected in response to the indication that valid data changes state from "de-set" to "set," and de-setting may be detected in response to the indication that out-of-band data changes state from "de-set" to "set."

[0091] In operation 1210, suppressing signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY MAC interface corresponding to the one or more symbols ends in response at least in part to at least one of: detecting the assertion of an indication of valid data or the deassertion of an indication of out-of-band data.

[0092] Fig. 13 illustrates a timing diagram 1300 of signals according to one or more examples. The timing diagram 1300 illustrates signals on a cable 1302 (i.e., a transmission medium from which a PHY receives symbols) and corresponding signals: RX data 1306, valid RX data 1308, RX error 1310, carrier sense 1312, and emulated carrier sense 1314.

[0093] At time T 1 an ignore symbol 1304 is present on the cable 1302 and is represented as ignore symbol 1316 in the RX data 1306. Valid RX data 1308 is transmitted at time T 1 canceled 1326 because there is no valid data in the RX data 1306. The RX error 1310 is raised at time T 1canceled 1318, since the symbol to be ignored in this example is special data (e.g., a commit symbol or a beacon, but not limited to these). The carrier sense 1312 is set 1324, since the carrier is active on the cable 1302. The emulated carrier sense 1314 is set at time T 1 canceled 1322. Accordingly, the signaling by the carrier detection 1312 at the emulated carrier detection 1314 at time T 1 (the dashed line is intended to illustrate that the signaling from the carrier sense 1312 is suppressed in the emulated carrier sense 1314 (not present in this particular example)) suppressed according to one of the logics discussed above: the symbol to be ignored 1304 is recognized, the valid RX data 1308 is not set, the RX error 1310 is canceled 1318, or combinations thereof.

[0094] Fig. 14 illustrates a timing diagram 1400 of signals according to one or more examples. The timing diagram 1400 illustrates respective signals on: a cable 1402, RX data 1410, valid RX data 1418, RX error 1422, carrier sense 1428, and emulated carrier sense 1432.

[0095] At time T 1 the first symbol to be ignored 1404 is present on the cable 1402, which is represented as the first symbol to be ignored 1412 in the RX data 1410. The valid RX data 1418 is generated at time T 1 not set (ie, canceled 1444) because there is no valid data in the RX data 1410. The RX error 1422 is raised at time T 1 canceled 1424, since the symbol to be ignored in this example is special data (e.g., a commit symbol or a beacon). The carrier detection 1428 is performed at time T 1set 1430, since an active carrier is present on the cable 1402. The emulated carrier detection 1432 is initiated at time T 1 canceled 1440. Thus, the signaling at carrier detection 1428 at emulated carrier detection 1432 at time T 1 (the dashed line is intended to illustrate that a signal on the emulated carrier sense 1432 is suppressed) suppressed 1434 according to one of the logics discussed above:

[0096] The first symbol to be ignored 1404 is recognized, the valid RX data 1418 is not set, the RX error 1422 is canceled, or combinations thereof.

[0097] At time T 2 Symbol data 1406 is present on the cable 1402, which is represented as symbol data 1414 in the RX data 1410. The valid RX data 1418 is transmitted at time T 2 set 1420, because the RX data 1410 contains valid data. The RX error 1422 is set at time T2 set 1442, since in this example the symbol data 1406 is not special data. The carrier detection 1428 is initiated at time T 1 set 1430, since the carrier on the cable 1402 is active. The emulated carrier detection 1432 is initiated at time T 2 set 1436. Thus, signaling of the carrier sense 1428 is unsuppressed (not suppressed), which can also be characterized as faithful propagation of signals on the carrier sense 1428 (e.g., carriers on the emulated carrier sense 1432 at time T 2 ).

[0098] At time T 3 the second symbol to be ignored 1408 is present on the cable 1402, which is represented as the second symbol to be ignored 1416 in the RX data 1410. The valid RX data 1418 is transmitted at time T 3 canceled 1446 because there is no valid data in the RX data 1410. The RX error 1422 is raised at time T 3canceled 1426, since the symbol data 1406 in this example is not special data. The emulated carrier detection 1432 is performed at time T 3 canceled 1438. Thus, signaling at carrier detection 1428 at emulated carrier detection 1432 at time T 3 (the dashed line is intended to illustrate that a signal on the carrier sense 1428 is suppressed on the emulated carrier sense 1432) is suppressed according to one of the logics discussed above: the second symbol to be ignored 1416 is detected, the valid RX data 1418 is not set, the RX error 1422 is canceled 1426, or combinations thereof.

[0099] In some cases, filtering symbols to be ignored by suppressing signaling at carrier sense 1428, according to one or more examples, may create or increase an interframe gap (IFG) between frames of in-band symbols from the perspective of a MAC receiving the emulated carrier sense signal 1432. If a frame of an out-of-band symbol is specified as a frame of an in-band symbol, and the gap between the frame of the out-of-band symbol and an immediately preceding or following frame may be less than an IFG, a MAC may misprocess one or all of the frames. For example, the disclosed filtering of the first symbol to be ignored 1412 has the effect of increasing the IFG between a frame of symbol data 1414 and a frame that immediately preceded the frame of the first symbol to be ignored 1412. The time between T 1 and T 2(ΔT) may be characterized as the IFG, or at least a portion of the IFG, between a frame of symbol data 1414 and a frame immediately preceding the frame of the first symbol to be ignored 1412. Some examples generally relate to guaranteeing an IFG size. Accordingly, in one or more examples, the disclosed symbol filtering and suppression may guarantee an interframe gap size.

[0100] Fig. 15 illustrates a timing diagram 1500 of signals according to one or more examples. The timing diagram illustrates signals for carrier detection 1508, emulated carrier detection 1510, and receive data 1512.

[0101] The carrier detection 1508 is performed at time T 1set and remains set, so that the first symbol to be ignored 1502 would be appended to the in-band data 1514 received from a MAC. Similarly, the carrier detection 1508 is initiated at time T 2 set and remains set, so that the second symbol to be ignored 1506 would be appended to the in-band data 1504. The emulated carrier detection 1510 is initiated at time T 2 set, but remains not set, so that the first symbol to be ignored 1502 is not appended to the in-band data 1514 received from a MAC. The emulated carrier detection 1510 is initiated at time T 2 set, but remains unset, so the second ignore symbol 1506 is not appended to the in-band data 1504.

[0102] It will be understood by one of ordinary skill in the art that functional elements of examples disclosed herein (e.g., functions, operations, acts, processes, and / or methods) may be implemented in any suitable hardware, software, firmware, or combinations thereof. Fig. 16 illustrates non-limiting examples of implementations of functional elements disclosed herein. In some examples, some or all portions of the functional elements disclosed herein may be performed by hardware specifically configured to perform the functional elements.

[0103] Fig.16 is a block diagram of circuitry 1600 that, in some examples, may be used to implement various functions, operations, acts, processes, and / or methods disclosed herein. Circuitry 1600 includes one or more processors 1602 (sometimes referred to herein as "processors 1602") operably coupled to one or more data storage devices (sometimes referred to herein as "memory 1604"). Memory 1604 includes machine-executable code 1606 stored thereon, and processors 1602 include logic circuitry 1608. Machine-executable code 1606 includes information describing functional elements that may be implemented (e.g., performed) by logic circuitry 1608. The logic circuit 1608 is adapted to implement (e.g., execute) the functional elements described by the machine-executable code 1606.Circuitry 1600, when executing the functional elements described by machine-executable code 1606, should be considered special-purpose hardware configured to execute functional elements disclosed herein. In some examples, processors 1602 may be configured to execute the functional elements described by machine-executable code 1606 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0104] When implemented by logic circuitry 1608 of processors 1602, machine-executable code 1606 is configured to adapt processors 1602 to perform operations of examples disclosed herein. As a non-limiting example, machine-executable code 1606 may be configured to adapt processors 1602 to perform some or all of the operations of one or more of: process 700, process 800, process 900, process 1000, process 1100, process 1200, timing diagram 1300, timing diagram 1400, or timing diagram 1500.

[0105] Also as a non-limiting example, machine-executable code 1606 may be configured to adapt processors 1602 to perform some or all of the features, functions, or operations disclosed herein for one or more of: device 100, PHY side of PHY-MAC interface 200, interface section 300, symbol filter 400, symbol filter 500, or symbol filter 600. More specifically, features, functions, or operations disclosed herein for one or more of a PHY side of PHY-MAC interface 102, logic circuit 104, or symbol filter 106; interface 204, interface wrapper 206, or symbol filter 208; a PHY side of MII 304, a PHY side of RMII wrapper 306, or symbol filter 308; Matching logic 402, detection logic 406, or suppression logic 408; matching logic 502 or suppression logic 506 or detection logic 602 or suppression logic 604.

[0106] Processors 1602 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, another programmable device, or any combination thereof configured to perform the functions disclosed herein. A general-purpose computer, including a processor, is considered a special-purpose computer, while the general-purpose computer is configured to execute functional elements according to machine-executable code 1606 (e.g., software code, firmware code, hardware descriptions) related to examples of the present disclosure.It should be noted that a general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, the processors 1602 may include any conventional processor, controller, microcontroller, or state machine.

[0107] Processors 1602 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0108] In some examples, memory 1604 includes volatile data storage (e.g., random access memory (RAM)), non-volatile data storage (e.g., flash memory, a hard disk drive, a solid-state drive, an erasable programmable read-only memory (EPROM), etc.). In some examples, processors 1602 and memory 1604 may be implemented in a single device (e.g., a semiconductor device product, a system-on-chip (SOC), etc.). In some examples, processors 1602 and memory 1604 may be implemented in separate devices.

[0109] In some examples, machine-executable code 1606 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by memory 1604, which may be directly accessible by processors 1602, and executed by processors 1602 using at least logic circuitry 1608. Also as a non-limiting example, the computer-readable instructions may be stored on memory 1604, transferred to a storage device (not shown) for execution, and executed by processors 1602 using at least logic circuitry 1608. Accordingly, in some examples, logic circuitry 1608 includes electrically configurable logic circuitry 1608.

[0110] In some examples, machine-executable code 1606 may describe hardware (e.g., circuit logic) to be implemented in logic circuitry 1608 to perform the functional elements. This hardware may be described at a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high abstraction level, a hardware description language (HDL), such as an IEEE standard hardware description language (HDL), may be used. As non-limiting examples, Verilog, SystemVerilog, or Very Large Scale Integration (VLSI) hardware description languages ​​(VHDL) may be used.

[0111] HDL descriptions can be freely converted into descriptions at any of numerous other abstraction levels. As a non-limiting example, a high-level description can be converted into a logic-level description, such as a register transfer language (RTL), a gate-level description (GL), a layout-level description, or a mask-level description. As a non-limiting example, micro-operations performed by hardware logic circuitry (e.g.,The operations to be performed by logic circuitry 1608 (including, but not limited to, gates, flip-flops, registers) may be described in an RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, corresponding to a physical layout of an integrated circuit, a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Accordingly, in some examples, machine-executable code 1606 may include an HDL, an RTL, a GL description, a mask-level description, another hardware description, or any combination thereof.

[0112] In examples where machine-executable code 1606 includes a hardware description (at any level of abstraction), a system (not shown, but including memory 1604) may be configured to implement the hardware description described by machine-executable code 1606. As a non-limiting example, processors 1602 may include a programmable logic device (e.g., an FPGA or a PLC), and logic circuitry 1608 may be electrically controlled to implement circuitry corresponding to the hardware description into logic circuitry 1608. Also as a non-limiting example, logic circuitry 1608 may include hard-wired logic manufactured by a manufacturing system (not shown, but including memory 1604) according to the hardware description of machine-executable code 1606.

[0113] Regardless of whether the machine-executable code 1606 includes computer-readable instructions or a hardware description, the logic circuitry 1608 is configured to perform the functional elements described by the machine-executable code 1606 when implementing the functional elements of the machine-executable code 1606. It should be noted that although a hardware description may not directly describe functional elements, a hardware description indirectly describes functional elements that the hardware elements described by the hardware description can perform.

[0114] Terms used in the present disclosure and in particular in the appended claims (e.g., contents of the appended claims) are generally intended to be "open-ended" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "comprising" should be interpreted as "at least comprising," the term "includes" should be interpreted as "includes, but not limited to," etc.).

[0115] Furthermore, if a specific number of introduced claim statements are intended, that intention will be expressly stated in the claim, and in the absence of such reciting, no such intention exists. As an aid to understanding, for example, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed to imply that the introduction of a claim statement by the indefinite articles "a" or "an" limits a particular claim containing such introduced claim statement to embodiments containing only one such statement, even if the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" and / or "an" (e.g.,"a" and / or "an" should be interpreted to mean "at least one" or "one or more"; the same applies to the use of certain articles used to introduce claim particulars.

[0116] Furthermore, even if a particular number of introduced claim statements is explicitly recited, those skilled in the art will recognize that such a statement should be interpreted to mean at least the recited number (e.g., simply stating "two statements" without other modifiers means at least two statements or two or more statements). Furthermore, where a convention analogous to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such construction is generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc. As used herein, "each" means some or a whole, and "all" means a whole.

[0117] Furthermore, any disjunctive word or phrase representing two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibility of including either term, one term or the other, or both. For example, the phrase "A or B" should be understood to include the possibilities "A" or "B" or "A and B."

[0118] Additional non-limiting examples of the present disclosure include: Example 1: A method comprising: transmitting symbols from a PHY to a MAC via a PHY side of a PHY-MAC interface, and filtering one or more symbols at an input of a PHY side of an interface wrapper of the PHY side of a PHY-MAC interface. Example 2: The method of example 1, wherein filtering one or more symbols present at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface comprises: detecting a symbol corresponding to a predetermined symbol; and suppressing signaling to the input of the PHY side of an interface wrapper associated with the symbol. Example 3: The method of any one of examples 1 and 2, wherein the predetermined symbol is associated with out-of-band data. Example 4: The method according to any one of examples 1 to 3, wherein the predetermined symbol is associated with a physical layer collision avoidance. Example 5: The method of any one of examples 1 to 4, wherein the signaling is associated with a state of a bearer of a shared transmission medium. Example 6: The method of any one of Examples 1 to 5, wherein filtering one or more symbols present at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface comprises: detecting an assertion of an indication of out-of-band data; beginning to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to detecting the assertion of the indication of out-of-band data; detecting an unassertion of an indication of out-of-band data; and ending to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to detecting the unassertion of an indication of out-of-band data.Example 7: The method of any one of Examples 1 to 6, wherein filtering one or more symbols present at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface comprises: detecting a deassertion of an indication of valid data; beginning to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to detecting the deassertion of an indication of valid data; detecting a setting of an indication of valid data; and ending to suppress signaling at the input of the PHY side of the interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to detecting the setting of an indication of valid data. Example 8: The method of any one of Examples 1 to 7, wherein filtering one or more symbols present at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface comprises: detecting a de-indication of valid data and a de-indication of out-of-band data; beginning to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to detecting the de-indication of valid data and the de-indication of out-of-band data;detecting a setting of an indication of valid data and a de-setting of an indication of out-of-band data and ceasing to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY MAC interface at least in part in response to detecting the setting of an indication of valid data and the de-setting of an indication of out-of-band data; Example 9: The method of any one of Examples 1 to 8, wherein filtering one or more symbols present at an input of a PHY side of an interface wrapper of the PHY side of a PHY-MAC interface comprises: detecting a symbol corresponding to a predetermined symbol; detecting at least one of: deasserting an indication of valid data or asserting an indication of out-of-band data; beginning to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface corresponding to the symbol, at least in part in response to detecting at least one of: deasserting an indication of valid data or asserting an indication of out-of-band data;detecting at least one of: asserting an indication of valid data or deasserting an indication of out-of-band data and ceasing to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY MAC interface corresponding to the symbol, at least in part in response to at least one of: detecting the assertion of an indication of valid data or deasserting an indication of out-of-band data; Example 10: A device comprising: a PHY side of a PHY-MAC interface and logic circuitry provided on the PHY side of the PHY-MAC interface, wherein the logic circuitry includes a filter for filtering one or more symbols transmitted over the PHY side of a PHY-MAC interface. Example 11: The device of example 10, wherein the PHY side of a PHY-MAC interface comprises: a PHY side of an interface and a PHY side of an interface wrapper, wherein the filter is coupled to filter an input of the PHY side of an interface wrapper. Example 12: The device of any of examples 10 and 11, wherein the filter filters one or more symbols at least in part in response to a detection of out-of-band data. Example 13: The device of any one of examples 10 to 12, wherein the filter comprises: detection logic to detect one or both of: setting an indication of out-of-band data or de-indicating valid data; matching logic to detect whether a symbol corresponds to a predetermined symbol; and suppression logic to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY MAC interface at least in part in response to a detection by the detection logic and a detection by the matching logic. Example 14: The device of any one of examples 10 to 13, wherein suppressed signaling is associated with a detected carrier state of a shared transmission medium. Example 15: The device of any one of examples 10 to 14, wherein the filter comprises: matching logic to detect whether a symbol corresponds to a predetermined symbol; and suppression logic to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to a detection by the matching logic. Example 16: The device of any one of examples 10 to 15, wherein the filter comprises: detection logic to detect one or both of: asserting an indication of out-of-band data or asserting an indication of valid data; and suppression logic to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY MAC interface at least in part in response to detection by the detection logic. Example 17: The device of any one of examples 10 to 16, wherein the PHY side of an interface wrapper is a reduced media independent interface wrapper. Example 18: The device of any one of examples 10 to 17, wherein a filtered symbol is a physical layer collision avoidance symbol.

[0119] 10, where a filtered symbol is a Physical Layer Collision Avoidance symbol.

[0120] Although the present disclosure has been described herein with reference to certain illustrated examples, those of ordinary skill in the art will recognize and understand that the present invention is not limited thereto. Rather, many additions, omissions, and modifications may be made to the illustrated and described examples without departing from the scope of the invention as claimed below, along with their legal equivalents. Furthermore, features of one example may be combined with features of another example and still be included within the scope of the invention contemplated by the inventor. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] CN 202210950844.7

[0001]

Claims

A method comprising: transmitting symbols from a PHY towards a MAC via a PHY side of a PHY-MAC interface; and filtering one or more symbols at an input of a PHY side of an interface wrapper of the PHY side of a PHY-MAC interface. The method of claim 1, wherein filtering one or more symbols present at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface comprises:detecting a symbol corresponding to a predetermined symbol; andsuppressing signaling to the input of the PHY side of an interface wrapper associated with the symbol. The method of claim 2, wherein the predetermined symbol is associated with out-of-band data. The method of claim 2, wherein the predetermined symbol is associated with a physical layer collision avoidance. The method of claim 2, wherein the signaling is linked to a state of a bearer of a shared transmission medium. The method of claim 1, wherein filtering one or more symbols present at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface comprises:detecting an assertion of an indication of out-of-band data;beginning suppressing signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to detecting the assertion of an indication of out-of-band data;detecting an unassertion of an indication of out-of-band data; andterminating suppressing signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to detecting the unassertion of an indication of out-of-band data. The method of claim 1, wherein filtering one or more symbols present at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface comprises:detecting a deassertion of a valid data indication;beginning suppressing signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to detecting the deassertion of a valid data indication;detecting a setting of a valid data indication; andterminating suppressing signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to detecting the setting of a valid data indication. The method of claim 1, wherein filtering one or more symbols present at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface comprises:detecting a de-indication of valid data and a setting of an indication of out-of-band data,initiating suppression of signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to detecting the de-indication of valid data and the setting of an indication of out-of-band data;detecting a setting of an indication of valid data and a de-indication of out-of-band data; and ceasing suppression of signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY MAC interface at least in part in response to detecting the setting of an indication of valid data and the de-indication of out-of-band data; The method of claim 1, wherein filtering one or more symbols present at an input of a PHY side of an interface wrapper of the PHY side of a PHY-MAC interface comprises:detecting a symbol corresponding to a predetermined symbol;detecting at least one of: deasserting an indication of valid data or asserting an indication of out-of-band data;initiating suppressing signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface corresponding to the symbol, at least in part in response to detecting at least one of: deasserting an indication of valid data or asserting an indication of out-of-band data;detecting at least one of: asserting an indication of valid data or deasserting an indication of out-of-band data; and ceasing to suppress signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY MAC interface corresponding to the symbol, at least in part in response to at least one of: detecting the assertion of an indication of valid data or deasserting an indication of out-of-band data; A device comprising: a PHY side of a PHY-MAC interface and a logic circuit provided on the PHY side of a PHY-MAC interface, wherein the logic circuit includes a filter for filtering one or more symbols transmitted over the PHY side of a PHY-MAC interface. The device of claim 10, wherein the PHY side of a PHY-MAC interface comprises: a PHY side of an interface and a PHY side of an interface wrapper, wherein the filter is coupled to filter an input of the PHY side of an interface wrapper. The device of claim 11, wherein the filter is to filter one or more symbols at least in part in response to detection of out-of-band data. The device of claim 11, wherein the filter comprises:detection logic for detecting one or both of: setting an indication of out-of-band data or de-enforcing an indication of valid data;matching logic for detecting whether a symbol corresponds to a predetermined symbol; andsuppression logic for suppressing signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to a detection by the detection logic and a detection by the match logic. The device of claim 13, wherein suppressed signaling is associated with a detected carrier state of a shared transmission medium. The device of claim 13, wherein the filter comprises:matching logic for detecting whether a symbol corresponds to a predetermined symbol; andsuppression logic for suppressing signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY-MAC interface at least in part in response to a detection by the matching logic. The device of claim 11, wherein the filter comprises:detection logic for detecting one or both of: setting an indication of out-of-band data or setting an indication of valid data; andsuppression logic for suppressing signaling at the input of the PHY side of an interface wrapper of the PHY side of a PHY MAC interface at least in part in response to detection by the detection logic. The device of claim 11, wherein the PHY side of an interface wrapper is a reduced media independent interface wrapper. The device of claim 10, wherein a filtered symbol is a physical layer collision avoidance symbol.

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