Display substrate, display panel and display device

Abstract

A display substrate, a display panel, and a display device are provided. The display substrate comprises a base substrate; a plurality of pixel units arranged on the base substrate, the plurality of pixel units arranged in an array in a first direction and a second direction to form a plurality of rows of pixel units and a plurality of columns of pixel units, at least one pixel unit comprising a plurality of subpixels, and at least one subpixel comprising a light-emitting element and a pixel driving circuit for driving the light-emitting element;a plurality of initialization voltage signal lines arranged on the base substrate, each of the plurality of initialization voltage signal lines providing an initialization voltage signal to the plurality of target pixel units, the plurality of initialization voltage signal lines being spaced apart from each other in a second direction, with at least one of the initialization voltage signal lines extending along a first direction. The plurality of target pixel units includes the 2n-1st row of row pixel units and the 2n-th row of row pixel units, where n is a positive integer, and the pixel driver circuits of the 2n-1st and 2n-th rows of row pixel units share an initialization voltage signal line.

Description

FIELD OF THE INVENTIONThe present disclosure relates to the field of display technology, and more particularly, to a display substrate, a display panel, and a display device.BACKGROUND OF THE INVENTIONOLED (Organic Light-Emitting Diode) is a kind of power-type organic light-emitting devices, in which there occurs a phenomenon in which light is emitted by carrier injection and carrier recombination, and the light emission intensity of the OLED is proportional to the injected current. Holes generated by an anode of the OLED and electrons generated by a cathode of the OLED may move under an electric field to inject into a hole transport layer and an electron transport layer, respectively, and travel to a light emitting layer. When the two meet in the light emitting layer, high-energy excitons are generated, so that the light emitting molecules are excited to finally generate visible light.For the above light emitting devices, a compensation circuit must be developed due to a certain brightness display deviation in order to reduce the display deviation. When the design of the compensation circuit is added, the pixel driver becomes more complicated and the design of the driver circuit in the pixel requires more space and high resolution display design cannot be achieved.SUMMARY OF THE INVENTIONIn order to solve at least one aspect of the above problems, the embodiments of the present disclosure provide a display substrate, a display panel, and a display device.In one aspect, there is provided a display substrate, comprising: a base substrate; a plurality of pixel units arranged on the base substrate, the plurality of pixel units arranged in an array in a first direction and a second direction to form a plurality of rows of pixel units and a plurality of columns of pixel units, wherein at least one of the pixel units comprises a plurality of sub-pixels, and at least one sub-pixel comprises a light emitting element and a pixel driving circuit for driving the light emitting element; and a plurality of initialization voltage signal lines disposed on the base substrate, wherein an initialization voltage signal is provided to the plurality of targets of pixel units by the plurality of initialization voltage signal lines, respectively, wherein the plurality of initialization voltage signal lines are spaced apart from each other in the second direction, wherein at least one of the initialization voltage signal lines extends along the first direction, wherein the plurality of targets of pixel units includes the 2n-1th row of pixel units and the 2n-th row of pixel units, wherein n is a positive integer, and wherein the pixel driver circuits of the 2n-1th and 2n-th rows of pixel units share an initialization voltage signal line.According to embodiments of the present disclosure, the display substrate further includes a plurality of initialization voltage signal leads disposed on the base substrate, the initialization voltage signal lead being electrically connected to the initialization voltage signal lead, the plurality of initialization voltage signal leads being spaced apart from each other along the first direction, and at least one of the initialization voltage signal leads extending along the second direction; wherein the plurality of columns of pixel units includes the 2m-1th column of pixel units and the 2mth column of pixel units, where m is a positive integer, and wherein the pixel driver circuits of the 2m-1th and 2mth columns of pixel units share an initialization voltage signal lead.According to embodiments of the present disclosure, the display substrate further includes a plurality of reference voltage signal leads arranged on the substrate substrate, the reference voltage signal leads being used to provide a reference voltage, the plurality of reference voltage signal leads being spaced apart from each other along the first direction, at least one of the reference voltage signal leads extending along the second direction; wherein the pixel driver circuits of the 2m-1th and 2mth columns of pixel units share a reference voltage signal lead.According to embodiments of the present disclosure, the display substrate further includes a plurality of first voltage signal leads arranged on the base substrate, the first voltage signal leads being used to provide a first voltage to the light emitting element, the plurality of first voltage signal leads being spaced apart from each other along the first direction and at least one of the first voltage signal leads extending along the second direction; wherein the plurality of rows of pixel units includes the 2m+1thcolumn of pixel units, wherein the pixel driver circuits of the 2mthand 2m+1thcolumn of pixel units share a first voltage signal lead.According to embodiments of the present disclosure, the display substrate further includes a plurality of first voltage signal lines disposed on the base substrate, the first voltage signal line being electrically connected to the first voltage signal line, the plurality of first voltage signal lines being spaced apart from each other along the second direction, and at least one of the first voltage signal lines extending along the first direction; wherein the plurality of rows of pixel units includes the 2n+1th row of pixel units, wherein the pixel driver circuits of the 2nth and 2n+1th rows of pixel units share a first voltage signal line.According to the embodiments of the present disclosure, the pixel driving circuits of the 2n-1th and 2n-th rows of pixel units are arranged symmetrically with respect to the common initialization voltage signal line.According to the embodiments of the present disclosure, the pixel driving circuit of the 2n-th and 2n+1-th rows of pixel units are arranged symmetrically with respect to the common first voltage signal line.According to the embodiments of the present disclosure, the pixel driving circuit of the column of sub-pixels in the 2m-th column of pixel units close to the common first voltage signal supply line and the pixel driving circuit of the column of sub-pixels in the 2m+1-th column of pixel units close to the common first voltage signal supply line are arranged symmetrically with respect to the common first voltage signal supply line.According to the embodiments of the present disclosure, the display substrate further includes: a plurality of light emission control signal lines disposed on the base substrate, each of the plurality of light emission control signal lines providing a light emission control signal to the plurality of rows of pixel units, the plurality of light emission control signal lines being disposed spaced apart from each other along the second direction, and at least one of the light emission control signal lines extending along the first direction; a plurality of first scan signal lines disposed on the base substrate, each of the plurality of first scan signal lines providing a first scan signal to the plurality of rows of pixel units, the plurality of first scan signal lines being disposed spaced apart from each other along the second direction, and at least one of the first scan signal lines extending along the first direction; a plurality of second scan signal lines arranged on the base substrate, wherein a second scan signal is provided to the plurality of rows of pixel units by the plurality of second scan signal lines, respectively, wherein the plurality of second scan signal lines are arranged spaced apart from each other along the second direction and at least one of the second scan signal lines extends along the first direction; a plurality of reference voltage signal lines arranged on the base substrate, wherein the reference voltage signal line is electrically connected to the reference voltage signal line, wherein the plurality of reference voltage signal lines are arranged spaced apart from each other along the second direction and at least one of the reference voltage signal lines extends along the first direction; a plurality of third scan signal lines disposed on the base substrate, wherein a third scan signal is provided to the plurality of rows of pixel units by the plurality of third scan signal lines, respectively, wherein the plurality of third scan signal lines are spaced apart from each other along the second direction, and at least one of the third scan signal lines extends along the first direction.According to the embodiments of the present disclosure, for the 2n-1th row of pixel units and the 2n-th row of pixel units, the respective first voltage signal lines, the respective light emission control signal lines, the respective first scan signal lines, the respective second scan signal lines, the respective reference voltage signal lines, and the respective third scan signal lines of this two row of pixel units are respectively located on both sides of the common initialization voltage signal line in the second direction.According to the embodiments of the present disclosure, the distances of the first voltage signal line, the light emission control signal line, the first scan signal line, the second scan signal line, the reference voltage signal line, and the third scan signal line of the pixel units in the 2n-1th row are gradually decreased from the common initialization voltage signal line in the second direction, and / or the distances of the first voltage signal line, the light emission control signal line, the first scan signal line, the second scan signal line, the reference voltage signal line, and the third scan signal line of the pixel units in the 2n-1th row are gradually decreased from the common initialization voltage signal line in the second direction.According to embodiments of the present disclosure, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; wherein the display substrate further includes: a plurality of first data lines arranged on the base substrate, wherein a first data signal is provided to a plurality of columns of first sub-pixels by the plurality of first data lines, respectively, wherein the plurality of first data lines are arranged spaced apart from each other along the first direction, and at least one of the first data lines extends along the second direction; a plurality of second data lines arranged on the base substrate, wherein a second data signal is provided to a plurality of columns of second sub-pixels by the plurality of second data lines, respectively, wherein the plurality of second data lines are arranged spaced apart from each other along the first direction, and at least one of the second data lines extends along the second direction; a plurality of third data leads arranged on the base substrate, wherein a third data signal is provided to a plurality of columns of third sub-pixels by the plurality of third data leads, wherein the plurality of third data leads are arranged spaced apart from one another along the first direction and at least one of the third data leads extends along the second direction.According to the embodiments of the present disclosure, for the 2m-1th column of pixel units and the 2m-th column of pixel units, the respective first voltage signal leads, the respective first data leads, the respective second data leads, and the respective third data leads of these two rows of pixel units are respectively located on both sides of the common initialization voltage signal lead and the common reference voltage signal lead in the first direction.According to the embodiments of the present disclosure, the first voltage signal supply line, the first data supply line, the second data supply line, and the third data supply line of the 2m-1th column of pixel units are located on a side of the common initialization voltage signal supply line opposite to the common reference voltage signal supply line, and the distances of the first voltage signal supply line, the first data supply line, the second data supply line, and the third data supply line of the 2m-1th column of pixel units from the common initialization voltage signal supply line are gradually decreased in the first direction; and / or the first voltage signal supply line, the first data supply line, the second data supply line and the third data supply line of the 2m-th column of pixel units are located on a side of the common reference voltage signal supply line facing away from the common initialization voltage signal supply line, wherein the distances of the first data supply line, the second data supply line, the third data supply line and the first voltage signal supply line of the 2m-th column of pixel units from the common reference voltage signal supply line are gradually increased in the first direction.According to the embodiments of the present disclosure, the first voltage signal line, the reference voltage signal line, and the initialization voltage signal line are on a first conductive layer; and the light emission control signal line, the first scan signal line, the second scan signal line, and the third scan signal line are on a second conductive layer, wherein the first conductive layer and the second conductive layer are different conductive layers disposed on the base substrate.According to the embodiments of the present disclosure, for the first voltage signal line, the light emission control signal line, the first scan signal line, the second scan signal line, the reference voltage signal line, the third scan signal line, and the initialization voltage signal line in the same row of pixel units, the minimum distance of the orthogonal projections of two adjacent signal lines in different conductive layers onto the base substrate in the second direction is smaller than the minimum distance of the orthogonal projections of two adjacent signal lines in the same conductive layers onto the base substrate in the second direction.According to the embodiments of the present disclosure, the display substrate further includes a semiconductor layer and a third conductive layer located on the base substrate, wherein the first conductive layer, the semiconductor layer, the second conductive layer, and the third conductive layer are sequentially disposed away from the base substrate; wherein the display substrate further includes a light shielding portion, wherein the pixel driving circuit includes a driving transistor, wherein the driving transistor includes a channel region, and wherein an orthogonal projection of the channel region onto the base substrate is covered by an orthogonal projection of the light shielding portion onto the base substrate; wherein the light shielding portion is located in the first conductive layer.According to embodiments of the present disclosure, the driving transistor further includes a gate electrode located in the second conductive layer.According to the embodiments of the present disclosure, the pixel driving circuit further includes a storage capacitor, the storage capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode including a first electrode portion located on the semiconductor layer, the second capacitor electrode including a second electrode portion located in the first conductive layer and a third electrode portion located in the third conductive layer, the second electrode portion and the third electrode portion being electrically connected; wherein an orthogonal projection of the first electrode portion onto the base substrate at least partially overlaps an orthogonal projection of the second electrode portion onto the base substrate, and wherein the orthogonal projection of the first electrode portion onto the base substrate at least partially overlaps an orthogonal projection of the third electrode portion onto the base substrate.According to embodiments of the present disclosure, the gate electrode of the driver transistor is electrically connected to the first electrode portion via a first via and / or, the driver transistor further comprises a source electrode and a drain electrode, wherein one of the source electrodes and the drain electrode of the driver transistor is electrically connected to the third electrode portion via a second via, wherein the second electrode portion is electrically connected to the third electrode portion via a third via, and wherein orthogonal projections of the second via and the third via onto the base substrate at least partially overlap.According to embodiments of the present disclosure, the display substrate further includes: a pixel definition layer located on a side of the third conductive layer opposite the base substrate and a plurality of openings located in the pixel definition layer; wherein the plurality of subpixels each include a plurality of openings; wherein, for two adjacent rows of pixel units, orthogonal projections of the openings of the subpixels of one row of pixel units onto the base substrate overlap at least partially with an orthogonal projection of the initialization voltage line of that row of pixel units onto the base substrate, wherein orthogonal projections of the openings of the subpixels of another row of pixel units onto the base substrate overlap at least partially with an orthogonal projection of the first voltage signal line of the other row of pixel units onto the base substrate.According to the embodiments of the present disclosure, the light emitting element includes a first electrode electrically connected to one of the source electrode or the drain electrode of the driving transistor via an anode connection hole; wherein an orthogonal projection of the anode connection hole onto the base substrate is within the orthogonal projection of the third electrode portion onto the base substrate.According to the embodiments of the present disclosure, the pixel driving circuit further includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor each include a gate electrode, a source electrode, and a drain electrode; wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the gate electrode of the driving transistor; wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to the gate electrode of the driving transistor; wherein one of the source electrode and the drain electrode of the third transistor is electrically connected to the second capacitor electrode; and wherein one of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the driving transistor.According to the embodiments of the present disclosure, the gate electrode of the first transistor is electrically connected to the first scan signal line and one of the first data line, the second data line, and the third data line is electrically connected to the gate electrode of the first transistor; and / or the gate electrode of the second transistor is electrically connected to the second scan signal line and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the reference voltage signal line; and / or the gate electrode of the third transistor is electrically connected to the third scan signal line and the other of the source electrode and the drain electrode of the third transistor is electrically connected to the initialization voltage signal line; and / or the gate electrode of the fourth transistor is electrically connected to the light emission control signal line, and the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the first voltage signal line.In another aspect, a display panel is provided that includes the display substrate described above.In yet another aspect, a display device is provided that includes the above-described display substrate or the above-described display panel.BRIEF DESCRIPTION OF THE DRAWINGSWith the following description of the present disclosure with reference to the accompanying drawings, other objects and advantages of the present disclosure will become apparent and the present disclosure may be broadly understood thereby. It shows FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure; FIG. 2 is a schematic top view of multiple subpixels of a display substrate according to an embodiment of the present disclosure; FIG. 3 is a schematic top view of pixel driver circuits of multiple subpixels of a display substrate according to an embodiment of the present disclosure; FIG. 4A is a schematic illustration of a pixel driver circuit of a display substrate according to some embodiments of the present disclosure; FIG. 4B is a partial timing diagram of a pixel driver circuit of a display substrate according to some embodiments of the present disclosure; FIGS. 5 to 14 are each a partial plan view of a display substrate according to embodiments of the present disclosure, schematically illustrating a plan view of a pixel driving circuit of a plurality of subpixels included in the display substrate, wherein FIG. 5 is a partial plan view of a first conductive layer included in the display substrate according to an embodiment of the present disclosure; FIG. 6 is a partial plan view of a semiconductor layer included in the display substrate according to an embodiment of the present disclosure; FIG. 7 is a partial plan view of a second conductive layer included in the display substrate according to an embodiment of the present disclosure; FIG. 8 is a partial plan view of a via included in the display substrate according to an embodiment of the present disclosure; FIG. 9 is a partial plan view of a partial plan view of a third conductive layer included in the display substrate according to an embodiment of the present disclosure; FIG. 10 is a partial plan view of a planarization layer included in the display substrate according to an embodiment of the present disclosure; FIG. 11 is a partial plan view of an anode film layer included in the display substrate according to an embodiment of the present disclosure; FIG. 12 is a partial plan view of a color filter layer included in the display substrate according to an embodiment of the present disclosure; FIG. 13 is a partial plan view of a combination of the film layers included in FIGS. 5 to 12 included in the display substrate according to an embodiment of the present disclosure; and FIG. 14 is a partial plan view of a combination of the film layers included in FIGS. 5 to 10 included in the display substrate according to an embodiment of the present disclosure; FIG. 15 is a partial plan view of a plurality of pixel units included in the display substrate according to an embodiment of the present disclosure; and FIG. 16 is a cross-sectional view of the display substrate along the line AA' in FIG. 13, according to an embodiment of the present disclosure.Note that, for the sake of clarity, in the accompanying drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures, or regions may be enlarged or reduced, that is, these drawings are not drawn to the actual scale.DETAILED DESCRIPTIONTechnical solutions of the present disclosure will be described in more detail below based on the embodiments with reference to the accompanying drawings. In the specification, like or similar reference numerals denote like or similar components. The following descriptions of the embodiments of the present disclosure with reference to the accompanying drawings are intended to explain a general inventive concept of the present disclosure and should not be understood as limiting the present disclosure.Moreover, in the following detailed descriptions, for convenience of explanation, many specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It is to be understood, however, that one or more embodiments may be practiced without these specific details.It should be noted that although the terms "first," "second," etc. may be used herein to describe various components, components, elements, regions, layers, and / or sections, these components, components, elements, regions, layers, and / or sections should not be limited to these terms. Rather, these terms are used to distinguish one component, component, element, region, layer, and / or portion from / another. For example, the first component, the first component, the first element, the first region, the first layer, and / or the first portion discussed below may also be referred to as the second component, the second component, the second element, the second region, the second layer, and / or the second portion without departing from the teachings of the present disclosure.For convenience of description, spatial relational terms such as "top," "bottom," "left," "right," "front," "back," etc. may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It is understood that the spatial relationship terms also cover different orientations of the device during use or operation in addition to the orientation described in the figures. For example, if the device in the figures is turned over, elements described as "below" or "below" other elements or features would then be oriented "above" or "on" the other elements or features.In the present disclosure, the terms "substantially", "about", "about", "approximately" and other similar terms are used as approximate terms rather than degree terms, and these terms explain an inherent deviation of a measured value or a calculated value known to those skilled in the art. Considering factors such as process variations, measurement problems, and errors that are dependent on the measurement of certain quantities (i.e., the constraints of the measurement system), an expression labeled "substantially" or "about" includes the stated value and means that a certain value is within an acceptable range of the deviation for those skilled in the art. For example, "about" may mean that the value is within one or more standard deviations or within ±30%, ±20%, ±10%, ±5% of the stated value.Note that, in the present disclosure, the term "same layer" refers to a layered structure formed by forming a film layer for forming a specific pattern by the same film forming process and then patterning the film layer by a one-time patterning process using the same mask. Depending on the specific pattern, the one-time patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layered structure may be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same patterning process. Generally, the plurality of elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.It will be understood by those skilled in the art that in the present disclosure, unless otherwise specified, the terms "continuous extension", "integrated structure", "overall structure", or similar terms mean that multiple elements, components, structures, and / or portions are in a same view and are normally formed by the same patterning process during the manufacturing process. There are no gaps or fractures between these elements, components, structures and / or sections, but rather structures running continuously.In the present disclosure, the directional terms "first direction" and "second direction" are used to describe different directions along the pixel region, for example, the longitudinal direction and the transverse direction of the pixel region. It should be understood that such illustrations are merely exemplary descriptions and do not limit the disclosure.The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics. Since a source electrode and a drain electrode of the thin film transistor used herein are symmetrical, the source electrode and the drain electrode may be interchanged. In embodiments of the present disclosure, the transistor may include a gate electrode, a first electrode, and a second electrode, wherein the first electrode may represent one of the source electrode and the drain electrode, and the second electrode may represent another one of the source electrode and the drain electrode. In the following examples, a P-type thin film transistor used as a driving transistor will be mainly described, and the types of other transistors may be identical to or different from those of the driving transistor depending on the circuit design. Similarly, in other embodiments, the driver transistor may also be shown as an N-type thin film transistor.In the present disclosure, the term "PPI" (pixels per inch) means the pixel density, i.e., the number of pixels per inch set. Generally, the higher the PPI value, the higher the density at which the display device can display images.In the present disclosure, the term "sharing" may mean that the same signal line, power line, etc. are used together as long as the excitation current or the excitation voltage of the circuit is satisfied. It can be divided, for example, at the same location or at different locations.In the present disclosure, the term "symmetric arrangement" may mean that a certain signal line is used as an axis of symmetry, and the circuits on both sides with respect to the signal line as an axis of symmetry represent a symmetric structure. Alternatively, a particular point may be used as the center of symmetry and the circuits surrounding the center of symmetry may be a symmetric structure.Some example embodiments of the present disclosure provide a display substrate, comprising: a base substrate; a plurality of pixel units arranged on the base substrate, the plurality of pixel units being arranged in an array in a first direction and a second direction to form a plurality of rows of pixel units and a plurality of columns of pixel units, wherein at least one of the pixel units comprises a plurality of sub-pixels, and at least one sub-pixel comprises a light emitting element and a pixel driving circuit for driving the light emitting element; and a plurality of initialization voltage signal lines disposed on the base substrate, wherein an initialization voltage signal is provided to the plurality of targets of pixel units by the plurality of initialization voltage signal lines, the plurality of initialization voltage signal lines being spaced apart from each other in a second direction, wherein at least one of the initialization voltage signal lines extends along a first direction, wherein the plurality of targets of pixel units comprises the 2n-1th row of pixel units and the 2n-th row of pixel units, wherein n is a positive integer, wherein the pixel driver circuits of the 2n-1th and 2n-th rows of pixel units share an initialization voltage signal line.For example, in a plurality of pixel units in a display substrate, adjacent pixel units share an initialization voltage signal line in each row. By adopting the layout provided in this embodiment, the area occupied by the initialization voltage signal line in the display substrate can be reduced, which improves the space utilization of the display substrate, thus contributing to realization of a display device with high PPI and improvement of the display quality of the display device.FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. Referring to FIG. 1, a display substrate according to an embodiment of the present disclosure may include a base substrate 1 and a pixel unit PX disposed on the base substrate 1.The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area in which the pixel unit PX for displaying an image is disposed. Each pixel unit PX will be described later. The non-display area NA is an area where no pixel unit PX is arranged, i.e., no image is displayed. The non-display area NA corresponds to a frame in a final display device, and a width of the frame may be determined according to a width of the non-display area NA.The display area AA may have various shapes. For example, the display area AA may be provided in various shapes such as a closed polygon having straight sides (e.g., a rectangle), a circle, an ellipse, etc. having curved sides, and a semicircle, a half ellipse, etc. having straight sides and curved sides. In the embodiments of the present disclosure, the display area AA is provided as an area having a quadrangular shape with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not a limitation of the present disclosure.The non-display area NA may be disposed on at least one side of the display area AA. In the embodiments of the present disclosure, the non-display area NA may surround an outer periphery of the display area AA. In the embodiments of the present disclosure, the non-display region NA may include a lateral part extending in a first direction X and a longitudinal part extending in a second direction Y.The pixel unit PX is disposed in the display area AA. The pixel unit PX is a minimum unit for displaying an image, and a plurality of pixel units may be provided. For example, the pixel unit PX may include light emitting devices that emit white light and / or colored light.A plurality of pixel units PX may be provided, and the plurality of pixel units PX may be arranged in a matrix form along rows extending in the first direction X and columns extending in the second direction Y. However, in the embodiments of the present disclosure, the arrangement shape of the pixel units PX is not particularly limited, and the pixel units PX may be arranged in various shapes. For example, the pixel units PX may be arranged such that a direction inclined with respect to the first direction X and the first direction Y is a column direction and a direction intersecting the column direction is a row direction.That is, a plurality of pixel units PX are arrayed along the first direction X and the second direction Y to form a plurality of rows of pixel units and a plurality of columns of pixel units.A pixel unit PX may include a plurality of subpixels. For example, a pixel unit PX may include three sub-pixels, i.e., a first sub-pixel SP 1, a second sub-pixel SP 2, and a third sub-pixel SP 3. For example, the first subpixel SP 1 may be a red subpixel, the second subpixel SP 2 may be a green subpixel, the third subpixel SP 3 may be a blue subpixel.Note that, in the embodiments of the present disclosure, the number of subpixels included in one pixel unit is not particularly limited and is not limited to the above three.For example, in the embodiment shown in FIG. 1, a scan signal line 101 and a data line 102 are schematically illustrated. That is, the display substrate may further include: a plurality of scan signal lines 101 and a plurality of data lines 102 arranged on the base substrate. A scan signal is provided to a plurality of rows of pixel units by the plurality of scan signal lines 101 and a data signal is provided to a plurality of columns of pixel units by the plurality of data lines 102. The scan signal lines 101 extend along the first direction X, and the plurality of scan signal lines 101 are spaced apart from each other along the second direction Y. The data lines 102 extend along the second direction Y, and the plurality of data lines 102 are spaced apart from each other along the first direction X.For example, the scan signal lines may represent a horizontal conductive trace and the data lines may represent a vertical conductive trace. It is understood that the horizontal conductive path may also include other types of lines or conductive paths used to provide other signals, and that the vertical conductive paths may also include other types of lines or conductive paths used to provide other signals.Each subpixel may include a light emitting element and a pixel driving circuit for driving the light emitting element. For example, in an OLED display substrate or an OLED display panel, the light emitting element of the subpixel may include an anode, a light emitting material layer, and a cathode, which are arranged in a stack. The anodes of the light-emitting elements of the individual subpixels are arranged spaced apart from one another and arranged in a matrix along the rows running in the first direction X and the columns running in the second direction Y.For convenience of description, in the present disclosure, in each of the plan views, a corresponding subpixel is represented by orthogonally projecting the anode of the light emitting element of the subpixel onto the base substrate.FIG. 2 is a schematic plan view of a plurality of subpixels of a display substrate according to an embodiment of the present disclosure, and FIG. 3 is a schematic plan view of pixel driving circuits of a plurality of subpixels of a display substrate according to an embodiment of the present disclosure.Referring to FIGS. 2 and 3 together, the display substrate may include multiple rows of pixel units, for example, the 2n-1th row of pixel units and the 2n-th row of pixel units, each pixel unit including multiple sub-pixels, e.g., sub-pixels SP 1, SP 2, and SP 3, wherein sub-pixels SP 1, SP 2, and SP 3 are arranged in the same row side by side along the first direction X, i.e., arranged side by side in the horizontal direction.The first subpixel SP 1 may include a first light emitting element located in a first light emitting region and a first pixel driving circuit SPC 1 used for driving the first light emitting element, and the first light emitting element may emit red light; the second subpixel SP 2 may include a second light emitting element located in a second light emitting region and a second pixel driving circuit SPC 2 used for driving the second light emitting element, and the second light emitting element may emit green light; The third subpixel SP 3 may include a third light emitting element located in a third light emitting region and a third pixel driving circuit SPC 3 used for driving the third light emitting element, and the third light emitting element may emit blue light.Note that the light emitting region of the subpixel may be a region where the light emitting element of the subpixel is located. For example, the light emitting region of the subpixel may represent a region corresponding to the anode of the light emitting element of the subpixel, or the light emitting region of the subpixel may represent a region corresponding to a portion of the light emitting material layer that is between the anode and the cathode.In an embodiment of the present disclosure, the orthogonal projections of the pixel driver circuits of a plurality of subpixels onto the base substrate each at least partially overlap with the orthogonal projection of the light emitting element of the same subpixel onto the base substrate. For example, referring to FIGS. 2 and 3, the orthogonal projections of the pixel driving circuits SPC 1 of a plurality of sub-pixels onto the base substrate each at least partially overlap with the orthogonal projection of the light emitting element of the same sub-pixel SP 1 onto the base substrate. In an optional embodiment, different pixel driver circuits may also overlap with the orthogonal projection of the light emitting element of the same subpixel onto the substrate.For example, in the embodiment of the present disclosure, the pixel driving circuits SPC 1, SPC 2, and SPC 3 of the plurality of subpixels SP 1, SP 2, and SP 3 respectively correspond to the corresponding subpixels. That is, the pixel driving circuit SPC 1 of the subpixel SP 1 overlaps at least partially with the orthogonal projection of the subpixel SP 1 onto the base substrate. The same applies to the subpixel SP 2 and the subpixel SP 3.Note that in the illustrated embodiment, the orthogonal projection of the pixel driving circuit of a subpixel onto the base substrate overlaps, at least in part, with the orthogonal projection of the light emitting element of the same subpixel onto the base substrate, i.e., the pixel driving circuit of a subpixel corresponds to the light emitting element of a subpixel, but embodiments of the present disclosure are not limited thereto. In other embodiments, the pixel driving circuits of more than 2 subpixels may be provided to correspond to the light emitting element of one subpixel. For example, the pixel driving circuits of three sub-pixels correspond to a light emitting element of one sub-pixel, or the pixel driving circuits of four sub-pixels correspond to a light emitting element of one sub-pixel.In FIG. 3, an anode connection hole VHA is schematically illustrated with a dotted box. Through the anode connection hole VHA, the anode of the light emitting element of each subpixel may be electrically connected to the underlying pixel driving circuit, so that the respective light emitting elements may be driven by the pixel driving circuits of the individual subpixels.In the embodiment of the present disclosure, the layout of the individual subpixels remains unchanged and the horizontal side-by-side layout is further adopted, wherein the pixel driving circuits of the individual subpixels are distributed in the same row at positions corresponding to the respective subpixels, wherein the light emitting elements of the individual subpixels can still be electrically connected to the underlying pixel driving circuits via the anode connection holes VHA, so that the respective light emitting elements can still be driven by the pixel driving circuits of the individual subpixels.For example, in FIG. 2, the contours of the orthogonal projections of the anodes of the light-emitting elements of the individual subpixels onto the substrate can be schematically represented by the individual rectangular frames; while in FIG. 3, the contours of the orthogonal projections of the pixel driver circuits of the individual subpixels onto the base substrate are schematically represented by the individual rectangular frames with solid lines.Note that, in FIGS. 1 to 3, although rectangular frames are used to represent the individual subpixels and their pixel driving circuits, it should be understood that the rectangular frame only schematically represents the layout of the individual subpixels and their pixel driving circuits, and the shape of the subpixels and their pixel driving circuits are not limited by the shape of the frames.In this embodiment, for the same subpixel, the relationship between the orthogonal projection of the subpixel's pixel driving circuit onto the base substrate and the orthogonal projection of the subpixel's light emitting element anode onto the base substrate is as follows: the orthogonal projection of the subpixel's pixel driving circuit onto the base substrate is located at the orthogonal projection of the subpixel's light emitting element anode onto the base substrate.In other optional embodiments, the orthogonal projection of the subpixel light-emitting element pixel driver circuit onto the base substrate exceeds the orthogonal projection of the subpixel light-emitting element anode onto the base substrate in the first direction X; and / or the orthogonal projection of the subpixel light-emitting element anode onto the substrate substrate exceeds the orthogonal projection of the subpixel light-emitting element pixel driver circuit onto the substrate substrate in the second direction Y.In an embodiment of the present disclosure, as shown in FIG. 3, each row has a plurality of pixel units, the subpixels of each pixel unit are arranged along the first direction X, and the display substrate has a plurality of rows of pixel units, e.g., the 2n-1st and 2n-th rows of pixel units, wherein the pixel driver circuits of the adjacent 2n-1st and 2n-th rows of pixel units share an initialization voltage signal line Vinil.In the embodiment of the present disclosure, each column also includes a plurality of pixel units, and the display substrate includes a plurality of columns of pixel units, for example, the 2m-1th column and the 2m-th column of pixel units, wherein the pixel driving circuits of the adjacent 2m-1th and 2m-th columns of pixel units share an initialization voltage signal line Vini 2, the initialization voltage signal line Vini being electrically connected to the initialization voltage signal line Vini 2. The pixel driving circuits of the 2m-1th and 2m-th columns of pixel units share a reference voltage signal line Vref2.FIG. 4A is a schematic illustration of a pixel driver circuit of a display substrate in accordance with some embodiments of the present disclosure. The pixel driving circuit shown in FIG. 4A may be any one of the above-mentioned pixel driving circuits SPC 1, SPC 2, and SPC 3. Referring to FIG. 4A, the pixel driving circuit may include a first transistor T 1, a second transistor T 2, a third transistor T 3, a fourth transistor T 4, a fifth transistor T 5, a first storage capacitor C, and a second storage capacitor C'. This pixel driver circuit may be referred to as a 5T2C structure.Note that the 5T2C structure is exemplified herein in the description of the pixel driving circuit included in the display substrate according to the embodiments of the present disclosure. However, the pixel driving circuit included in the display substrate according to the embodiments of the present disclosure is not limited to the 5T2C structure.With further reference to FIG. 4A, a gate electrode of the first transistor T 1 is electrically connected to a first scan signal line G 1 to receive a first scan signal. A first electrode (e.g., source electrode S 1) of the first transistor T 1 is electrically connected to data lines DR, DG, DB for receiving data signals. A second electrode (e.g., drain electrode D 1) of the first transistor T 1 is electrically connected to a node G.A gate electrode of the second transistor T 2 is electrically connected to a second scan signal line G 2 to receive a second scan signal. A first electrode (e.g., source electrode S 2) of the second transistor T 2 is electrically connected to a reference voltage signal line Vrefl. A second electrode (e.g., drain electrode D 2) of the second transistor T 2 is electrically connected to the node G.A gate electrode of the third transistor T 3 is electrically connected to a third scan signal line G 3. A first electrode (e.g., source electrode S 3) of the third transistor T 3 is electrically connected to an initialization voltage signal line ViniI to receive an initialization voltage signal. A second electrode (e.g., drain electrode D 3) of the third transistor T 3 is electrically connected to a node S.A gate electrode of the fourth transistor T 4 is electrically connected to a light emission control signal line EM to receive the light emission control signal. A first electrode (e.g., source electrode S 4) of the fourth transistor T 4 is electrically connected to a second electrode (e.g., drain electrode D 5) of the fifth transistor, and a second electrode (e.g., drain electrode D 4) of the fourth transistor is electrically connected to a first voltage signal line VDD 1.A gate electrode of the fifth transistor T 5 (also referred to as a driver transistor) is electrically connected to the node G. A first electrode (e.g., source electrode S 5) of the fifth transistor T 5 is electrically connected to the node S. The second electrode (e.g., drain electrode D 5) of the fifth transistor T 5 is electrically connected to the first electrode (e.g., source electrode S 4) of the fourth transistor.FIG. 4B is a partial timing diagram of a pixel driver circuit of a display substrate according to some embodiments of the present disclosure. The operation principle of the pixel driving circuit provided by the embodiment of the present disclosure will be described in more detail below with reference to FIGS. 4A and 4B.In a first reset phase T 1, EM is a high voltage turn-on signal, G 1, G 2, and G 3 are all low voltage turn-off signals. The EM controlled transistor T4 is turned on, the G1 controlled transistor T1, the G2 controlled transistor T2 and the G3 controlled transistor T3 are all turned off. A first voltage (e.g., VDD voltage) is written to the drain of the driver transistor T 5.In a second reset phase T 2, EM and G 1 are low-voltage turn-off signals, G 2 and G 3 are high-voltage turn-on signals. Transistor T1 controlled by G1 and transistor T4 controlled by EM are all off, and transistor T2 controlled by G2 and transistor T3 controlled by G3 are all on. The anode of the light emitting element (for example, the light emitting diode OLED) is electrically connected to the source electrode of the driving transistor T 5. The initialization voltage Vini is written in the source electrode of the driving transistor T 5 and the anode of the light emitting element, and the potential of the anode of the light emitting element is reset to Vini. At the same time, the potential difference between Vini and the cathode voltage VSS of the light-emitting element is optimally smaller than a turn-on threshold voltage of the light-emitting element. This ensures that no light is emitted from the light emitting element at this time, thereby improving the brightness quality of the display in the dark state and improving the contrast. The reference voltage Vref is written in the gate electrode of the driving transistor T 5. The potential difference between the reference voltage Vref and the VDD voltage is the Vgs of the driving transistor T5, thereby ensuring that a large current flows through the driving transistor T5 when a high current flows through the driving transistor T5, and thus the characteristic drift of the driving transistor T5 due to the load under the small current is eliminated or reduced, and the brightness ghosts resulting therefrom, which occur during the transition of shaked images to white images, are eliminated or attenuated when the display transitions from a state in which the display displays a low brightness for a longer period of time at a small current to another state in which the display displays a high brightness at a high current. In this case, the driver transistor T 5 can operate in the magnification range or in the saturation range in this phase at the high current of the driver transistor T 5 as a function of different Vref and Vini voltages. Theoretically, the driver transistor T5 best operates in the saturation region where the current flowing through the MDT can be maximized. At the same time, in the second reset phase T 2, the potentials at both ends of the storage capacitor Cst are reset, so that the writing of this frame signal is not influenced by the previous frame signal.In a compensation phase T 3, EM and G 2 are both high voltage turn-on signals, G 1 and G 3 are low voltage turn-off signals, the transistor T 1 controlled by G 1 and the transistor T 3 controlled by G 3 are all turned off, and the transistor T 2 controlled by G 2 and the transistor T 4 controlled by EM are all turned on. During this process, the voltage of the node S is gradually charged to the difference between the reference voltage and the transistor threshold voltage Vth until the transistor T 5 is turned off and the compensation process is ended. At this time, Vgs-Vth=0 of the driving transistor T 5. Since Vg= Vref, Vs= Vg-Vth= Vref-Vth, whereby the potential difference between the both ends of the storage capacitor Cst represents the threshold voltage Vth of the driving transistor T 5.In a data writing phase T 4, G 1 is a high voltage turn-on signal, G 2, G 3, and EM are all low voltage turn-off signals. Transistor T1 controlled by G1 is turned on, transistor T2 controlled by G2, transistor T3 controlled by G3, and transistor T4 controlled by EM are all turned off. The data signal Vdata is written into the gate electrode of the driving transistor T 5. At this time, since one end of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T 5, the data voltage Vdata is stored at the node G, i.e., the voltage of the storage capacitor Cst at the node G represents Vdata.In a light emission phase T 5, G 1, G 2, and G 3 are low voltage turn-off signals, EM is a high voltage turn-on signal, the transistor T 1 controlled by G 1, the transistor T 2 controlled by G 2, and the transistor T 3 controlled by G 3 are all turned off, and the transistor T 4 controlled by EM is turned on. The voltage difference Vsg between the source and gate of the driving transistor T5 can be calculated by the following formula: Vsg=Vdata-Vref. From this, it can be concluded that the current flowing through the driver transistor T 5 (i.e., the current flowing through the OLED) is Id=k(Vdata-Vref)2, where k is a constant coefficient that depends on the mobility and width-to-length ratio and the value of gate-source capacitor of the driver transistor T 5. In this way, the magnitude of Id depends only on the data voltage Vdata and the reference voltage Vref. Vref is a DC signal, therefore the magnitude of Id depends only on the data voltage Vdata. Therefore, in the embodiment of the present disclosure, by the circuit structure of the specific embodiment of the pixel driving circuit as shown in FIG. 4A, not only the threshold voltage difference of the driving transistor but also the IR drop (IR voltage drop) on the first voltage signal line VDD 1 can be compensated.FIGS. 5 to 14 are each a partial plan view of a display substrate according to embodiments of the present disclosure, schematically illustrating a plan view of a pixel driving circuit of a plurality of subpixels included in the display substrate, wherein FIG. 5 is a partial plan view of a first conductive layer included in the display substrate according to an embodiment of the present disclosure; FIG. 6 is a partial plan view of a semiconductor layer included in the display substrate according to an embodiment of the present disclosure; FIG. 7 is a partial plan view of a second conductive layer included in the display substrate according to an embodiment of the present disclosure; FIG. 8 is a partial plan view of a via included in the display substrate according to an embodiment of the present disclosure; FIG. 9 is a partial plan view of a third conductive layer included in the display substrate according to an embodiment of the present disclosure; FIG. 10 is a partial plan view of a planarization layer included in the display substrate according to an embodiment of the present disclosure; FIG. 11 is a partial plan view of an anode film layer included in the display substrate according to an embodiment of the present disclosure; FIG. 12 is a partial plan view of a color filter layer included in the display substrate according to an embodiment of the present disclosure; FIG. 13 is a partial plan view of a combination of the film layers included in the display substrate according to an embodiment of the present disclosure; FIG. 14 is a partial plan view of a combination of the film layers included in FIGS. 5 to 10 included in the display substrate according to an embodiment of the present disclosure; FIG. 15 is a partial plan view of a plurality of pixel units included in the display substrate according to an embodiment of the present disclosure; FIG. 16 is a cross-sectional view of the display substrate along the line AA' in FIG. 13 according to an embodiment of the present disclosure.Referring to FIGS. 5 to 16, the display substrate may include at least one semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers. For example, at least one insulating layer may be provided between adjacent semiconductor layers and conductive layers and between adjacent conductive layers.First, as shown in FIGS. 5 to 16, the first conductive layer 10 is formed on the base substrate, the semiconductor layer 20 is formed on a base substrate opposite side of the first conductive layer 10, the second conductive layer 30 is formed on a base substrate opposite side of the semiconductor layer 20, the third conductive layer 40 is formed on a base substrate opposite side of the second conductive layer 30, and the planarization layer 50, the anode film layer 60, the color filter layer 70, and other film layers are sequentially formed on a base substrate 50 opposite side of the third conductive layer 40. In embodiments of the present disclosure, one or more insulating layers may be disposed between conductive layers.For example, the semiconductor layer may include materials such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor, and include, for example, a channel region, a source region, and a drain region. The channel region may be undoped or doped with a type other than the source region and the drain region and thus has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and are doped with impurities and are therefore conductive. The impurities may be varied depending on whether the TFT is an N- or P-type transistor. For example, in embodiments of the present disclosure, the individual transistors may be N-type thin film transistors.In embodiments of the present disclosure, as shown in FIGS. 5 to 14, a plurality of pixel units are provided on one side of the base substrate of the display substrate, the plurality of pixel units being arrayed in a first direction X and a second direction Y to form a plurality of targets of pixel units and a plurality of columns of pixel units, at least one of the pixel units including a plurality of sub-pixels, and at least one sub-pixel including a light emitting element and a pixel driving circuit for driving the light emitting element. A plurality of initialization voltage signal lines Vinilis provided on the base substrate, an initialization voltage signal is provided to the plurality of targets of pixel units by the plurality of initialization voltage signal lines Vini, respectively, the plurality of initialization voltage signal lines Viniare arranged spaced apart from each other in the second direction Y, that is, a plurality of initialization voltage signal lines Viniare arranged spaced apart from each other in the second direction Y. The at least one of the initialization voltage signal lines Vini extends along the first direction X, i.e., the initialization voltage signal line Vini extends horizontally in the first direction X. Each row of pixel units includes pixel units in odd rows and even rows, where the pixel units in odd rows and even rows share an initialization voltage signal line Vini.For example, as illustrated in FIGS. 5 and 15, the 2n-1st row (e.g., the first row) of pixel units that is below the initialization voltage signal line ViniI and the 2n-th row (e.g., the second row) of pixel units that is above the initialization voltage signal line ViniI share a middle initialization voltage signal line ViniI. Other rows of pixel units, such as the third row of pixel units and the fourth row of pixel units, share an initialization voltage signal line ViniI. Similarly, the pixel driving circuits of the adjacent rows of pixel units may be allowed to share an initialization voltage signal line, thereby effectively reducing the area occupied by the initialization voltage signal line, so that the design of the pixel driving circuit may be simplified and, at the same time, a reduction in the area occupied by the pixel driving circuit or the pixel units may be achieved to meet the high resolution requirements of the display substrate.As shown in FIG. 9, the display substrate also includes a plurality of initialization voltage signal leads Vini 2 disposed on the base substrate. The initialization voltage signal line Vini 2 is electrically connected to the initialization voltage signal line Vini 2 via a via, for example. The plurality of initialization voltage signal lines Vini 2 are arranged spaced apart from each other along the first direction X, wherein at least one initialization voltage signal line Vini 2 extends along the second direction, i.e., the initialization voltage signal line Vini 2 extends in the Y direction.The pixel driving circuits of the pixel units in odd and even columns share an initialization voltage signal line Vini 2. For example, the pixel driving circuits of the pixel units in the first column and the second column share an initialization voltage signal line Vini 2, the pixel driving circuits of the pixel units in the third column and the fourth column share an initialization voltage signal line Vini 2, and so on.According to embodiments of the present disclosure, the area occupied by the initialization voltage signal line can be effectively reduced by the pixel driving circuits of adjacent pixel units of column pixels sharing the initialization voltage signal line Vini 2. At this time, based on the above-mentioned use of the initialization voltage signal line ViniI, the design of the pixel driving circuits is further simplified, and the area occupied by the pixel driving circuit or pixel unit is significantly reduced, and the ultra high resolution requirements of the display substrate are satisfied.As shown in FIG. 9, the display substrate also includes a plurality of reference voltage signal leads Vref 2 disposed on the substrate substrate. The reference voltage signal line Vref 2 is used to provide a reference voltage. The plurality of reference voltage signal lines Vref2 are spaced apart from each other along the first direction, and at least one reference voltage signal line Vref2 extends along the second direction, the reference voltage signal line Vref2 as shown in FIG. 9 extends in the Y direction. The pixel driving circuits of the pixel units in odd and even columns share the reference voltage signal line Vref 2.As shown in FIG. 5, the display substrate also includes a plurality of first voltage signal leads VDD 2 disposed on the base substrate. The first voltage signal supply line VDD 2 is used to provide a first voltage to the light emitting element. The plurality of voltage signal leads VDD 2 are spaced apart from each other along the first direction, and at least one first voltage signal lead VDD 2 extends along the second direction. The pixel driving circuits of the pixel units other than the above-mentioned pixel units in the column pixel unit share the first voltage signal line. For example, the pixel driving circuits of the pixel units in the second column and the third column share a first voltage signal supply line VDD 2. The pixel driving circuits of the pixel units in the fourth column and the fifth column share a first voltage signal supply line VDD 2.As shown in FIG. 9, the display substrate also includes a plurality of first voltage signal lines VDD 1 disposed on the base substrate and electrically connected to the first voltage signal lines VDD 2. In particular, the electrical connection can be achieved by a through-via, wherein the plurality of first voltage signal lines VDD 1 are arranged spaced apart from one another along the second direction and at least one first voltage signal line VDD 1 extends along the first direction, i.e. the first voltage signal line VDD 1 extends along the X direction.The pixel driving circuits of the pixel units of adjacent pixel rows share the first voltage signal line VDD 1. The pixel units of the adjacent pixel lines here are different from the above-mentioned pixel units of the adjacent pixel lines, for example, which here refer to the pixel driving circuits of the pixel units in the second and third lines sharing a first voltage signal line VDD 1, and the pixel driving circuits of the pixel units in the fourth and fifth lines sharing a first voltage signal line VDD 1.As shown in FIG. 5, the pixel driving circuits of the pixel units in odd and even rows are arranged symmetrically with respect to the common initialization voltage signal line Vinil. That is, the driving circuits of the pixel units on both sides of the initialization voltage signal line Vinil are arranged symmetrically to each other with respect to the initialization voltage signal line Vinil as an axis of symmetry. For example, the pixel driving circuits of the pixel units in the first and second rows are symmetric with respect to the common initialization voltage signal line Vinil, and the pixel driving circuits of the pixel units in the third and fourth rows are symmetric with respect to the common initialization voltage signal line Vinil, etc.As shown in FIGS. 5 and 15, the pixel driving circuits of adjacent row pixel units are arranged symmetrically with respect to the common first voltage signal line VDD 1. That is, the pixel driving circuits of the pixel units in the 2n-th row and the 2n+1-th row are arranged symmetrically with respect to the first voltage signal line VDD 1. For example, the pixel driving circuits of the pixel units in the second row and the third row are arranged symmetrically with respect to the common first voltage signal line VDD 1, and the pixel driving circuits of the pixel units in the fourth row and the fifth row are arranged symmetrically with respect to the common first voltage signal line VDD 1, and so on.As shown in FIGS. 9 and 15, the pixel driving circuits of the sub-pixel columns close to the common first voltage signal line are arranged in adjacent column pixel units symmetrically with respect to the common first voltage signal line VDD 2. That is, the pixel driving circuits of the sub-pixel columns close to the common first voltage signal supply line in the pixel units of the 2m-th column and the 2m+1-th column are arranged symmetrically with respect to the first voltage signal supply line VDD 2. For example, the pixel driving circuits of the sub-pixel columns close to the common first voltage signal line in the pixel units of the second column and the pixel driving circuits of the sub-pixel columns close to the common first voltage signal line in the pixel units of the third column are arranged symmetrically with respect to the common first voltage signal line VDD 2, and the pixel driving circuits of the sub-pixel columns close to the common first voltage signal line in the pixel units of the fourth column and the pixel driving circuits of the sub-pixel columns close to the common first voltage signal line in the pixel units of the fifth column are arranged symmetrically with respect to the common first voltage signal line VDD 2.As shown in FIG. 7, the base substrate further includes a light emission control signal line EM, a first scan signal line G 1, a second scan signal line G 2, a third scan signal line G 3, and a reference voltage signal line Vrefl.Here, a plurality of light emission control signal lines EM are arranged on one side of the base substrate, a light emission control signal is provided to a plurality of rows of pixel units by the plurality of light emission control signal lines EM, respectively, and the plurality of light emission control signal lines EM are arranged spaced apart from each other along the second direction Y, and at least one of the light emission control signal lines EM extends along the first direction X.A plurality of first scan signal lines G 1 are disposed on one side of the base substrate, a first scan signal is provided to a plurality of rows of pixel units by the plurality of first scan signal lines G 1, and the plurality of first scan signal lines G 1 are spaced apart from each other along the second direction Y, and at least one of the first scan signal lines G 1 extends along the first direction X.A plurality of second scan signal lines G 2 are disposed on one side of the base substrate, a second scan signal is provided to a plurality of rows of pixel units by the plurality of second scan signal lines G 2, the plurality of second scan signal lines G 2 are spaced apart from each other along the second direction Y, and at least one of the second scan signal lines G 2 extends along the first direction X.A plurality of third scan signal lines G 3 are disposed on one side of the base substrate, a third scan signal is provided to a plurality of rows of pixel units by the plurality of third scan signal lines G 3, the plurality of third scan signal lines G 3 are spaced apart from each other along the second direction, and at least one of the third scan signal lines G 3 extends along the first direction.As shown in FIG. 14, the reference voltage signal lines Vrefl are disposed on one side of the base substrate. The reference voltage signal line Vrefl is electrically connected to the reference voltage signal line Vref 2 via a via, for example, wherein the plurality of reference voltage signal lines Vrefl are arranged spaced apart from each other along the second direction Y, and wherein at least one of the reference voltage signal lines Vrefl extends along the first direction X.As shown in FIG. 14, for pixel units in adjacent rows, the respective first voltage signal lines VDD 1, the respective light emission control signal lines EM, the respective first scan signal lines G 1, the respective second scan signal lines G 2, the respective reference voltage signal lines Vrefl, and the respective third scan signal lines G 3 of the two rows of pixel units, e.g., the first and second rows of pixel units or the third and fourth rows of pixel units, etc., are located on both sides of the common initialization voltage signal line, respectively, in the second direction Y.In the embodiment of the present disclosure, as shown in FIGS. 7 and 14, the distances of the first voltage signal lines VDD 1, the light emission control signal lines EM, the first scan signal lines G 1, the second scan signal lines G 2, the reference voltage signal lines Vrefl, and the third scan signal lines G 3 of the pixel units in the odd-numbered row are gradually decreased from the common initialization voltage signal line Vinil in the second direction Y.In the embodiment of the present disclosure, the distances of the first voltage signal lines VDD 1, the light emission control signal lines EM, the first scan signal lines G 1, the second scan signal lines G 2, the reference voltage signal lines Vrefl, and the third scan signal lines G 3 of the pixel units in the even-numbered row adjacent to this odd-numbered row are gradually decreased from the common initialization voltage signal line Vinil in the second direction Y.As mentioned above, the first voltage signal lines VDD 1, the light emission control signal lines EM, the first scan signal lines G 1, the second scan signal lines G 2, the reference voltage signal lines Vrefl, and the third scan signal lines G 3 of the pixel units in the even and odd rows are arranged symmetrically in the second direction Y with respect to the common initialization voltage signal line Vinil as an axis of symmetry.As shown in FIGS. 12 to 14, the plurality of sub-pixels on the display substrate include a first sub-pixel, a second sub-pixel, and a third sub-pixel. For example, the first subpixel may be a red subpixel R, the second subpixel may be a green subpixel G, and the third subpixel may be a blue subpixel B. The display substrate also includes a first data lead DR, a second data lead DG, and a third data lead DB. As shown in FIGS. 9 and 14, the first data line DR, the second data line DG, and the third data line DB may be disposed on the third conductive layer 40. In this case, a first data signal is provided to a plurality of columns of first subpixels R by the first data lines DR, wherein the plurality of first data lines DR are arranged spaced apart from one another along the first direction X and at least one of the first data lines DR extends along the second direction Y. A second data signal is provided to the plurality of columns of second subpixels G by the second data lines DG, wherein the plurality of second data lines DG are arranged spaced apart from one another along the first direction X and at least one of the second data lines DG extends along the second direction Y. A third data signal is respectively provided to the plurality of columns of third subpixels B by the third data lines DB, wherein the plurality of third data lines DB are arranged spaced apart from one another along the first direction X and at least one of the third data lines DB extends along the second direction Y.For example, a first data signal is provided to each column of first subpixels R by each first data line DR extending along the second direction Y, a second data signal is provided to each column of second subpixels G by each second data line DG extending along the second direction Y, and a third data signal is provided to each column of third subpixels B by each third data line DB extending along the second direction Y.As shown in FIGS. 9 and 14, for the pixel units in an odd-numbered and even-numbered column (as in the first and second columns), the respective first voltage signal leads VDD 2, the first data leads DR, the second data leads DG, and the third data leads DB of the pixel units in the two adjacent columns are respectively located on both sides of the common initialization voltage signal lead Vini 2 and the common reference voltage signal lead Vref 2 in the first direction X.In embodiments of the present disclosure, as shown in FIGS. 9 and 14, the first voltage signal supply line VDD 2, the first data supply line DR, the second data supply line DG, and the third data supply line DB of the pixel units are located in an odd-numbered column (e.g., the first column) on a side of the common initialization voltage signal supply line Vini 2 facing away from the common reference voltage signal supply line Vref 2, and the distances of the first voltage signal supply line VDD 2, the first data supply line DR, the second data supply line DG, and the third data supply line DB of the odd-numbered column pixel units are gradually decreased from the common initialization voltage signal supply line Vini 2 in the first direction X. The first voltage signal line VDD 2, the first data line DR, the second data line DG, and the third data line DB of the pixel units in an even-numbered column adjacent to this odd-numbered column and having the common initialization voltage signal line Vini 2 are located on a side of the common reference voltage signal line Vref 2 facing away from the common initialization voltage signal line Vini 2. The distances of the first data line DR, the second data line DG, the third data line DB, and the first voltage signal line VDD 2 of the even-numbered column pixel units are gradually increased from the common reference voltage signal line Vref 2 in the first direction X.In the embodiment of the present disclosure, as shown in FIG. 5, the first voltage signal line VDD 1, the reference voltage signal line Vrefl, and the initialization voltage signal line Vinil are located in the first conductive layer 10.As shown in FIGS. 7 and 16, the light emission control signal line EM, the first scan signal line G 1, the second scan signal line G 2, and the third scan signal line G 3 are located in the second conductive layer 30, and the first conductive layer 10 and the second conductive layer 30 are different conductive layers disposed on the base substrate. For example, other film layers, such as an insulating layer and a semiconductor layer 20, may be disposed between the first conductive layer 10 and the second conductive layer 30.In the embodiment of the present disclosure, the minimum distance between the orthogonal projections of the two adjacent and in-different-layer signal lines of the first voltage signal line VDD 1, the light emission control signal lines EM, the first scan signal line G 1, the second scan signal line G 2, the reference voltage signal line Vrefl, the third scan signal line G 3, and the initialization voltage signal line Vinil of the pixel units in the same row onto the base substrate in the second direction is smaller than the minimum distance between the orthogonal projections of the two adjacent and in-layer signal lines onto the base substrate in the second direction.For example, in various conductive layers, the first voltage signal line VDD 1 is adjacent to the light emission control signal line EM, and d 1 represents the minimum distance between the orthogonal projections of the first voltage signal line VDD 1 and the light emission control signal line EM on the base substrate in the second direction Y. In the same conductive layer, the reference voltage signal line Vrefl is adjacent to the initialization voltage signal line Vinil, and d 2 represents the minimum distance between the orthogonal projections of the reference voltage signal line Vrefl and the initialization voltage signal line Vinil onto the base substrate in the second direction Y, where d 1 is less than d 2. According to an embodiment of the present disclosure, by disposing the first voltage signal line VDD 1, the light emission control signal lines EM, the first scan signal line G 1, the second scan signal line G 2, the reference voltage signal line Vrefl, the third scan signal line G 3, and the initialization voltage signal line Vinil in different conductive layers with the above-mentioned intervals, the space occupied by the pixel driving circuits of the pixel units is saved as much as possible to achieve high resolution of the display substrate.As shown in FIG. 16, the display substrate also includes a semiconductor layer 20 and a third conductive layer 40 disposed on the base substrate. The first conductive layer 10, the semiconductor layer 20, the second conductive layer 30, and the third conductive layer 40 are sequentially disposed away from the base substrate. In embodiments of the present disclosure, other film layers, such as insulating layers, etc., may also be provided between the first conductive layer 10, the semiconductor layer 20, the second conductive layer 30, and the third conductive layer 40.In an embodiment of the present disclosure, as shown in FIG. 14, the pixel driving circuit includes a plurality of transistors such as a first transistor T 1, a second transistor T 2, a third transistor T 3, a fourth transistor T 4, and a fifth transistor T 5. Each transistor has a source electrode S and a drain electrode D. For example, the first transistor includes a source electrode S 1 and a drain electrode D 1, the second transistor includes a source electrode S 2 and a drain electrode D 2, the third transistor includes a source electrode S 3 and a drain electrode D 3, the fourth transistor includes a source electrode S 4 and a drain electrode D 4, and the fifth transistor includes a source electrode S 5 and a drain electrode D 5.In an embodiment of the present disclosure, as shown in FIGS. 5 and 14, the display substrate further includes a light shielding portion LS, the pixel driving circuit includes a driving transistor (for example, the fifth transistor T 5). The transistor includes a channel region, wherein from an orthogonal projection of the light shielding portion LS onto the base substrate, an orthogonal projection of the channel region onto the base substrate is covered, wherein the light shielding portion LS is located in the first conductive layer 10.As shown in FIGS. 7 and 14, the driving transistor further includes a gate electrode Ga. The gate electrode Ga is located in the second conductive layer 30 and is used for controlling the on-state of the driving transistor.In an embodiment of the present disclosure, as shown in FIG. 16, the pixel driving circuit also includes a storage capacitor (such as Cst 1 and Cst 2). The storage capacitor includes a first capacitor electrode Cst 1 and a second capacitor electrode Cst 2. The first capacitor electrode Cst 1 includes a first electrode portion C 1 located in the semiconductor layer. The second capacitor electrode Cst 2 includes a second electrode portion C 2 located in the first conductive layer and a third electrode portion C 3 located in the third conductive layer 40. The second electrode portion C 2 is electrically connected to the third electrode portion C 3 through the third via VH 3, for example.As shown in FIG. 16, an orthogonal projection of the first electrode portion C 1 onto the base substrate 1 overlaps at least partially with an orthogonal projection of the second electrode portion C 2 onto the base substrate 1, and the orthogonal projection of the first electrode portion C 1 onto the base substrate 1 overlaps at least partially with an orthogonal projection of the third electrode portion C 3 onto the base substrate 1.As shown in FIG. 8, the gate electrode of the driving transistor T 5 is electrically connected to the first electrode portion C 1 via the first via VH 1. The driver transistor also includes a source electrode S5 and a drain electrode D5. One (for example, the source electrode S 5) of the source electrode S 5 and the drain electrode D 5 of the driving transistor T 5 is electrically connected to the third electrode portion C 3 via the second via VH 2, and the second electrode portion C 2 is electrically connected to the third electrode portion C 3 via the third via VH 3, wherein orthogonal projections of the second via VH 2 and the third via VH 3 onto the base substrate at least partially overlap. The drain electrode D 4 of the fourth transistor T 4 is electrically connected to the first voltage signal line VDD 1 via the third via VH 3, and the source electrode S 4 of the fourth transistor T 4 is electrically connected to the drain electrode D 5 of the driving transistor T 5 via the fifth via VH 5 and the sixth via VH 6. Specifically, the source electrode S 4 of the fourth transistor is electrically connected to ACT 3 in the third conductive layer via the fifth via VH 5, and ACT 3 is electrically connected to the drain electrode D 5 of the driving transistor T 5 via the sixth via VH 6. The source electrode S 1 of the first transistor T 1 is electrically connected to the first data lead DR via the seventh via VH 7. The source electrode S 2 of the second transistor T 2 is electrically connected to the reference voltage signal line Vrefl via the eighth via VH 8 and the ninth via VH 9, and the drain electrode D 2 of the second transistor T 2 is electrically connected to the second electrode portion C 2. The drain electrode D 3 of the third transistor T 3 is electrically connected to the second electrode portion C 2 via the tenth via VH 10.As shown in FIG. 13, the display substrate also includes a pixel defining layer located on a side of the third conductive layer 40 opposite from the base substrate, and a plurality of openings M in the pixel defining layer, the plurality of sub-pixels each including at least one opening M, for example, each sub-pixel includes one opening M.As shown in FIGS. 11 and 13, for two adjacent rows of pixel units, orthogonal projections of the openings M of the subpixels in one row of pixel units onto the substrate at least partially overlap with an orthogonal projection of the initialization voltage line Vinil of that row of pixel units onto the substrate, such as the middle row of pixel units in FIG. 13. Orthogonal projections of the openings M of the subpixels in another row of pixel units onto the base substrate at least partially overlap with an orthogonal projection of the first voltage signal line VDD 1 of the other row of pixel units onto the base substrate, such as the bottom row of pixel units in FIG. 13.As shown in FIG. 13, the light emitting element includes a first electrode. The first electrode is electrically connected to one of the source electrode S 5 and the drain electrode D 5 of the driving transistor T 5 via the anode connection hole VHA, and an orthogonal projection of the anode connection hole VHA on the base substrate is within an orthogonal projection of the third electrode portion C 3 on the base substrate.Optionally, the embodiments of the present disclosure also provide a display panel that may include the above-mentioned display substrate.Optionally, the embodiments of the present disclosure also provide a display device that may include the display substrate or the display panel described above. The display device may include any product or component having a display function, but is not limited to, such as electronic paper, handy phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. It is understood that the display device has the same advantageous effects as the display substrate provided in the foregoing embodiments.Although some embodiments have been illustrated and described according to the general concept of the present disclosure, it should be understood by those skilled in the art that changes may be made in these embodiments without departing from the principle and spirit of the general inventive concept of the present disclosure. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

A display substrate, characterized in that the display substrate comprises: a base substrate; a plurality of pixel units arranged on the base substrate, the plurality of pixel units being arranged in an array in a first direction and a second direction to form a plurality of rows of pixel units and a plurality of columns of pixel units, wherein at least one of the pixel units comprises a plurality of sub-pixels, and at least one sub-pixel comprises a light emitting element and a pixel driving circuit for driving the light emitting element; and a plurality of initialization voltage signal lines arranged on the base substrate, wherein an initialization voltage signal is provided to the plurality of targets of pixel units by the plurality of initialization voltage signal lines, respectively, wherein the plurality of initialization voltage signal lines are arranged spaced apart from each other in a second direction, wherein at least one of the initialization voltage signal lines extends along a first direction, wherein the plurality of targets of pixel units comprises the 2n-1th row of pixel units and the 2n-th row of pixel units, wherein n is a positive integer, and wherein the pixel driver circuits of the 2n-1th and 2n-th rows of pixel units share an initialization voltage signal line.The display substrate of claim 1, wherein the display substrate further comprises a plurality of initialization voltage signal leads disposed on the base substrate, the initialization voltage signal lead being electrically connected to the initialization voltage signal lead, the plurality of initialization voltage signal leads being spaced apart from each other along the first direction, and at least one of the initialization voltage signal leads extending along the second direction; wherein the plurality of columns of pixel units comprises the 2m-1th column of pixel units and the 2m-th column of pixel units, where m is a positive integer, wherein the pixel driver circuits of the 2m-1th and 2m-th columns of pixel units share an initialization voltage signal lead.The display substrate of claim 1, wherein the display substrate further comprises a plurality of reference voltage signal leads disposed on the substrate substrate, the reference voltage signal lead being used to provide a reference voltage, the plurality of reference voltage signal leads being spaced apart from each other along the first direction, at least one of the reference voltage signal leads extending along the second direction; wherein the pixel driver circuits of the 2m-1th and 2m-th columns of pixel units share a reference voltage signal lead.The display substrate of claim 3, wherein the display substrate further comprises a plurality of first voltage signal leads disposed on the base substrate, the first voltage signal lead being used to provide a first voltage to the light emitting element, the plurality of first voltage signal leads being spaced apart from each other along the first direction and at least one of the second voltage signal leads extending along the second direction; wherein the plurality of columns of pixel units comprises the 2m+1th column of pixel units, wherein the pixel driver circuits of the 2mth and 2m+1th columns of pixel units share a first voltage signal lead.The display substrate of claim 4, wherein the display substrate further comprises a plurality of first voltage signal lines disposed on the base substrate, the first voltage signal line being electrically connected to the first voltage signal line, the plurality of first voltage signal lines being spaced apart from each other along the second direction, and at least one of the first voltage signal lines extending along the first direction; wherein the plurality of rows of pixel units also comprises the 2n+1th row of pixel units, wherein the pixel driver circuits of the 2nth and 2n+1th rows of pixel units share a first voltage signal line.The display substrate according to claim 1, wherein the pixel driving circuits of the 2n-1th and 2n-th rows of pixel units are arranged symmetrically with respect to the common initialization voltage signal line.The display substrate according to claim 5, wherein the pixel driving circuits of the 2n-th and 2n+1-th rows of pixel units are arranged symmetrically with respect to the common first voltage signal line.The display substrate of claim 4, wherein the pixel driving circuit of the column of sub-pixels in the 2m-th column of pixel units close to the common first voltage signal lead and the pixel driving circuit of the column of sub-pixels in the 2m+1-th column of pixel units close to the common first voltage signal lead are arranged symmetrically with respect to the common first voltage signal lead.The display substrate according to claim 5, wherein the display substrate further comprises: a plurality of light emission control signal lines arranged on the base substrate, wherein a light emission control signal is provided to the plurality of rows of pixel units, respectively, by the plurality of light emission control signal lines, wherein the plurality of light emission control signal lines are arranged spaced apart from each other along the second direction, and at least one of the light emission control signal lines extends along the first direction; a plurality of first scan signal lines arranged on the base substrate, wherein a first scan signal is provided to the plurality of rows of pixel units, respectively, by the plurality of first scan signal lines, wherein the plurality of first scan signal lines are arranged spaced apart from each other along the second direction, and at least one of the first scan signal lines extends along the first direction; a plurality of second scan signal lines disposed on the base substrate, wherein a second scan signal is provided to the plurality of rows of pixel units by the plurality of second scan signal lines, respectively, wherein the plurality of second scan signal lines are spaced apart from each other along the second direction and at least one of the second scan signal lines extends along the first direction; a plurality of reference voltage signal lines disposed on the base substrate, wherein the reference voltage signal line is electrically connected to the reference voltage signal line, wherein the plurality of reference voltage signal lines are spaced apart from each other along the second direction and at least one of the reference voltage signal lines extends along the first direction; a plurality of third scan signal lines disposed on the base substrate, wherein a third scan signal is provided to the plurality of rows of pixel units by the plurality of third scan signal lines, respectively, wherein the plurality of third scan signal lines are spaced apart from each other along the second direction, and at least one of the third scan signal lines extends along the first direction.The display substrate according to claim 9, wherein for the 2n-1th row of pixel units and the 2n-th row of pixel units, the respective first voltage signal lines, the respective light emission control signal lines, the respective first scan signal lines, the respective second scan signal lines, the respective reference voltage signal lines, and the respective third scan signal lines of these two rows of pixel units are respectively located on both sides of the common initialization voltage signal line in the second direction.The display substrate according to claim 9, wherein the distances of the first voltage signal line, the light emission control signal line, the first scan signal line, the second scan signal line, the reference voltage signal line, and the third scan signal line of the pixel units in the 2n-1th row are gradually decreased from the common initialization voltage signal line in the second direction, and / or wherein the distances of the first voltage signal line, the light emission control signal line, the first scan signal line, the second scan signal line, the reference voltage signal line, and the third scan signal line of the pixel units in the 2n-1th row are gradually decreased from the common initialization voltage signal line in the second direction.The display substrate of claim 9, wherein the plurality of sub-pixels comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel; wherein the display substrate further comprises: a plurality of first data leads arranged on the base substrate, wherein a first data signal is provided to a plurality of columns of first sub-pixels by the plurality of first data leads, respectively, wherein the plurality of first data leads are arranged spaced apart along the first direction and at least one of the first data leads extends along the second direction; a plurality of second data leads arranged on the base substrate, wherein a second data signal is provided to a plurality of columns of second sub-pixels by the plurality of second data leads, respectively, wherein the plurality of second data leads are arranged spaced apart along the first direction and at least one of the second data leads extends along the second direction; a plurality of third data leads arranged on the base substrate, wherein a third data signal is provided to a plurality of columns of third sub-pixels by the plurality of third data leads, wherein the plurality of third data leads are arranged spaced apart from one another along the first direction and at least one of the third data leads extends along the second direction.The display substrate of claim 12, wherein for the 2m-1th column of pixel units and the 2mth column of pixel units, the respective first voltage signal leads, the respective first data leads, the respective second data leads, and the respective third data leads of that two row of pixel units are respectively located on both sides of the common initialization voltage signal lead and the common reference voltage signal lead in the first direction.The display substrate of claim 12, wherein the first voltage signal lead, the first voltage signal lead, the first data lead, the second data lead, and the third data lead of the 2m-1th column of pixel units are located on a side of the common initialization voltage signal lead opposite the common reference voltage signal lead, wherein the distances of the first voltage signal lead, the first data lead, the second data lead, and the third data lead of the 2m-1th column of pixel units are gradually decreased from the common initialization voltage signal lead in the first direction; and / or wherein the first voltage signal lead, the first data lead, the second data lead and the third data lead of the 2m-th column of pixel units are located on a side of the common reference voltage signal lead facing away from the common initialization voltage signal lead, wherein the distances of the first data lead, the second data lead, the third data lead and the first voltage signal lead of the 2m-th column of pixel units from the common reference voltage signal lead are gradually increased in the first direction.The display substrate of claim 14, wherein the first voltage signal line, the reference voltage signal line, and the initialization voltage signal line are on a first conductive layer; wherein the light emission control signal line, the first scan signal line, the second scan signal line, and the third scan signal line are on a second conductive layer, wherein the first conductive layer and the second conductive layer are different conductive layers disposed on the base substrate.The display substrate according to claim 9, wherein for the first voltage signal line, the light emission control signal line, the first scan signal line, the second scan signal line, the reference voltage signal line, the third scan signal line, and the initialization voltage signal line in the same row of pixel units, the minimum distance of the orthogonal projections of two adjacent signal lines in different conductive layers onto the base substrate in the second direction is smaller than the minimum distance of the orthogonal projections of two adjacent signal lines in the same conductive layers onto the base substrate in the second direction.The display substrate of claim 15, wherein the display substrate further comprises a semiconductor layer and a third conductive layer located on the base substrate, wherein the first conductive layer, the semiconductor layer, the second conductive layer, and the third conductive layer are sequentially disposed away from the base substrate; wherein the display substrate further comprises a light shielding portion, wherein the pixel driving circuit comprises a driving transistor, wherein the driving transistor comprises a channel region, and wherein an orthogonal projection of the light shielding portion onto the base substrate is covered by an orthogonal projection of the light shielding portion onto the base substrate; wherein the light shielding portion is located in the first conductive layer.The display substrate of claim 17, wherein the driver transistor further comprises a gate electrode located in the second conductive layer.The display substrate of claim 17, wherein the pixel driver circuit further comprises a storage capacitor, wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode comprises a first electrode portion located on the semiconductor layer, wherein the second capacitor electrode comprises a second electrode portion located in the first conductive layer and a third electrode portion located in the third conductive layer, wherein the second electrode portion and the third electrode portion are electrically connected; wherein an orthogonal projection of the first electrode portion onto the base substrate at least partially overlaps an orthogonal projection of the second electrode portion onto the base substrate, and wherein the orthogonal projection of the first electrode portion onto the base substrate at least partially overlaps an orthogonal projection of the third electrode portion onto the base substrate.The display substrate of claim 19, wherein the gate electrode of the driver transistor is electrically connected to the first electrode portion via a first via, and / or wherein the driver transistor further comprises a source electrode and a drain electrode, wherein one of the source electrodes and the drain electrode of the driver transistor is electrically connected to the third electrode portion via a second via, wherein the second electrode portion is electrically connected to the third electrode portion via a third via, and wherein orthogonal projections of the second via and the third via onto the base substrate at least partially overlap.The display substrate of claim 17, wherein the display substrate further comprises: a pixel definition layer located on a side of the third conductive layer opposite the base substrate, and a plurality of openings located in the pixel definition layer, the plurality of subpixels each comprising a plurality of openings; wherein for two adjacent rows of pixel units, orthogonal projections of the openings of the subpixels of one row of pixel units onto the base substrate at least partially overlap with an orthogonal projection of the initialization voltage line of that row of pixel units onto the base substrate, wherein orthogonal projections of the openings of the subpixels of another row of pixel units onto the base substrate at least partially overlap with an orthogonal projection of the first voltage signal line of the other row of pixel units onto the base substrate.The display substrate of claim 19, wherein the light emitting element comprises a first electrode electrically connected to one of the source electrode or the drain electrode of the driving transistor via an anode connection hole; wherein an orthogonal projection of the anode connection hole onto the base substrate is within the orthogonal projection of the third electrode portion onto the base substrate.The display substrate of claim 19, wherein the pixel driver circuit further comprises a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor each comprise a gate electrode, a source electrode, and a drain electrode; wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the gate electrode of the driver transistor; wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to the gate electrode of the driver transistor; wherein one of the source electrode and the drain electrode of the third transistor is electrically connected to the second capacitor electrode; and wherein one of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the driving transistor.The display substrate of claim 23, wherein the gate electrode of the first transistor is electrically connected to the first scan signal line, wherein one of the first data line, the second data line, and the third data line is electrically connected to the gate electrode of the first transistor; and / or wherein the gate electrode of the second transistor is electrically connected to the second scan signal line, wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the reference voltage signal line; and / or wherein the gate electrode of the third transistor is electrically connected to the third scan signal line, wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to the initialization voltage signal line; and / or wherein the gate electrode of the fourth transistor is electrically connected to the light emission control signal line, the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the first voltage signal line.A display panel, characterized in that the display panel comprises the display substrate according to any one of claims 1 to 24.A display device, characterized in that the display device comprises the display substrate according to any one of claims 1 to 24 or the display panel according to claim 25.

Images