Method and device for detecting radio frequency power signals

Abstract

The present application discloses a method and a device for acquiring radio frequency power signals, wherein the method comprises: determining a rising edge interval and a falling edge interval within a current pulse cycle; setting the data bits in a sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level or blank signal, thereby solving the prior art problem of the signals continuing to be continuously acquired and output during the ramp generation phase, which leads to inaccurate output data because the acquisition board continuously acquires voltage and current signals and continuously outputs signals, even in on / off mode and PULSE mode.

Description

TECHNICAL FIELD

[0001] The invention relates to the technical field of detecting radio frequency power signals and specifically to a method and apparatus for detecting radio frequency power signals. STATE OF THE ART

[0002] A typical data acquisition system acquires signals from the environment or various objects under test through various sensors. These signals are generally randomly generated, so the data acquisition system must continuously sample to ensure that no important signals are missed. With radio frequency power, the current acquisition board can acquire voltage and current signals through continuous sampling. In the prior art, the signals are still continuously acquired and output during the ramp generation phase, leading to problems such as inaccurate output data because the acquisition board continuously acquires voltage and current signals and continuously outputs signals, even in power-on, power-off, and pulse modes. DISCLOSURE OF THE INVENTION

[0003] Therefore, the technical problem to be solved by the present invention is to overcome the following problems in existing radio frequency power supply technologies that the signals continue to be continuously acquired and output during the ramp generation phase, resulting in inaccurate output data because the acquisition board continuously acquires voltage and current signals and continuously outputs signals even in the on / off mode and PULSE mode, thereby providing a method and apparatus for acquiring radio frequency power signals.

[0004] To solve the above-mentioned technical problems, the embodiments disclosed by the invention provide at least one method and apparatus for detecting radio frequency power signals.

[0005] In a first aspect, the embodiments disclosed by the invention provide a method for detecting radio frequency power signals, comprising: Determining a rising edge interval and a falling edge interval within a current pulse cycle; Setting the data bits in a sample array corresponding to the rising edge interval and the falling edge interval to 0, signal low, or empty.

[0006] Alternatively, it is provided that setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal is performed by setting the data bit in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal, by delaying the sampling or by setting the output of the sampled data to 0.

[0007] Alternatively, it is provided that setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal by delaying the sampling or setting the output of the sampled data to 0 comprises the following: when data is sampled in the rising edge interval, setting the data bit in the sampling array corresponding to the rising edge interval to 0, low signal level, or empty signal by delaying the sampling time, or when the sampled data is output, setting the data bit in the sampling array corresponding to the rising edge interval to 0, low signal level, or empty signal;When data is sampled in the falling edge interval, the data bit in the sample array corresponding to the falling edge interval is set to 0, low signal level, or empty signal by delaying the sampling time, or when the sample data is output, the data bit in the sample array corresponding to the falling edge interval or the falling edge interval is set to 0, low signal level, or empty signal.;

[0008] Alternatively, it is provided that setting the data bit in the sampling array corresponding to the rising edge interval by delaying the sampling time to 0, a low signal level, or an empty signal comprises the following: starting from a starting point of the rising edge in the current pulse cycle, the first sampling delay is started and a data bit in the sampling array corresponding to the first sampling delay is set to 0, a low signal level, or an empty signal; wherein setting the data bit in the sampling array corresponding to the falling edge interval by delaying the sampling time to 0, a low signal level, or an empty signal comprises the following: starting from a starting point of the falling edge in the current pulse cycle, the second sampling delay is started and a data bit in the sampling array corresponding to the second sampling delay is set to 0, a low signal level, or an empty signal.

[0009] Alternatively, it is provided that setting the data bit in the sampling array corresponding to the rising edge interval to 0, low signal level, or empty signal comprises the following: while the signal sampling of an end point of the rising edge within the current pulse cycle is completed, first abnormal data is determined, the first abnormal data being the data within a first preset length in the sampling array starting with the data bit corresponding to the end point of the rising edge and counting up, the first abnormal data being set to 0, low signal level, or empty signal, the first preset length being the array length corresponding to the rising edge interval; that setting the data bit in the sampling array corresponding to the falling edge interval to 0, low signal level, or empty signal comprises: while the signal sampling of an end point of the falling edge within the current pulse cycle is completed, second abnormal data is determined, the second abnormal data being the data within a second preset length in the sampling array starting with the data bit corresponding to the end point of the falling edge and counting up, the second abnormal data being set to 0, low signal level, or empty signal, the second preset length being the array length corresponding to the falling edge interval.

[0010] Alternatively, it is provided that the data bit in the sampling array corresponding to the first sampling delay is set to 0, low signal level, or empty signal by setting the data bit in the sampling array corresponding to a first preset sampling period to 0, low signal level, or empty signal and the delay ends; the data bit in the sampling array corresponding to the second sampling delay is set to 0, low signal level, or empty signal by setting the data bit in the sampling array corresponding to a second preset sampling period to 0, low signal level, or empty signal and the delay ends.

[0011] Alternatively, it is provided that the data bit in the sampling array corresponding to the first sampling delay is set to 0, low signal level, or empty signal by setting the data bit in the sampling array corresponding to a first preset array length to 0, low signal level, or empty signal and the delay ends; the data bit in the sampling array corresponding to the second sampling delay is set to 0, low signal level, or empty signal by setting the data bit in the sampling array corresponding to a second preset array length to 0, low signal level, or empty signal and the delay ends.

[0012] Alternatively, it is contemplated that determining a rising edge interval and a falling edge interval within a current pulse cycle comprises: Determining the rising edge interval and the falling edge interval within the current pulse cycle based on a reference threshold, the duration of the rising edge, and the duration of the falling edge, wherein the reference threshold is used to mark the low signal level; or Determining the rising edge interval and the falling edge interval within the current pulse cycle using a reference threshold and an upper threshold, the upper threshold being used to mark the high signal level; or Determine the rising edge interval and the falling edge interval within the current pulse cycle based on a power change of the sample point.

[0013] Alternatively, it is provided that the first preset sampling duration is equal to the duration of the rising edge, with the second preset sampling duration being equal to the duration of the falling edge.

[0014] Alternatively, it is provided that the first preset array length and the second preset array length are determined by the duration of the rising edge or the duration of the falling edge and the sampling period according to a preset calculation relationship.

[0015] Alternatively, it is provided that the first preset array length = the duration of the rising edge / sample period, and the second preset array length = the duration of the falling edge / sample period; or the first preset array length = the second preset array length = the duration of the rising edge / sample period; or the first preset array length = the second preset array length = the duration of the falling edge / sample period.

[0016] Alternatively, it is provided that determining the rising edge interval and the falling edge interval within the current pulse cycle based on a power change of the sampling point comprises the following: detecting the starting point of the rising edge, wherein the starting point of the rising edge is a sampling point at which the power in the current pulse cycle is greater than the reference threshold of the rising edge for the first time; detecting the starting point of the falling edge, wherein the starting point of the falling edge is a sampling point at which the power in the current pulse cycle is less than the reference threshold of the falling edge for the first time.

[0017] Alternatively, it is contemplated that the above method further comprises: outside the rising edge interval and the falling edge interval, the sampling array may read the sampled data and output them sequentially.

[0018] Alternatively, it is provided that setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal by delaying the sampling or setting the output of the sampled data to 0 when the first preset array length = the second preset array length = the duration of the rising edge / sampling period and the duration of the rising edge is greater than the duration of the falling edge, comprises the following: when the sample data is output while the signal sampling of the end point of the falling edge is completed within the current pulse cycle, a duration of a third delay is calculated, the duration of the third delay being a difference between the duration of the rising edge and the duration of the falling edge, and determining third abnormal data at the end of the third delay,wherein the third abnormal data is the data within a third preset length in the sampling array, starting with the data bit corresponding to the end point of the third delay and counting forward, wherein the third abnormal data is set to 0, low signal level, or empty signal, wherein the third preset length is the array length corresponding to the falling edge interval.

[0019] Optionally, determining a rising edge interval and a falling edge interval within a current pulse cycle comprises: the rising edge interval and the falling edge interval in the current pulse cycle are determined according to a preset power increase threshold, a preset power decrease threshold, a preset number of padded data for the rising edge, and a preset number of padded data for the falling edge, respectively.

[0020] Optionally, before determining the rising edge interval and the falling edge interval within the current pulse cycle, the method further comprises: Continuous sampling tests capture the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge.

[0021] Optionally, the detection of the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge by continuous sampling tests comprises: first radio frequency power signals are continuously acquired at a plurality of sampling points, each of the first radio frequency power signals comprising a first voltage V and a first current I; wherein the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge are determined according to the first voltage V and the first current I.

[0022] Optionally, determining the rising edge interval and the falling edge interval in the current pulse cycle, each corresponding to a preset power increase threshold, a preset power decrease threshold, a preset number of padded data for the rising edge, and a preset number of padded data for the falling edge, comprises: second radio frequency power signals are continuously acquired at a plurality of sampling points, each of the second radio frequency power signals comprising a second voltage V and a second current I; the power of each sampling point is determined using the second voltage V and the second current I; the starting point of the rising edge interval and the preset number of padded data for the rising edge are determined based on the power of each sampling point, the power rise threshold, and a number of padded data for the rising edge; The starting point of the falling edge interval and the preset number of padded data for the falling edge are determined based on the power of each sample point, the power decay threshold, and a number of padded data for the falling edge.

[0023] Optionally, determining the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge according to the first voltage V and the first current I comprises: Calculating the power value of each sample point from P=VI, and obtaining: a first specific power value Pr after the zero potential, a first non-Pe power value Pd after a peak potential power average Pe, where Pr serves as a preset power increase threshold and Pd serves as a preset power decrease threshold.

[0024] Optionally, determining the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge according to the first voltage V and the first current I also includes: Determining the preset number of padded data for the rising edge during the rising edge process based on Tr / T, and determining the preset number of padded data for the falling edge during the falling edge process based on Td / T, where Td is the falling edge time, Tr is the rising edge time, and T is the sampling period.

[0025] In a second aspect, the embodiments disclosed by the invention also provide an apparatus for detecting radio frequency power signals, comprising: an abnormal data interval determination module used to determine a rising edge interval and a falling edge interval within a current pulse cycle; a sampled data set to 0 module used to set the data bits in the sample array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal.

[0026] In a third aspect, the embodiments disclosed by the invention also provide a computing device comprising: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, wherein the processor and the memory communicate via the bus when the computing device is running, wherein when the machine-readable instructions are executed by the processor, the steps in the above-mentioned first aspect or any possible embodiment of the first aspect are performed.

[0027] In a fourth aspect, the embodiments disclosed by the invention also provide a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, wherein when the computer program is executed by the processor, the steps are performed as in the first aspect above or in any possible embodiment of the first aspect.

[0028] The technical solutions provided by the embodiments of the present application can have at least the following advantageous effects: The rising edge interval and the falling edge interval within the current pulse cycle are determined, and the data bit in the sample array corresponding to the rising edge interval and the falling edge interval is set to 0, low signal level or empty signal, and the sample array is set to 0 with FIFO (First Input First Output) to mask the data in the abnormal segment, that is, the data output of a ramp segment is 0 in the on and off modes and PULSE mode, and the power is only output in the correct period except the ramp.

[0029] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. PRESENTATION OF THE REGISTRATION

[0030] In order to more clearly explain the specific embodiments of the present invention or the technical solutions in the prior art, the drawings necessary for the descriptions in specific embodiments or in the prior art are briefly described below. Obviously, the accompanying drawings in the following description represent some embodiments of the present invention, and those of ordinary skill in the art can also derive other drawings from these drawings without creative effort. Fig. 1 shows a flowchart of a method for detecting radio frequency power signals provided by the embodiment disclosed in the present invention; Fig. 2 shows a flowchart of another method for detecting radio frequency power signals provided by the embodiment disclosed in the present invention; Fig. 3 shows a schematic diagram of the pulse structure in an embodiment disclosed in the present invention; Fig. 4 shows a schematic diagram of the pulse structure in Example 1 in an embodiment disclosed in the present invention; Fig. 5 shows a schematic diagram of the pulse structure in Example 2 in an embodiment disclosed in the present invention; Fig. 6 shows a schematic diagram of the pulse structure in Example 3 in an embodiment disclosed in the present invention; Fig. 7 shows a flowchart of another method for detecting radio frequency power signals provided by the embodiment disclosed in the present invention; Fig. 8 shows a schematic diagram of a pulse structure in one embodiment disclosed in the present invention, in which a data fill method is used to shield the ramp segment data; Fig. 9 shows a schematic diagram of another pulse structure in an embodiment disclosed in the present invention, in which a data fill method is used to shield the ramp segment data; Fig. 10 shows a flowchart of another method for detecting radio frequency power signals provided by the embodiment disclosed in the present invention; Fig. 11 shows a flowchart of another method for detecting radio frequency power signals provided by the embodiment disclosed in the present invention and based on the Fig. 10 shown procedures; Fig. 12 shows a schematic structural diagram of an apparatus for detecting radio frequency power signals provided by the embodiment disclosed in the present invention; Fig. 13 shows a schematic structural diagram of another apparatus for detecting radio frequency power signals provided by the embodiment disclosed in the present invention; Fig. 14 shows a schematic structural diagram of a computing device provided by the embodiment disclosed in the present invention. CONCRETE EMBODIMENTS

[0031] Exemplary embodiments are described in detail below, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numerals refer to the same or similar elements in different drawings unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of devices and methods consistent with aspects of the present invention, as detailed in the appended claims. Example 1

[0032] As in Fig. 1, there is a flowchart of a method for detecting radio frequency power signals provided by the embodiment disclosed in the present invention, the method comprising: S11: Determining a rising edge interval and a falling edge interval within a current pulse cycle; S12: Set the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level or empty signal; S13: outside the rising edge interval and the falling edge interval, the sampling array can read the sampled data and output them sequentially.

[0033] It should be understood that in the technical solution provided by the present embodiment, the rising edge interval and the falling edge interval are determined within the current pulse cycle, and the data bit in the sampling array corresponding to the rising edge interval and the falling edge interval is set to 0, low signal level, or empty signal, and the sampling array is set to 0 with FIFO (First Input First Output) to mask the data in the abnormal segment, that is, the data output of a ramp segment in the on / off mode and PULSE mode is 0, and the power is output only in the correct period except the ramp. Example 2

[0034] As in Fig. 2, there is a flowchart of another method for detecting radio frequency power signals provided by the embodiment disclosed in the present invention, the method according to Fig. 3 masks abnormal data generated during the ramp phase within the pulse cycle, the method comprising: S21: Determining a rising edge interval and a falling edge interval within a current pulse cycle; S22: Set the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level or empty signal; S23: outside the rising edge interval and the falling edge interval, the sampling array can read the sampled data and output them sequentially.

[0035] In some embodiments, setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal at S22 may be: setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal by delaying the sampling or setting the output of the sampled data to 0.

[0036] In some embodiments, it is provided that S22 may include the following steps: S221: Different data processing methods can be used in the rising edge interval depending on the data judgment mode. The data judgment mode includes the following: (A) Through the reference threshold, it can be determined whether the input signal changes from the low signal level to the rising edge interval, that is, when the signal data is lower than the reference threshold, it is regarded as a low signal level (or signal zero output or 0 output), while when the signal data is higher than the reference threshold, it is regarded as the signal rising to a high level and the rising process as the rising edge interval.

[0037] When reading sample data, once the sampled data specified for import into the sample array is read out and exceeds the reference threshold, the signal is considered to have reached the rising edge, and at this point, the sample delay is initiated. When the sample delay ends, normal reading of the sampled data resumes. In some embodiments, the duration of the sample delay is set to the duration of the rising edge interval. The corresponding data processing method is adopted according to the length of the corresponding acquired array, as explained below: (A-1) If the duration corresponding to the data bit of the acquired array is greater than or equal to the duration of the rising edge interval, one of the following methods is used for processing: (A-11) During the sampling delay, the read sampled data is first set to 0, low signal level or empty signal and then filled into the sampling array.

[0038] (A-12) The sampled data read during the sample delay and imported into the sample array is marked, and when the sampled data is output, the data bit in the sample array corresponding to the rising edge interval is set to 0, low signal level, or empty signal.

[0039] (A-13) During the active sample delay, the data of the entire sample array continues to maintain FIFO operation regardless of the type of sampled data read, and when the sample delay ends, all data fields in the sample array are set to 0, low signal level, or empty signal, and normal data sampling operations are performed at the same time.

[0040] (A-2) If the duration corresponding to the data bit of the acquired array is shorter than the duration of the rising edge interval, the read data is processed via (A-11) or (A-12).

[0041] (B) The reference threshold can determine whether the input signal changes from the low signal level to the rising edge interval, and the upper threshold can determine whether the input signal changes from the rising edge interval to the high signal level.

[0042] When reading sample data, once the sampled data specified for import into the sample array is read out and exceeds the reference threshold, the signal is considered to reach the rising edge, and at this time, the sample delay is started. When the sampled data specified for import into the sample array exceeds the upper threshold, the signal is considered to reach the high signal level from the rising edge. At this time, the sample delay ends, and normal operation of reading the sampled data and filling the sample array resumes.

[0043] In some embodiments, it is contemplated that the corresponding data processing methods are based on the length of the corresponding acquired array as described above (A-1) and (A-2) when the duration of the rising edge interval is known.

[0044] In some embodiments, the duration of the sampling delay depends on the duration of the read sample value between the reference threshold and the upper threshold, i.e., on the actual duration of the rising edge interval. This means that the low signal level, the rising edge, and the high signal level are determined only by the reference threshold and the upper threshold. The data processing methods are as described above (A-1) and (A-2).

[0045] (C) The samples read before and after are compared, and it is determined from the change in data size whether the input signal changes from the low signal level to the rising edge interval and whether it changes from the rising edge interval to the high signal level.

[0046] When reading sampled data, once several consecutive sampled data specified for import into the sampling array are read out and change from constant low level data to rising data (the read upstream data is lower than the downstream data), the signal is considered to enter the rising edge, and at this time the sampling delay starts. When several consecutive sampled data specified for import into the sampling array change from rising data to constant high level data (the read upstream data is equal to the downstream data), the signal is considered to enter the high signal level from the rising edge. At this time, the sampling delay ends, and the normal operation of reading the sampled data and filling the sampling array resumes.

[0047] In some embodiments, it is contemplated that the corresponding data processing methods are based on the length of the corresponding acquired array as described above (A-1) and (A-2) when the duration of the rising edge interval is known.

[0048] In some embodiments, the duration of the sampling delay depends on the duration during which the read sample lies between the reference threshold and the upper threshold, i.e., on the actual duration of the rising edge interval. This means that the duration of the rising edge interval can be neglected, with the low signal level, the rising edge, and the high signal level being determined by converting constant data and rising data. The data processing methods are as described above (A-11) and (A-12).

[0049] S222: Different data processing methods can be used in the falling edge interval depending on the data judgment mode. The data judgment mode includes the following: (D) The reference threshold determines whether the input signal has reached the falling edge interval and changes to the low signal level, that is, the signal has reached the end of the falling edge interval and can still be regarded as entering the low signal level, zero position, or no output of the signal.

[0050] When reading sample data, once the sampled data specified for import into the sample array is read out and falls below the reference threshold, it is considered that the signal passes the end of the falling edge and even reaches the low signal level, zero position, or no output of the signal, and at this time the sample delay is started. When the sample delay ends, the normal reading process of the sampled data resumes.

[0051] In some embodiments, the sampling delay duration is the sum of the data sampling duration corresponding to the data bits of the acquired array minus the duration of the falling edge. The sum of the data sampling duration corresponding to the data bits of the acquired array is not shorter than the duration of the falling edge. Depending on the length of the corresponding acquired array, the delay processing method is as follows: (D-1) The sum of the data sampling periods corresponding to the data bits of the acquired array is equal to the duration of the falling edge, and the sampling delay duration is 0, which means that the sampling delay is not enabled and the subsequent data processing is performed directly.

[0052] (D-2) The sum of the data sampling durations corresponding to the data bits of the acquired array is greater than the duration of the falling edge, and the sampling delay duration is the difference between the two, with subsequent data processing taking place after the delay has elapsed.

[0053] In some embodiments, it is provided that when delayed sampling (D-2 as above) is started, the data of the entire sample array continues to maintain FIFO operation regardless of the type of sampled data read, wherein when the sample delay time ends (or the sample delay is not enabled for D-1 above), all data fields in the sample array are set to 0, low signal level, or empty signal and normal data sampling operations are performed at the same time.

[0054] (E) Through the upper threshold, it can be determined whether the input signal changes from the high signal level to the falling edge interval, that is, when the signal data is higher than the upper threshold, it is regarded as the high signal level, whereas when the signal data is lower than the upper threshold, it is regarded as a signal falling to a low level, and the falling process is regarded as the falling edge interval.

[0055] When reading sample data, as soon as the sampled data specified for import into the sample array is read out and falls below the upper threshold, the signal is considered to have reached the falling edge, and the sample delay is initiated at this time. When the sample delay ends, normal reading of the sampled data resumes.

[0056] In some embodiments, the duration of the sampling delay is the sum of the falling edge interval duration and the data sampling duration corresponding to the data bits of the sensed array, with the longer of the two being selected; if both are equal, either can be selected. Therefore, the sensed data read falls to the low signal level after the delay has elapsed.

[0057] Depending on the length of the corresponding array acquired, the corresponding data processing method is adopted, which is explained as follows: (E-1) If the duration corresponding to the data bit of the acquired array is greater than or equal to the duration of the falling edge interval, one of the following methods is used for processing: (E-11) During the sampling delay, the read sampled data is first set to 0, low signal level or empty signal and then filled into the sampling array.

[0058] (E-12) The sampled data read during the sample delay and imported into the sample array is marked, and when the sampled data is output, the data bits in the sample array corresponding to the falling edge interval are set to 0, low signal level, or empty signal.

[0059] (E-13) During the active sample delay, the data of the entire sample array continues to maintain FIFO operation regardless of the type of sampled data read, and when the sample delay ends, all data fields in the sample array are set to 0, low signal level, or empty signal, and normal data sampling operations are performed at the same time.

[0060] (E-2) If the duration corresponding to the data bit of the acquired array is shorter than the duration of the falling edge interval, the read data is processed via (E-11) or (E-12).

[0061] (F) The upper threshold can determine whether the input signal changes from the high signal level to the falling edge interval, and the reference threshold can determine whether the input signal changes from the falling edge interval to the low signal level.

[0062] When reading sample data, once the sampled data specified for import into the sample array is read out and falls below the upper threshold, the signal is considered to have reached the falling edge, and at this time, the sample delay is started. When the sampled data specified for import into the sample array is read out and is lower than the reference threshold, the signal is considered to have entered the low signal level from the falling edge. At this time, the sample delay ends, and normal operation of reading the sampled data and filling the sample array resumes.

[0063] In some embodiments, the duration of the sampling delay depends on the duration of the read sample value between the reference threshold and the upper threshold, i.e., on the actual duration of the falling edge interval. This means that the high signal level, the falling edge, and the low signal level are determined only by the reference threshold and the upper threshold. The data processing methods are as described above (E-1) and (E-2).

[0064] (G) The samples read before and after are compared, and it is determined from the change in data size whether the input signal changes from the high signal level to the falling edge interval and whether it changes from the falling edge interval to the low signal level.

[0065] When reading sampled data, once several consecutive sampled data specified for import into the sampling array are read out and change from constant high level data to rising data (the read upstream data is lower than the downstream data), the signal is considered to enter the falling edge, and at this time the sampling delay starts. When several consecutive sampled data specified for import into the sampling array are read out and change from falling data to constant low level data (the read upstream data is equal to the downstream data), the signal is considered to enter the low signal level from the falling edge. At this time, the sampling delay ends, and the normal operation of reading the sampled data and filling the sampling array resumes.

[0066] In some embodiments, it is contemplated that the corresponding data processing methods are based on the length of the corresponding acquired array as described above (E-1) and (E-2) when the duration of the falling edge interval is known.

[0067] In some embodiments, the duration of the sampling delay depends on the duration during which the read sample lies between the reference threshold and the upper threshold, i.e., on the actual duration of the rising edge interval. This means that the duration of the rising edge interval can be neglected, with the low signal level, the rising edge, and the high signal level being determined by converting constant data and rising data. The data processing methods are as described above (E-11) and (E-12).

[0068] In some embodiments, S22 is provided to include: when data is sampled, the data bit in the sample array corresponding to the falling edge interval is set to 0, low signal level, or empty signal by delaying the sample time, or when the sample data is output, the data bit in the sample array corresponding to the falling edge interval or the falling edge interval is set to 0, low signal level, or empty signal.

[0069] In some embodiments, S221 may include: starting with a starting point of the rising edge in the current pulse cycle, starting the first sampling delay and setting a data bit in the sampling array corresponding to the first sampling delay to 0, low signal level, or empty signal; wherein the above step of setting the data bit in the sampling array corresponding to the falling edge interval to 0, low signal level, or empty signal by delaying the sampling time may comprise: starting from a starting point of the falling edge in the current pulse cycle, the second sampling delay is started and a data bit in the sampling array corresponding to the second sampling delay is set to 0, low signal level, or empty signal.

[0070] In some embodiments, it is contemplated that, particularly in some cases where the power reference threshold for the rising edge cannot be reached, S222 may include: while the signal sampling of an end point of the rising edge within the current pulse cycle is completed, first abnormal data is determined, the first abnormal data being the data within a first preset length in the sampling array starting with the data bit corresponding to the end point of the rising edge and counting up, the first abnormal data being set to 0, low signal level, or empty signal, the first preset length being the array length corresponding to the rising edge interval; wherein the above step of setting the data bit in the sampling array corresponding to the falling edge interval to 0, low signal level, or empty signal is achieved by the following process: while the signal sampling of an end point of the falling edge within the current pulse cycle is completed, second abnormal data is determined, the second abnormal data being the data within a second preset length in the sampling array starting from the data bit corresponding to the end point of the falling edge and counting up, the second abnormal data being set to 0, low signal level, or empty signal, the second preset length being the array length corresponding to the falling edge interval.

[0071] In some embodiments, it is contemplated that the above step of setting the data bit in the sampling array corresponding to the first sampling delay to 0, low signal level, or empty signal may be the following: the data bit in the sampling array corresponding to a first preset sampling period is set to 0, low signal level, or empty signal, and the delay ends; the above step of setting the data bit in the sampling array corresponding to the second sampling delay to 0, low signal level, or empty signal may be the following: the data bit in the sampling array corresponding to a second preset sampling period is set to 0, low signal level, or empty signal, and the delay ends.

[0072] In some embodiments, it is contemplated that the above step of setting the data bit in the sampling array corresponding to the first sampling delay to 0, low signal level, or empty signal may be the following: the data bit in the sampling array corresponding to a first preset array length is set to 0, low signal level, or empty signal, and the delay ends; the above step of setting the data bit in the sampling array corresponding to the second sampling delay to 0, low signal level, or empty signal may be the following: the data bit in the sampling array corresponding to a second preset array length is set to 0, low signal level, or empty signal, and the delay ends.

[0073] In some embodiments, it is contemplated that S21 may include: a. Determining the rising edge interval and the falling edge interval within the current pulse cycle based on a reference threshold, the duration of the rising edge, and the duration of the falling edge, wherein the reference threshold is used to mark the low signal level; or b. Determining the rising edge interval and the falling edge interval within the current pulse cycle using a reference threshold and an upper threshold, the upper threshold being used to mark the high signal level; or c. Determine the rising edge interval and the falling edge interval within the current pulse cycle based on a power change of the sample point.

[0074] In some embodiments, it is provided that, specifically for the detection sampling, the sampling period is used as a basis, starting when the power rises above the rising threshold and ending when the power reaches the falling threshold, the number of samples or the sampling time being calculated to determine the rising edge interval; on the contrary, it will start when the power falls below the falling threshold and ending when the power reaches the rising threshold, the number of samples or the sampling time being calculated to determine the falling edge interval;

[0075] In some embodiments, it is provided that the first sampling delay period is equal to the duration of the rising edge, wherein the second sampling delay period is equal to the duration of the falling edge.

[0076] In some embodiments, it is provided that the first preset array length ≥ the duration of the falling edge / sampling period, the second preset array length ≥ the duration of the falling edge / sampling period.

[0077] In some embodiments, the first preset array length and the second preset array length are determined by the duration of the rising edge or the duration of the falling edge and the sampling period according to a preset calculation relationship.

[0078] In a specific embodiment, it is provided that the first preset array length = the duration of the rising edge / sampling period, and the second preset array length = the duration of the falling edge / sampling period; or the first preset array length = the second preset array length = the duration of the rising edge / sampling period; or the first preset array length = the second preset array length = the duration of the falling edge / sampling period.

[0079] In some embodiments, setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal by delaying the sampling or setting the output of the sampled data to 0 when the first preset array length = the second preset array length = the duration of the rising edge / sampling period and the duration of the rising edge is greater than the duration of the falling edge comprises: when the sample data is output while the signal sampling of the end point of the falling edge is completed within the current pulse cycle, a duration of a third delay is calculated, the duration of the third delay being a difference between the duration of the rising edge and the duration of the falling edge, wherein third abnormal data is determined at the end of the third delay, the third abnormal data being the data within a third preset length in the sample array starting from the data bit corresponding to the end point of the third delay and counting up, the third abnormal data being set to 0, low signal level, or empty signal, the third preset length being the array length corresponding to the falling edge interval.

[0080] In some embodiments, it is provided that S21 may comprise the following: detecting the starting point of the rising edge, wherein the starting point of the rising edge is a sampling point at which the power in the current pulse cycle is greater than the reference threshold for the first time; detecting the end point of the rising edge, wherein the end point of the rising edge is a sampling point at which the power in the current pulse cycle is greater than the upper threshold for the first time; detecting the starting point of the falling edge, wherein the starting point of the falling edge is a sampling point at which the power in the current pulse cycle is less than the reference threshold of the falling edge for the first time; detecting the end point of the falling edge, wherein the end point of the falling edge is a sampling point at which the power in the current pulse cycle is less than the reference threshold for the first time.

[0081] To facilitate readers' understanding, the above-mentioned method for acquiring radio-frequency power signals is explained below using specific examples. First, assume that the duration of the rising edge is 10 µs (T1) and the duration of the falling edge is 4 µs (T2), with the sample array length set to 5 µs and the period to 1 µs: Example 1 (where the reference threshold is known), as in Fig. 7 and Fig. 4 shown: In the rising edge interval, whether the input signal transitions from the low signal level to the rising edge interval can be determined by the reference threshold. Once the sampled data specified for import into the sampling array is read out and exceeds the reference threshold, the signal is considered to have reached the rising edge, and at this time, the sampling delay starts. When the first data bit of the FIFO array reaches a point A on the rising edge and the power (Pa) at the next sampling point exceeds the reference threshold, the start delay T1 at this time is 10 μs, at which time all data in the FIFO array is limited to 0.When the first data bit of the FIFO array reaches point A on the rising edge, the sampling delay ends at this time. The first data bit of the FIFO array begins filling with data until the entire FIFO array is preliminarily filled at bit C. Then, according to FIFO theory, the data input first will be output first. The output data is still 0 before the FIFO array reaches bit C, and the data originally input at point B is not output until point C, and the output data is normal until point E is reached.

[0082] In the falling edge interval, the reference threshold determines whether the input signal has reached the falling edge interval and transitioned to the low signal level. When reading sample data, once the sampled data specified for import into the sample array is read out and falls below the reference threshold, it is considered that the signal passes the end of the falling edge and even reaches the low signal level, zero position, or no output of the signal, and at this time the sampling delay is started.During the falling edge phase, when the first data bit of the FIFO array reaches point F on the falling edge, the power (Pb) at the detection point is lower than the reference threshold and the actual output is data at point D, and at this time the start delay T2 = 5us-4us = 1us, and at the end of the delay, the first data bit of the FIFO array reaches point G, the last data bit reaches point E and the FIFO array clears the data to 0 and outputs it.

[0083] Example 2 (where the reference threshold and the upper threshold are known), as in Fig. 7 and Fig. 5 shown: In the rising edge interval, the reference threshold determines whether the input signal changes from the low signal level to the rising edge interval, and the upper threshold determines whether the input signal changes from the rising edge interval to the high signal level. In the rising edge phase, when the first data bit of the FIFO array reaches point A on the rising edge and the power (Pa) at the next sampling point is higher than the reference threshold, the sampling delay starts at this time. When the first data bit of the FIFO array reaches point B on the rising edge and the power (Pa) at the next sampling point is higher than the upper threshold, the sampling delay ends at this time.The first data bit of the FIFO array begins filling with data until the entire FIFO array is temporarily filled at the C bit. Then, according to FIFO theory, the data input first will be output first. The output data is still 0 before the FIFO array reaches the C bit, and the data originally input at point B is not output until point C, and the output data is normal until point E is reached.

[0084] In the falling edge interval, the upper threshold determines whether the input signal changes from the high signal level to the falling edge interval, and the reference threshold determines whether the input signal changes from the falling edge interval to the low signal level. The data bit in the sampling array corresponding to the falling edge interval is set to 0, low signal level, or empty signal, and the data processing method is as above (E-1). When the first data bit of the FIFO array reaches point E on the falling edge, the power (Pb) at the sampling point is lower than the upper threshold, and the sampling delay is started at this time; when the first data bit of the FIFO array reaches point F on the falling edge, the power (Pb) at the sampling point is lower than the reference threshold.At this time, the sampling delay ends and the normal operation of reading the sampled data and filling the sampling array continues.

[0085] Example 3, as in Fig. 6 shown: In the rising edge interval, the samples read before and after are compared, and it is determined based on the change in data size whether the input signal changes from the low signal level to the rising edge interval and whether it changes from the rising edge interval to the high signal level. Specifically, the determination of the rising edge interval within the current pulse cycle can be performed based on the power change of the sampling point. The data bit in the sample array corresponding to the rising edge interval is set to 0, low signal level, or empty signal, and the data processing method is as above (A-1) or (A-1).

[0086] When reading sampled data, once multiple consecutive sampled data specified for import into the sampling array are read out and change from constant low level data to rising data (the read upstream data is lower than the downstream data), the signal is considered to enter the rising edge, and at this time the sampling delay starts. When multiple consecutive sampled data specified for import into the sampling array change from rising data to constant high level data (the read upstream data is equal to the downstream data), the signal is considered to enter the high signal level from the rising edge. At this time, the sampling delay ends, and the normal operation of reading the sampled data and filling the sampling array resumes.

[0087] The low-power data collected from the beginning to point A is accurate; point A to point B represents an upward ramp, and the data collected at that time is inaccurate; the high-power data collected from point B to point C is accurate.

[0088] In the falling edge interval, the samples read before and after are compared, and it is determined from the change in data size whether the input signal changes from the high signal level to the falling edge interval and whether it changes from the falling edge interval to the low signal level, where the data processing method is as above (E-1) and (E-2).

[0089] When reading sampled data, once several consecutive sampled data specified for import into the sampling array are read out and change from constant high level data to rising data (the read upstream data is lower than the downstream data), the signal is considered to enter the falling edge, and at this time the sampling delay starts. When several consecutive sampled data specified for import into the sampling array are read out and change from falling data to constant low level data (the read upstream data is equal to the downstream data), the signal is considered to enter the low signal level from the falling edge. At this time, the sampling delay ends, and the normal operation of reading the sampled data and filling the sampling array resumes.

[0090] Point C to point D represents a downward ramp, and the data acquired at this time are inaccurate; the data acquired from point D to point E with low powers are accurate. The time sequence of the three consecutive power values ​​P1, P2 and P3 acquired is shown in Fig. 6, where P1 represents the most recently acquired data, P2 represents the second-most recently acquired data, and P3 represents the earliest acquired data.

[0091] The acquired power values ​​are differentiated sequentially to obtain the changes Δ1=P1-P2, Δ2=P2-P3; where Δth is greater than 0, which is a threshold for determining whether the acquired data is accurate. If the absolute values ​​of the two changes are greater than or equal to 0, empty signal value, or low signal level value, and less than the determination threshold Δth, the acquired data is accurate. At this time, the corresponding acquired data should be retained; otherwise, the abnormal data bit should be set to 0, empty signal value, or low signal level value, or when outputting sampled data, the data output of the abnormal data bit is skipped. That is, if the absolute value of at least one of Δ1 and Δ2 is greater than or equal to +Δth, the data is incorrect, and in this case, all acquired data is discarded.

[0092] It should be noted that in the embodiments of the present invention, the duration of the rising edge (T1) and the duration of the falling edge (T2) can be detected and sampled using the sampling period as a basis, starting when the power rises above the rise threshold and ending when the power reaches the fall threshold, calculating the number of samples or the sampling time to determine the duration of the rising edge; on the contrary, it will start when the power falls below the fall threshold and ending when the power reaches the rise threshold, calculating the number of samples or the sampling time to determine the duration of the falling edge, and it can also be other methods selected by the person skilled in the art according to technical needs, which will not be described again here.The method is particularly suitable for solving the problem of inaccurate signal detection within a pulse cycle in on- and off-mode as well as PULSE mode.

[0093] It should be understood that in the technical solution provided by the present embodiment, the rising edge interval and the falling edge interval are determined within the current pulse cycle, and the data bit in the sampling array corresponding to the rising edge interval and the falling edge interval is set to 0, low signal level, or empty signal, and the sampling array is set to 0 with FIFO (First Input First Output) to mask the data in the abnormal segment, that is, the data output of a ramp segment is 0 in the on and off modes and in the PULSE mode, and the power is output only in the correct period except the ramp. Example 3

[0094] In some optional embodiments, a sample test stage based on Embodiment 1 may be added to obtain the parameter values ​​required to determine the rising edge interval and the falling edge interval. Specifically, as in Fig. 7, there is a flowchart of another method for detecting radio frequency power signals provided by the embodiment disclosed in the present invention, the method comprising: S31: Sampling test stage, where the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge are acquired through continuous sampling tests. S32: Signal sampling stage, which specifically comprises: S321: The rising edge interval (also called the rising edge data padding interval) and the falling edge interval (also called the falling edge data padding interval) within the current pulse cycle are determined. Specifically, the rising edge interval and the falling edge interval in the current pulse cycle are determined according to a preset power increase threshold, a preset power decrease threshold, a preset number of rising edge padding data, and a preset number of falling edge padding data. S322: During the sampling process, the data fill method is used to set (ie, fill) the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, a low signal level (also called a low signal level value), or empty signal (also called an empty signal value). S323: At times other than the rising edge interval and the falling edge interval, the sampled data is read and output sequentially.

[0095] In concrete practice in step S31, as shown in the dashed line in Fig. 7, capturing the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge through continuous sampling tests includes the following: S311: first radio frequency power signals are continuously acquired at a plurality of sampling points, each of the first radio frequency power signals comprising a first voltage V and a first current I; S312: the preset power increase threshold, the preset power decrease threshold, the number of padded data for the rising edge and the number of padded data for the falling edge are determined according to the first voltage V and the first current I.

[0096] In concrete practice in step S321, determining the rising edge interval and the falling edge interval in the current pulse cycle, respectively according to a preset power increase threshold, a preset power decrease threshold, a preset number of padded data for the rising edge, and a preset number of padded data for the falling edge, comprises the following: S3211: second radio frequency power signals are continuously acquired at a plurality of sampling points, each of the second radio frequency power signals comprising a second voltage V and a second current I; S3212: the power of each sampling point is determined from the second voltage V and the second current I; S3213: the starting point of the rising edge interval and the preset number of padded data for the rising edge are determined based on the power of each sampling point, the power rise threshold and a number of padded data for the rising edge; S3214: the starting point of the falling edge interval and the preset number of padded data for the falling edge are determined based on the power of each sample point, the power decay threshold and a number of padded data for the falling edge.

[0097] In concrete practice, in step S312, determining the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge according to the first voltage V and the first current I includes the following: Calculate the power value of each sample point from P=VI, and obtain: a first specific power value P r after the zero potential, a first non-P e -Performance value P d according to a peak potential performance average P e , where P r serves as a preset power increase threshold and P d serves as a preset performance degradation threshold; In concrete practice, in step S312, determining the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge according to the first voltage V and the first current I also includes the following: In actual practice, the preset number of padded data for the rising edge during the rising edge process can be set based on T r / T and the preset number of padded data for the falling edge during the falling edge process based on T d / T, where T d the falling edge time is, T ris the rising edge time and T is the sampling period, wherein the falling edge time and the rising edge time can be determined by one skilled in the art by testing or other known means and are not described again here.

[0098] In practice, in the power-on and power-off modes, as well as in pulse mode, it takes a certain amount of time for the output of the radio-frequency power supply to rise from zero potential to the maximum potential, which is called the rising process. Similarly, the process of falling from the maximum potential to zero potential is called the falling process. Therefore, when the radio-frequency power supply is continuously sampled, ramp data segments are generated. The rising and falling processes mentioned above correspond to the rising and falling edges of the ramp segment, respectively. These data are inaccurate for the radio-frequency power supply, and corresponding shielding methods should be adopted. Fig. 8 is a schematic diagram of using the data padding method to shield ramp segment data. By padding the appropriate number of 0 data during the rising edge and falling edge phases, the default output of the ramp data can be set to 0, thereby achieving the purpose of shielding the ramp segment data and avoiding the acquisition of inaccurate values.

[0099] To facilitate the reader's understanding, the implementation of the above-mentioned method for acquiring radio frequency power signals is illustrated below using specific examples.

[0100] First, the determination threshold and the number of padded data are determined: In the sampling test stage, several sets of ramp data are first acquired by continuous sampling. The data are then analyzed, with the acquired data being voltage V and current I, and the power value is calculated from P=VI. As shown in Fig. As shown in Figure 9, the first specific power value after the zero potential is used as the power increase threshold P r used, the peak potential power average is called P e and the first non-P e -Power value after the maximum potential is called the decay threshold P d used. The time from the rise threshold P r up to the peak potential performance average P e is called rising edge time T r taken to determine the number of padded data, and assuming that the sampling period is T, the number of padded data is T r / T; in the same way, the number of padded data is T d / T, if the time from the drop threshold P d to the zero potential as falling edge time T d is taken, and the padded data is 0, which is used to shield the ramp segment data, the specific power value being calculated and adjusted by a person skilled in the art according to the technical requirements and will not be described again here.

[0101] Second, the specific process of the data filling method is: First method: When the RF power supply is at zero potential, the acquisition board operates normally, using the FIFO array to acquire data, and the sampling period is T. In power-on mode or PULSE mode, the RF power supply gradually increases from zero potential to the maximum potential, and accordingly, the power begins to increase when the first data bit of the FIFO array reaches point A on the rising edge. If the power value is higher than the increase threshold P r is enabled, limited data padding is enabled and 0 is filled into the FIFO array, where the number T r / T is.

[0102] After the data 0 with a number of T r / T have been filled, the first data bit of the FIFO array reaches point B on the rising edge. When limited data padding is turned off, the first data bit of the FIFO array begins to be filled with the sampled data until the entire FIFO array at the C bit is temporarily filled with sampled data. Then, according to FIFO theory, the data that is input first will be output first. The output data is still limited data 0 before the FIFO array reaches the C bit, and the originally input data at point B is not output until point C. The output data is normal until point E is reached, at which time the power value is the peak potential power average P e .

[0103] In power-off or PULSE mode, the radio-frequency power supply gradually drops from the maximum potential to zero potential. When the corresponding first data bit of the FIFO array reaches point E on the falling edge, the power begins to decrease. If the power value is lower than the decrease threshold P d is enabled, limited data padding is enabled and 0 is filled into the FIFO array, where the number T d / T is.

[0104] After filling the data 0 with a number of T d / T the first data bit of the FIFO array reaches point F on the falling edge, the limited data padding is turned off and the first data bit of the FIFO array begins to fill with the sampled data, and at this time the radio frequency power supply is at zero potential.

[0105] The above sampling flowchart based on the data filling method is in Fig. 10 shown.

[0106] Second method: As in Fig. As shown in Figure 11, in the power-on or PULSE mode, the radio frequency power supply gradually increases from zero potential to the maximum potential, and accordingly, the power begins to increase when the first data bit of the FIFO array reaches point A on the rising edge. When the power value exceeds the increase threshold P r or higher, limited data padding is enabled and 0 is padded into the FIFO array.

[0107] The difference from the first method is that if the power value is higher than the drop threshold P dis or reaches, the corresponding first data bit of the FIFO array is very close to or reaches point B on the rising edge. At this time, the limited data padding is turned off and the first data bit of the FIFO array begins to be filled with sampled data. In general, the number of zeros padded on the rising edge corresponds to the interval duration between the two thresholds. In some embodiments, it is T r / T or the adjacent number.

[0108] After the limited data filling is turned off, the first data bit of the FIFO array begins to fill with the sampled data until the entire FIFO array at the C bit is temporarily filled with sampled data. Then, according to FIFO theory, the data input first will be output first. The output data is still limited data 0 before the FIFO array reaches the C bit, and the data originally input at point B is not output until point C. The output data is normal until point E is reached, and at this time, the power value is the peak potential power average P. e .

[0109] In contrast, in power-off or PULSE mode, the radio-frequency power supply gradually decays from the maximum potential to zero potential. When the corresponding first data bit of the FIFO array reaches point E on the falling edge, the power begins to decay. If the power value is lower than the decay threshold P d , limited data padding is enabled and 0 is padded into the FIFO array.

[0110] The difference from the first method is that if the power value is lower than the drop threshold P ris or reaches the falling edge, the corresponding first data bit of the FIFO array is very close to or reaches the point F on the falling edge. At this point, limited data padding is turned off, and the first data bit of the FIFO array begins to be filled with sampled data. Generally, the number of zeros padded on the falling edge corresponds to the interval duration between the two thresholds.

[0111] In some embodiments it is T d / T or the adjacent number.

[0112] After the limited data padding is turned off, the first data bit of the FIFO array begins to fill with the sampled data. At this point, the radio frequency power supply is at zero potential.

[0113] Third method: It can be considered as a combination of the first method and the second method.

[0114] On the rising edge, the power begins to increase when the first data bit of the FIFO array reaches point A on the rising edge. If the power value is higher than the increase threshold P r is enabled, limited data padding is enabled and 0 is filled into the FIFO array, where the number T r / T is.

[0115] If it is judged that the performance value is higher than the drop threshold P d or reaches it, the corresponding first data bit of the FIFO array will be very close to or reach point B on the rising edge. At this time, the limited data padding is turned off, and the first data bit of the FIFO array begins to be filled with sampled data. On the other hand, if the power value exceeds the decay threshold P d is not reached, refilling will continue.

[0116] When the first data bit of the FIFO array reaches point E on the falling edge, the power begins to decrease. If the power value is lower than the decrease threshold P d is enabled, limited data padding is enabled and 0 is filled into the FIFO array, where the number T d / T is.

[0117] If it is judged that the power value is lower than the increase threshold P r or reaches it, the corresponding first data bit of the FIFO array will be very close to or reach the rising edge point F. At this time, the limited data padding is turned off, and the first data bit of the FIFO array begins to be filled with sampled data. On the other hand, if the power value exceeds the rising threshold P r is not reached, refilling will continue.

[0118] It should be understood that the technical solution provided by the present embodiment uses a data padding method to shield the ramp segment data. By padding the appropriate number of 0 data during the rising edge and falling edge phases, the default output of the ramp data can be set to 0, thereby achieving the purpose of shielding the ramp segment data and avoiding the acquisition of inaccurate values. The appropriate number of limited data is filled in at the rising edge and falling edge, thereby solving the problem of related technologies that the data read by the acquisition board during the ramp phase is incorrect and affects the calculation of subsequent power values ​​and impedance values. Example 4

[0119] As in Fig. 12, the embodiment of the present invention also provides an apparatus for detecting radio frequency power signals, comprising: an abnormal data interval determination module 71 used to determine a rising edge interval and a falling edge interval within a current pulse cycle; a sampled data set to 0 module 72 used to set the data bits in the sample array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal.

[0120] In some embodiments, it is provided that the device, as shown in the dashed line in Fig. 12, also includes the following: a FIFO array output module 73 used so that outside the rising edge interval and the falling edge interval, the sampling array can read the sampled data and output them sequentially.

[0121] In some embodiments, the above sampled data set to 0 module 72 is used to set the data bits in the sample array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal by delaying the sampling or setting the output of the sampled data to 0.

[0122] In some embodiments, the module 72 for setting sampled data to 0, as shown in the dashed line in Fig. 12, includes: a rising edge exception processing sub-module 721 used so that when data is sampled in the rising edge interval, the data bit in the sample array corresponding to the rising edge interval is set to 0, low signal level, or empty signal by delaying the sampling time, or when the sample data is output, the data bit in the sample array corresponding to the rising edge interval is set to 0, low signal level, or empty signal; a falling edge exception processing sub-module 722 used so that when data is sampled in the falling edge interval, the data bit in the sample array corresponding to the falling edge interval is set to 0, low signal level, or empty signal by delaying the sampling time, or when the sample data is output, the data bit in the sample array corresponding to the falling edge interval or the falling edge interval is set to 0, low signal level, or empty signal.

[0123] In some embodiments, the rising edge exception processing sub-module 721 above includes setting the data bit in the sampling array corresponding to the rising edge interval to 0, low signal level, or empty signal by delaying the sampling time: the rising edge exception processing sub-module 721 starts the first sampling delay starting from a starting point of the rising edge in the current pulse cycle and sets a data bit in the sampling array corresponding to the first sampling delay to 0, low signal level, or empty signal.By the above falling edge exception processing sub-module 722, setting the data bit in the sample array corresponding to the falling edge interval by delaying the sample time to 0, low signal level, or empty signal includes: starting from a starting point of the falling edge in the current pulse cycle, starting the second sample delay and setting a data bit in the sample array corresponding to the second sample delay to 0, low signal level, or empty signal.

[0124] In some embodiments, the rising edge exception processing sub-module 721 above includes setting the data bit in the sampling array corresponding to the rising edge interval to 0, low signal level, or empty signal: while the signal sampling of an end point of the rising edge within the current pulse cycle is completed, first abnormal data is determined, the first abnormal data being the data within a first preset length in the sampling array starting with the data bit corresponding to the end point of the rising edge and counting up, the first abnormal data being set to 0, low signal level, or empty signal, the first preset length being the array length corresponding to the rising edge interval;by the above falling edge exception processing sub-module 722, setting the data bit in the sampling array corresponding to the falling edge interval to 0, low signal level, or empty signal; while the signal sampling of an end point of the falling edge within the current pulse cycle is completed, second abnormal data is determined, the second abnormal data being the data within a second preset length in the sampling array starting from the data bit corresponding to the end point of the falling edge and counting up, the second abnormal data being set to 0, low signal level, or empty signal, the second preset length being the array length corresponding to the falling edge interval;

[0125] In some embodiments, the rising edge exception processing sub-module 721 above sets the data bit in the sample array corresponding to the first sample delay to 0, low signal level, or empty signal by setting the data bit in the sample array corresponding to a first preset sample duration to 0, low signal level, or empty signal and ending the delay; the falling edge exception processing sub-module 722 above sets the data bit in the sample array corresponding to the second sample delay to 0, low signal level, or empty signal by setting the data bit in the sample array corresponding to a second preset sample duration to 0, low signal level, or empty signal and ending the delay.

[0126] In some embodiments, the rising edge exception processing sub-module 721 above sets the data bit in the sample array corresponding to the first sample delay to 0, low signal level, or empty by the rising edge exception processing sub-module 721 above setting the data bit in the sample array corresponding to a first preset array length to 0, low signal level, or empty and the delay ends;the above falling edge exception processing sub-module 722 sets the data bit in the sampling array corresponding to the second sampling delay to 0, low signal level, or empty by the above falling edge exception processing sub-module 722 setting the data bit in the sampling array corresponding to a second preset array length to 0, low signal level, or empty and the delay ends;

[0127] In some embodiments, the abnormal data interval determination module 71 comprises: a reference threshold determination unit used to determine the rising edge interval and the falling edge interval within the current pulse cycle based on a reference threshold, the duration of the rising edge, and the duration of the falling edge, wherein the reference threshold is used to mark the low signal level; or an upper threshold determination unit used to determine the rising edge interval and the falling edge interval within the current pulse cycle based on a reference threshold and an upper threshold, the upper threshold being used to mark the high signal level; or a power determination unit used to determine the rising edge interval and the falling edge interval within the current pulse cycle based on a power change of the sampling point.

[0128] In some embodiments, it is provided that the first preset sampling duration is equal to the duration of the rising edge, wherein the second preset sampling duration is equal to the duration of the falling edge.

[0129] In some embodiments, the first preset array length and the second preset array length are determined by the duration of the rising edge or the duration of the falling edge and the sampling period according to a preset calculation relationship.

[0130] In a specific embodiment, it is provided that the first preset array length = the duration of the rising edge / sampling period, and the second preset array length = the duration of the falling edge / sampling period; or the first preset array length = the second preset array length = the duration of the rising edge / sampling period; or the first preset array length = the second preset array length = the duration of the falling edge / sampling period.

[0131] In some embodiments, it is provided that the module 71 for determining abnormal data intervals, as shown in the dashed line in Fig. 12, includes: a sub-module 711 for detecting the starting point of the rising edge, wherein the starting point of the rising edge is a sample point at which the power in the current pulse cycle is greater than the reference threshold of the rising edge for the first time; a falling edge start point detection sub-module 712, wherein the falling edge start point is a sample point at which the power in the current pulse cycle is less than the falling edge reference threshold for the first time.

[0132] In some embodiments, using the sampled data set to 0 module 72 to set the data bits in the sample array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal by delaying the sampling or setting the output of the sampled data to 0 when the first preset array length = the second preset array length = the duration of the rising edge / sample period and the duration of the rising edge is greater than the duration of the falling edge comprises: if the sampled data is output while the signal sampling of the end point of the falling edge is completed within the current pulse cycle by the sampled data set to 0 module 72, calculating a duration of a third delay,wherein the duration of the third delay is a difference between the duration of the rising edge and the duration of the falling edge, wherein at the end of the third delay, third abnormal data is determined, wherein the third abnormal data is the data within a third preset length in the sample array, starting with the data bit corresponding to the end point of the third delay and counting forward, wherein the third abnormal data is set to 0, low signal level, or empty signal, wherein the third preset length is the array length corresponding to the falling edge interval.

[0133] It should be understood that in the technical solution provided by the present embodiment, the rising edge interval and the falling edge interval are determined within the current pulse cycle, and the data bit in the sampling array corresponding to the rising edge interval and the falling edge interval is set to 0, low signal level, or empty signal, and the sampling array is set to 0 with FIFO (First Input First Output) to mask the data in the abnormal segment, that is, the data output of a ramp segment is 0 in the on and off modes and in the PULSE mode, and the power is output only in the correct period except the ramp. Example 5

[0134] As in Fig. 13, the embodiment of the present invention also provides an apparatus for detecting radio frequency power signals, comprising a signal sampling module 81, wherein the signal sampling module 81 comprises: an abnormal data interval determination module 811 (also called a padding interval determination sub-module) used to determine the rising edge interval and the falling edge interval in the current pulse cycle according to a preset power increase threshold, a preset power decrease threshold, a preset number of padded data for the rising edge, and a preset number of padded data for the falling edge, respectively; a sampled data zero module 812 (also called a data padding submodule), which is used during sampling to set the data bits in the sample array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal.

[0135] In practice, the signal sampling module 81 comprises, as shown in the dashed line in Fig. 13, also: an array output module 813 used to acquire and output corresponding sample point data within a time period other than the rising edge interval and the falling edge interval.

[0136] In practice, the device includes, as shown in the dashed line in Fig. 13, also: a scan test module 82, wherein the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge are detected by continuous scan tests.

[0137] In concrete practice, as shown in the dotted line in Fig. As shown in Figure 13, the scan test module 82 comprises: a first signal acquisition sub-module 821 used to continuously acquire first radio frequency power signals at a plurality of sampling points, each of the first radio frequency power signals comprising a first voltage V and a first current I; a threshold determination sub-module 822 used to determine the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge according to the first voltage V and the first current I.

[0138] In practice, the module 811 for determining abnormal data intervals includes: a second signal acquisition sub-module used to continuously acquire second radio frequency power signals at a plurality of sampling points, each of the second radio frequency power signals comprising a second voltage V and a second current I; a sampling point power determination submodule used to determine the power of each sampling point based on the second voltage V and the second current I; a rising edge threshold data determination sub-module used to determine the starting point of the rising edge interval and the preset number of padded rising edge data based on the power of each sampling point, the power rise threshold, and a number of padded rising edge data; a falling edge threshold data determination sub-module used to determine the starting point of the falling edge interval and the preset number of padded falling edge data based on the power of each sample point, the power decay threshold, and a number of padded falling edge data.

[0139] In actual practice, determining the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge according to the first voltage V and the first current I by the threshold determination sub-module 822 includes the following: the threshold determination sub-module 822 may calculate the power value of each sample point from P=VI, obtaining: a first specific power value P r after the zero potential, a first non-P e -Performance value P d according to a peak potential performance average P e , where P r serves as a preset power increase threshold and P d serves as a preset performance degradation threshold.

[0140] The threshold determination sub-module 822 can determine the preset number of padded data for the rising edge during the rising edge process based on T r / T and the preset number of padded data for the falling edge during the falling edge process based on T d / T, where T d the falling edge time is, T r is the rising edge time and T is the sampling period.

[0141] It should be understood that the technical solution provided by the present embodiment uses a data padding method to shield the ramp segment data. By padding the corresponding number of 0 data during the rising edge and falling edge phases, the default output of the ramp data can be set to 0, thereby achieving the purpose of shielding the ramp segment data and avoiding the acquisition of inaccurate values. The corresponding number of limited data is filled in at the rising and falling edges, thereby solving the problem of related technologies that the data read by the acquisition board during the ramp phase is incorrect and affects the calculation of subsequent power values ​​and impedance values. Example 6

[0142] Based on the same technical concept, the embodiment of the present application also provides a computer device including a memory 1 and a processor 2. As in Fig. 14, the memory 1 can store a computer program, wherein the processor 2, when executing the computer program, implements one of the above-mentioned methods for detecting radio frequency power signals.

[0143] The memory 1 comprises at least one type of readable storage medium, wherein the readable storage medium includes a flash memory, a hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory or the like), a magnetic memory, a floppy disk, an optical memory, and the like. In some embodiments, the memory 1 may be an internal storage unit of the OTT video service surveillance system, for example, a hard disk. In further embodiments, the memory 1 may also be an external storage device of the OTT video service surveillance system, for example, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital device (SD card), a flash memory card (Flash Card), or the like. Furthermore, the memory 1 may also comprise both an internal storage unit of the OTT video service surveillance system and an external storage device.The memory 1 can be used not only for storing the application software installed in the OTT video service monitoring system and various data, such as the code of the OTT video service monitoring program or the like, but also for temporarily storing output or yet-to-be-output data.

[0144] In some embodiments, the processor 2 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip and is used to execute the program code stored in the memory 1 or to process data, for example, to execute an OTT video service monitoring program or the like.

[0145] It should be understood that in the technical solution provided by the present embodiment, the rising edge interval and the falling edge interval are determined within the current pulse cycle, and the data bit in the sampling array corresponding to the rising edge interval and the falling edge interval is set to 0, low signal level, or empty signal, and the sampling array is set to 0 with FIFO (First Input First Output) to mask the data in the abnormal segment, that is, the data output of a ramp segment is 0 in the on and off modes and in the PULSE mode, and the power is output only in the correct period except the ramp.

[0146] The embodiments disclosed by the invention also provide a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, wherein, when the computer program is executed by the processor, the steps of the method for detecting radiofrequency power signals in the above method embodiments are carried out. The storage medium may be a volatile or non-volatile computer-readable storage medium.

[0147] The computer program product of the method for detecting radiofrequency power signals provided by the embodiments disclosed by the invention comprises a computer-readable storage medium on which the program code is stored, wherein the instructions contained in the program code can be used to execute the steps of the method for detecting radiofrequency power signals in the above method embodiments. Details can be found in the above method embodiments, which are not described again here.

[0148] The embodiments disclosed by the invention also provide a computer program, wherein, when the computer program is executed by the processor, one of the methods of the above-mentioned embodiments is implemented. The computer program product can be specifically implemented by hardware, software, or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium. In a further optional embodiment, the computer program product is specifically embodied as a software product, for example, as a software development kit (SDK), and so on.

[0149] It is understood that the same or similar parts in the respective embodiments above may be referred to one another, and content not described in detail in some embodiments may refer to the same or similar content in other embodiments.

[0150] It should be noted that in the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and should not be understood to indicate or imply a relative meaning. Furthermore, in the description of the present invention, unless otherwise specified, the meaning of "plurality" means at least two.

[0151] Any process or method descriptions in flowcharts or otherwise described herein may be understood to represent modules, segments, or portions of code containing one or more executable instructions for implementing particular logical functions or steps of the process, and the scope of the preferred embodiments of the present invention includes alternative implementations that may perform functions outside of the order shown or discussed, including performing involved functions substantially concurrently or in reverse order, as should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0152] It should be understood that any part of the present invention may be implemented by hardware, software, firmware, or a combination thereof. In the embodiments described above, various steps or methods may be implemented by software or firmware stored in memory and executed by a suitable instruction execution system. For example, when implemented by hardware, as in another embodiment, it may be implemented by any one or a combination of the following techniques known in the art: discrete logic circuits with logic gates for implementing logical functions on data signals, ASICs with suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0153] One of ordinary skill in the art can understand that all or parts of the steps required in implementing the methods of the above-mentioned embodiments can be completed by instructing relevant hardware through programs, which program can be stored on a computer-readable storage medium, which program, when executed, comprises one of the steps of the method embodiments or a combination thereof.

[0154] Furthermore, in various embodiments of the present invention, each functional unit may be integrated into a processing module, or each unit may physically exist alone, or two or more units may be integrated into a module. The above-mentioned integrated modules may be implemented as hardware or software functional modules. Integrated modules may be stored on a computer-readable storage medium even if they are implemented as software functional modules and sold or used as standalone products.

[0155] The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk or the like.

[0156] As used herein, reference in the descriptions of the terms "one embodiment," "some embodiments," "example," "specific examples," or "some examples," or like terms means that specific features, structures, materials, or special features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this description, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials, or special features may be combined in any suitable manner in any one or more embodiments or examples.

[0157] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and those skilled in the art may make changes, modifications, substitutions and alterations to the above-mentioned embodiments within the scope of the present invention.

Claims

[1] Method for detecting radio frequency power signals, characterized by that the procedure includes: Determining a rising edge interval and a falling edge interval within a current pulse cycle; Setting the data bits in a sample array corresponding to the rising edge interval and the falling edge interval to 0, signal low, or empty. [2] A method for detecting radio frequency power signals according to claim 1, characterized by that setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal is achieved by setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal, by delaying the sampling, or by setting the output of the sampled data to 0. [3] A method for detecting radio frequency power signals according to claim 2, characterized by that setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal by delaying the sampling or setting the output of the sampled data to 0 comprises: when data is sampled in the rising edge interval, the data bit in the sampling array corresponding to the rising edge interval is set to 0, low signal level, or empty signal by delaying the sampling time, or when the sampling data is output, the data bit in the sampling array corresponding to the rising edge interval is set to 0, low signal level, or empty signal; When data is sampled in the falling edge interval, the data bit in the sample array corresponding to the falling edge interval is set to 0, low signal level, or empty signal by delaying the sampling time, or when the sample data is output, the data bit in the sample array corresponding to the falling edge interval or the falling edge interval is set to 0, low signal level, or empty signal. [4] A method for detecting radio frequency power signals according to claim 3, characterized bythat setting the data bit in the sampling array corresponding to the rising edge interval to 0, a low signal level, or an empty signal by delaying the sampling time comprises the following: starting from a starting point of the rising edge in the current pulse cycle, starting the first sampling delay and setting a data bit in the sampling array corresponding to the first sampling delay to 0, a low signal level, or an empty signal; wherein setting the data bit in the sampling array corresponding to the falling edge interval to 0, a low signal level, or an empty signal by delaying the sampling time comprises the following: starting from a starting point of the falling edge in the current pulse cycle, starting the second sampling delay and setting a data bit in the sampling array corresponding to the second sampling delay to 0, a low signal level, or an empty signal. [5] A method for detecting radio frequency power signals according to claim 3, characterized byin that setting the data bit in the sampling array corresponding to the rising edge interval to 0, low signal level, or empty signal comprises: while the signal sampling of an end point of the rising edge within the current pulse cycle is completed, first abnormal data is determined, the first abnormal data being the data within a first preset length in the sampling array starting with the data bit corresponding to the end point of the rising edge and counting up, the first abnormal data being set to 0, low signal level, or empty signal, the first preset length being the array length corresponding to the rising edge interval;that setting the data bit in the sampling array corresponding to the falling edge interval to 0, low signal level, or empty signal comprises: while the signal sampling of an end point of the falling edge within the current pulse cycle is completed, second abnormal data is determined, the second abnormal data being the data within a second preset length in the sampling array starting with the data bit corresponding to the end point of the falling edge and counting up, the second abnormal data being set to 0, low signal level, or empty signal, the second preset length being the array length corresponding to the falling edge interval; [6] A method for detecting radio frequency power signals according to claim 4, characterized bythat setting the data bit in the sampling array corresponding to the first sampling delay to 0, low signal level, or empty signal is effected by setting the data bit in the sampling array corresponding to a first preset sampling period to 0, low signal level, or empty signal, and the delay ends; setting the data bit in the sampling array corresponding to the second sampling delay to 0, low signal level, or empty signal is effected by setting the data bit in the sampling array corresponding to a second preset sampling period to 0, low signal level, or empty signal, and the delay ends. [7] A method for detecting radio frequency power signals according to claim 4, characterized bythat setting the data bit in the sampling array corresponding to the first sampling delay to 0, low signal level, or empty signal is performed by setting the data bit in the sampling array corresponding to a first preset array length to 0, low signal level, or empty signal, and the delay ends; setting the data bit in the sampling array corresponding to the second sampling delay to 0, low signal level, or empty signal is performed by setting the data bit in the sampling array corresponding to a second preset array length to 0, low signal level, or empty signal, and the delay ends. [8] A method for detecting radio frequency power signals according to claim 4, characterized by that determining a rising edge interval and a falling edge interval within a current pulse cycle comprises: Determining the rising edge interval and the falling edge interval within the current pulse cycle based on a reference threshold, the duration of the rising edge, and the duration of the falling edge, wherein the reference threshold is used to mark the low signal level; or Determining the rising edge interval and the falling edge interval within the current pulse cycle using a reference threshold and an upper threshold, the upper threshold being used to mark the high signal level; or Determine the rising edge interval and the falling edge interval within the current pulse cycle based on a power change of the sample point. [9] A method for detecting radio frequency power signals according to claim 6, characterized bythat the first preset sampling duration is equal to the duration of the rising edge, whereas the second preset sampling duration is equal to the duration of the falling edge. [10] A method for detecting radio frequency power signals according to claim 7, characterized by that the first preset array length and the second preset array length are determined by the duration of the rising edge or the duration of the falling edge and the sampling period according to a preset calculation relationship. [11] A method for detecting radio frequency power signals according to claim 10, characterized bythat the first preset array length = the duration of the rising edge / sample period, and the second preset array length = the duration of the falling edge / sample period; or the first preset array length = the second preset array length = the duration of the rising edge / sample period; or the first preset array length = the second preset array length = the duration of the falling edge / sample period. [12] A method for detecting radio frequency power signals according to claim 8, characterized by that determining the rising edge interval and the falling edge interval within the current pulse cycle based on a power change of the sample point comprises: detecting the starting point of the rising edge, wherein the starting point of the rising edge is a sample point at which the power in the current pulse cycle is greater than the reference threshold of the rising edge for the first time; Detecting the starting point of the falling edge, wherein the starting point of the falling edge is a sample point at which the power in the current pulse cycle is less than the reference threshold of the falling edge for the first time. [13] Method for detecting radio frequency power signals according to one of claims 1 to 12, characterized by that the method also includes the following: outside the rising edge interval and the falling edge interval, the sampling array can read the sampled data and output them sequentially. [14] A method for detecting radio frequency power signals according to claim 11, characterized bythat setting the data bits in the sampling array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal by delaying the sampling or setting the output of the sampled data to 0 when the first preset array length = the second preset array length = the duration of the rising edge / sampling period and the duration of the rising edge is greater than the duration of the falling edge, comprises: when the sample data is output while the signal sampling of the end point of the falling edge is completed within the current pulse cycle, a duration of a third delay is calculated, the duration of the third delay being a difference between the duration of the rising edge and the duration of the falling edge, wherein third abnormal data is determined at the end of the third delay, the third abnormal data being the data within a third preset length in the sample array starting from the data bit corresponding to the end point of the third delay and counting up, the third abnormal data being set to 0, low signal level, or empty signal, the third preset length being the array length corresponding to the falling edge interval. [15] A method for detecting radio frequency power signals according to claim 1, characterized bythat determining the rising edge interval and the falling edge interval within the current pulse cycle comprises: the rising edge interval and the falling edge interval in the current pulse cycle are determined according to a preset power increase threshold, a preset power decrease threshold, a preset number of padded data for the rising edge, and a preset number of padded data for the falling edge, respectively. [16] A method for detecting radio frequency power signals according to claim 15, characterized by that before determining the rising edge interval and the falling edge interval within the current pulse cycle, the method further comprises: Continuous sampling tests capture the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge. [17] A method for detecting radio frequency power signals according to claim 16, characterized by that capturing the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge by continuous sampling tests comprises: first radio frequency power signals are continuously acquired at a plurality of sampling points, each of the first radio frequency power signals comprising a first voltage V and a first current I; wherein the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge, and the preset number of padded data for the falling edge are determined according to the first voltage V and the first current I. [18] A method for detecting radio frequency power signals according to claim 16, characterized by that determining the rising edge interval and the falling edge interval in the current pulse cycle respectively according to a preset power increase threshold, a preset power decrease threshold, a preset number of padded data for the rising edge and a preset number of padded data for the falling edge comprises: second radio frequency power signals are continuously acquired at a plurality of sampling points, each of the second radio frequency power signals comprising a second voltage V and a second current I; the power of each sampling point is determined using the second voltage V and the second current I; the starting point of the rising edge interval and the preset number of padded data for the rising edge are determined based on the power of each sampling point, the power rise threshold, and a number of padded data for the rising edge; The starting point of the falling edge interval and the preset number of padded data for the falling edge are determined based on the power of each sample point, the power decay threshold, and a number of padded data for the falling edge. [19] A method for detecting radio frequency power signals according to claim 17, characterized by that determining the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge and the preset number of padded data for the falling edge according to the first voltage V and the first current I comprises: Calculating the power value of each sample point from P=VI, and obtaining: a first specific power value Pr after the zero potential, a first non-Pe power value Pd after a peak potential power average Pe, where Pr serves as a preset power increase threshold and Pd serves as a preset power decrease threshold. [20] A method for detecting radio frequency power signals according to claim 19, characterized bythat determining the preset power increase threshold, the preset power decrease threshold, the preset number of padded data for the rising edge and the preset number of padded data for the falling edge according to the first voltage V and the first current I also comprises: Determining the preset number of padded data for the rising edge during the rising edge process based on Tr / T, and determining the preset number of padded data for the falling edge during the falling edge process based on Td / T, where Td is the falling edge time, Tr is the rising edge time, and T is the sampling period. [21] Device for detecting radio frequency power signals, characterized by that the device comprises: an abnormal data interval determination module used to determine a rising edge interval and a falling edge interval within a current pulse cycle; a sampled data set module used to set the data bits in a sample array corresponding to the rising edge interval and the falling edge interval to 0, low signal level, or empty signal. [22] Computer device, characterized by in that the computing device comprises: a processor, a memory, and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating via the bus when the computing device is running, the method for detecting radio frequency power signals according to any one of claims 1 to 20 being performed when the machine-readable instructions are executed by the processor. [23] Computer-readable storage medium, characterized by that a computer program is stored on the computer-readable storage medium, wherein the method for detecting radio frequency power signals according to one of claims 1 to 20 is carried out when the computer program is executed by the processor.

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