METHODS AND DEVICES FOR MATRIX MULTIPLICATION WITH REINFORCEMENT LEARNING

Abstract

Technical solutions for matrix multiplication using reinforcement learning are revealed. An exemplary setup includes an interface circuit arrangement, machine-readable instructions, and a programmable circuit arrangement for instantiating and / or executing the machine-readable instructions for identifying matrices to be multiplied, splitting the matrices into subgroups, determining an initial tiling state based on the subgroups, determining an action to be performed on the matrices, transforming the initial tiling state by performing the action on the matrices, calculating a tiling state latency based on the execution of the action on the matrices, and updating the initial tiling state based on the transformed tiling state and / or the calculated tiling state latency.

Description

AREA OF REVELATION

[0001] This revelation concerns scientific computing in general, and in particular methods and devices for matrix multiplication with reinforcement learning. BACKGROUND

[0002] Matrix multiplication is a fundamental aspect of scientific computing. It is defined as multiplying two input matrices to obtain an output matrix. A linear algebraic routine for multiplying matrices is used in many applications, such as image processing, physics simulations, eigenvalue decomposition, and more. In particular, General Matrix Multiplication (GEMM), a Basic Linear Algebra Subprogram (BLAS), is a fundamental operator in deep learning (e.g., machine learning, artificial intelligence (AI), neural networks, etc.). BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A is a block diagram of an example environment in which an example trainer works to generate a tiling solution. Fig. 1B is an exemplary flow process for creating a Soling solution based on a General Matrix Multiplication (GEMM) problem. Fig. Figure 2 is a block diagram of an exemplary implementation of the tiling solution circuit arrangement of Fig. 1A. Fig. 3 is an exemplary tiling state, which is defined by the exemplary tiling solution circuit arrangement of Fig. 2 to be calculated. Fig. Figure 4 is an exemplary machine learning model training process implemented using the tiling state training circuit arrangement of Fig. 2 is to be used. Fig. Figure 5 is a flowchart that presents exemplary machine-readable instructions and / or exemplary operations that can be executed, instantiated, and / or performed by exemplary programmable circuit arrangements to implement the tiling solution circuit arrangement of Fig. 2 to implement. Fig. Figure 6 is a flowchart that represents exemplary machine-readable instructions and / or exemplary operations that can be executed, instantiated, and / or performed by exemplary programmable circuit arrangements to implement the tiling state initialization circuit arrangement of Fig. 2 to implement. Fig. Figure 7 is a flowchart that represents exemplary machine-readable instructions and / or exemplary operations that can be executed, instantiated, and / or performed by exemplary programmable circuit arrangements to define the action-determining circuit arrangement of Fig. 2 to implement. Fig. Figure 8 is a block diagram of an exemplary processing platform that includes a programmable circuit arrangement structured to execute, instantiate, and / or perform the exemplary machine-readable instructions and / or the exemplary operations of Fig. 5-7 to perform the tiling solution circuit arrangement of Fig. 2 to implement. Fig. Figure 9 is a block diagram of an exemplary implementation of the programmable circuit arrangement of Fig. 8. Fig. Figure 10 is a block diagram of another exemplary implementation of the programmable circuit arrangement of Fig. 8. Fig. Figure 11 is a block diagram of an exemplary software / firmware / instruction distribution platform (e.g., one or more servers) for distributing software, instructions, and / or firmware (e.g., according to the exemplary machine-readable instructions of Fig. 5-7) to client devices associated with end users and / or consumers (e.g., for licensing, sale, and / or use), retailers (e.g., for sale, resale, licensing, and / or sublicensing), and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products intended for distribution to retailers and / or other end users such as direct customers).

[0003] Generally, the same reference numbers are used throughout the drawing(s) and accompanying written description to refer to the same or similar parts. The figures are not necessarily to scale. Rather, the thickness of the layers or areas in the drawings may be enlarged. Although the figures show layers and areas with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be imperceptible, blend into one another, and / or be irregular.

[0004] Unless specifically stated otherwise, the descriptors "first," "second," "third," etc., are used herein without implying or otherwise assigning to them any meaning of priority, physical order, position in a list, and / or any arbitrary order, but are used merely as labels and / or arbitrary names to distinguish elements for ease of understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element in a claim may be referred to by a different descriptor, such as "second" or "third."In such cases, it is understood that such descriptors are used only to uniquely identify those elements within the context of the discussion (for example, within a claim), where the elements might otherwise share the same name.

[0005] As used herein, the term “in communication”, including variations thereof, encompasses direct communication and / or indirect communication through one or more intermediaries, and does not require direct physical (for example, wired) communication and / or continuous communication, but additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals and / or one-off events.

[0006] As used herein, “programmable circuit arrangement” is defined to include (i) one or more specialized electrical circuits (e.g., an application-specific integrated circuit (ASIC)) structured to perform one or more specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits programmable with instructions to perform one or more specific functions and / or operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of a programmable circuit arrangement include programmable microprocessors, such as central processing units (CPUs).that can execute first instructions to perform one or more operations and / or functions, field-programmable gate arrays (FPGAs) that can be programmed with second instructions to configure and / or structure the FPGAs to instantiate one or more operations and / or functions according to the first instructions, graphics processing units (GPUs) that can execute first instructions to perform one or more operations and / or functions, digital signal processors (DSPs) that can execute first instructions to perform one or more operations and / or functions, XPUs, network processing units (NPUs), one or more microcontrollers that can execute first instructions to perform one or more operations and / or functions,and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous data processing system that includes several types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) and an orchestration technology (e.g., application programming interface(s) (API(s)) that can assign one or more data processing tasks to any of the several types of programmable circuitry that are suitable and available to perform the data processing task(s)). DETAILED DESCRIPTION

[0007] Matrix multiplication is a computationally intensive operation that requires significant computing resources. GEMM is a foundation of deep learning / AI / neural networks and represents core building blocks for such operations. GEMM operations involve computationally intensive and therefore time-consuming building blocks for creating fully connected layers of neural networks.

[0008] Optimizing GEMM operations typically involves manual tiling solution configurations, grid searches in the input matrices, random searches in the input matrices, and many other procedures. Each of these procedures introduces complexity and requires significant computational resources to operate, which is inefficient on smaller and / or computationally limited platforms.

[0009] The examples revealed here provide a model for deep reinforcement learning to dynamically execute GEMM operations in order to generate low-latency tiling solutions tailored to the platform on which the GEMM operations are to be performed. In some examples, the computational size of the GEMM operations is dynamically modified. In some examples, the training of a machine learning model is performed based on an iterative execution process.

[0010] Fig. Figure 1A is a block diagram of an example environment 100 in which an example trainer works to create a tiling solution (e.g., a matrix multiplication space / computation permutation for a GEMM problem). The example environment 100 includes a trainer 110 for creating the tiling solution. In some examples, the trainer 110 is trained to learn one or more tiling configurations of the GEMM, such as modeling the tiling configuration of the GEMM problem as a Markov decision process (MDP), where state, policy, and action are associated with the GEMM tiling configuration. The trained model is augmented through continuous training (e.g., at runtime) so that the model can adapt to changes in the example environment 100.

[0011] The trainer 110 includes a tiling solution circuit arrangement 120 and a database 130. In some examples, the tiling solution circuit arrangement 120 communicates with the database 130 within the trainer 110. In other examples, the database 130 is independent of the trainer 110 and communicates with the tiling solution circuit arrangement 120 via a network connection (e.g., WiFi, Ethernet, etc.). The tiling solution circuit arrangement 120 includes instructions for creating the tiling solution.

[0012] Database 130 stores current and / or previous tiling solutions. In some examples, the tiling solution circuit arrangement 120 accesses database 130 to train a machine learning model based on previous tiling solutions. In some examples, database 130 stores logs of previous tiling solutions and / or computation times for the instructions executed by the tiling solution circuit arrangement 120.

[0013] Fig. 1B is an exemplary flow process 150 for creating a tiling solution based on a GEMM problem. In the exemplary flow process 150 of Fig. 1B includes a GEMM problem with two matrices (e.g., matrix A with dimensions of mxk and matrix B with dimensions of kxn), where an MDP modeling process models the GEMM problem.

[0014] The tiling space is investigated using an Advantage-Actor-Critic (A2C) algorithm. The A2C algorithm uses a state design. i , an action design a i , a reward design r i , a multi-layer perceptron (MLP) training strategy (MLP model) and an inference strategy. In some examples, the hardware environment in which the exemplary flow process 150 is executed is changed, and the exemplary flow process 150 is still applicable to the newly changed hardware environment.

[0015] Once the tiling space has been examined and the MLP model trained, the desired tiling solution with low latency is obtained. The exemplary flow process 150 can be repeated as often as necessary to retrain the MLP model and obtain a new tiling state with lower latency.

[0016] Fig. Figure 2 is a block diagram of an exemplary implementation of the tiling solution circuit arrangement 120 by Fig. 1A for creating a tiling solution for a GEMM problem. The tiling solution circuit arrangement 120 of Fig. 2 can be instantiated (e.g., an instance of it is created, launched for any desired duration, realized, implemented, etc.) by programmable circuit arrangements such as a central processing unit (CPU) that executes initial instructions. Additionally or alternatively, the tiling solution circuit arrangement 120 of Fig. 2. Instantiated (e.g., an instance of it is created, launched for any duration, realized, implemented, etc.) by (i) an application-specific integrated circuit (ASIC) and / or (ii) a field-programmable gate array (FPGA), which, in response to the execution of two instructions, is structured and / or configured to perform operations corresponding to the first instructions. It is understood that some or all of the circuit arrangements of Fig. 2 can therefore be instantiated at the same time or at different times. Part or all of the circuit arrangement of Fig. 2 can, for example, be instantiated in one or more threads that run concurrently on hardware and / or sequentially on hardware. Furthermore, in some examples, part or all of the circuitry of Fig. 2. be implemented by a microprocessor circuit arrangement that executes instructions, and / or an FPGA circuit arrangement that performs operations to implement one or more virtual machines and / or containers.

[0017] The tiling solution circuit arrangement 120 includes a matrix detection circuit arrangement 210, a Tiling state initialization circuit arrangement 220, a Action determination circuit arrangement 230, a Action modification circuit arrangement 235, a Tiling state transformation circuit arrangement 240, a Tiling state latency calculation circuit arrangement 250, one Tiling state training circuit arrangement 260 and a Tiling state update circuit arrangement 270.

[0018] The matrix detection circuit arrangement 210 detects matrices and the dimensions of the matrices. In some examples, the matrix detection circuit arrangement 210 is instantiated by a programmable circuit arrangement that executes matrix detection instructions and / or is designed to perform operations such as those described by the flowchart of Fig. 5 will be shown, to be carried out.

[0019] In some examples, the tiling solution circuit arrangement 120 includes means for detecting matrices and matrix dimensions. For example, the means for detection can be implemented by the matrix detection circuit arrangement 210. In some examples, the matrix detection circuit arrangement 210 can be replaced by a programmable circuit arrangement, such as the programmable circuit arrangement 812 from Fig. 8. For example, the matrix detection circuit arrangement 210 can be instantiated by the exemplary microprocessor 900 of Fig. 9 is instantiated, which executes machine-executable instructions, such as those defined by at least block 510 of Fig. 5 can be implemented. In some examples, the matrix detection circuit arrangement 210 can be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit arrangement 1000. Fig. 10 can be implemented, designed and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the matrix detection circuit arrangement 210 can be instantiated by any other combination of hardware, software, and / or firmware. For example, the matrix detection circuit arrangement 210 can be implemented by at least one or more hardware circuits (e.g., a processor circuit arrangement, a discrete and / or integrated analog and / or digital circuit arrangement, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier, a logic circuit, etc.), designed and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing any software or firmware, although other structures are equally suitable.

[0020] The tiling state initialization circuit arrangement 220 initializes a tiling state for the execution of actions on the matrices. In some examples, the tiling state initialization circuit arrangement 220 is instantiated by a programmable circuit arrangement that executes tiling state initialization instructions and / or is designed to perform operations such as those described by the flowcharts of Fig. 5 and / or 6 are shown to be carried out.

[0021] In some examples, the tiling solution circuit arrangement 120 includes means for initializing a tiling state. For example, the means for initialization can be implemented by a tiling state initialization circuit arrangement 220. In some examples, the tiling state initialization circuit arrangement 220 can be implemented by a programmable circuit arrangement, such as the exemplary programmable circuit arrangement 812 of Fig. 8. For example, the tiling state initialization circuit arrangement 220 can be instantiated by the exemplary microprocessor 900 of Fig. 9 is instantiated, which executes machine-executable instructions, such as those made up of at least 520 blocks of Fig. 5 and Fig. 610, Fig. 620 and Fig. 630 of Fig. 6 can be implemented. In some examples, the tiling state initialization circuit arrangement 220 can be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit arrangement 1000 of Fig. 10 can be implemented, designed and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the tiling state initialization circuit arrangement 220 can be instantiated by any other combination of hardware, software, and / or firmware. For example, the tiling state initialization circuit arrangement 220 can be implemented by one or more hardware circuits (e.g., a processor circuit arrangement, a discrete and / or integrated analog and / or digital circuit arrangement, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier, a logic circuit, etc.).), designed and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally suitable.

[0022] The action determination circuit arrangement 230 determines actions to be performed on the matrices. In some examples, the action determination circuit arrangement 230 is instantiated by a programmable circuit arrangement that executes action determination instructions and / or is designed to perform operations such as those defined by the flowcharts of Fig. 5 and / or 7 are shown to be carried out.

[0023] In some examples, the tiling solution circuit arrangement 120 includes means for determining actions to be performed on the matrices. These means of determination can be implemented, for example, by the action determination circuit arrangement 230. In some examples, the action determination circuit arrangement 230 can be replaced by a programmable circuit arrangement, such as the programmable circuit arrangement 812. Fig. 8. For example, the action determination circuit arrangement 230 can be instantiated by the exemplary microprocessor 900 of Fig. 9 is instantiated, which executes machine-executable instructions, such as those made up of at least blocks 530 of Fig. 5 and Fig. 710 and Fig. 720 of Fig. 7 can be implemented. In some examples, the action determination circuit arrangement 230 can be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit arrangement 1000. Fig. 10 can be implemented, designed and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the action-determining circuit arrangement 230 can be instantiated by any other combination of hardware, software, and / or firmware. For example, the action-determining circuit arrangement 230 can be implemented by at least one or more hardware circuits (e.g., a processor circuit arrangement, a discrete and / or integrated analog and / or digital circuit arrangement, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier, a logic circuit, etc.), designed and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing any software or firmware, although other structures are equally suitable.

[0024] The action modification circuit arrangement 235 modifies the actions to be performed on the matrices. In some examples, the action modification circuit arrangement 235 is instantiated by a programmable circuit arrangement that executes action modification instructions and / or is designed to perform operations such as those described by the flowchart of Fig. 7 will be shown, to be carried out.

[0025] In some examples, the tiling solution circuit arrangement 120 includes means for updating a factorization permutation or a computation order of the actions performed on the matrices. The means for updating can be implemented, for example, by the action modification circuit arrangement 235. In some examples, the action modification circuit arrangement 235 can be replaced by a programmable circuit arrangement, such as the programmable circuit arrangement 812 of Fig. 8. For example, the action modification circuit arrangement 235 can be instantiated by the exemplary microprocessor 900 of Fig. 9 is instantiated, which executes machine-executable instructions, such as those defined by at least blocks 730 and 740 of Fig. 7 can be implemented. In some examples, the action modification circuit arrangement 235 can be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit arrangement 1000 of Fig. 10 can be implemented, designed and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the action modification circuit arrangement 235 can be instantiated by any other combination of hardware, software, and / or firmware. For example, the action modification circuit arrangement 235 can be implemented by at least one or more hardware circuits (e.g., a processor circuit arrangement, a discrete and / or integrated analog and / or digital circuit arrangement, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier, a logic circuit, etc.), designed and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing any software or firmware, although other structures are equally suitable.

[0026] The tiling state transformation circuit arrangement 240 transforms the initial tiling state by performing actions on the matrices. In some examples, the tiling state transformation circuit arrangement 240 is instantiated by a programmable circuit arrangement that executes tiling state transformation instructions and / or is designed to perform operations such as those described by the flowchart of Fig. 5 will be shown, to be carried out.

[0027] In some examples, the tiling solution circuit arrangement 120 includes means for transforming the initial tiling state by performing actions on the matrices. For example, the means for transformation can be implemented by the tiling state transformation circuit arrangement 240. In some examples, the tiling state transformation circuit arrangement 240 can be implemented by a programmable circuit arrangement, such as the exemplary programmable circuit arrangement 812 of Fig. 8. For example, the tiling state transformation circuit arrangement 240 can be instantiated by the exemplary microprocessor 900 of Fig. 9 is instantiated, which executes machine-executable instructions, such as those defined by at least blocks 540 and 560 of Fig. 5 can be implemented. In some examples, the tiling state transformation circuit arrangement 240 can be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit arrangement 1000 of Fig. 10 can be implemented, designed and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the tiling state transformation circuit arrangement 240 can be instantiated by any other combination of hardware, software, and / or firmware. For example, the tiling state transformation circuit arrangement 240 can be implemented by one or more hardware circuits (e.g., a processor circuit arrangement, a discrete and / or integrated analog and / or digital circuit arrangement, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier, a logic circuit, etc.).), designed and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally suitable.

[0028] The tiling state latency calculation circuit arrangement 250 calculates a tiling state latency for the actions performed on the matrices. In some examples, the tiling state latency calculation circuit arrangement 250 is instantiated by a programmable circuit arrangement that executes tiling state latency calculation instructions and / or is designed to perform operations such as those described by the flowchart of Fig. 5 will be shown, to be carried out.

[0029] In some examples, the tiling solution circuit arrangement 120 includes means for calculating a tiling state latency based on the execution of actions on the matrices. For example, the means for calculation can be implemented by the tiling state latency calculation circuit arrangement 250. In some examples, the tiling state latency calculation circuit arrangement 250 can be implemented by a programmable circuit arrangement, such as the exemplary programmable circuit arrangement 812 from Fig. 8. For example, the tiling state latency calculation circuit arrangement 250 can be instantiated by the exemplary microprocessor 900 of Fig. 9 is instantiated, which executes machine-executable instructions, such as those defined by at least block 550 of Fig. 5 can be implemented. In some examples, the tiling state latency calculation circuit arrangement 250 can be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit arrangement 1000. Fig. 10 can be implemented, designed and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the tiling state latency calculation circuit arrangement 250 can be instantiated by any other combination of hardware, software, and / or firmware. For example, the tiling state latency calculation circuit arrangement 250 can be implemented by one or more hardware circuits (e.g., processor circuit arrangement, discrete and / or integrated analog and / or digital circuit arrangement, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier, a logic circuit, etc.).), designed and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally suitable.

[0030] The tiling state training circuit arrangement 260 trains a machine learning model using the transformed tiling state and the computed tiling state latency. In some examples, the tiling state training circuit arrangement 260 is instantiated by a programmable circuit arrangement that executes tiling state training instructions and / or is designed to perform operations such as those described by the flowchart of Fig. 5 will be shown, to be carried out.

[0031] In some examples, the tiling solution circuit arrangement 120 includes means for training a machine learning model using the transformed tiling state and the computed tiling state latency. For example, the means for training can be implemented by the tiling state training circuit arrangement 260. In some examples, the tiling state training circuit arrangement 260 can be implemented by a programmable circuit arrangement, such as the exemplary programmable circuit arrangement 812 from Fig. 8. For example, the tiling state training circuit arrangement 260 can be instantiated by the exemplary microprocessor 900 of Fig. 9 is instantiated, which executes machine-executable instructions, such as those defined by at least block 570 of Fig. 5 can be implemented. In some examples, the tiling state training circuit arrangement 260 can be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit arrangement 1000. Fig. 10 can be implemented, designed and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the tiling state training circuit arrangement 260 can be instantiated by any other combination of hardware, software, and / or firmware. For example, the tiling state training circuit arrangement 260 can be implemented by one or more hardware circuits (e.g., a processor circuit arrangement, a discrete and / or integrated analog and / or digital circuit arrangement, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier, a logic circuit, etc.).), designed and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally suitable.

[0032] The tiling state update circuit arrangement 270 updates the initial tiling state based on the transformed tiling state, the calculated tiling state latency, and / or a newly trained machine learning model (e.g., during subsequent training iterations). In some examples, the tiling state update circuit arrangement 270 is instantiated by a programmable circuit arrangement that executes tiling state update instructions and / or is designed to perform operations such as those described by the flowchart of Fig. 5 will be shown, to be carried out.

[0033] In some examples, the tiling solution circuit arrangement 120 includes means for updating the initial tiling state based on the transformed tiling state and the computed tiling state latency and / or the newly trained machine learning model. For example, the means for updating can be implemented by the tiling state update circuit arrangement 270. In some examples, the tiling state update circuit arrangement 270 can be implemented by a programmable circuit arrangement, such as the exemplary programmable circuit arrangement 812 from Fig. 8. For example, the tiling state update circuit arrangement 270 can be instantiated by the exemplary microprocessor 900 of Fig. 9 is instantiated, which executes machine-executable instructions, such as those defined by at least block 580 of Fig. 5 can be implemented. In some examples, the tiling state update circuit arrangement 270 can be instantiated by a hardware logic circuit implemented by an ASIC, an XPU, or the FPGA circuit arrangement 1000 of Fig. 10 can be implemented, designed and / or structured to perform operations corresponding to the machine-readable instructions. Additionally or alternatively, the tiling state update circuit arrangement 270 can be instantiated by any other combination of hardware, software, and / or firmware. For example, the tiling state update circuit arrangement 270 can be implemented by one or more hardware circuits (e.g., a processor circuit arrangement, a discrete and / or integrated analog and / or digital circuit arrangement, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier, a logic circuit, etc.).), designed and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally suitable.

[0034] While an example of the implementation of the tiling solution circuit arrangement 120 of Fig. 1A in Fig. As shown in 2, one or more of the elements in Fig. The elements, processes, and / or devices shown in Figure 2 may be combined, divided, rearranged, omitted, removed, and / or implemented in any other way. Furthermore, the exemplary matrix detection circuit arrangement 210, the exemplary tiling state initialization circuit arrangement 220, the exemplary action determination circuit arrangement 230, the exemplary action modification circuit arrangement 235, the exemplary tiling state transformation circuit arrangement 240, the exemplary tiling state latency calculation circuit arrangement 250, the exemplary tiling state training circuit arrangement 260, the exemplary tiling state update circuit arrangement 270, and / or more generally, the exemplary tiling solution circuit arrangement 120, may be combined, divided, rearranged, omitted, removed, and / or implemented in any other way. Fig. 2. can be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, any of the exemplary matrix detection circuit arrangement 210, the exemplary tiling state initialization circuit arrangement 220, the exemplary action determination circuit arrangement 230, the exemplary action modification circuit arrangement 235, the exemplary tiling state transformation circuit arrangement 240, the exemplary tiling state latency calculation circuit arrangement 250, the exemplary tiling state training circuit arrangement 260, the exemplary tiling state update circuit arrangement 270, and / or more generally, the exemplary tiling solution circuit arrangement 120, could be implemented by a programmable circuit arrangement in combination with machine-readable instructions (e.g.,Firmware or software), processor circuit arrangement, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), ASIC(s), programmable logic device(s) (PLD(s)) and / or field-programmable logic device(s) (FPLD(s)), such as FPGAs, can be implemented. Furthermore, the exemplary tiling solution circuit arrangement 120 of . Fig. 2 one or more elements, processes and / or devices in addition to or instead of those in Fig. 2 include and / or may include more than one or all of the elements, processes and devices shown.

[0035] Fig. 3 is an exemplary tiling state 300, which is defined by the exemplary tiling solution circuit arrangement 120 of Fig. 2 is to be calculated. The exemplary tiling state 300 includes a first matrix 310, which contains a first subgroup 320, a second matrix 330, which contains a second subgroup 340, a third subgroup 350, an arrangement of action variables 360 and a third matrix 370.

[0036] The first matrix 310 contains m rows and k columns (e.g., dimensions of mxk). In the examples disclosed here, the first matrix 310 is partitioned into the first subgroup 320. In some examples, the first subgroup 320 contains subdivisions, such as m-groups, which determine the number of groups per row (m). Gruppen ) represents m-blocks, which is the number of blocks per row (m Block ) represents, and per-m represents the number of blocks per group (m Block-pro-Gruppe ) represents. In some examples, each of the subdivisions of the first subgroup 320 is determined independently.

[0037] The second matrix 330 contains k rows and n columns (e.g., dimensions of k x n). In the examples disclosed here, the second matrix 330 is partitioned into the second subgroup 340. In some examples, the second subgroup 340 contains the same subdivisions as the first subgroup 320, tailored to the n dimension, such as n-groups, which determine the number of groups per column (n). Gruppen ) represents n blocks, which is the number of blocks per column (n Block ) represents, and pro-n, which is the number of blocks per group (n Block-pro-Gruppe ) represents. In some examples, each of the subdivisions of the second subgroup 340 is determined independently.

[0038] The third subgroup 350 contains subdivisions for the k-dimensionality of the first and second matrices 310 and 330. In some examples, the third subgroup 350 contains the same subdivisions as the first and second subgroups 320 and 340, tailored to the k-dimensionality, such as k-groups that represent the number of groups in the k-dimensionality (k Gruppen ) represents k-blocks, which is the number of blocks in the k-dimension (k Block ) represents, and per-k represents the number of blocks per group in the k-dimension (k Block-pro-Gruppe ) represents. In some examples, each of the subdivisions of the third subgroup 350 is determined independently.

[0039] The arrangement of action variables 360 includes each of the first, second, and third subgroups 320, 340, 350, which are arranged to perform a multiplication operation on the matrices 310, 330. In some examples, each of the subdivisions of the first, second, and third subgroups 320, 340, 350 is arranged in an initial factorization permutation (e.g., specific numbers in each subdivision) and a computational order (e.g., multiplication iteration). The determination of which actions are to be performed and in what order the actions are to be performed is described in more detail herein (e.g., Fig. 7).

[0040] The third matrix 370 is the resulting matrix from performing the actions / calculations on the first matrix 310 and the second matrix 330 (e.g., performing a matrix multiplication operation). The third matrix contains m rows and n columns (e.g., dimensions of m x n).

[0041] Fig. 4 is an exemplary machine learning model training process 400, which is implemented by the tiling state training circuit arrangement 260. Fig. 2 is to be used. The exemplary machine learning model training process 400 trains the machine learning model every n steps and updates the next iteration with the tiling state with the lowest latency from the training of the model.

[0042] In some examples, the machine learning model training process 400 initializes using a first starting tiling state 410. After a single computation (e.g., the actions performed on matrices 310 and 330 result in a calculated tiling state latency), process 400 recalculates the tiling state to obtain a second tiling state 420. The actions are then repeated on matrices 310 and 330 for n steps to obtain a final tiling state for the first iteration 430. Once the final tiling state for the first iteration 430 is obtained, initial training 435 is performed. During this time, a lower-latency initial tiling state 440 is obtained (e.g., by comparing each iteration to determine the lowest-latency tiling state).The first tiling state 440 with the lowest latency is applied to a second tiling start state 450 (e.g. illustrated by arrow 445).

[0043] Process 400 repeats for the second training cycle, in which a final tiling state for the second iteration 460 is obtained and a second training cycle 465 is performed. A second tiling state 470 with the lowest latency is obtained by the second training cycle and is then applied to a third tiling start state 480 (e.g., illustrated by arrow 475). Process 400 continues for as many training cycles as necessary to reduce the tiling state latency to acceptable values ​​(e.g., based on program / execution requirements, etc.).

[0044] One or more flowcharts representing exemplary machine-readable instructions that can be executed by a programmable circuit arrangement to implement the tiling state circuit arrangement 120 of Fig. 2 to implement and / or instantiate, and / or represent exemplary operations that can be performed by a programmable circuit arrangement to implement the tiling state circuit arrangement 120 of Fig. 2. To implement and / or instantiate are in Fig. 5-7 shown. The machine-readable instructions can be one or more executable programs or part(s) of one or more executable programs for execution by a programmable circuit arrangement, such as the processor circuit arrangement 812 shown below in conjunction with Fig. 8 discussed exemplary processor platform 800 is shown, and / or may be one or more functions or one or more parts of functions that are shown by the below in conjunction with the Fig. The exemplary programmable circuit arrangements (e.g., an FPGA) discussed in sections 9 and / or 10 are to be implemented. In some examples, the machine-readable instructions cause an operation, task, etc., to be performed automatically in the real world. As used here, "automated" means without human intervention.

[0045] The program may be formulated as instructions (e.g., software and / or firmware) stored on one or more non-transient computer-readable and / or machine-readable storage media, such as cache, magnetic storage device or disk (e.g., a floppy disk, a hard disk drive (HDD), etc.), optical storage device or disk (e.g., a Blu-ray disc, a compact disc (CD), a digital versatile disc (DVD), etc.), a redundant array of independent disks (RAID), a register, a ROM, a solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., random-access memory (RAM) of any type, etc.), and / or any other storage device or storage disk.The instructions of the non-volatile, computer-readable and / or machine-readable medium can be programmed and / or executed by programmable circuitry located in one or more hardware devices, but the entire program and / or parts thereof could alternatively be executed and / or instantiated by one or more hardware devices that are not part of the programmable circuitry and / or that are embodied in dedicated hardware. The machine-readable instructions can be distributed across multiple hardware devices and / or executed by two or more hardware devices (for example, a server and a client hardware device). For example, the client hardware device can be executed by an endpoint client hardware device (e.g., a server).a hardware device assigned to a human and / or machine user) or an intermediate client-hardware device gateway (e.g., a wireless access network (RAN)) can be implemented, which can facilitate communication between a server and an endpoint client hardware device. Similarly, the non-volatile, machine-readable storage medium can include one or more media. Furthermore, although the example program refers to the one in . Fig. As described in the flowchart shown in Figures 5-7, many other methods can alternatively be used to implement the exemplary tiling solution circuit arrangement 120. For example, the execution order of the flowchart blocks can be changed, and / or some of the described blocks can be modified, removed, or combined. Additionally or alternatively, any or all of the flowchart blocks can be implemented by one or more hardware circuits (e.g., a processor circuit arrangement, a discrete and / or integrated analog and / or digital circuit arrangement, an FPGA, an ASIC, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing any software or firmware.The programmable circuit arrangement can be distributed across different network locations and / or located locally on one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, an XPU, etc.)). For example, the programmable circuit arrangement could be a CPU and / or an FPGA located in the same package (e.g., in the same integrated circuit (IC) package or in two or more separate packages), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof.

[0046] The machine-readable instructions described here can be stored in one or more formats, including compressed, encrypted, fragmented, compiled, executable, and packaged. Machine-readable instructions, as described here, can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), or a data structure (e.g., as part(s) of instructions, code, representations of code, etc.) that can be used to generate, manufacture, and / or produce machine-executable instructions. For example, the machine-readable instructions can be fragmented and stored on one or more storage devices, disks, and / or computing devices (e.g., hard drives, hard disks, etc.).Machine-readable instructions may be stored on servers located in the same or different locations within a network or collection of networks (e.g., in the cloud, on edge devices, etc.). These instructions may require one or more of the following operations: installation, modification, adaptation, updating, combining, augmentation, configuration, decryption, decompression, unpacking, distribution, remapping, compilation, etc., to make them directly readable, interpretable, and / or executable by a computing device and / or another machine.For example, the machine-readable instructions may be stored in multiple parts, which are individually compressed, encrypted and / or stored on separate computing devices, the parts, when decrypted, decompressed and / or combined, forming a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations which together may form a program such as the one described herein.

[0047] In another example, the machine-readable instructions might be stored in a state where they can be read by a programmable circuit arrangement, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., to execute the machine-readable instructions on a specific computing device or other device. In yet another example, the machine-readable instructions might need to be configured (e.g., settings saved, data entered, network addresses recorded, etc.) before the machine-readable instructions and / or the corresponding program(s) can be executed, either fully or partially.Thus, machine-readable, computer-readable and / or machine-readable media, as used here, can include instructions and / or one or more programs, regardless of the specific format or state of the machine-readable instructions and / or the one or more programs.

[0048] The machine-readable instructions described here can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0049] As mentioned above, the exemplary operations of Figures 5-7 can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transient computer-readable and / or machine-readable media. As used herein, the terms non-volatile computer-readable medium, non-volatile computer-readable storage medium, non-volatile machine-readable medium, and / or non-volatile machine-readable storage medium are expressly defined to include any type of computer-readable storage device and / or storage disk, excluding propagating signals and transmission media.Examples of such a non-volatile computer-readable medium, a non-volatile computer-readable storage medium, a non-volatile machine-readable medium and / or a non-volatile machine-readable storage medium are optical storage devices, magnetic storage devices, a hard disk drive (HDD), flash memory, a read-only memory (ROM), a CD, a DVD, a cache, RAM of any type, a register and / or any other storage device or storage disk in which information is stored for any duration (e.g., for extended periods, permanently, for short periods, for temporary buffering and / or caching of information).As used herein, the terms “non-volatile computer-readable storage medium” and “non-volatile machine-readable storage medium” are defined to include any physical (mechanical, magnetic, and / or electrical) hardware used to store information for a period of time, but excluding signal propagation and transmission media. Examples of non-volatile computer-readable storage devices and / or non-volatile machine-readable storage devices include random-access storage of any kind, read-only storage of any kind, solid-state storage, flash memory, optical disks, magnetic disks, disk drives, and / or RAID (Redundant Array of Independent Disks) systems.As used herein, the term “device” refers to a physical structure such as mechanical and / or electrical equipment, hardware and / or circuit arrangement that may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0050] "Containing" and "comprising" (and all forms and tenses thereof) are used herein as open terms. Thus, if a claim uses any form of "containing" or "comprising" (e.g., includes, encompasses, encompassing, incorporating, exhibiting, etc.) as a preamble or within a claim recitation of any kind, it is understood that additional elements, terms, etc., may be present without falling outside the scope of protection of the claim or recitation in question. As used herein, if the phrase "at least" is used as the transitional expression in, for example, a preamble to a claim, it is an open term in the same way that the expressions "comprising" and "containing" are open terms.The term "and / or," when used in a form such as A, B and / or C, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used here in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" refers to implementations that include (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, the phrase "at least one of A or B," as used here in the context of describing structures, components, items, objects, and / or things, refers to implementations that include (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.As used here in the context of describing the execution or performance of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" refers to implementations that include any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Likewise, as used here in the context of describing the performance or performance of processes, instructions, actions, activities, etc., the phrase "at least one of A or B" refers to implementations that include any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0051] As used here, singular references (e.g., "a," "an," "one," "first," "second," etc.) do not preclude a plurality. The expression "a" object, as used here, refers to one or more of these objects. The terms "a," "one or more," and "at least one" are used interchangeably here. Furthermore, although listed individually, multiple means, elements, or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, they may potentially be combined, and inclusion in different examples or claims does not imply that a combination of features is not possible and / or advantageous.

[0052] Fig. Figure 5 is a flowchart representing exemplary machine-readable instructions and / or exemplary operations 300 that can be executed, instantiated, and / or performed by a programmable circuit arrangement to perform actions on matrices. The exemplary machine-readable instructions and / or exemplary operations 500 of Fig. The first five steps begin at block 510, where the matrix detection circuit arrangement 210 detects / identifies matrix dimensions. In some examples, the matrix detection circuit arrangement 210 detects the dimensions of two matrices that are to be multiplied together. One such example involves a first matrix 310 with dimensions of m rows and k columns and a second matrix 330 with dimensions of k rows and n columns.

[0053] When the matrix detection circuit arrangement 210 detects the dimensions of the first matrix 310 and the second matrix 330, the tiling state initialization circuit arrangement 220 initializes the tiling state for actions to be performed on the first and second matrices 310 and 330 (Block 520). In some examples, the initial tiling state is an empty tiling state. In other examples, the initial tiling state is not empty and is updated based on a previous action performed on matrices 310 and 330. In some examples, the tiling state is represented by Equation 1: si=[Fm,Fk,Fn,Omkn,J]

[0054] As shown by equation 1, s i the tiling state, F m represents the tiling space in the m-dimension, F k represents the tiling space in the k-dimension, F nrepresents the tiling space in the n-dimensional space, O mkn represents the calculation sequence of matrices 310, 330 (e.g., the calculation sequence of O would be mkn (first in the m-dimension, second in the k-dimension and third in the n-dimension) and J represents the validity of the current tiling state.

[0055] As revealed above, matrices 310 and 330 can be partitioned to allow for faster execution of calculations on matrices 310 and 330. Thus, the tiling space in the m-dimension (F) can be m ), the tiling space in the k-dimension (F k ) and the tiling space in the n-dimension (F n ) can be represented by equations 2-4 below: Fm=[mGroups,mBlock−pro−Group,mBlock] Fk=[kGroups,kBlock−pro−Group,kBlock] Fn=[nGroups,nBlock−pro−Group,nBlock]

[0056] As shown in equations 2-4, m represent Gruppen , k Gruppen and n Gruppen the number of groups in the m, k or n dimension into which matrices 310, 330 are divided m Block , k Block , and n Block represent the block size in the m, k and n dimensions into which matrices 310 and 330 are divided, and m Block-pro-Gruppe , k Block-pro-Gruppe and n Block-pro-Gruppe represent the number of blocks per group in the m-, k-, and n-dimensions of matrices 310 and 330, respectively. If all factorizations lie within a valid range and multiplication conditions (e.g., m) Gruppen × m Block-pro-Gruppe × M Block If the condition m (where m is a dimension of the first matrix 310) is satisfied, such a state is classified as valid (e.g., J returns a valid state).

[0057] Once the tiling state has been initialized by the tiling state initialization circuit arrangement 220, the action determination circuit arrangement 230 determines the actions to be performed on matrices 310 and 330 (block 530). In some examples, the actions to be performed on matrices 310 and 330 include any one of the following: a recalculation, a change in the matrix factorization permutation, or a change in the matrix calculation order. The determination of which action to perform is described here with reference to Fig. 7 revealed in more detail.

[0058] Once the actions to be performed on matrices 310 and 330 have been determined by the action determination circuit arrangement 230, the tiling state transformation circuit arrangement 240 transforms the tiling state by performing the actions on matrices 310 and 330 (Block 540). In the examples disclosed here, the tiling state is transformed into the third matrix 370 (e.g., the resulting matrix after multiplying the first matrix 310 and the second matrix 330).

[0059] Once the actions on matrices 310 and 330 are performed by the tiling state transformation circuit arrangement 240, the tiling state latency calculation circuit arrangement 250 calculates a tiling state latency for the actions performed (block 550). In the examples disclosed herein, the tiling state latency is the time required to perform the actions on matrices 310 and 330. In some examples, the tiling state latency is calculated using Equation 5 or Equation 6. r(s,a)=1cost(s';m,k,n) r(s,a)=cost(s0;m,k,n)cost(s';m,k,n)

[0060] In equations 5 and 6 above, r(s,a) is the tiling state latency based on the transformed tiling state s', where s is the tiling state solution and a are the actions performed on matrices 310 and 330. Equation 5 calculates the tiling state latency using the transformed tiling state s'. This example uses an absolute latency calculation where matrices 310 and 330 are relatively small. Conversely, the tiling state latency in equation 6 uses a relative latency calculation, which utilizes the latency of the initial tiling state s0, where matrices 310 and 330 are larger and require more computation time to perform the actions a.

[0061] Once the tiling state latency is calculated by the tiling state latency calculation circuit 250, the tiling state transformation circuit 240 determines whether the result is acceptable for output (e.g., latency requirements met) (Block 560). In some examples, the latency requirements for a given calculation are determined by the size of matrices 310 and 330 (e.g., proportional to the relative dimensions of the input matrices). If the tiling state transformation circuit 240 determines that the result is not acceptable (e.g., Block 560 returns the result NO), Blocks 530–560 are repeated until the result is acceptable.

[0062] When the tiling state transformation circuit 240 determines that the result is acceptable (e.g., block 560 returns the result YES), the tiling state training circuit 260 trains a machine learning model using the transformed tiling state and the computed tiling state latency (block 570). In some examples, the tiling state training circuit 260 uses an Advantage-Actor-Critic (A2C) algorithm to train the machine learning model. In some examples, the machine learning model is a multilayer perceptron (MLP) neural network. The A2C algorithm and the MLP neural network serve as exemplary implementations of training a machine learning model. Thus, any alternative training method can be used interchangeably here.

[0063] Once the machine learning model is trained or retrained by the tiling state training circuit 260, the tiling state update circuit 270 updates the initial tiling state based on the transformed tiling state, the calculated tiling state latency, and the newly trained machine learning model (Block 580). In some examples, updating the initial tiling state with a transformed tiling state creates a new starting point for the actions to be performed on matrices 310 and 330. Such a new starting point can reduce the latency in subsequent computations and aid in better training of the machine learning model to create better starting points for subsequent computations.

[0064] When the initial tiling state has been updated using the transformed tiling state by the tiling state update circuit arrangement 270, the exemplary machine-readable instructions and / or exemplary operations 500 of Fig. 5.

[0065] Fig. Figure 6 is a flowchart representing exemplary machine-readable instructions and / or exemplary operations that can be executed, instantiated, and / or performed by a programmable circuit arrangement to initialize a tiling state. The exemplary machine-readable instructions and / or exemplary operations of Fig. The first 6 starts at block 610, where the tiling state initialization circuit arrangement 220 divides matrices 310 and 330 into predefined subgroups. In some examples, the predefined subgroups involve dividing matrices 310 and 330 into a number of groups (e.g., m). Gruppen ), a block size (e.g. m Block ) and a number of blocks in each group (e.g., m Block-pro-Gruppe ).

[0066] Once the tiling state initialization circuit 220 divides matrices 310 and 330 into subgroups, it determines the initial tiling state using these subgroups (Block 620). In some examples where a previous computation has already taken place, the tiling state initialization circuit 220 also uses the trained or newly trained machine learning model from the previous computation to assist in determining the initial tiling state. The initial tiling state is represented by Equations 1-4 above.

[0067] Once the tiling state initialization circuitry 220 determines the initial tiling state, it generates an initial action strategy for performing the actions on matrices 310 and 330 (block 630). In some examples, the initial action strategy is generated using a separate machine learning model to analyze matrices 310 and 330 and / or the initial tiling state to determine the computation order (e.g., O). mkn ) or to determine an initial factoring permutation. In some examples, this assists the action determination circuit arrangement 230 in quickly determining the actions to be performed on matrices 310, 330.

[0068] Once the initial action strategy is determined by the tiling state initialization circuit arrangement 230, the exemplary machine-readable instructions and / or the exemplary operations of Fig. 6.

[0069] Fig. Figure 7 is a flowchart that presents exemplary machine-readable instructions and / or exemplary operations that can be executed, instantiated, and / or performed by programmable circuit arrangements to determine the actions to be performed on matrices 310 and 330. The exemplary machine-readable instructions and / or exemplary operations of Fig. The first 7 steps begin at block 710, where the action determination circuit arrangement 230 processes the previous computation iteration. In some examples, this processing includes determining the computed tiling state latency for the previous iteration. In other examples, this processing includes determining the current tiling state. Such determination of the actions to be performed on matrices 310 and 330 involves an analysis of the computational resources available to the platform on which the exemplary machine-readable instructions and / or operations are to be executed, such as the processor type, the amount of available memory (e.g., RAM), current and / or future workloads of the platform, etc.

[0070] Once the action determination circuit 230 has processed the previous computation iteration, it determines whether the actions to be performed on matrices 310 and 330 should be modified (block 720). In some examples, the action determination circuit 230 determines that no changes need to be made. In such an example, the action determination circuit 230 outputs that the actions should be performed again (e.g., recalculation), and the exemplary machine-readable instructions and / or the exemplary operations 700 of Fig. 7 (e.g., block 720 returns the result RECALCULATION).

[0071] If the action-determining circuit arrangement 230 determines that changes to the matrix factorization permutation are desired (e.g., block 720 returns the result FACTORIZATION), the action-modifying circuit arrangement 235 modifies the matrix factorization permutation (block 730). In some examples, changes to the factorization permutation involve keeping a factor constant (e.g., maintaining the number of groups (e.g., m)). Gruppen )), while the other two factors (e.g., the block size (e.g., m) Block ) and the number of blocks in each group (e.g., m Block-pro-Gruppe )) can be changed. Alternatively, the block size or the number of blocks per group could be kept constant, while the remaining two factors are modified.

[0072] If the action determination circuit arrangement 230 determines that changes to the computation order are desired (e.g., block 720 returns the result SEQUENCE), the action modification circuit arrangement 235 (block 740) modifies the computation order. In some examples, the order in which the dimensions are calculated first affects the computation latency. One such example might be to calculate the smallest dimension first. Another might be to calculate the largest dimension first. Alternatively, in some examples, the computation order can be modified based on any other determining factor, such as the relative complexity of matrices 310, 330, available computing resources, etc.

[0073] If the action determination circuit arrangement 230 determines that no changes are to be made, if the action modification circuit arrangement 235 determines that changes are to be made to the matrix factor permutation, or if the action modification circuit arrangement 235 changes the matrix calculation sequence, the exemplary machine-readable instructions and / or the exemplary operations of Fig. 7.

[0074] Fig. Figure 8 is a block diagram of an exemplary programmable circuit arrangement platform 800, structured to represent the exemplary machine-readable instructions and / or the exemplary operations of Fig. 5-7 for implementing the tiling solution circuit arrangement 120 of Fig. 2. To execute and / or instantiate. The Programmable Circuit Assembly Platform 800 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smartphone, a tablet such as an iPad™), a personal digital assistant (PDA), an internet device, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or any other wearable device, or any other type of computing device and / or electronic device.

[0075] The programmable circuit assembly platform 800 of the illustrated example includes a programmable circuit assembly 812. The programmable circuit assembly 812 of the illustrated example is hardware. For example, the programmable circuit assembly 812 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers of any desired family or manufacturer. The programmable circuit assembly 812 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices.In this example, the programmable circuit arrangement 812 implements a matrix detection circuit arrangement 210, a tiling state initialization circuit arrangement 220, an action determination circuit arrangement 230, an action modification circuit arrangement 235, a tiling state transformation circuit arrangement 240, a tiling state latency calculation circuit arrangement 250, a tiling state training circuit arrangement 260, and a tiling state update circuit arrangement 270.

[0076] The programmable circuit arrangement 812 of the illustrated example includes a local memory 813 (e.g., a cache, registers, etc.). The programmable circuit arrangement 812 of the illustrated example communicates via a bus 818 with a main memory 814, 816, which includes a volatile memory 814 and a non-volatile memory 816. The volatile memory 814 can be implemented by SDRAM (synchronous dynamic random-access memory), DRAM (dynamic random-access memory), RDRAM® (RAMBUS® dynamic random-access memory), and / or any other type of RAM device. The non-volatile memory 816 can be implemented by flash memory and / or any other desired type of storage device. Access to the main memory 814, 816 of the illustrated example is controlled by a memory controller 817.In some examples, the memory controller 817 can be implemented by one or more integrated circuits, logic circuits, microcontrollers of any desired family or manufacturer, or any other type of circuit arrangement to manage the data flow to and from the main memory 814, 816.

[0077] The programmable circuit assembly platform 800 of the illustrated example also includes an interface circuit assembly 820. The interface circuit assembly 820 can be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a USB (Universal Serial Bus) interface, a Bluetooth® interface, an NFC (Near Field Communication) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect Express (PCIe) interface.

[0078] In the illustrated example, one or more input devices 822 are connected to the interface circuit arrangement 820. The one or more input devices 822 enable a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuit arrangement 812. The one or more input devices 822 can be implemented, for example, by an audio sensor, a microphone, a camera (still image or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, and / or a speech recognition system.

[0079] One or more output devices 824 are also connected to the interface circuit arrangement 820 of the illustrated example. The one or more output devices 824 can be implemented, for example, by display devices (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, and / or a loudspeaker. The interface circuit arrangement 820 of the illustrated example thus typically includes a graphics driver card, a graphics driver chip, and / or a graphics processing unit (GPU) circuit arrangement.

[0080] The interface circuit arrangement 820 of the illustrated example also includes a communication device, such as a transmitter, a receiver, a transceiver, a modem, a home gateway, a wireless access point, and / or a network interface, to enable the exchange of data with external machines (e.g., computing devices of any type) through a network 826. Communication can be effected, for example, through an Ethernet connection, a DSL connection (DSL: Digital Subscriber Line), a telephone line connection, a coaxial cable system, a satellite system, a wireless beyond-line-of-site system, a wireless line-of-site system, a cellular system, an optical link, etc.

[0081] The programmable circuit arrangement platform 800 of the illustrated example also includes one or more mass storage disks or devices 828 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 828 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices such as flash memory devices and / or SSDs.

[0082] The machine-readable instructions 832, which are derived from the machine-readable instructions from Fig. 5-7 can be implemented, can be stored in the mass storage device 828, in volatile memory 814, in non-volatile memory 816 and / or on at least one non-volatile, computer-readable storage medium such as a CD or DVD.

[0083] Fig. Figure 9 is a block diagram of an implementation example of the programmable circuit arrangement 812 by Fig. 8. In this example, the programmable circuit arrangement 812 is used. Fig. 8 is implemented by a microprocessor 900. The microprocessor 900 can, for example, be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit). The microprocessor 900 executes some or all of the machine-readable instructions of the flowcharts of Fig. 5-7 for effectively instantiating the circuit arrangement of Fig. 2 as logic circuits for performing operations that correspond to these machine-readable instructions. In some such examples, the circuit arrangement of Fig. 2. The hardware circuitry of the microprocessor 900 is instantiated in combination with the machine-readable instructions. For example, the microprocessor 900 can be implemented by a multi-core hardware circuit arrangement, such as a CPU, DSP, GPU, XPU, etc. Although it can include any number of exemplary cores 902 (e.g., 1 core), the microprocessor 900 in this example is a multi-core semiconductor device containing N cores. The cores 902 of the microprocessor 900 can operate independently or work together to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program can be executed by one of the cores 902, or it can be executed by several of the cores 902 at the same time or at different times.In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is divided into threads and executed in parallel by two or more of the 902 cores. The software program may correspond to some or all of the machine-readable instructions and / or operations defined by the flowcharts of the firmware program. Fig. 5-7 are represented.

[0084] The 902 cores can communicate through a first exemplary bus 904. In some examples, the first bus 904 can be implemented as a communication bus to enable communication associated with one or more of the 902 cores. For example, the first bus 904 can be implemented as an Inter-Integrated Circuit (I2C) bus and / or a Serial Peripheral Interface (SPI) bus and / or a PCI bus and / or a PCIe bus. Additionally or alternatively, the first bus 904 can be implemented as any other type of computational or electrical bus. The 902 cores can receive data, instructions, and / or signals from one or more external devices through the exemplary interface circuit arrangement 906. The 902 cores can output data, instructions, and / or signals to the one or more external devices through the interface circuit arrangement 906.Although the 902 cores of this example include an exemplary local memory 920 (e.g., Level 1 (L1) cache, which may be partitioned into an L1 data cache and an L1 instruction cache), the 900 microprocessor also includes an exemplary shared memory 910, which can be shared by the cores (e.g., Level 2 (L2) cache) for high-speed access to data and / or instructions. Data and / or instructions can be transferred (e.g., shared) by writing to and / or reading from the shared memory 910. The local memory 920 of each of the 902 cores and the shared memory 910 can be part of a hierarchy of storage devices that includes multiple levels of cache memory and main memory (e.g., the main memory 814, 816 of ). Fig. 8) includes. Typically, higher storage levels in the hierarchy have lower access times and smaller storage capacities than lower storage levels. Changes at the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0085] Each Core 902 can be referred to as a CPU, a DSP, a GPU, etc., or any other type of hardware circuit arrangement. Each Core 902 includes a Control Unit Circuit Arrangement 914, an Arithmetic and Logic (AL) Circuit Arrangement (sometimes called an ALU) 916, several Registers 918, Local Memory 920, and a second example bus 922. Other structures may be present. For example, each Core 902 may include a Vector Unit Circuit Arrangement, a SIMD Unit Circuit Arrangement (SIMD: Single Instruction Multiple Data), a Load / Store Unit (LSU) Circuit Arrangement, a Branch / Jump Unit Circuit Arrangement, a Floating Point Unit (FPU) Circuit Arrangement, etc. The control unit circuit arrangement 914 includes semiconductor-based circuits structured for controlling (e.g., coordinating) a data movement within the corresponding core 902.The AL circuit arrangement 916 comprises semiconductor-based circuits structured to perform one or more mathematical and / or logical operations on the data within the corresponding core 902. In some examples, the AL circuit arrangement 916 performs integer-based operations. In other examples, the AL circuit arrangement 916 also performs floating-point operations. In still other examples, the AL circuit arrangement 916 may include a first AL circuit arrangement that performs integer-based operations and a second AL circuit arrangement that performs floating-point operations. In some exemplary cases, the AL circuit arrangement 916 may also be referred to as an arithmetic logic unit (ALU).

[0086] The 918 registers are semiconductor-based structures for storing data and / or instructions, such as the results of one or more of the operations performed by the AL circuit arrangement 916 of the corresponding 902 core. The 918 registers can include, for example, one or more vector registers, one or more SIMD registers, one or more general-purpose registers, one or more flag registers, one or more segment registers, one or more machine-specific registers, one or more instruction pointer registers, one or more control registers, one or more debug registers, one or more memory management registers, one or more machine check registers, and so on. The 918 registers can be arranged in a bank, as shown in Fig. Figure 9 shows this. Alternatively, the registers 918 can be organized in any other arrangement, format, or structure, such as being distributed within the core 902 to reduce access time. The second bus 922 can be implemented as an I2C bus, an SPI bus, a PCI bus, and / or a PCIe bus.

[0087] Each Core 902 and / or, more generally, the Microprocessor 900 may include additional and / or alternative structures to those shown and described above. For example, it may include one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more converged / common mesh stops (CMSs), one or more shifters (e.g., barrel shifters), and / or other circuit arrangements. The Microprocessor 900 is a semiconductor device manufactured to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages.

[0088] The Microprocessor 900 can include and / or work in conjunction with one or more accelerators (e.g., accelerator circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented by a logic circuitry to perform certain tasks faster and / or more efficiently than a general-purpose processor can. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. A GPU, DSP, and / or other programmable device can also be an accelerator. Accelerators can be located within the Microprocessor 900, in the same chip package as the Microprocessor 900, and / or in one or more packages separate from the Microprocessor 900.

[0089] Fig. Figure 10 is a block diagram of another exemplary implementation of the programmable circuit arrangement 812 by Fig. 8. In this example, the programmable circuit arrangement 812 is implemented by an FPGA circuit arrangement 1000. For example, the FPGA circuit arrangement 1000 can be implemented by an FPGA. The FPGA circuit arrangement 1000 can be used, for example, to perform operations that would otherwise be performed by the exemplary microprocessor 900. Fig. 9 could be performed, which executes the corresponding machine-readable instructions. However, once configured, the FPGA circuit arrangement 1000 instantiates the operations and / or functions in hardware according to the machine-readable instructions and can therefore often execute the operations / functions faster than they could be performed by a general-purpose microprocessor executing the corresponding software.

[0090] More precisely, unlike the microprocessor 900 described above, it includes Fig. 9 (which is a general-purpose device that can be programmed to execute some or all of the machine-readable instructions provided by the flowchart(s) of Fig. 5-7 are represented, whose intermediate connections and logic circuit arrangements are fixed after manufacture), the FPGA circuit arrangement 1000 of the example of Fig. 10 Intermediate connections and logic circuit arrangements that, after fabrication, can be configured, structured, programmed and / or connected in different ways to, for example, instantiate some or all of the operations / functions that are defined by the flowchart(s) of Fig. 5-7 represent machine-readable instructions. In particular, the FPGA circuit arrangement 1000 can be viewed as an arrangement of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit arrangement 1000 is reprogrammed). The configured logic circuits allow the logic gates to interact in different ways to perform different operations on data received by the input circuit arrangement. These operations can correspond to some or all of the instructions (e.g., software and / or firmware) provided by the one or more flowcharts from the Fig. 5-7 is represented. Thus, the FPGA circuit arrangement 1000 can be configured and / or structured to effectively perform some or all of the operations / functions according to the machine-readable instructions of one or more flowcharts of Fig. 5-7 are instantiated as dedicated logic circuits to perform the operations / functions corresponding to these software instructions in a dedicated manner analogous to an ASIC. Therefore, the FPGA circuit arrangement 1000 can perform the operations / functions corresponding to some or all of the machine-readable instructions of Fig. 5-7 are equivalent, faster than the general-purpose microprocessor can execute them.

[0091] In the example of Fig. 10. The FPGA circuit arrangement 1000 is configured and / or structured in response to programming (and / or one or more reprogramming) based on a binary file. In some examples, the binary file can be compiled and / or created based on instructions in a hardware description language (HDL) such as Lucid, Very High Speed ​​Integrated Circuits (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions in an HDL; the code / program can be translated into a low-level language as needed; and the code / program (e.g., the code / program in the low-level language) can be converted into the binary file (e.g., by a compiler, a software application, etc.).In some examples, the FPGA circuit arrangement can be 1000 of . Fig. 10. Access and / or load the binary file to cause the FPGA circuit arrangement to 1000 of Fig. 10 is configured and / or structured to perform one or more operations / functions. For example, the binary file can be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions to which the FPGA circuit arrangement 1000 of Fig. 10 can access to configure and / or structure the FPGA circuit arrangement 1000 of Fig. 10 or section(s) thereof.

[0092] In some examples, the binary file is compiled, generated, transformed, and / or otherwise output by a unified software platform used for programming FPGAs. The unified software platform can, for example, translate first instructions (e.g., code or a program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to the one or more operations / functions in an HDL. In some such examples, the binary file is compiled, generated, and / or otherwise output by the unified software platform based on the second instructions. In some examples, the FPGA circuit arrangement can be 1000 of Fig. 10. Access and / or load the binary file to cause the FPGA circuit arrangement to 1000 of Fig. 10 is configured and / or structured to perform one or more operations / functions. For example, the binary file can be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions to which the FPGA circuit arrangement 1000 of Fig. 10 can access to configure and / or structure the FPGA circuit arrangement 1000 of Fig. 10 or section(s) thereof.

[0093] The FPGA circuit arrangement 1000 from Fig. Section 10 includes an exemplary input / output (I / O) circuit arrangement 1002 for receiving and / or outputting data to the exemplary configuration circuit arrangement 1004 and / or external hardware 1006. For example, the configuration circuit arrangement 1004 can be implemented by an interface circuit arrangement that can receive a binary file, which may be implemented by a bitstream, data, and / or machine-readable instructions, to configure the FPGA circuit arrangement 1000 or section(s) thereof. In some such examples, the configuration circuit arrangement 1004 can receive the binary file from a user, a machine (e.g., a hardware circuit arrangement (e.g., a programmable or dedicated circuit arrangement) that can implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file), etc., and / or any combination thereof.In some examples, the external hardware 1006 can be implemented by an external hardware circuit arrangement. For example, the external hardware 1006 can be implemented by the microprocessor 900. Fig. 9 will be implemented.

[0094] The FPGA circuit arrangement 1000 also includes an array of an exemplary logic gate circuit arrangement 1008, several exemplary configurable interconnects 1010, and an exemplary storage circuit arrangement 1012. The logic gate circuit arrangement 1008 and the configurable interconnects 1010 are configurable to instantiate one or more operations / functions that implement at least some of the machine-readable instructions from the Fig. 5-7 and / or other desired operations correspond to those in Fig. The logic gate circuit assembly 1008 shown is manufactured in blocks or groups. Each block contains semiconductor-based electrical structures that can be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuit assemblies 1008 to allow configuration of the electrical structures and / or logic gates to form circuits for performing desired operations / functions. The logic gate circuit assembly 1008 may include other electrical structures, such as lookup tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0095] The configurable intermediate connections 1010 of the illustrated example are conductive paths, conductor tracks, vias or the like, which may include electrically controllable switches (e.g. transistors) whose state can be changed by programming (e.g. using an HDL instruction language) to enable or disable one or more connections between one or more of the logic gate circuit arrangements 1008 in order to program desired logic circuits.

[0096] The storage circuit arrangement 1012 of the illustrated example is structured to store the result(s) of one or more of the operations performed by the corresponding logic gates. The storage circuit arrangement 1012 can be implemented using registers or the like. In the illustrated example, the storage circuit arrangement 1012 is distributed across the logic gate arrangement 1008 to facilitate access and increase execution speed.

[0097] The exemplary FPGA circuit arrangement 1000 of Fig. Figure 10 also includes an exemplary dedicated operational circuit arrangement 1014. In this example, the dedicated operational circuit arrangement 1014 includes a special-purpose circuit arrangement 1016 that can be called upon to implement commonly used functions, thus avoiding the need to program these functions in the field. Examples of such a special-purpose circuit arrangement 1016 include a memory (e.g., DRAM) control circuit arrangement, a PCIe control circuit arrangement, a clock circuit arrangement, a transceiver circuit arrangement, a memory, and a multiplier-accumulator circuit arrangement. Other types of special-purpose circuit arrangements may be present. In some examples, the FPGA circuit arrangement 1000 may also include an exemplary programmable general-purpose circuit arrangement 1018, such as an exemplary CPU 1020 and / or an exemplary DSP 1022.Another programmable general-purpose circuit arrangement 1018 may be additionally or alternatively present, such as a GPU, an XPU, etc., which may be programmed to perform other operations.

[0098] Although Fig. 9 and Fig. 10 Two exemplary implementations of the programmable circuit arrangement 812 by Fig. As illustrated in Figure 8, many other approaches are considered. For example, an FPGA circuit arrangement can represent an internal CPU, such as one or more of the exemplary CPU 1020 from [reference missing]. Fig. 9, include. Therefore, the programmable circuit arrangement 812 of Fig. 8 additionally by combining at least the exemplary 900 microprocessor from Fig. 9 and the exemplary FPGA circuit arrangement 1000 of Fig. 10 can be implemented. In some such hybrid examples, one or more cores can be 902 of Fig. 9. Execute a first part of the machine-readable instructions specified by the flowchart(s) of Fig. Figures 5-7 are shown to perform initial operations / functions, with the FPGA circuit arrangement comprising 1000 of Fig. 10. It may be configured and / or structured to perform second operations / functions that correspond to a second part of the flowcharts of Fig. 5-7 represented machine-readable instructions, and / or an ASIC may be configured and / or structured to perform third operations / functions that correspond to a third part of the flowcharts of Fig. 5-7 represent machine-readable instructions.

[0099] It is understood that part or all of the circuit arrangement of the Fig. 2. They can therefore be instantiated at the same or different times. For example, one or more identical and / or different sections of the 900 microprocessor can be instantiated. Fig. 9 can be programmed to execute one or more sections of machine-readable instructions at the same and / or different times. In some examples, identical and / or different parts of the FPGA circuit arrangement 1000 of Fig. 10. be configured and / or structured to perform operations / functions according to one or more sections of machine-readable instructions at the same and / or different times.

[0100] In some examples, part or all of the circuit arrangement of Fig. 2. For example, it can be instantiated in one or more threads that are executed simultaneously and / or sequentially. For example, the 900 microprocessor from Fig. Execute 9 machine-readable instructions in one or more threads, which are executed concurrently and / or sequentially. In some examples, the FPGA circuit arrangement can handle 1000 of Fig. 10. It may be configured and / or structured to execute operations / functions simultaneously and / or sequentially. Furthermore, in some examples, part or all of the circuit arrangement may be Fig. 2 can be implemented within one or more virtual machines and / or containers running on the 900 microprocessor. Fig. 9 will be executed.

[0101] In some examples, the programmable circuit arrangement 812 can be used by Fig. 8 are located in one or more enclosures. For example, the 900 microprocessor from Fig. 9 and / or the FPGA circuit arrangement 1000 of Fig. 10 are located in one or more packages. In some examples, an XPU can be provided by the programmable circuit arrangement 812 from Fig. 8 can be implemented, which can be housed in one or more packages. The XPU can, for example, be a CPU (e.g., the 900 series microprocessor from Fig. 9, the CPU 1020 from Fig. 10 etc.) in a housing, a DSP (e.g. the DSP 1022 from Fig. 10) in another package, a GPU in another package and an FPGA (e.g. the FPGA circuit arrangement 1000 from Fig. 10) contained in yet another housing.

[0102] A block diagram illustrating an exemplary software distribution platform 1105 to distribute software such as the exemplary machine-readable instructions 832 of Fig. 8. Distributing to other hardware devices (e.g., hardware devices owned by third parties and / or operated by the owner and / or operator of the software distribution platform) is described in Fig. Figure 11 illustrates this. The exemplary software distribution platform 1105 can be implemented by any computer server, data facility, cloud service, etc., that is capable of storing and transferring software to other devices. The third parties can be customers of the entity that owns and / or operates the software distribution platform 1105. The entity that owns and / or operates the software distribution platform 1105 can be, for example, a developer, vendor, and / or licensor of software, such as the exemplary machine-readable instructions 832 of Fig. 8. Third parties may be consumers, users, retailers, OEMs, etc., who acquire and / or license the software for use and / or resale and / or sublicensing. In the illustrated example, the software distribution platform 1105 includes one or more servers and one or more storage devices. The storage devices store the machine-readable instructions 832, which correspond to the exemplary machine-readable instructions of Fig. 5-7 can correspond to, as described above. The one or more servers of the exemplary software distribution platform 1105 communicate with an exemplary network 1110, which can correspond to any one or more of the Internet and / or any of the exemplary networks described above. In some examples, the one or more servers, in response to requests, transfer the software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and / or licensing of the software can be processed by the one or more servers of the software distribution platform and / or by a third-party payment entity. The servers enable purchasers and / or licensors to download the machine-readable instructions 832 from the software distribution platform 1105. For example, the software, which corresponds to the exemplary machine-readable instructions from Fig. 5-7 can be downloaded to the exemplary programmable circuit arrangement platform 800, which is intended to execute the machine-readable instructions 832 to implement the tiling solution circuit arrangement 120. In some examples, one or more servers of the software distribution platform 1105 periodically offer, transmit, and / or enforce updates for the software (e.g., the machine-readable instructions 832 of Fig. 8) to ensure that improvements, patches, updates, etc. are distributed and applied to the software on end-user devices. Although referred to above as software, the distributed “software” could alternatively be firmware.

[0103] It is evident from the foregoing that exemplary systems, devices, manufactured articles, and methods implementing matrix multiplication with reinforcement learning have been disclosed. These systems, devices, manufactured articles, and methods improve the efficiency of using a computing device by modifying a tiling solution based on a machine learning model to provide low-latency matrix multiplication operations, which can be dynamically applied to platforms based on available computing resources. Accordingly, the disclosed systems, devices, manufactured articles, and methods are aimed at one or more improvements in the operation of a machine, such as a computer or other electronic and / or mechanical device.

[0104] Exemplary methods, facilities, systems, and manufactured items for implementing matrix multiplication with reinforcement learning are disclosed here. Further examples and combinations thereof include the following: Example 1 includes a setup comprising an interface circuit arrangement, machine-readable instructions, and a programmable circuit arrangement for instantiating and / or executing the machine-readable instructions for identifying matrices to be multiplied, splitting the matrices into subgroups, determining an initial tiling state based on the subgroups, determining an action to be performed on the matrices, transforming the initial tiling state by performing the action on the matrices, calculating a tiling state latency based on performing the action on the matrices, and updating the initial tiling state based on the transformed tiling state and / or the calculated tiling state latency. Example 2 includes the setup according to Example 1, wherein the programmable circuit arrangement is designed to generate an initial action strategy using the initial tiling state, wherein the initial action strategy includes a factorization permutation of one of the subgroups and / or a computation sequence in which the matrices are multiplied. Example 3 includes the setup according to Example 1, wherein the programmable circuit arrangement is designed to train a machine learning model using at least the initial tiling state of one or more subsets of the identified matrices. Example 4 includes the setup according to Example 3, wherein the programmable circuit arrangement is designed to retrain the machine learning model using the transformed tiling state and the calculated tiling state latency. Example 5 includes the setup according to Example 4, wherein the programmable circuit arrangement is designed to update the initial tiling state based on the newly trained machine learning model. Example 6 includes the setup according to Example 1, wherein the programmable circuit arrangement is designed to update a factorization permutation of one of the subgroups based on a trained machine learning model. Example 7 includes the setup according to Example 1, wherein the programmable circuit arrangement is designed to update a computation sequence in which the matrices are multiplied, based on a trained machine learning model. Example 8 includes the setup according to Example 1, where the subgroups include a number of groups and / or a block size and / or a number of blocks in each group. Example 9 includes a non-volatile, machine-readable storage medium containing instructions to cause a programmable circuit arrangement to at least identify matrices to be multiplied, divide the matrices into subgroups, determine an initial tiling state based on the subgroups, determine an action to be performed on the matrices, transform the initial tiling state by performing the action on the matrices, calculate a tiling state latency based on performing the action on the matrices, and update the initial tiling state based on the transformed tiling state and / or the calculated tiling state latency. Example 10 includes the non-volatile machine-readable storage medium of Example 9, wherein the instructions cause the programmable circuit arrangement to generate an initial action strategy using the initial tiling state, wherein the initial action strategy includes a factorization permutation of one of the subgroups and / or a computation sequence in which the matrices are multiplied. Example 11 includes the non-volatile machine-readable storage medium according to Example 9, wherein the instructions cause the programmable circuit arrangement to train a machine learning model using at least the initial tiling state of one or more subsets of the identified matrices. Example 12 includes the non-volatile machine-readable storage medium according to Example 11, wherein the instructions cause the programmable circuit arrangement to retrain the machine learning model using the transformed tiling state and the calculated tiling state latency. Example 13 includes the non-volatile machine-readable storage medium according to Example 12, wherein the instructions cause the programmable circuit arrangement to update the initial tiling state based on the newly trained machine learning model. Example 14 includes the non-volatile machine-readable storage medium according to Example 9, wherein the instructions cause the programmable circuit arrangement to update a factorization permutation of one of the subgroups based on a trained machine learning model. Example 15 includes the non-volatile machine-readable storage medium according to Example 9, wherein the instructions cause the programmable circuit arrangement to update a computation sequence in which the matrices are multiplied, based on a trained machine learning model. Example 16 includes the non-volatile machine-readable storage medium according to Example 9, wherein the subgroups include a number of groups and / or a block size and / or a number of blocks in each group. Example 17 includes a device comprising means for detecting matrices to be multiplied, means for initializing a tiling state, wherein the means for initializing are designed to partition the matrices into subgroups and determine an initial tiling state based on the subgroups, means for determining an action to be performed on the matrices, means for transforming the initial tiling state by performing the action on the matrices, means for calculating a tiling state latency based on performing the action on the matrices, and means for updating the initial tiling state based on the transformed tiling state or the calculated tiling state latency. Example 18 includes the setup according to Example 17, wherein the means for initialization are further designed to generate an initial action strategy using the initial tiling state, wherein the initial action strategy includes a factorization permutation of one of the subgroups and / or a computation sequence in which the matrices are multiplied. Example 19 includes the setup according to Example 17, further including means for training a machine learning model using at least the initial tiling state of one or more subsets of the detected matrices. Example 20 includes the setup according to Example 19, wherein the training means are designed to retrain the machine learning model using the transformed tiling state and the computed tiling state latency. Example 21 includes the setup according to Example 20, wherein the means for initialization is designed to update the initial tiling state based on the newly trained machine learning model. Example 22 includes the setup according to Example 17, further including means for updating a factorization permutation of one of the subgroups based on a trained machine learning model. Example 23 includes the setup according to Example 17, further including means for updating a computation sequence in which the matrices are multiplied, based on a trained machine learning model. Example 24 includes the setup according to Example 17, where the subgroups include a number of groups and / or a block size and / or a number of blocks in each group. Example 25 includes a procedure comprising identifying matrices to be multiplied, splitting the matrices into subgroups and determining an initial tiling state based on the subgroups, determining an action to be performed on the matrices, transforming the initial tiling state by performing the action on the matrices, calculating a tiling state latency based on performing the action on the matrices, and updating the initial tiling state based on the transformed tiling state and / or the calculated tiling state latency. Example 26 includes the procedure according to Example 25, further including generating an initial action strategy using the initial tiling state, wherein the initial action strategy includes a factorization permutation of one of the subgroups and / or a computation sequence in which the matrices are multiplied. Example 27 includes the procedure according to Example 25, further including training a machine learning model using at least the initial tiling state of one or more subsets of the identified matrices. Example 28 includes the procedure according to Example 27, further including retraining the machine learning model using the transformed tiling state and the calculated tiling state latency. Example 29 includes the procedure according to Example 28, further including updating the initial tiling state based on the newly trained machine learning model. Example 30 includes the procedure according to Example 25, further including updating a factorization permutation of one of the subgroups based on a trained machine learning model. Example 31 includes the procedure according to Example 25, further including updating a computation sequence in which the matrices are multiplied, based on a trained machine learning model. Example 32 includes the procedure according to Example 25, wherein the subgroups include a number of groups and / or a block size and / or a number of blocks in each group.

[0105] The following claims are hereby incorporated into this detailed description by reference. Although certain exemplary systems, devices, articles, and processes have been disclosed herein, the scope of protection of this patent is not limited thereto. Rather, the present patent covers all systems, devices, articles, and processes that reasonably fall within the scope of protection of the claims of this patent.

Claims

[1] Facility comprising the following: an interface circuit arrangement; machine-readable instructions; and a programmable circuit arrangement for instantiating and / or executing the machine-readable instructions for: Identifying matrices to be multiplied; Dividing the matrices into subgroups; Determining an initial tiling state based on the subgroups; Determine an action to be performed on the matrices; Transforming the initial tiling state by performing the action on the matrices; Calculating a tiling state latency based on executing the action on the matrices; and Updating the initial tiling state based on the transformed tiling state or the calculated tiling state latency. [2] Device according to claim 1, wherein the programmable circuit arrangement is designed to generate an initial action strategy using the initial tiling state, wherein the initial action strategy includes a factorization permutation of one of the subgroups and / or a computation sequence in which the matrices are multiplied. [3] Device according to claim 1, wherein the programmable circuit arrangement is designed to train a machine learning model using at least the initial tiling state of one or more subsets of the identified matrices. [4] Device according to claim 3, wherein the programmable circuit arrangement is intended to retrain the machine learning model using the transformed tiling state and the calculated tiling state latency. [5] Device according to claim 4, wherein the programmable circuit arrangement is designed to update the initial tiling state based on the newly trained machine learning model. [6] Device according to claim 1, wherein the programmable circuit arrangement is designed to update a factorization permutation of one of the subgroups based on a trained machine learning model. [7] Device according to claim 1, wherein the programmable circuit arrangement is designed to update a computation sequence in which the matrices are multiplied, based on a trained machine learning model. [8] Device according to claim 1, wherein the subgroups include a number of groups and / or a block size and / or a number of blocks in each group. [9] Non-volatile machine-readable storage medium comprising instructions to cause a programmable circuit arrangement to perform at least the following: Identifying matrices to be multiplied; Dividing the matrices into subgroups; Determining an initial tiling state based on the subgroups; Determine an action to be performed on the matrices; Transforming the initial tiling state by performing the action on the matrices; Calculating a tiling state latency based on executing the action on the matrices; and Updating the initial tiling state based on the transformed tiling state or the calculated tiling state latency. [10] Non-volatile machine-readable storage medium according to claim 9, wherein the instructions cause the programmable circuit arrangement to generate an initial action strategy using the initial tiling state, wherein the initial action strategy includes a factorization permutation of one of the subgroups and / or a computation sequence in which the matrices are multiplied. [11] Non-volatile machine-readable storage medium according to claim 9, wherein the instructions cause the programmable circuit arrangement to train a machine learning model using at least the initial tiling state of one or more subsets of the identified matrices. [12] Non-volatile machine-readable storage medium according to claim 11, wherein the instructions cause the programmable circuit arrangement to retrain the machine learning model using the transformed tiling state and the calculated tiling state latency. [13] Non-volatile machine-readable storage medium according to claim 12, wherein the instructions cause the programmable circuit arrangement to update the initial tiling state based on the newly trained machine learning model. [14] Non-volatile machine-readable storage medium according to claim 9, wherein the instructions cause the programmable circuit arrangement to update a factorization permutation of one of the subgroups based on a trained machine learning model. [15] Non-volatile machine-readable storage medium according to claim 9, wherein the instructions cause the programmable circuit arrangement to update a computation sequence in which the matrices are multiplied, based on a trained machine learning model. [16] Non-volatile machine-readable storage medium according to claim 9, wherein the subgroups include a number of groups and / or a block size and / or a number of blocks in each group. [17] Institution comprising the following: Means for detecting matrices that are to be multiplied; Means for initializing a tiling state, wherein the means for initializing are designed to: Dividing the matrices into subgroups; and Determining an initial tiling state based on the subgroups; Means for determining an action to be performed on the matrices; Means of transforming the initial tiling state by performing the action on the matrices; Means for calculating a tiling state latency based on the execution of the action on the matrices; and Means of updating the initial tiling state based on the transformed tiling state or the calculated tiling state latency. [18] Device according to claim 17, wherein the means for initialization are further configured to generate an initial action strategy using the initial tiling state, wherein the initial action strategy includes a factorization permutation of one of the subgroups and / or a computation sequence in which the matrices are multiplied. [19] Device according to claim 17, further comprising means for training a machine learning model using at least the initial tiling state of one or more subgroups of the detected matrices. [20] Device according to claim 19, wherein the training means are designed to retrain the machine learning model using the transformed tiling state and the calculated tiling state latency. [21] Device according to claim 20, wherein the initializing means is designed to update the initial tiling state based on the newly trained machine learning model. [22] Device according to claim 17, further comprising means for updating a factorization permutation of one of the subgroups based on a trained machine learning model. [23] Device according to claim 17, further comprising means for updating a computation sequence in which the matrices are multiplied, based on a trained machine learning model. [24] Device according to claim 17, wherein the subgroups include a number of groups and / or a block size and / or a number of blocks in each group. [25] Method comprising the following: Identifying matrices to be multiplied; Dividing the matrices into subgroups; and Determining an initial tiling state based on the subgroups; Determine an action to be performed on the matrices; Transforming the initial tiling state by performing the action on the matrices; Calculating a tiling state latency based on executing the action on the matrices; and Updating the initial tiling state based on the transformed tiling state or the calculated tiling state latency.

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