COMMUNICATION DEVICE, COMMUNICATION METHOD AND IMAGE SENSOR

Abstract

The circuit includes a plurality of signal processing units, each of which outputs a clock signal and output data based on input data and synchronized with the clock signal to a corresponding track from among the plurality of tracks. A first circuit, acting on a reference track selection signal to choose a reference track from the plurality of tracks, selects an output clock signal corresponding to the reference track from among the output clock signals output by each of the plurality of signal processing units and outputs this signal to each of the plurality of signal processing units. Each of the plurality of signal processing units then compares and outputs the clock signal and output data based either on a reference clock signal or on the clock signal output by another signal processing unit from among the plurality of signal processing units.

Description

Area

[0001] The present disclosure relates to a communication device, a communication method and an image sensor. background

[0002] As image sensor quality and frame rate have increased in recent years, a high-speed technology for reading the data captured by the image sensor has been required. For example, a high-speed technology for reading image data by serially and parallelally transmitting a large number of image data points has been proposed. Patent literature 1 discloses a technology for adjusting the synchronization of serially and parallel-transmitted image data. List of quotations Patent literature

[0003] Patent literature 1: Japanese patent application disclosure number 2019-036833 Overview Technical Problem

[0004] However, patent literature 1 shows a configuration in which a synchronization code is added in units of frames on a sending side and parallel tracks are compared and synchronized on a receiving side, and switching from standby operation to normal operation is not easy, resulting in a reduction in the transmission efficiency of the image data.

[0005] The subject of the present disclosure is to provide a communication device, a communication method and an image sensor that are capable of efficiently transmitting data by using a multitude of tracks. Solution to the problem

[0006] To solve the problem described above, a communication device according to one aspect of the present disclosure has a plurality of signal processing units, each of which outputs a clock signal and output data based on the input data and synchronized with the clock signal to a corresponding track from a plurality of tracks;and a first circuit which, according to a reference track selection signal in order to select a reference track from the plurality of tracks, selects an output clock signal corresponding to the reference track from among the output clock signals each output by the plurality of signal processing units, and performs an output thereof to each of the plurality of signal processing units, each of the plurality of signal processing units aligning and outputting the output clock signal and output data on the basis of either a reference clock signal or the output clock signal output by another signal processing unit among the plurality of signal processing units. Brief description of the drawings Fig. Figure 1 is a schematic representation describing a data transmission using a multitude of tracks according to an existing technology. Fig. Figure 2 is a schematic representation to describe a factor that reduces the transmission efficiency of image data during data transmission using the multitude of tracks according to existing technology. Fig. Figure 3 is a schematic diagram describing an image transmission using a plurality of tracks according to the present disclosure. Fig. Figure 4 is a block diagram that represents an exemplary configuration of an electronic device applicable to each embodiment. Fig. Figure 5 is a block diagram that represents an exemplary configuration of an image sensor applicable to a first embodiment. Fig. Figure 6 is a block diagram showing an exemplary configuration of a transmission data processing circuit according to the first embodiment. Fig. Figure 7 is a block diagram that represents an exemplary configuration of a synchronization circuit applicable to the first embodiment. Fig. Figure 8 is a block diagram showing an exemplary configuration of a clock synchronization circuit applicable to the first embodiment. Fig. Figure 9 is a block diagram that represents an exemplary configuration of a data matching circuit applicable to the first embodiment. Fig. Figure 10 is a schematic diagram that represents an exemplary data structure of the data applicable to the first embodiment. Fig. Figure 11 is a block diagram representing an exemplary configuration of an image processing unit applicable to the first embodiment. Fig. Figure 12 is a timing diagram illustrating an exemplary processing operation in a transmission data processing circuit according to the first embodiment. Fig. Figure 13 is a flowchart illustrating an exemplary processing operation in the transmission data processing circuit according to the first embodiment. Fig. Figure 14A is a schematic diagram that represents the flow of a signal during the processing of the flowchart according to the first embodiment. Fig. Figure 14B is a schematic diagram that represents the flow of a signal during the processing of the flowchart according to the first embodiment. Fig. Figure 15 is a timing diagram of an example illustrating the transfer processing according to the first embodiment. Fig. Figure 16 is a timing diagram of an example illustrating the receiving process according to the first embodiment. Fig. Figure 17A is a schematic representation that shows an example of a simulation result of the processing according to the first embodiment. Fig. Figure 17B is a schematic diagram that presents an example of the simulation result of the processing according to the first embodiment. Fig. Figure 17C is a schematic diagram that presents an example of the simulation result of the processing according to the first embodiment. Fig. Figure 18 is a schematic representation describing the noise mixing in the case where a new track in the embodiment according to the first embodiment is switched into a communication state. Fig. Figure 19 is a schematic diagram describing the noise mixing in the case where the new track in the embodiment according to the first embodiment is switched to the communication state. Fig. Figure 20A is a block diagram illustrating an exemplary configuration of an image sensor according to a second embodiment. Fig. Figure 20B is a block diagram illustrating an exemplary configuration of a transmission data processing circuit according to the second embodiment. Fig. Figure 21 is a time diagram for an example to describe an operation according to the second embodiment. Fig. Figure 22 is a block diagram that illustrates, in particular, the exemplary configuration of the image sensor according to the second embodiment. Fig. Figure 23 is a circuit diagram that represents an exemplary circuit of a transmission control circuit applicable to the second embodiment. Fig. Figure 24 is a circuit diagram that represents an exemplary circuit of a slow current superposition circuit applicable to the second embodiment. Fig. Figure 25 is a circuit diagram illustrating the exemplary circuit of the slow current superposition circuit applicable to the second embodiment. Fig. Figure 26 is a time diagram to describe an operation according to the second embodiment. Fig. Figure 27 is a schematic representation that provides an example of the simulation of an operation by an embodiment according to the second embodiment. Description of the embodiments

[0007] The following section describes embodiments of the present disclosure in detail with reference to the drawings. Note that in the following embodiments, overlaps are eliminated by assigning the same reference numeral to the same parts.

[0008] The embodiments of the present disclosure are described below in the following order. 1. Existing technology 2. First embodiment of the present disclosure 2-1. Technology applicable to the first embodiment 2-2. Configuration according to the first embodiment 2-3. Processing according to the first embodiment 3. Second embodiment of the present disclosure 3-1. Problem of the first embodiment 3-2. Outline of the second embodiment 3-3. Specific example of the second embodiment 3-3-1. Configuration example according to the second embodiment 3-3-2. Operational example according to the second embodiment 4. Conclusion

[0009] The present disclosure relates to a communication device for carrying out data transmissions and has the configuration such that it outputs input image data to a transmission circuit which, after performing the synchronization of clocks and data for the plurality of tracks, carries out a data transmission for each of the tracks. The communication device according to the present disclosure is particularly suitable for use in the transmission of image data. (1. Existing technology)

[0010] Before describing the individual embodiments of the present disclosure, an existing technology related to a technology of the present disclosure will be described.

[0011] Fig. Figure 1 is a schematic representation describing data transmission using multiple tracks according to an existing technology. An example where multiple image data (video data) are transmitted in parallel using three tracks (Track #1, Track #2, and Track #3) is shown in Figure 1. Fig. Figure 1 illustrates a state in which image data is sequentially transferred to track #2 and track #3 with track #1 as the reference track. Fig. 1 shown.

[0012] With existing technology, image data is generally transmitted in units of frames, and the image data is transmitted with a predetermined synchronization code that is added to the header of each frame on a transmission page. In the example of Fig. 1, a transmission of the image data of track #2 is started synchronously with a transmission of the image data of an Nth frame of track #1, and a transmission of the image data of track #3 is started synchronously with a transmission of the image data of an (N+1)th frame of track #1.

[0013] Incidentally, in recent years a device with an image sensor capable of recording video at so-called 4K resolution (approximately 4000 horizontal pixels × 2000 vertical pixels) and a frame rate of 60 frames per second (fps) has appeared in the field of portable information devices such as smartphones. In this case, with a bit depth of 16 bits per pixel, the transmission rate of the image data read by the image sensor is approximately 8 gigabits per second (Gbps).

[0014] Furthermore, a device for information was proposed that is equipped with an image sensor capable of recording higher-resolution and higher-frame-rate videos, e.g., with so-called 8K resolution (approximately 8000 horizontal pixels × 4000 vertical pixels) and a frame rate of 120 fps. In this case, if the bit depth of a pixel is 16 bits, the transmission rate of the image data read by the image sensor is approximately 60 Gbit / s.

[0015] As image quality and frame rates have increased in recent years, a high-speed technology for reading the data captured by the image sensor has been needed. For example, a high-speed image data reading technology has been proposed that involves serially and parallel transmission of a large number of image data points.

[0016] While this increases the transmission rate, the speed increase must also be controlled from the perspective of power consumption and design difficulties.

[0017] Fig. Figure 2 is a schematic diagram describing a factor that reduces the transmission efficiency of image data in a data transmission that uses a large number of tracks according to an existing technology that is in Fig. 1 is shown. In an example of Fig. 2, where a synchronization code is added to each frame and the image data is transmitted according to an IDLE code. Note that the IDLE code is used when no valid data to be transmitted is output by an image sensor.

[0018] A first factor that reduces the efficiency of image data transmission is that any given track cannot be switched from a standby state to a communication state during image data transmission. That is, as indicated by an “× (cross)” sign in a section (a) of Fig. 2. In a case where the state of track #2 is switched from the ready state to the communication state during the transmission of image data in track #1, track #1 and track #2 cannot be synchronized by a synchronization code.

[0019] A second factor that reduces the efficiency of image data transmission is that the standby state can only be switched to the communication state in units of frames. That is, in a section (b) of Fig. 2, in track 2, the switch from standby state to communication state must be performed at a point indicated by an “× (cross)” sign.

[0020] As described above, with existing technology it is difficult to increase the speed of data transmission, since the image data is transmitted in units of frames using the synchronization code.

[0021] Furthermore, as described in patent literature 1 above, since the synchronization setting is performed in units of frames, it is difficult to track switching between telephoto, wide-angle, and similar features of a moving image in a multi-functional smartphone, and it is not suitable for data compression, i.e., increasing speed. Moreover, patent literature 1 requires a circuit that compares synchronization codes between tracks, increasing the number of components due to a large mounting area, increasing power consumption due to the large number of adjustment steps between transmit and receive processing, and miniaturization and energy savings are difficult. (Image transmission using a multitude of traces according to the present disclosure)

[0022] Fig. Figure 3 is a schematic diagram describing an image transmission using a plurality of tracks according to the present disclosure. In the present disclosure, as in Fig. As shown in Figure 3, data transmission can be started from standby mode over any of tracks #1 to #3 without using a synchronization code.

[0023] As described above, by transmitting image data in each track without using the synchronization code, it is possible to increase the image data period compared to a case where the synchronization code is used, and it is possible to control a significant data transfer rate in this case, thereby increasing the transmission speed. Furthermore, the image data can be transmitted not only in frames but also in arbitrary units. (2nd embodiment of the present disclosure)

[0024] The first embodiment of the present disclosure is described below. (2-1. Technology applicable to the first embodiment)

[0025] First, a technology applicable to the first embodiment is described. Fig. Figure 4 is a block diagram that represents an exemplary configuration of an electronic device applicable to each embodiment. Fig. 4 comprises an electronic device 1000, an optical system 1002, a control unit 1003, an image sensor 1004, an image processing unit 1005, a memory 1006, a storage unit 1007, a display unit 1008, an interface unit (I / F) 1009 and an input device 1012.

[0026] Here, a digital camera, a digital video camera, a mobile phone or a smartphone with an imaging function, or the like, can be used as an electronic device 1000. Furthermore, a surveillance camera, an onboard camera, a medical camera, or the like can also be used as an electronic device 1000.

[0027] The 1004 image sensor, for example, features a multitude of photoelectric conversion elements arranged in a matrix array. Each of these photoelectric conversion elements converts received light into an electrical charge through photoelectric conversion. The 1004 image sensor includes a drive circuit that controls the multitude of photoelectric conversion elements, a signal processing circuit that reads the electrical charge from each of the photoelectric conversion elements and generates image data based on this reading, and a power supply circuit that provides power to the drive circuit.

[0028] The optical system 1002 comprises a main lens, formed by a combination of one or more lenses and a mechanism for controlling the main lens, and forms an image from image light (incident light) of an object onto a light-receiving surface of the image sensor 1004 via the main lens. Furthermore, the optical system 1002 includes an autofocus mechanism that adjusts the focus according to a control signal and a zoom mechanism that changes the zoom factor according to the control signal. Additionally, the optical system 1002 in the electronic device 1000 is removable and can be replaced by another optical system 1002.

[0029] The image processing unit 1005 processes the pixel data output by the image sensor 1004. For example, the image processing unit 1005 is connected to a memory 1006, such as a frame memory, and writes the image data output by the image sensor 1004 to the memory 1006. The image processing unit 1005 performs predefined image processing on the pixel data written to the memory 1006 and writes the processed pixel data back to the memory 1006. Note that the memory 1006 can store the pixel data for a frame as image data.

[0030] The storage unit 1007, for example, is non-volatile memory such as flash memory or a hard disk drive and stores the image data output by the image processing unit 1005 in non-volatile form. The display unit 1008 includes, for example, a display device such as a liquid crystal display (LCD) and a control circuit that controls the device and can display an image based on the data output by the image processing unit 1005. The interface unit 1009 is an interface through which the image data output by the image processing unit 1005 is transmitted externally. For example, a universal serial bus (USB) can be used as the interface unit 1009. The above descriptions do not constitute a limitation, and the interface 1009 can be connected to a network via wired or wireless communication.

[0031] The input device 1012 includes an operator for receiving user input. If the electronic device 1000 is, for example, a digital camera, a digital video camera, or a mobile phone or smartphone with an imaging function, the input device 1012 can have a release button to instruct the image sensor 1004 to initiate imaging or to instruct an operator to perform the function of the release button.

[0032] The control unit 1003, for example, contains a processor such as a central processing unit (CPU), a read-only memory (ROM), and a random-access memory (RAM), and controls the entire operation of the electronic device 1000 by using the RAM as working memory according to a program stored in the ROM. For example, the control unit 1003 can control the operation of the electronic device 1000 according to user input received from the input device 1012. Furthermore, the control unit 1003 can control the autofocus mechanism in the optical system 1002 based on an image processing result from the image processing unit 1005. (2-2. Configuration according to the first embodiment)

[0033] Fig. Figure 5 is a block diagram illustrating an exemplary configuration of the image sensor 1004 applicable to a first embodiment.

[0034] In Fig. 5 the image sensor 1004 contains an image acquisition unit 10, a data transmission processing circuit 20, a transmission unit 30, an oscillator 40, a synchronization signal generation unit 50, a phase control loop (PLL) 60 and a clock generator (TG) 70.

[0035] The image acquisition unit 10 comprises a pixel unit 11, an A / D conversion unit 12, and a logic circuit 13. The pixel unit 11 includes a pixel array in which pixels, which output electrical signals according to the incident light by photoelectric conversion, are arranged in a grid, as well as a vertical scanning circuit and a horizontal scanning circuit that drive the pixels of the pixel array. The pixel unit 11 outputs an analog signal as an image signal, the image signal being based on an electrical signal output by each pixel according to the incident light.

[0036] A pixel signal output by the pixel unit 11 is converted into a digital pixel signal by the A / D conversion unit 12. The digital pixel signal, which is converted from the pixel signal by the A / D conversion unit 12, is fed to the logic circuit 13.

[0037] Logic circuit 13 performs a predefined code conversion of the supplied digital pixel signal and generates pixel data. Furthermore, logic circuit 13 adds predefined information to the pixel data in units of frames and generates image data in units of frames. It should be noted that each of the frames contains, for example, pixel data from pixels in an effective pixel area within the pixel matrix of pixel unit 11. Logic circuit 13 delivers the generated image data in units of frames to the transmission data processing circuit 20.

[0038] Furthermore, a control signal from a higher-level configuration, such as the control unit 1003, is supplied to the logic circuit 13. Based on the control signal, a PLL clock signal supplied by the PLL 60 (described later), and the digital pixel signal supplied by the A / D conversion unit 12, the logic circuit 13 generates a transmission control signal relating to the transmission of the image data.

[0039] For example, the control signal supplied by the higher-level configuration can contain a track selection signal to select a reference track from a multitude of tracks to which the image data is transferred in parallel. Furthermore, the control signal can also contain a transfer start instruction signal that signals the start of a data transfer to the designated track. Logic circuit 13 generates a transfer control signal that includes the track selection signal and the transfer start instruction signal. Logic circuit 13 supplies the generated transfer control signal to the TG 70.

[0040] It should be noted that, in response to the instruction to start data transmission, logic circuit 13 generates alignment data that indicates the start of the data transmission and adds this alignment data to a header of the image data to be transmitted. Logic circuit 13 then delivers the image data, to which the alignment data has been added, to the transmission data processing circuit 20. Details of the alignment data are described later.

[0041] In Fig. Oscillator 40 generates a reference clock signal, which serves as a reference for an operation of the image sensor 1004. This reference clock signal is supplied to the synchronization signal generation unit 50, the PLL 60, and the TG 70. The synchronization signal generation unit 50 generates a horizontal synchronization signal and a vertical synchronization signal to control the pixel array in the pixel unit 11 based on this reference clock. The synchronization signal generation unit 50 then supplies the generated horizontal synchronization signal and the vertical synchronization signal to the TG 70.

[0042] The PLL 60 performs phase synchronization processing based on the reference clock signal supplied by the oscillator 40 and generates a PLL clock signal. The PLL 60 supplies the generated PLL clock signal to the logic circuit 13 and the transfer data processing circuit 20.

[0043] The TG 70 supplies the horizontal synchronization signal and the vertical synchronization signal received from the synchronization signal generation unit 50 to the pixel unit 11. The pixel unit 11 controls each pixel of the pixel matrix unit by means of the horizontal scanning circuit and the vertical scanning circuit on the basis of the horizontal synchronization signal and the vertical synchronization signal.

[0044] The TG 70 generates a reference track selection signal and an alignment signal based on the reference clock signal supplied by the oscillator 40 and the transmission control signal supplied by the logic circuit 13. The TG 70 delivers the generated reference track selection signal and the alignment signal to the transmission data processing circuit 20.

[0045] For example, the TG 70 generates the reference track selection signal based on the track selection signal contained in the transmission control signal in order to select a reference track from a multitude of tracks in order to first perform the transmission of data.

[0046] For example, the reference track selection signal can be a signal with a bit length corresponding to the number of tracks, and it can be a 3-bit signal where each bit specifies a track if the number of tracks is three. For example, in the reference track selection signal, a first bit from the least significant bit (LSB) can specify track #1, a second bit track #2, a third bit track #3, and it can be specified that a track is the reference track if one value of the bit is "1".

[0047] For example, the TG 70 generates the alignment signal, which serves as the trigger for the start of synchronization on the selected track, based on the transmission start instruction signal contained in the transmission control signal and the track selection signal described above. The alignment signal can be, for example, a signal whose state changes at the time data transmission begins on the designated track, and in particular, it can be a signal whose value changes from a low state to a high state, or from "0" to "1", at the time of start.

[0048] Similar to the reference track selection signal described above, the alignment signal can be a signal with a bit length corresponding to the number of tracks, and it can be a 3-bit signal where each bit specifies a track if the number of tracks is three. The alignment signal is not limited to the above and can be a signal provided for each track. Hereinafter, the alignment signals corresponding to tracks #1, #2, and #3 are referred to as alignment signals #1, #2, and #3.

[0049] The transmission data processing circuit 20 outputs output data and a clock signal based on the image data supplied by the logic circuit 13. The clock signal is based on the PLL clock signal supplied by the PLL 60, with the output data and the clock signal corresponding to each of the plurality of tracks, corresponding to the number of tracks on which the transmission unit 30 performs the data transmission. In the example of Fig. The data processing circuit 20 outputs the data and clock signal corresponding to each of the three tracks #1, #2, and #3. The number of tracks from which the data processing circuit 20 outputs the data and clock signal is not limited to 3 and can, for example, be two tracks of tracks #1 and #2, or four or more tracks.

[0050] Unless otherwise specified, in the following, a signal corresponding to any track will be referred to as a signal of the track.

[0051] The transmission unit 30 contains a plurality of parallel-to-serial conversion circuits (labeled P / S in the drawing), each corresponding to a plurality of tracks, and a plurality of transmission circuits (labeled Tx in the drawing). In the example of Fig. 5, the transmission unit contains 30 parallel-to-serial conversion circuits 311, 312 and 313 as well as transmission circuits 321, 322 and 323, each containing the correspondence to tracks #1, #2 and #3.

[0052] For example, the parallel-to-serial conversion circuit 311 is supplied by the transmission data processing circuit 20 with a clock signal (first clock signal) and output data from track #1 (first output data), which is output as a parallel signal. Based on the first clock signal, the parallel-to-serial conversion circuit 311 converts the first output data into a serial signal and supplies the serial signal to the transmission circuit 321. Based on the signal supplied by the parallel-to-serial conversion circuit 311, the transmission circuit 321 generates transmission data and transmits the generated data to track #1.

[0053] The same applies to the parallel-to-serial conversion circuits 312 and 313 and the transmission circuits 322 and 323. That is, the parallel-to-serial conversion circuits 312 and 313 convert the second and third output data supplied by the transmission data processing circuit 20 into serial signals based on the second and third clock signals, respectively, and supply these serial signals to the transmission circuits 322 and 323. The transmission circuits 322 and 323 each generate transmission data based on the signals supplied by the parallel-to-serial conversion circuits 312 and 313 and transmit the generated transmission data to tracks #2 and #3.

[0054] Fig. Figure 6 is a block diagram showing an exemplary configuration of the transmission data processing circuit 20 according to the first embodiment.

[0055] In Fig. 6, the transmission data processing circuit 20 contains the signal processing circuits 211, 212 and 213, the number of which corresponds to the number of tracks (three in the example of Fig. 6), and a selector 204.

[0056] The image data to be transmitted is input into each of the signal processing circuits 211, 212, and 213. Additionally, a reference track selection signal #1 and the alignment signal #1 are input into signal processing circuit 211, and signal processing circuit 211 outputs the first clock signal and the first output data according to the input image data. Similarly, reference track selection signals #2 and #3 and the alignment signals #2 and #3 are input into signal processing circuits 212 and 213, and the second clock signal and the second output data, as well as the third clock signal and the third output data, are output, respectively.

[0057] The selector 204 selects one of the first, second and third clock signals supplied by the signal processing circuits 211, 212 and 213 according to the reference signals for selecting track #1, #2 and #3 supplied by the TG 70 according to each of the tracks, and supplies the selected clock signal to each of the signal processing circuits 211, 212 and 213.

[0058] The signal processing circuits 211, 212 and 213 include selectors 2001, 2002 and 2003, synchronization circuits 2011, 2012 and 2013, clock synchronization circuits 2021, 2022 and 2023 and data synchronization circuits 2031, 2032 and 2033.

[0059] Since the signal processing circuits 211 to 213 have a common configuration, the signal processing circuit 211 is described here as an example.

[0060] In Selector 2001, a clock signal selected by Selector 204 from the first to third clock signals is fed into a first input port, and the PLL clock signal is fed into a second input port. Selector 2001 then selects either the first or second input port according to the value of the reference signal supplied by TG 70 for selecting track #1. For example, Selector 2001 selects the first input port if the value of the first bit of the reference track selection signal is "1", and selects the second input port if the value is "0".

[0061] Selector 2001 outputs the clock signal selected from the clock signals input to the first and second input terminals as synchronization clock signal #1 and supplies this signal to synchronization circuit 2011. The adjustment signal #1 is also input to synchronization circuit 2011. Synchronization circuit 2011 outputs the input adjustment signal #1 in synchronization with the clock signal supplied by selector 2001.

[0062] Fig. Figure 7 is a block diagram illustrating an exemplary configuration of the synchronization circuit 2011 applicable to the first embodiment. As shown, the synchronization circuit 2011 can incorporate a plurality of flip-flop (FF) circuits 2101, 2102, ... and 210 connected in series. nInclude a synchronization clock #1 supplied by selector 2001, which is fed into a clock input terminal of each of the flip-flop circuits 2101, 2102, ... and 210. n entered.

[0063] The calibration signal #1 is input into a data input terminal D of the FF circuit 2101, which is located at the head of the FF circuits 2101, 2102, ... and 210. n The synchronization signal #1, synchronized by the synchronization clock #1, is output from a data output terminal Q. An output of flip-flop circuit 2101 is fed into a data input terminal D of flip-flop circuit 2102 in the next stage. Subsequently, the outputs of the respective flip-flop circuits are transmitted sequentially, and in the last stage, the output of flip-flop circuit 210 is output. n A matched signal #1 was output.

[0064] In the synchronization circuits from 2011 to 201 n The number of stages of the FF circuits will be 2101 to 210 npreferably determined taking into account the number of stages in which no metastable state is generated.

[0065] Back to the description of Fig. 6. The synchronized signal #1, output by the synchronization circuit 2011, is fed into the clock synchronization circuit 2021. The clock synchronization circuit 2021 also receives the PLL clock signal.

[0066] The clock synchronization circuit 2021 sets the validity and invalidity of the PLL clock signal according to the synchronized signal #1. Fig. Figure 8 is a block diagram illustrating an exemplary configuration of the clock synchronization circuit 2021 applicable to the first embodiment. As shown, the clock synchronization circuit 2021 includes an AND gate 220 and a frequency divider 221.

[0067] In the AND gate 220, the matched signal #1 is input to a first input terminal and the PLL clock signal to a second input terminal. As described above, the matched signal #1 is a signal detected by synchronizing the matching signal #1, whose state changes with the synchronization clock #1 at the start of data transmission on track #1, and whose value changes, for example, from "0" to "1" according to the passage of time. The PLL clock signal, which is input to the AND gate 220, is validated in a period during which the matched signal #1 has the value "1" and is output by the AND gate 220.

[0068] The PLL clock signal output by the AND circuit 220 is divided in the frequency divider 221 with a predetermined frequency division ratio and output as the first clock signal.

[0069] Back to the description of Fig. 6 The first clock signal issued by the clock synchronization circuit 2021 is supplied by the transmission data processing circuit 20 to the transmission unit 30 and also to the data synchronization circuit 2031 and the selector 204.

[0070] The data matching circuit 2031 receives an input of image data, synchronizes the input image data with the first clock signal and outputs the image data as the first output data. Fig. Figure 9 is a block diagram illustrating an exemplary configuration of the data synchronization circuit 2031 applicable to the first embodiment. As shown, the data synchronization circuit 2031 includes a flip-flop circuit 230.

[0071] In the flip-flop circuit 230, the image data is input to a data input port D and the first clock signal to a clock input port. The flip-flop circuit 230 synchronizes the image data input to data input port D with the first clock signal input to the clock input port and outputs the image data as the first output data. The first output data is forwarded by the transmission data processing circuit 20 to the transmission unit 30.

[0072] Fig. Figure 10 is a schematic diagram representing an exemplary data structure of the data applicable to the first embodiment. Fig. 10. The output data has a structure in which, for example, the matching data is arranged as identification information at the head of the image data. The matching data only needs to be a unique pattern, and the bit width and the number of symbols can be arbitrarily determined. As described above, the matching data is generated and added to the logic circuit 13 according to the instruction to start the data transmission. Furthermore, the image data can, for example, consist of data in which identification information for a frame is arranged to identify a frame, or identification information for a line is arranged to identify each line at a predefined position relative to a data chain of pixel data.

[0073] It should be noted that selectors 2002 and 2003, synchronization circuits 2012 and 2013, clock synchronization circuits 2022 and 2023, and data synchronization circuits 2032 and 2033 each have a similar configuration to selector 2001, synchronization circuit 2011, clock synchronization circuit 2021, and data synchronization circuit 2031 described above, and therefore their description is omitted here.

[0074] As described above, each of the signal processing circuits 211, 212, and 213, according to the first embodiment, functions as a signal processing unit that outputs the output clock signal and the input data-based output data synchronized with the output clock signal to the corresponding track of the plurality of tracks. Furthermore, the selector 204 functions as a first selection circuit that selects an output clock signal corresponding to the reference track from among the output clock signals output by each of the plurality of signal processing units, according to the reference track selection signal from the plurality of tracks, and outputs the selected output clock signal to each of the plurality of signal processing units.

[0075] Fig. Figure 11 is a block diagram illustrating an exemplary configuration of the image processing unit 1005 applicable to the first embodiment. Fig. 11, the image processing unit 1005 contains a receiver unit 80, a receive data processing circuit 90 and an image processing circuit 1050.

[0076] The receiver unit 80 contains a receiving circuit (labeled Rx in the drawing), corresponding to each of the multiple tracks, and a multiple of serial-to-parallel conversion circuits (labeled S / P in the drawing). In the example of Fig. 11 contains the receiving unit 80 receiving circuits 811, 812 and 813 as well as serial-to-parallel conversion circuits 821, 822 and 823, each corresponding to tracks #1, #2 and #3.

[0077] For example, the receiving circuit 811 identifies the alignment data from the data received from track #1, recognizes the header of the image data, and extracts the image data. The image data extracted by the receiving circuit 811 is converted into image data of a parallel signal by the serial-to-parallel conversion circuit 821 and fed to the receiving data processing circuit 90.

[0078] The same applies to the receiving circuits 812 and 813 and the serial-to-parallel conversion circuits 822 and 823. That is, the receiving circuits 812 and 813 identify the alignment data from the signals received by tracks #2 and #3, recognize the header of the image data, and extract the image data. The receiving circuits 812 and 813 supply the extracted image data to the serial-to-parallel conversion circuits 822 and 823, respectively. Each of the serial-to-parallel conversion circuits 822 and 823 converts the supplied image data into a parallel signal and supplies the parallel signal to the receiving data processing circuit 90.

[0079] The receive data processing circuit 90 performs predetermined processing of the image data from each of tracks #1, #2, and #3 supplied by the receive unit 80 and delivers the processed image data to the image processing circuit 1050. For example, the receive data processing circuit 90 can reconstruct a frame image based on the supplied image data. The image processing circuit 1050 can be, for example, a digital signal processor (DSP) that performs predetermined image processing on the supplied data and provides a corresponding output. (2-3. Processing according to the first embodiment)

[0080] The processing according to the first embodiment is described in more detail below.

[0081] Fig. Figure 12 is a timing diagram illustrating an exemplary processing operation in the transmission data processing circuit 20 according to the first embodiment. Furthermore, Fig. 13 a flowchart illustrating an exemplary processing operation in the transmission data processing circuit 20 according to the first embodiment. Furthermore, Fig. 14A and Fig. 14B schematic diagrams showing the signaling flows in step S1 and step S2 of the flowchart in Fig. 13 illustrate.

[0082] Note that Fig. 12 and Fig. 13 as well Fig. 14A and Fig. Figure 14B presents an example of a case in which track #1 is selected as the reference point and the image data is transferred, and then the transfer of the image data to track #2 is started.

[0083] In Fig. Figure 12, for example, illustrates in its upper part an example of the reference track selection signal supplied by the TG 70 to the transmission data processing circuit 20, in accordance with the control signal from the higher-level configuration (such as the control unit 1003) of the image sensor 1004, the alignment signals #1, #2, and #3, and the image data transmitted by the image sensor 1004 to tracks #1, #2, and #3. Note that the alignment data located in the header of the image data is omitted here.

[0084] In the example of Fig. 12 is the reference track selection signal, a 3-bit signal where the bits correspond to tracks #1, #2, and #3, and the value of each of the 3 bits is "0" in its initial state. In its initial state, the second terminal is selected in each of selectors 2001, 2002, and 2003, and the PLL clock signal is input into each of the synchronization circuits 2011, 2012, and 2013 via selectors 2001, 2002, and 2003, respectively.

[0085] In this case, up to and including time t 10 The synchronization signals #1, #2, and #3 are set to the value "0" (low state), and accordingly, the synchronized signals #1, #2, and #3 are also set to the value "0" (low state). Therefore, the first clock signal, the second clock signal, and the third clock signal are not output in the clock synchronization circuits 2021, 2022, and 2023, respectively. Up to time points t 10 , t 11 and t 12, to which the values ​​of the adjustment signals #1, #2 and #3 become “1” (high state), track #1, track #2 and track #3 are in the ready state.

[0086] At time t 10 , t 11 and t 12 In tracks #1, #2, and #3, the values ​​of the corresponding synchronization signals #1, #2, and #3 are set to "1" (high state), and accordingly, the synchronized signals #1, #2, and #3 are set to the value "1". The first, second, and third clock signals are each output by the clock synchronization circuits 2021, 2022, and 2023 in response to the moment the value of each of the synchronized signals #1, #2, and #3 becomes "1". The output of the image data on tracks #1, #2, and #3 is then initiated.

[0087] In Fig. 12, in the lower part, are the PLL clock signal, the reference track selection signal, the alignment signal #1, the first clock signal, a first data input, a first data output, a second clock input of the synchronization circuit, the aligned signal #2, the second clock signal, a second data input and a second data output shown from above.

[0088] The first and second data inputs indicate that data is being fed into signal processing circuits 211 and 212 (data matching circuits 2031 and 2032). Additionally, the second clock input of the synchronization circuit specifies a synchronization clock #2, which is fed into synchronization circuit 2012.

[0089] The processing in the transmission data processing circuit 20 is described with reference to the flowchart in Fig. 13 described. In the flowchart of Fig. 13, processing with respect to the reference track (track #1) is carried out in step S1, and processing with respect to track #2, where data transmission begins next to the reference track, is carried out in step S2.

[0090] First, the processing in step S1 is carried out with reference to Fig. 14A is described. For the signals used to select reference tracks #1, #2 and #3, the value of each bit in the initial state is "0" (low state).

[0091] In step S1, in the first step S10, the second input terminal in each of selectors 2001, 2002, and 2003 of the transfer data processing circuit 20 is selected according to the reference track selection signal #1, and the PLL clock signal is selected as each of the synchronization clocks #1, #2, and #3. Next, in step S11, the transfer data processing circuit 20 outputs the PLL clock signal via selector 2001 according to the selection by selector 2001 (P1 in Fig. 14A) as synchronization clock signal #1 into the synchronization circuit 2011.

[0092] Next, in step S12, for example at time t 10 , the state of the alignment signal #1 changes from the low state to the high state (or from the value "0" to "1"), and the alignment signal #1 is fed into the synchronization circuit 2011 (P2 in Fig. 14A). The transmission data processing circuit 20 causes the synchronization circuit 2011 to increase the alignment signal #1 at time t. 10 with the PLL clock signal at time t 20 to synchronize, and generates the matched signal #1 (not shown).

[0093] The data processing circuit 20 passes the generated, adjusted signal #1 to the clock synchronization circuit 2021. In step S13, the data processing circuit 20 validates the PLL clock signal according to signal #1, which was adjusted at the input by the clock synchronization circuit 2021, and outputs the first clock signal from time t. 20 from (P3 in Fig. 14A). The first clock signal is supplied to the transmission unit 30 as well as to the data synchronization circuit 2031 and to the selector 204.

[0094] In the next step S14, the transmission data processing circuit 20 synchronizes the image data entered via the first data input with the first clock signal of the data synchronization circuit 2031 and performs data synchronization processing on the image data (P4 in Fig. 14A). In the next step S15, the transmission data processing circuit 20 outputs the input image data as the first input data and synchronizes it with the first clock signal as the first output data by the data synchronization circuit 2031 (P5 in Fig. 14A).

[0095] The first initial data are collected at time t 20 adjusted, to which the rise of the adjusted signal #1 (not shown), which corresponds to the adjustment signal #1 at time t 10 This corresponds to being synchronized by the PLL clock signal.

[0096] Next, the processing in step S2 will be carried out with reference to Fig. 14B described.

[0097] In step S2, in the first step S20, the transmission data processing circuit 20 selects track #1 as the reference track according to the reference track selection signal #2 (P10 in Fig. 14B), the first input terminal in selector 2002 is selected, and the first clock signal is selected as synchronization clock #2. In step S21, the transfer data processing circuit 20 outputs the first clock signal as synchronization clock signal #2 via selector 2002 according to the selection by selector 2002 (P11 in Fig. 14B) to the synchronization circuit 2012.

[0098] In the next step S22, the transmission data processing circuit 20 outputs the adjustment signal #2, where the value of the adjustment signal #2 at time t 11 when changed from "0" to "1", the synchronization circuit 2012 is entered (P12 in Fig. 14B). The transmission data processing circuit 20 synchronizes a rise in the alignment signal #2 at time t 11The first clock signal passes through the synchronization circuit 2012 and generates the synchronized signal #2 (not shown). The transmission data processing circuit 20 forwards the generated synchronized signal #2 to the clock synchronization circuit 2022.

[0099] In step S23, the transmission data processing circuit 20 makes the PLL clock signal valid according to the adjusted signal #2 input by the clock synchronization circuit 2022 and outputs the second clock signal from time t. 21 from (P13 in Fig. 14B). The second clock signal is supplied to the transmission unit 30 as well as the data synchronization circuit 2032 and the selector 204.

[0100] In the next step S24, the transmission data processing circuit 20 synchronizes the image data entered via the second data input with the second clock signal of the data synchronization circuit 2032 and performs the processing of the image data for data synchronization (P14 in Fig. 14B). In the next step S25, the transmission data processing circuit 20 outputs the image data as the second output data, which is synchronized with the second clock signal by the data synchronization circuit 2032 (P15 in Fig. 14B).

[0101] The second set of initial data is collected at time t 21 adjusted, to which the increasing timing of the adjusted signal #2, which corresponds to the adjustment signal #2 (not shown) at time t 11 corresponds to being synchronized by the first clock signal.

[0102] Fig. Figure 15 is a timing diagram of an example illustrating the transfer processing according to the first embodiment.

[0103] In the example of Fig. 15 assumes that track #1 is selected as the reference track. Fig. 15 is a neighborhood of time t 11 in the upper part of Fig. 12 selected and depicted in an upper part, and one of the upper part of Fig. 15 corresponding section in the lower part of Fig. Number 12 is selected and shown in the lower part. The lower part of Fig. 15 partially corresponds to the lower part of Fig. 12, and the alignment signal #1, the first clock signal, the first output data, the second clock input of the synchronization circuit, the aligned signal #2, the second clock signal, a second data alignment input, and the second output data are shown from above. Furthermore, the second data alignment input specifies the aligned signal #2, which is input into the clock alignment circuit 2022.

[0104] Note that in Fig. 15 the alignment signal #1, the first clock signal and the first output data are, for the sake of description, located near time t 11 be displayed.

[0105] For example, circuit 321, corresponding to track #1, transmits as transmission data the first output data, which contains the image data and the alignment data that is at the head of the image data at time t. 20 are arranged according to the rise of the alignment signal #1 at time t 10 corresponds.

[0106] Similarly, circuit 322, corresponding to track #2, transmits the second output data, including the image data and the alignment data, as transmission data. This data is located at the head of the image data at time t. 21 are arranged, to which the signal #2 based on the matched signal #2 is at time t 11 (not shown) is adjusted by the first clock signal. In the example of Fig. 15. The alignment data has a length of three clock cycles each of the first clock signal and the second clock signal.

[0107] Fig. Figure 16 is a timing diagram of an example illustrating the receive processing according to the first embodiment. Fig. Figure 16 shows the first and second output data in the upper section, which are transmitted as transfer data from each of tracks #1, #2, and #3. As described above, the matching data is added as identification information to the header of each part of the output data transmitted as transfer data for each of tracks #1, #2, and #3.

[0108] In Fig. For the sake of description, the time of transfer of the comparison data in the first output data and the time of transfer of the comparison data in the second output data are shown in such a way that they are close to each other.

[0109] For example, the receiving circuit 811 receives the first output data, which is transmitted as transmission data from the transmitting unit 30 to track 1, and supplies the received first output data to the serial-to-parallel conversion circuit 821. The serial-to-parallel conversion circuit 821 converts the supplied first output data into a parallel signal and supplies the parallel signal to the receiving data processing circuit 90.

[0110] The same applies to tracks #2 and #3. That is, the receiving circuits 812 and 813 each receive the second and third output data, which are transmitted as transfer data from the transmitting unit 30 to tracks #2 and #3, and supply the received second and third output data to the serial-to-parallel conversion circuits 822 and 823, respectively. The serial-to-parallel conversion circuits 822 and 823 convert the supplied second and third output data into parallel signals and forward the parallel signals to the receiving data processing circuit 90.

[0111] The receive data processing circuit 90 identifies the alignment data from the first output data, supplied, for example, by the serial-to-parallel conversion circuit 821, and detects the image data header. The receive data processing circuit 90 extracts the image data from the received first output data based on the image data header detection result. Similarly, the receive data processing circuit 90 extracts the image data from the received second and third output data.

[0112] The receiving data processing circuit 90 can generate image data based on the frame identification information and the line identification information contained in the image data extracted from the individual output data. The frame data generated by the receiving data processing circuit 90 is forwarded to the image processing circuit 1050.

[0113] As described above, in the first embodiment, synchronization processing on the receiving side is not required because the data on the transmitting side (circuit for processing the transmitted data 20) is synchronized. Therefore, by applying the configuration according to the first embodiment, it is possible to eliminate processing and redundant data that hinder an increase in speed. Thus, the configuration according to the first embodiment is particularly suitable for use in an image sensor that needs to process a large amount of data at high speed. (Simulation result of the processing according to the first embodiment)

[0114] Next, a simulation result of the processing according to the first embodiment described above will be presented with reference to Fig. 17A, Fig. 17B and Fig. 17C described.

[0115] Note that an example simulating a waveform of each signal in a case where track #1 is set as the reference track and the single-track drive of track #1 is switched to a three-track drive of tracks #1 to #3 is shown in Fig. 17A, Fig. 17B and Fig. 17C is shown. More precisely, the left side of time t. 30 in Fig. 17A indicates a single-lane driving state where lane #1 is on and lanes #2 and #3 are off. On the other hand, a right-hand side of time t indicates 30 a state in which each of lanes #1 to #3 is switched on and the switch to three-lane driving is being performed.

[0116] In Fig. 17A shows the input image data, the reference track selection signal for three tracks, the PLL clock signal, a reference track frequency division clock, the alignment signal (alignment signal #1), an internal synchronization circuit signal, the synchronized alignment signal, the synchronized clock signal and the synchronized output data from above.

[0117] The alignment signal includes alignment signal #1, which is input according to track #1 and is an inverted signal in this example. Additionally, the synchronized alignment signals are those corresponding to tracks #2 and #3, which are synchronized with the first clock signal output in response to the aligned signal #1; that is, alignment signal #1 synchronized based on the PLL clock signal.

[0118] The synchronized clock signals indicate the input and output clock signals in the clock synchronization circuits 2021, 2022, and 2023. More precisely, the top three waveforms of the six synchronized clock signals indicate the outputs of the AND gates 220 in the clock synchronization circuits 2021, 2022, and 2023, respectively. That is, the waveforms in the second and third rows from the top indicate signals where the PLL clock signals input to the clock synchronization circuits 2022 and 2023 are synchronized by signals #2 and #3, which are balanced by the AND gates 220. Furthermore, the bottom three waveforms indicate the outputs of the frequency dividers 221 in the clock synchronization circuits 2021, 2022, and 2023, respectively.

[0119] The internal signal of the synchronization circuit, for example, gives an exemplary waveform of an output signal of each of the FF circuits 2101, 2102, ..., and 210. nwithin the synchronization circuit 2011. In the drawing, the parts that look like stages are outputs via the multi-stage FF circuits 210.

[0120] In Fig. In frame 17A, an internal signal of the synchronization circuit 2011 is moved by a change in the alignment signal #1, which is specified by a frame C as a trigger, and the synchronized alignment signal is generated. With this synchronized alignment signal as a trigger, the alignment of the second clock signal and the third clock signal is performed in a section specified by a frame D in Fig. 17A is indicated.

[0121] In Fig. 17B represents a state in which the frame D part of Fig. 17A is enlarged. In Fig. In Figure 17B, the top three waveforms show the alignment signal #1 and the synchronized alignment signals of tracks #2 and #3. Furthermore, the bottom three waveforms, as described above, show the outputs of the AND gates 220 in the clock alignment circuits 2021, 2022, and 2023, respectively. That is, the bottom three waveforms are the PLL clock signals, and the waveforms in the second and third rows are the PLL clock signals synchronized by the alignment signals of tracks #2 and #3.

[0122] The frequencies of the PLL clock signals of tracks #1, #2, and #3 are divided by the frequency dividers 221 in the clock synchronization circuits 2021, 2022, and 2023, and the first clock signal corresponding to track #1, the second clock signal corresponding to track #2, and the third clock signal corresponding to track #3 are generated. Fig. 17B shows that the clock edges of the start tracks for operations (track #2 and #3), on which operations are performed at time t 30 They are operated by being aligned to a clock edge of the reference track (track #1).

[0123] A state in which part of frame E is removed Fig. 17A is enlarged, is in Fig. 7C is shown. As in Fig. As shown in Figure 17C, each bit value corresponds to each of the operation start tracks (tracks #2 and #3) in which the operations took place at time t. 30 The operation is started by matching each bit value of the first output data of track #1, which is the reference track. That is, it can be seen that the data of the starting tracks of the operation are aligned with the data of the reference track through the data alignment processing in each of the data matching circuits 2032 and 2033. (3. Second embodiment of the present disclosure)

[0124] Next, the second embodiment of the present disclosure will be described. (3-1. Problem of the first embodiment)

[0125] In the first embodiment described above, the transmission unit 30, which performs the serial transmission, provides a synchronization signal in each output track, and the other tracks are synchronized based on the clock of the reference track. Thus, by applying the configuration developed in the first embodiment, it becomes possible to synchronize the serially transmitted data in parallel without using a synchronization code during data transmission and without providing a separate circuit for synchronization adjustment on the receiving side. This makes it possible to eliminate a process and redundant data that hinder speed increases, to transmit data efficiently by using a large number of tracks, and to process large amounts of data at high speed.

[0126] On the other hand, in the configuration of the first embodiment, in a case where a new track is added to a track that is already in the communication state, and the switch from the standby state to the communication state is performed, there is a possibility that the noise in the track that is first in the communication state will become mixed.

[0127] Fig. 18 and Fig. Figure 19 shows schematic diagrams describing the noise mixing in the case where a new track in the embodiment according to the first embodiment is switched into a communication state. In an example of Fig. 18 It is assumed that the transmission unit 30 corresponds to two tracks (track #1 and track #2) and includes the serial-to-parallel conversion circuits 311 and 312 and the transmission circuits 321 and 322.

[0128] In the transmission unit 30, a supply current from a power supply 33 is supplied to the parallel-to-serial conversion circuit 311 and the circuit 321 of the first track (track #1) via a power supply line with finite impedance 34. In addition, the current of the power supply 33 is tapped at the output of the impedance 34 and also supplied to the serial-to-parallel conversion circuit 312 and the transmission circuit 322 of the second track (track #2).

[0129] In this configuration, as described in section (a) of Fig. As shown in Figure 19, for example, a case is considered in which track #2 is switched from the standby state to the communication state while track #1 is in the communication state. In this case, a highly fluctuating current flows in the power supply line connected to the parallel-to-serial conversion circuit 312 and the transmission circuit 322, accompanied by a rapid voltage fluctuation at the time of switching. This transient, steeply changing current is transformed into a flutter 35 by the finite impedance 34 present in the power supply line (see Figure 19). Fig. 18) converted and then propagates as noise 36 via the power supply line to track #1, as described in section (b) of Fig. Figure 19 shows that the noise 36 can worsen the jitter of the communication signal in the serial-to-parallel conversion circuit 311 and the transmission circuit 321 and hinder an increase in the communication speed.

[0130] The deterioration of the communication signal jitter due to noise 36 and the associated impediment to increasing communication speed become significant with increasing communication speed. Consequently, a speed increase limited by noise 36 leads to a reduction in the amount of data transmitted per unit of time and can reduce the efficiency of data transmission.

[0131] In view of this problem, the second embodiment according to the present disclosure aims to provide a communication device and a communication method that achieve both an improvement in transmission efficiency and an increase in interference immunity. (3-2. Outline of the second embodiment)

[0132] A configuration and an operation according to the second embodiment of the present disclosure are described schematically below.

[0133] Fig. Figure 20A is a block diagram illustrating an exemplary configuration of an image sensor 1004a according to the second embodiment. Fig. 20A the image sensor 1004a has a configuration in which a slow current superposition circuit 300 and a transfer control circuit 400 are added to the configuration of the image sensor 1004 according to the first, with reference to Fig. 5 described embodiment were added.

[0134] Fig. Figure 20B is a block diagram illustrating an exemplary configuration of a transmission data processing circuit 20a according to the second embodiment. Fig. 20B, the transmission data processing circuit 20a is designed to supply aligned signals #1, #2, and #3 to the clock synchronization circuits 2021, 2022, and 2023, and to output an output of these signals from the transmission data processing circuit 20a with respect to the configuration of the transmission data processing circuit 20 according to the first embodiment, which refers to Fig. As described in section 6, it is carried out.

[0135] Returning to the description of Fig. 20A the transmission control circuit 400 generates a transmission control signal 450 to control a parallel-to-serial conversion circuit 311 and a transmission circuit 321, a parallel-to-serial conversion circuit 312 and a transmission circuit 322, as well as a parallel-to-serial conversion circuit 313 and a transmission circuit 323 of tracks #1, #2 and #3 on the basis of the alignment signals #1, #2 and #3 output by the transmission data processing circuit 20a.

[0136] Furthermore, the slow-current superposition circuit 300 generates a slow start / stop current 350 for each of the tracks #1, #2, and #3 based on the matched signals #1, #2, and #3 output by the transmission data processing circuit 20a. The slow start / stop current 350 is a signal for damping a steep current change before a start and after an interruption of the supply of a power supply Vcc (labeled power supply ext.Vcc in the drawing) to each circuit according to the transmission control signal 450.

[0137] The slow current superposition circuit 300 superimposes the slow start / stop current 350 generated for each of tracks #1, #2 and #3 with the power supply Vcc, which is supplied to each of the parallel-to-serial conversion circuit 311 and the transfer circuit 321, the parallel-to-serial conversion circuit 312 and the transfer circuit 322, as well as the parallel-to-serial conversion circuit 313 and the transfer circuit 323 of tracks #1, #2 and #3.

[0138] Fig. Figure 21 is a timing diagram for an example describing the operation according to the second embodiment. Here, a case is considered in which the second track (track #2) is switched from the standby state to the communication state with respect to the first track (track #1) in the communication state, and then back to the standby state. It should be noted that the transmission control signal 450 is assumed to start an operation of a corresponding circuit in a high state, i.e., a value "1", and to stop the operation of the circuit in a low state, i.e., a value "0".

[0139] During a period in which track #2 is in standby mode, the corresponding aligned signal #2 switches at time t 101from the value "0" to the value "1". The transmission control circuit 400 switches the value of the transmission control signal 450 (labeled in the drawing as transmission control signal (track #2)), which corresponds to track #2, at time t. 102 after a predetermined time has elapsed from time t 101 with reference to time t 101 , to which the matched signal #2 is switched to the value “1”, from “0” to “1”.

[0140] The operations of the parallel-to-serial conversion circuit 312 and the transfer circuit 322 of track #2 are started when the transfer control signal 450 of track #2 is received at time t 102The value "1" is assumed. When the operations of the parallel-to-serial conversion circuit 312 and the transfer circuit 322 are started, a current draw, corresponding to the operating current of the circuits, is generated by the supply of power supply Vcc, as shown in the diagram as the current draw of the transfer circuit (track #2). This current draw is the operating current for the circuits' operations.

[0141] On the other hand, the slow-current superposition circuit 300 generates the slow start / stop current 350 as a slow current in which a current value is determined over a period of time t. 101 until time t 102 gradually increases in response to the switching of the adjustment signal #2 from the value "0" to the value "1" at time t 101 and the switching of the transmission control signal 450 from the value '0' to the value "1" at time t 102The slow-current superposition circuit 300 superimposes the generated slow start / stop current 350 with the power supply of the parallel-to-serial conversion circuit 312 and the transfer circuit 322 of track #2.

[0142] As a result of the superposition of the slow start / stop current 350 on the power supply, a current value Icc, which is supplied to the parallel-to-serial conversion circuit 312 and the transfer circuit 322, gradually increases from, for example, 0 from time t 101 , at which the matched signal #2 switches from the value "0" to the value "1", at time t 102 , at which the transmission control signal (track #2) is switched from the value "0" to "1", and at time t 102 a current value of the operating current of the parallel-to-serial conversion circuit 312 and the circuit 322 has been reached.

[0143] At time t 102The slow-current superposition circuit 300 sets the current value of the slow start / stop current 350 to the current value before the increase at time t. 101 (e.g., 0) back. The current supplied to the parallel-to-serial conversion circuit 312 and the transfer circuit 322 is superimposed on the current through the power supply Vcc at time t by the slow start / stop current 350 from the slow-current superposition circuit 300. 102 The system has been switched over, and the operating current is maintained.

[0144] The same applies if track #2 transitions from the communication state to the ready state relative to track #1 during communication. That is, if track #2 is in the communication state at time t 103 in Fig. When module 21 transitions from the communication state to the standby state, the aligned signal #2 changes from the value "1" to the value "0". The transmission control circuit 400 switches the value of the transmission control signal (track #2) corresponding to track #2 according to the time t. 103 , to which the adjustment signal #2 is switched to the value “0”, from “1” to “0”.

[0145] The operations of the parallel-to-serial conversion circuit 312 and the transfer circuit 322 of track #2 are stopped when the transfer control signal (track #2) is received at time t 103 assumes the value "0". When the operations of the parallel-to-serial conversion circuit 312 and the transmission circuit 322 are stopped, the generation of the consumption current due to the supply from the power supply Vcc ends.

[0146] On the other hand, in response to the switching of the matched signal #2 from the value "1" to the value "0" at time t 103, the slow current superposition circuit 300 generates the slow start / stop current 350 as a slow current whose current value in a period from time t 103 up to the point in time t 104 , at which a predetermined time from time t 103 The time elapsed gradually decreases. The slow-current superposition circuit 300 superimposes the generated slow start / stop current 350 with the power supply of the parallel-to-serial conversion circuit 312 and the transfer circuit 322 of track #2.

[0147] As a result of the superposition of the slow start / stop current 350 on the power supply, the current value Icc supplied to the parallel-series conversion circuit 312 and the transmission circuit 322 decreases from the operating current of the parallel-series conversion circuit 312 and the transmission circuit 322 from time t 103 until time t 104 gradually decreases and becomes, for example, at time t104 to 0.

[0148] As described above, the slow start / stop current 350 is superimposed on the operating current of the serial-to-parallel conversion circuit 312 and the transfer circuit 322. At the beginning of the operations of the serial-to-parallel conversion circuit 312 and the transfer circuit 322, the value of this current gradually increases from 0 to the operating current, and at the end of the operations, it gradually decreases from the operating current back to 0. This makes it possible, as shown in parts 500 and 501 of the diagram, to control a steep change in the current Icc, which results from an increase in the number of tracks and the start of operations of the parallel-to-serial conversion circuit 312 and the transfer circuit 322, the change of which causes the noise 36. (3-3. Specific example of the second embodiment)

[0149] The configuration and operation according to the second embodiment are described in more detail below.

[0150] Fig. Figure 22 is a block diagram that illustrates, in particular, the exemplary configuration of the image sensor 1004a according to the second embodiment. Fig. 22 is a configuration on a left side of the transmission data processing circuit 20a and the synchronization signal generation unit 50, the same as in Fig. 20A described above. On the other hand, in Fig. 22 the slow-current superposition circuit 300 in Fig. 20A separately for the first track, the second track and the third track are represented as slow current superposition circuits 300up1, 300up2 and 300up3, which increase the current, and slow current superposition circuits 300dn1, 300dn2 and 300dn3, which decrease the current value.

[0151] In Fig. In the transmission control circuit 400, a release signal 451, a start signal 452, and a shutdown signal 453 are generated as transmission control signals 450. The release signal 451, the start signal 452, and the shutdown signal 453 can be signalings of the number of bits corresponding to the number of tracks that can be supported by a transmission unit 30. In the example of Fig. 22 The transmission unit 30 supports the transmission of the three tracks, which are tracks #1 to #3, and each of the enable signals 451, the start signal 452 and the shut-down signal 453 is a 3-bit signal and controls the parallel-to-serial conversion and transmission in one track, corresponding to one bit position.

[0152] In Fig. Figure 22 contains the slow-current superposition circuit 300up1 (also referred to as SI#1-1 in the drawing) a slow-current generating unit 301up1 (also referred to as SC#1 in the drawing) and a superposition unit 302up1. The slow-current generating unit 301up1 generates a slow current in which the current gradually increases according to a value of the bit corresponding to track #1 of the start signal 452.

[0153] The superposition unit 302up1 superimposes the slow current generated by the slow current generation unit 301up1 with the power supply Vcc, which is supplied to the parallel-to-serial conversion circuit 311 and the transmission circuit 322.

[0154] Similar to the slow-current superheterodyne circuit 300up1, the slow-current superheterodyne circuits 300up2 and 300up3 also contain a slow-current generating unit 301up2 and a superheterodyne unit 302up2, and a slow-current generating unit 301up3 and a superheterodyne unit 302up3, respectively. Each of the slow-current generating units 301up2 and 301up3 generates a slow current in which the current gradually increases according to a value of the bit of the corresponding track of the start signal 452.

[0155] The superposition unit 302up2 superimposes the slow current generated by the slow current generator 301up2 with the power supply Vcc, which is supplied to the parallel-to-serial conversion circuit 312 and the transfer circuit 322 of track 2. Similarly, the superposition unit 302up3 superimposes the slow current generated by the slow current generator 301up3 with the power supply Vcc, which is supplied to the parallel-to-serial conversion circuit 313 and the transfer circuit 323 of track 3.

[0156] In Fig. Figure 22 contains the slow-current superposition circuit 300dn1 (also referred to as SI#2-1 in the drawing) a slow-current generating unit 301dn1 (also referred to as SC#2 in the drawing) and a superposition unit 302dn1, similar to the slow-current superposition circuit 300up1. The slow-current generating unit 301dn1 generates a slow current in which the current gradually decreases according to the value of the bit corresponding to track #1 of the shutdown signal 453.

[0157] The superposition unit 302dn1 superimposes the slow current generated by the slow current generation unit 301dn1 with the power supply Vcc, which is supplied to the parallel-to-serial conversion circuit 311 and the transmission circuit 322.

[0158] Similar to the slow-current superheterodyne circuit 300dn1, the slow-current superheterodyne circuits 300dn2 and 300dn3 also contain a slow-current generating unit 301dn2 and a superheterodyne unit 302dn2, and a slow-current generating unit 301dn3 and a superheterodyne unit 302dn3, respectively. Each of the slow-current generating units 301dn2 and 301dn3 generates the slow current, in which the current gradually decreases according to the value of the bit of the corresponding track of the turn-off signal 453.

[0159] The superposition unit 302dn2 superimposes the slow current generated by the slow current generator 301dn2 with the power supply Vcc, which is supplied to the parallel-to-serial conversion circuit 312 and the transmission circuit 322 of track 2. Similarly, the superposition unit 302dn3 superimposes the slow current generated by the slow current generator 301dn3 with the power supply Vcc, which is supplied to the parallel-to-serial conversion circuit 313 and the transmission circuit 323 of track 3.

[0160] In the following description, the slow-current superposition circuits 300up1 to 300up3 are referred to as the slow-current superposition circuit 300up and the slow-current superposition circuits 300dn1 to 300dn3 are referred to as the slow-current superposition circuit 300dn, unless a special distinction is necessary.

[0161] Specific configurations of the transmission control circuit 400 and the slow-current superposition circuits 300up and 300dn according to the second embodiment, as well as the operation of these circuits, are described with reference to Fig. 23 to Fig. 26 described. Fig. Figure 23 is a circuit diagram that shows an exemplary circuit of the transmission control circuit 400 for the second embodiment. Fig. 24 and Fig. 25 are circuit diagrams that represent exemplary circuits of the slow-current superposition circuits 300up and 300dn applicable to the second embodiment. Fig. Figure 26 is a timing diagram describing the operation according to the second embodiment. Note that track #2 is shown below tracks #1 to #3 as an example in Fig. 26 is shown.

[0162] In Fig. The transmission control circuit 400 contains a delay circuit 410 in which an even number of inverter circuits are connected in series, an inverter circuit 411, AND gates 412 and 413, and a NOR gate 414. The balanced signal is fed to the transmission control circuit 400 and input into the delay circuit 410, into one terminal each of the AND gates 412 and 413, and into one input terminal of the NOR gate 414. The balanced signal is processed within a period of time t. 110 until time t 112 set to the value "1" (high state).

[0163] The adjusted signal, delayed by the delay circuit 410, is input to the other input terminal of the AND circuit 412. The AND circuit 412 outputs, as enable signal 451, the logical combination of the adjusted signal input at one input terminal and the delayed adjusted signal input at the other input terminal. As in Fig. As shown in Figure 26, the enable signal 451 is a signal with the value "1" (high state) for a period of time t. 111 until time t 113 The parallel-to-serial conversion circuit 312 and the transmission circuit 322 of track #2 are operated during the period in which the enable signal 451 has the value "1", and a consumption current is generated.

[0164] The adjusted signal, delayed by the delay circuit 410, is inverted by the inverter circuit 411 and fed into the other input terminal of the AND gate 413 and the other input terminal of the NOR gate 414. The AND gate 413 outputs, as start signal 452, the logical combination of the output of the inverter circuit 411 and the adjusted signal. Furthermore, the NOR gate 414 outputs, as turn-off signal 453, the NOR signal of the output of the inverter circuit 411 and the adjusted signal.

[0165] Referring to Fig. 26 the matched signal changes at time t 110 from the value “0” (low state) to the value “1” (high state), and the adjusted signal delayed by the delay circuit 410 (not shown) changes at time t 111 from the value "0" (low state) to the value "1" (high state). The start signal 452 is generated within a period from time t. 110until time t 111 by logically combining the matched signal and the signal detected by the delay of the matched signal, the value “1” (high state) is set.

[0166] On the other hand, the matched signal changes at time t. 112 from the value "1" to the value "0", and the adjusted signal, delayed by the delay circuit 410, changes at time t 113 from the value "1" to the value "0". The release signal 451 has a change in the period from time t. 111 until time t 112 The value "1" is obtained through the logical combination of the adjusted signal and the delayed adjusted signal. Furthermore, the shutdown signal 453 is generated within a period from time t. 112 until time t 113 The value “1” is set by the NOR of the matched signal and the delayed and inverted matched signal.

[0167] It should be noted that jitter in a communication signal increases when the slope of the current rise or fall is steep due to the slow current, and the generation of jitter decreases above a certain slope when the slope is gentle. Thus, the slope, i.e., the length of the time period t, can 110 are 111 and the duration of t 112 are 113 The jitter generation can be determined based on the slope at which it decreases. For example, these periods could be the shortest time during which jitter generation decreases. Furthermore, the length of these periods can be adjusted based on a value written to a register or similar.

[0168] Referring to Fig. Figure 24 contains the slow-current superposition circuit 300up, a delay circuit 310 in which several inverter circuits are connected in series, several AND gates 3111, 3112, and 3113, and a resistor 3121 and an integrated circuit 3131, a resistor 3122 and an integrated circuit 3132, and a resistor 3123 and an integrated circuit 3133, each connected in series. It should be noted that the resistance values ​​of resistors 3121 to 3124 and the delay time in the delay circuit 310 are arbitrary and can be adjusted appropriately according to a circuit characteristic and a required characteristic.

[0169] The start signal 452 is fed into the delay circuit 310 and into one input terminal each of the AND gates 3111, 3112, and 3113, and configured as a control signal for opening and closing the circuit 3134. The start signal 452 is delayed in a predetermined manner and extracted by the delay circuit 310 and fed into one input terminal at the other end of each of the AND gates 3111, 3112, and 3113. The AND gates 3111, 3112, and 3113 output a logical combination of the signals fed into each input terminal as control signals that control the opening and closing of the circuits 3131, 3132, and 3133, respectively.

[0170] On the other hand, one end of each resistor 3121 and circuit 3131, resistor 3122 and circuit 3132, and resistor 3123 and circuit 3133, which are connected in series, is connected to the power supply Vcc, and the other end is connected to ground potential GND. Each of the circuits 3131 to 3134 is sequentially controlled to open and close according to the start signal 452 and each of the control signals output by the AND circuits 3111 to 3113 at a time when the start signal 452 is sequentially delayed, thus generating a slow current Icc-up, where the current gradually increases from time t 110 at that time t 111 increases, is generated and fed into a power supply line of the power supply Vcc.

[0171] Referring to Fig. Figure 25 contains the slow-current superposition circuit 300dn, a delay circuit 320 in which several inverter circuits are connected in series, several AND circuits 3211, 3212, and 3213, as well as a resistor 3221 and an integrated circuit 3231, a resistor 3222 and an integrated circuit 3232, and a resistor 3223 and an integrated circuit 3233, each connected in series. It should be noted that the resistance values ​​of resistors 3221 to 3224 and the delay time in the delay circuit 320 are arbitrary and can be adjusted appropriately according to a circuit characteristic and a required characteristic.

[0172] The shutdown signal 453 is fed into the delay circuit 320 and into a non-inverting input terminal of each of the AND circuits 3211, 3212, and 3213, and configured as a control signal that controls the opening and closing of the circuit 3234. The shutdown signal 453 is delayed in a predetermined manner and extracted by the delay circuit 320 and fed into an inversion input terminal of each of the AND circuits 3211, 3212, and 3213. The AND circuits 3211, 3212, and 3213 output a logical combination of the signals received at the non-inversion and inversion input terminals, respectively, as control signals for controlling the opening and closing of the circuits 3231, 3232, and 3233.

[0173] On the other hand, one end of each of resistor 3221 and circuit 3231, resistor 3222 and circuit 3232, and resistor 3223 and circuit 3233, which are connected in series, is connected to the power supply Vcc, and the other end is connected to ground potential GND. Each of the circuits 3231 to 3234 is sequentially controlled according to the turn-off signal 453 and each of the control signals output by the AND circuits 3211 to 3213, such that it is opened and closed at a time when the turn-off signal 453 is sequentially delayed, thereby allowing a slow current Icc-dn, where the current gradually decreases from time t. 112 currently t 113 takes off, is generated and is delivered to the power supply line of the power supply Vcc.

[0174] As in Fig. 26, shown, during the period in which the release signal 451 has the value "1" (time t) 111 until time t112 The serial-to-parallel conversion circuit 312 and the transfer circuit 322 of track #2 are operated, and a consumption current Icc-L is generated. In the second embodiment, before and after the period in which the enable signal 451 has the value "1", the slow current Icc-up, whose current value increases, and the slow current Icc-dn, whose current value decreases, are superimposed on Vcc.

[0175] In the second embodiment, therefore, even in a case where the ready state and the communication state are switched in lane #2, as in parts 502 and 503 of Fig. As shown in Figure 26, it is possible to control a strong fluctuation of the current Icc supplied to the parallel-to-serial conversion circuit 312 and the transmission circuit 322 of track #2 by means of the power supply Vcc. In this way, the generation of noise 35 by switching between the standby state and the communication state in the track can be prevented, and it is possible to prevent the propagation of noise 36 to another track due to noise 35.

[0176] Since the second embodiment makes it possible to control the steep change in current at the time of switching the number of tracks to which image data is transferred, it is also possible to improve resistance to electromagnetic waves such as electromagnetic interference (EMI) or disturbances during flight in an aircraft.

[0177] Fig. Figure 27 is a schematic representation that illustrates an example of the simulation of an operation by one embodiment according to the second embodiment. The time sequence is shown in Fig. 27 shown in the right direction.

[0178] In Fig. Line 27 represents the top line of transmitted image data, indicating that the image data is transmitted during a communication state period. The second line represents the current draw Icc-L in the parallel-to-serial conversion circuit and the transmission circuit in the track. The current draw Icc-L is generated in response to the transmission time of the image data and is 0 in the standby state. The third line shows the slow current Icc-up during the current rise and the slow current Icc-dn during the current fall.

[0179] In Fig. Figure 27 shows the first half of the third row representing the slow current Icc-up of the current increase. It can be seen that the current value of the slow current Icc-up gradually increases to the current value of the consumption current Icc-L over a period from a predetermined time before the generation of the consumption current Icc-L until the generation of the consumption current Icc-L, and that the current value is set to 0 when the consumption current Icc-L is generated. Similarly, the second half of the third row represents the slow current Icc-dn of the current decrease, and it can be seen that the current value gradually decreases from the current value of the consumption current Icc-L to 0 over a period of a predetermined time from the end of the generation of the consumption current Icc-L.

[0180] In Fig.Figure 27 represents a fourth line, the current Icc, where the slow currents Icc-up and Icc-dn are superimposed on the load current Icc-L. The parallel-to-serial conversion circuit and the transfer circuit in the track are controlled by the current Icc. As shown in the diagram, it can be seen that the slow currents Icc-up and Icc-dn before and after the load current Icc-L control the steep current change at the time of track switching, which can be a factor in the noise 36.

[0181] Note that while the Slow Current Superposition Circuit 300 does generate the slow current where the current changes gradually as described above, this example is not a limitation. For instance, the Slow Current Superposition Circuit 300 can generate a slow current where the current changes continuously. (3. Conclusion)

[0182] As described above, according to the present disclosure, the alignment signal in each track of the output is provided by the transmission unit 30, which performs the serial transmission, and the other tracks are aligned, i.e., synchronized on the basis of the clock of the reference track.

[0183] By applying the embodiment according to the present disclosure, it is thus possible to synchronize the serially transmitted data in parallel without using a synchronization code during data transmission and furthermore without providing a separate synchronization setting circuit on the receiving side. This makes it possible to eliminate a process and redundant data that hinder speed increases, to transmit data efficiently by using a multitude of tracks, and to process a large amount of data at high speed.

[0184] Furthermore, by applying the configuration of each embodiment according to the present disclosure, a synchronization adjustment procedure between tracks on the receiving side and a circuit is performed to make it unnecessary. In this way, it is possible to reduce the size and power consumption of a device and to lower costs by reducing the circuit area.

[0185] Due to the effects described above, the embodiment according to the present disclosure is suitable for use in an image sensor that needs to process a large amount of data at high speed. Furthermore, since the size and power consumption of the device can be reduced, it is also suitable for use in a mobile device.

[0186] Furthermore, the configuration of each embodiment according to the present disclosure can be applied to various interfaces that perform serial transmissions in parallel on a multitude of tracks, such as Mobile Industry Processor Interface (MIPI), Peripheral Component Interconnect express (PCIe), DisplayPort, Universal Serial Bus (USB), Thunderbolt (registered trademark) and High-Definition Multimedia Interface (HDMI) (registered trademark).

[0187] Please note that the effects described in this description are only examples and not limitations, and that other effects may occur.

[0188] Please note that the present technology can also have the following configurations. (1) Communication device comprising the following: a multitude of signal processing units, each of which outputs a clock signal and output data, which are output to a corresponding track among a multitude of tracks based on input data and synchronized with the clock signal; and a first circuit which, according to a reference track selection signal in order to select a reference track from the plurality of tracks, selects an output clock signal corresponding to the reference track from the output clock signals each output by the plurality of signal processing units, and performs an output of it to each of the plurality of signal processing units, wherein each of the multitude of signal processing units The output clock signal and output data are adjusted and output based on either a reference clock signal or the output clock signal provided by another signal processing unit from among the multitude of signal processing units. (2) Communication device as described above (1), wherein a first signal processing unit, which corresponds to the reference track among the multitude of signal processing units performs the alignment of the output clock signal and the output data based on the reference clock signal and outputs them, and a second signal processing unit that differs from the first signal processing unit among the multitude of signal processing units performs the adjustment to the output clock signal and the output data based on the output clock signal issued by the first signal processing unit and makes the output of the same. (3) Communication device according to points (1) or (2) above, wherein Each of the multiple signal processing units selects the reference clock signal or the output clock signal that is output by the first circuit according to the reference track selection signal, and on the basis of the selected clock signal generates a synchronization clock signal to synchronize a matching signal whose state changes in response to the timing determination of a track for data transmission among the multiple tracks. (4) Communication device as described above (3), wherein each of the multitude of signal processing units a calibration signal is generated, which is obtained by synchronizing the timing sequence, during which the state of the calibration signal changes, with the synchronization clock signal. (5) Communication device as described above (4), wherein the output data is sent to a transmitter unit, which then transmits the output data to a subsequent circuit corresponding to the track, the communication device further includes the following: a control unit that controls the start and end of an operation of the transmission unit with reference to a timing control in which a state of the matched signal changes, and determines a first timing control in which the state of the matched signal changes, and a second timing control in which a predetermined time elapses from the first timing control, and a slow current superposition unit that generates a slow current whose current value gradually changes from the first time to the second time, and that superimposes the slow current on a supply current supplied to the transmission unit. (6) Communication device as described above (5), wherein the control unit the first time point and the second time point are determined, whereby the beginning and end of the operation of the transmission unit are specified in each case. (7) Communication device as described above (6), wherein the slow-current superposition unit The current of the power supply at the first time and the second time, which is intended for the start of the operation of the transmission unit, is superimposed with a current that gradually increases from the first time to the second time, and The current of the power supply at the first time and at the second time, which is intended for the interruption of the operation of the transmission unit, is superimposed with a current that gradually decreases from the first time to the second time. (8) Communication device as described above (7), wherein the control unit controls the transmission unit so that it is in an operating state for a period of time from the second time scheduled for the start of the operation of the transmission unit to the first time scheduled for the end of the operation of the transmission unit. (9) Communication device according to any of points (5) to (8) above, wherein The transmission unit includes the following: a conversion unit that converts the output data from parallel data to serial data, and a transmitter unit that transmits the serial data to the subsequent circuit for each of the multitude of tracks. (10) Communication device according to any of the above points (4) to (9), wherein each of the multitude of signal processing units toggles the validity and invalidity of the reference clock signal according to the matched signal and generates the output clock signal based on the reference clock signal that is set as valid. (11) Communication device as described above (10), wherein each of the multitude of signal processing units outputs the input data as output data synchronously with the output clock signal. (12) Communication device according to any of points (1) to (11) above, wherein Identification information for identifying the time of determining a track for a data transmission among the multitude of tracks is arranged in a header of the output data. (13) Communication device according to any of points (1) to (12) above, wherein The input data is image data. (14) Communication procedure comprising the following: an output step of outputting an output clock signal and output data based on the input data and synchronized with the output clock signal to a corresponding track among a plurality of tracks; and a first selection step of selecting, according to a reference track selection signal, a reference track from the plurality of tracks, an output clock signal corresponding to the reference track, among the output clock signals each output by a plurality of signal processing units, and performing an output of it to each of the plurality of signal processing units, the steps performed by each of the multitude of signal processing units, whereby In the output step, each of the multitude of signal processing units outputs the output clock signal and output data based on either a reference clock signal or the output clock signal output by another signal processing unit from the multitude of signal processing units. (15) Image sensor comprising the following: an imaging unit that outputs image data corresponding to the emitted light; a multitude of signal processing units, into which the image data is input as input data, and of which each outputs a clock signal and output data based on the input data, synchronized with the clock signal to a corresponding track among a multitude of tracks; and a first circuit which, according to a reference track selection signal in order to select a reference track from the plurality of tracks, selects an output clock signal corresponding to the reference track from the output clock signals each output by the plurality of signal processing units, and performs an output of it to each of the plurality of signal processing units, wherein each of the plurality of signal processing units The output clock signal and output data are adjusted and output based on either a reference clock signal or the output clock signal provided by another signal processing unit from among the multitude of signal processing units. List of reference symbols 10 IMAGE CAPTURE UNIT 20 TRANSFER DATA PROCESSING CIRCUIT 211, 212, 213 SIGNAL PROCESSING CIRCUIT 30 TRANSMISSION UNIT 311, 312, 313 Parallel-to-serial conversion circuit 321, 322, 323 TRANSFER CIRCUIT 40 OSCILLATOR 50 SYNCHRONIZATION SIGNAL GENERATION UNIT 60 PLL 70-beat generator 80 RECEIVING UNIT 811, 812, 813 RECEIVING CIRCUIT 821, 822, 823 SERIAL-PARALLEL CONVERSION CIRCUIT 90 RECEIVING DATA PROCESSING CIRCUIT 2001, 2002, 2003, 204 SELECTOR 2011, 2012, 2013 SYNCHRONIZATION CIRCUIT 2021, 2022, 2023 TIMER ALIGNMENT CIRCUIT 2031, 2032, 2033 DATA MATCHING CIRCUIT 2101, 2102, 210 n , 230 FLIP-FLOP CIRCUIT 220 AND switch 221 Frequency Divider 300, 300dn, 300dn1, 300dn2, 300dn3, 300up, 300up1, 300up2, 300up3 SLOW CURRENT SUPERCHARGING CIRCUIT 350 SLOW START / CUT-OFF CURRENT 400 TRANSMISSION CONTROL CIRCUIT 450 TRANSFER TAX SIGNAL 451 RELEASE SIGNAL 452 START SIGNAL 453 Shutdown Signal 1004, 1004a IMAGE SENSOR 1005 Image Processing Unit QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2019-036833

[0003]

Claims

[1] Communication device comprising the following: a multitude of signal processing units, each of which outputs a clock signal and output data, which are output to a corresponding track among a multitude of tracks based on input data and synchronized with the clock signal; and a first circuit which, according to a reference track selection signal in order to select a reference track from the plurality of tracks, selects an output clock signal corresponding to the reference track from the output clock signals each output by the plurality of signal processing units, and performs an output of it to each of the plurality of signal processing units, wherein Each of the multitude of signal processing units compares and outputs the output clock signal and output data based on either a reference clock signal or the output clock signal output by another signal processing unit from the multitude of signal processing units. [2] Communication device according to claim 1, wherein a first signal processing unit, which corresponds to the reference track among the multitude of signal processing units performs the alignment of the output clock signal and the output data based on the reference clock signal and outputs them, and a second signal processing unit that differs from the first signal processing unit among the multitude of signal processing units performs the adjustment to the output clock signal and the output data based on the output clock signal issued by the first signal processing unit and makes the output of the same. [3] Communication device according to claim 1, wherein each of the multitude of signal processing units selects the reference clock signal or the output clock signal that is output by the first circuit according to the reference track selection signal, and on the basis of the selected clock signal generates a synchronization clock signal to synchronize a matching signal whose state changes in response to the timing determination of a track for data transmission among the multitude of tracks. [4] Communication device according to claim 3, wherein each of the multitude of signal processing units a calibration signal is generated, which is obtained by synchronizing the timing sequence, during which the state of the calibration signal changes, with the synchronization clock signal. [5] Communication device according to claim 4, wherein the output data is sent to a transmitter unit, which then transmits the output data to a subsequent circuit corresponding to the track, the communication device further includes the following: a control unit that controls the start and end of an operation of the transmission unit with reference to a timing control in which a state of the matched signal changes, and determines a first timing control in which the state of the matched signal changes, and a second timing control in which a predetermined time elapses from the first timing control, and a slow current superposition unit that generates a slow current whose current value gradually changes from the first time to the second time, and that superimposes the slow current on a supply current supplied to the transmission unit. [6] Communication device according to claim 5, wherein the control unit the first time point and the second time point are determined, whereby the beginning and end of the operation of the transmission unit are specified in each case. [7] Communication device according to claim 6, wherein the slow-current superposition unit The current of the power supply at the first time and the second time, which is intended for the start of the operation of the transmission unit, is superimposed with a current that gradually increases from the first time to the second time, and The current of the power supply at the first time and at the second time, which is intended for the interruption of the operation of the transmission unit, is superimposed with a current that gradually decreases from the first time to the second time. [8] Communication device according to claim 7, wherein the control unit controls the transmission unit so that it is in an operating state for a period of time from the second time scheduled for the start of the operation of the transmission unit to the first time scheduled for the end of the operation of the transmission unit. [9] Communication device according to claim 5, wherein the transmission unit comprises the following: a conversion unit that converts the output data from parallel data to serial data, and a transmitter unit that transmits the serial data to the subsequent circuit for each of the multitude of tracks. [10] Communication device according to claim 4, wherein Each of the multiple signal processing units switches the validity and invalidity of the reference clock signal according to the matched signal and generates the output clock signal based on the reference clock signal that is set as valid. [11] Communication device according to claim 10, wherein Each of the numerous signal processing units outputs the input data as output data synchronously with the output clock signal. [12] Communication device according to claim 1, wherein Identification information for identifying the time of determining a track for a data transmission among the multitude of tracks is arranged in a header of the output data. [13] Communication device according to claim 1, wherein The input data is image data. [14] Communication methods, including the following: an output step of outputting an output clock signal and output data based on the input data and synchronized with the output clock signal to a corresponding track among a plurality of tracks; and a first selection step of selecting, according to a reference track selection signal, to select a reference track from the plurality of tracks, an output clock signal corresponding to the reference track, among the output clock signals each output by a plurality of signal processing units, and performing an output of it to each of the plurality of signal processing units, the steps performed by each of the multitude of signal processing units, whereby In the output step, each of the multitude of signal processing units outputs the output clock signal and output data based on either a reference clock signal or the output clock signal output by another signal processing unit from the multitude of signal processing units. [15] Image sensor comprising the following: an imaging unit that outputs image data corresponding to the emitted light; a multitude of signal processing units, into which the image data is input as input data, and of which each outputs a clock signal and output data based on the input data, synchronized with the clock signal to a corresponding track among a multitude of tracks; and a first circuit which, according to a reference track selection signal in order to select a reference track from the plurality of tracks, selects an output clock signal corresponding to the reference track from the output clock signals each output by the plurality of signal processing units, and performs an output of it to each of the plurality of signal processing units, wherein Each of the multitude of signal processing units compares and outputs the output clock signal and output data based on either a reference clock signal or the output clock signal output by another signal processing unit from the multitude of signal processing units.

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