Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a base substrate (01) and a plurality of data lines (100), a plurality of gate lines (200), a first electrode layer (310), and a plurality of transistors (400) arranged on the base substrate (01). The first electrode layer (310) is located on the side of a film layer furthest from the base substrate (01), on which the plurality of data lines (100) are located. Each transistor (400) comprises a gate (403), a first electrode (401), and a second electrode (402). The gate (403) of the transistor (400) is electrically connected to the gate line (200), the first electrode (401) of the transistor (400) is electrically connected to the data line (100), and the second electrode (402) of the transistor (400) is electrically connected to the first electrode layer (310).The gate line (200) is located on the side of the data line (100) facing away from the base substrate (01). The gate (403) of the transistor (400) is located on the same layer as the data line (100), and an orthographic projection of the gate (403) of at least one transistor (400) on the base substrate (01) is spaced apart from orthographic projections of the gate lines (200) on the base substrate (01). By placing the data lines (100) between the gate lines (200) and the base substrate (01) and by placing the gate (403) of at least one transistor at a distance from the gate lines (200), the permeability of the display substrate can be improved while maintaining the complexity of the manufacturing process.

Description

[0001] The present application claims priority over Chinese patent application No. 202310594994.3, which was filed on May 24, 2023. The content of that disclosure is hereby incorporated in its entirety by reference into the present application and forms an integral part thereof. AREA OF TECHNOLOGY

[0002] The embodiments of the present disclosure relate to a display substrate and a display device. STATE OF THE ART

[0003] A liquid crystal display (LCD) panel features an advanced super dimension switching (ADS) display mode, where the ADS horizontal electric field liquid crystal mode and other technologies improve the transmittance of the liquid crystal display panel by improving the electrodes or partially adjusting the backlight brightness, thus improving the contrast and brightness of the liquid crystal display panel.

[0004] The LCD panels, which use the advanced Super-Dimension-Switching (High Advanced-Super Dimensional Switching, HADS) display mode with a high aperture ratio, are characterized by a high aperture ratio, high resolution, high transmittance and a wide viewing angle. SUMMARY

[0005] The embodiments of the present disclosure provide a display substrate and a display device.

[0006] The present disclosure provides a display substrate comprising a base substrate and a plurality of data lines, a plurality of gate lines, a first electrode layer and a plurality of transistors located on the base substrate.The plurality of data lines are arranged in a first direction; the plurality of gate lines are arranged in a second direction, and the second direction intersects the first direction; the first electrode layer is located on a side of a film layer on which the plurality of data lines are located, away from the base substrate; each of the plurality of transistors comprises a gate electrode, a first electrode, and a second electrode, wherein the gate electrodes of the plurality of transistors are electrically connected to the plurality of gate lines, the first electrodes of the plurality of transistors are electrically connected to the plurality of data lines, and the second electrodes of the plurality of transistors are electrically connected to the first electrode layer.The plurality of gate lines are located on a side of the plurality of data lines away from the base substrate, the gate electrodes of the plurality of transistors are arranged on the same layer as the plurality of data lines, and an orthographic projection of the gate electrode of at least one transistor on the base substrate is spaced apart from an orthographic projection of a gate line electrically connected to the gate electrode of the at least one transistor on the base substrate.

[0007] For example, according to one embodiment of the present disclosure, the display substrate further comprises: a plurality of subpixels, wherein the first electrode layer comprises several spaced-apart first electrodes and each subpixel comprises one of the plurality of first electrodes; a plurality of first interconnect sections located on a side of the plurality of gate lines remote from the base substrate and configured to connect the gate electrodes of the plurality of transistors to the plurality of gate lines. At least one gate line comprises a plurality of protrusion structures, each protrusion structure being configured to be electrically connected to the gate electrode of a corresponding transistor via at least one of the plurality of first interconnect sections, and the plurality of protrusion structures comprising at least a first protrusion structure and a second protrusion structure.The multitude of subpixels comprises at least a first subpixel and a second subpixel; a transistor electrically connected to the first electrode of the first subpixel is a first transistor; a transistor electrically connected to the first electrode of the second subpixel is a second transistor; the gate electrode of the first transistor is electrically connected to the first protrusion structure; the gate electrode of the second transistor is electrically connected to the second protrusion structure; and the shape of the first protrusion structure differs from the shape of the second protrusion structure.

[0008] For example, according to one embodiment of the present disclosure, the area of ​​the first projection structure is larger than that of the second projection structure.

[0009] For example, according to one embodiment of the present disclosure, the first projection structure comprises a first sub-projection structure and a second sub-projection structure, and the first sub-projection structure and the second projection structure have substantially the same shape and are substantially the same size.

[0010] For example, according to one embodiment of the present disclosure, the second sub-projection structure is arranged on a side of the first sub-projection structure that is remote from the gate electrode electrically connected to the first sub-projection structure.

[0011] For example, according to one embodiment of the present disclosure, in the second direction the size of the second sub-projection structure is larger than the size of the first sub-projection structure.

[0012] For example, according to one embodiment of the present disclosure, in the first direction the ratio of the distance between the first protrusion structure and a data line closest to the first protrusion structure to the distance between the second protrusion structure and a data line closest to the second protrusion structure is in a range of 0.8 to 1.2.

[0013] For example, according to one embodiment of the present disclosure, the data line closest to the first protrusion structure has a different shape than the data line closest to the second protrusion structure.

[0014] For example, according to one embodiment of the present disclosure, two data lines located on both sides of the first protrusion structure comprise a first data line and a second data line; two data lines located on both sides of the second protrusion structure comprise the second data line and a third data line, or the first data line and a third data line, and the second data line or the first data line is located between the first protrusion structure and the second protrusion structure, and the first data line, the second data line, and the third data line have different shapes.

[0015] For example, according to one embodiment of the present disclosure, the first data line and the second data line are bent away from the first protrusion structure on two sides at positions corresponding to the first protrusion structure.

[0016] For example, according to one embodiment of the present disclosure, a distance between the first data line and one of the gate electrodes closest to the first data line is a first distance, a distance between the second data line and one of the gate electrodes closest to the second data line is a second distance, a distance between the third data line and one of the gate electrodes closest to the third data line is a third distance, and a ratio of the first distance, the second distance and the third distance is (0.8~1.2):(0.8~1.2).

[0017] For example, according to one embodiment of the present disclosure, the shape of the gate electrode of the first transistor is approximately the same as that of the gate electrode of the second transistor, the shape of the first electrode of the first transistor is approximately the same as that of the first electrode of the second transistor, and the shape of the second electrode of the first transistor is approximately the same as that of the second electrode of the second transistor; and the ratio of the distance between the gate electrode of the first transistor and a data line electrically connected to the first transistor to the distance between the gate electrode of the second transistor and a data line electrically connected to the second transistor is in the range of 0.8 to 1.2.

[0018] For example, according to one embodiment of the present disclosure, the display substrate further comprises: a spacer located on a side of the first electrode layer furthest from the base substrate. An orthographic projection of the spacer on the base substrate overlaps orthographic projections of the first protrusion structure and the gate electrode electrically connected to the first protrusion structure on the base substrate, and the dimensions of the spacer are larger than those of the second protrusion structure in both the first and second directions.

[0019] For example, according to one embodiment of the present disclosure, the first electrodes and the second electrodes of the plurality of transistors are arranged on the same layer as the plurality of gate lines.

[0020] For example, according to one embodiment of the present disclosure, the display substrate further comprises: a second electrode layer located on the same layer as the plurality of first interconnect sections, wherein the plurality of subpixels share the second electrode layer, and the second electrode layer comprises a plurality of strip electrodes that overlap the first electrode layer in a direction perpendicular to the base substrate. The first electrode layer is located between a film layer on which the plurality of gate lines are located and the film layer on which the plurality of data lines are located, and the plurality of data lines overlap the second electrode layer in a direction perpendicular to the base substrate.

[0021] For example, according to one embodiment of the present disclosure, the display substrate further comprises: a plurality of second interconnect sections located on the same layer as the plurality of first interconnect sections and configured to connect the first electrodes of the plurality of transistors to corresponding data lines.

[0022] For example, according to one embodiment of the present disclosure, the display substrate further comprises: an insulating layer located between the plurality of second interconnect sections and the base substrate. The insulating layer comprises a plurality of first through-holes, and the first electrode of the transistor and a data line electrically connected to the first electrode of the transistor are connected to the same second interconnect section via the same first through-hole.

[0023] For example, according to one embodiment of the present disclosure, the display substrate further comprises: an insulating layer located between the plurality of first interconnect sections and the base substrate. The insulating layer comprises a second through-hole and a third through-hole, wherein the first interconnect section is connected to the gate electrode of the transistor via the second through-hole and the first interconnect section is connected to the protrusion structure via the third through-hole.

[0024] One embodiment of the present disclosure provides a display device comprising the display substrate in one of the examples mentioned above.

[0025] For example, according to one embodiment of the present disclosure, the display device has a resolution of 8k. BRIEF DESCRIPTION OF THE FIGURES

[0026] In order to clearly illustrate the technical solution of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below; it is obvious that the described drawings relate only to some embodiments of the present disclosure and thus do not limit the present disclosure. Fig. Figure 1 is a schematic diagram of a sublevel structure of a display substrate. Fig. 2 is a schematic diagram of a partial cross-sectional structure of a display device that shows the in Fig. The display substrate shown comprises, along a Fig. 1 shown line AA' recorded. Fig. Figure 3 is a schematic diagram of a sub-level structure of a display substrate provided according to an embodiment of the present disclosure. Fig. 4 is a schematic diagram of a partial cross-sectional structure along a line in Fig. 3 shown line BB'. Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. Figure 11 are schematic diagrams of different film layers in a display substrate. Fig. 12 is a partially enlarged view of the in Fig. 3 display substrates shown. Fig. 13 is a partially enlarged view of the in Fig. 8 film layers shown. Fig. 14A is a partially enlarged view of the in Fig. 12 displayed display substrates. Fig. 14B is a sectional view along the in Fig. Line DD' shown on 14A. Fig. Figure 15 is a schematic block diagram of a display device provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE REVELATION

[0027] To clarify the objects, technical details, and advantages of the embodiments of this disclosure, the technical solutions of the embodiments are described clearly and comprehensively in conjunction with the drawings relating to the embodiments of this disclosure. It is evident that the described embodiments represent only some, but not all, of the embodiments of this disclosure. Based on the embodiments described herein, those skilled in the art can derive other embodiments, without inventive step, which should fall within the scope of this disclosure.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as they are generally understood by a person skilled in the art in the field of the present disclosure. The terms "first," "second," etc., used in the present application for disclosure are not intended to indicate any order, quantity, or meaning, but rather to distinguish different components. The terms "comprise," "comprising," "including," etc., are intended to indicate that the elements or objects mentioned before these terms include the elements or objects listed after these terms and their equivalents, but do not exclude other elements or objects.The features “parallel”, “perpendicular”, and “equal” used in the embodiments of the present disclosure encompass all features such as “parallel”, “perpendicular”, and “equal” in the narrower sense, as well as cases involving certain errors, such as “approximately parallel”, “approximately perpendicular”, “about equal”, or similar, taking into account measurements and errors associated with the measurement of a particular quantity (e.g., limitations of the measuring system) and indicating that they lie within an acceptable range of deviation for a given value, as determined by a person skilled in the art in this field. For example, “about” may mean that a value lies within one or more standard deviations or within 10% or 5% of the stated value.If the quantity of a component is not expressly specified in the embodiments of this disclosure, this means that the component may be one or more, or may be understood as at least one. "At least one" means one or more, and "plural" means at least two. The "same layer" in this disclosure refers to the structure formed from two (or more) structures formed by the same deposition process and structured by the same structuring process, their materials being either the same or different.

[0029] The power consumption of a television (TV) is primarily derived from the backlight structure, the system-on-a-chip (SoC) board, and the display panel. The backlight structure accounts for 70% to 80% of the power consumption, the SoC board for 10% to 20%, and the display panel for another 10% to 20%. Therefore, the overall power consumption of the device can be effectively reduced by decreasing the power consumption of the backlight structure. For example, reducing the brightness of the backlight structure can lower its power consumption. If the backlight brightness is reduced, the overall brightness of the product can be maintained at a nearly identical level by increasing the transmittance of the display panel.For example, the transmittance of the display panel must be increased by 40%, and by using the double luminance enhancement foil (DBEF), the power consumption of the display device can be reduced by 70% to 80%.

[0030] Fig. Figure 1 is a schematic diagram of a sublevel structure of a display substrate, and Fig. 2 is a schematic diagram of a partial cross-sectional structure of a display device that shows the in Fig. The display substrate shown comprises, along a Fig. 1 shown line AA' recorded. As in Fig. 1 and Fig. As shown in Figure 2, the display substrate comprises a plurality of data lines 11 arranged in the X direction and a plurality of gate lines 12 arranged in the Y direction, wherein the plurality of data lines 11 and the plurality of gate lines 12 are isolated and intersect to limit a plurality of subpixels.Each subpixel comprises a first electrode 13, a second electrode 14, and a transistor 15. The first electrode 13 and the second electrode 14 are stacked. The gate line 12 is electrically connected to the gate electrode of the transistor 15 to switch the transistor 15 on or off. The first electrode 13 is electrically connected to one of the source electrodes and the drain electrode of the transistor 15. The data line 11 is electrically connected to the other of the source electrode and the drain electrode of the transistor 15. The data line 11 inputs a voltage signal required for a screen via the transistor 15 to the first electrode 13 to implement the display device, including the display substrate. The display substrate uses the advanced Super-Dimension-Switching (ADS) display mode.The first electrode 13 can be a pixel electrode, and the second electrode 14 can be a common electrode.

[0031] As in Fig. As shown in Figure 2, the data line 11 is located between a film layer containing the first electrode 13 and a film layer containing the second electrode 14. The first electrode 13 is located on the side of the second electrode 14 furthest from the first base substrate 10. An insulating layer 16, for example an inorganic insulating layer, is provided between the film layer containing the second electrode 14 and the film layer containing the data line 11. An insulating layer 17, for example an inorganic insulating layer, is provided between the film layer containing the first electrode 13 and the film layer containing the data line 11. The first electrode 13 comprises a plurality of strip electrodes, and the second electrode 14 can be a block electrode that does not overlap the data line 11 in a direction perpendicular to the first base substrate 10.

[0032] As in Fig. As shown in Figure 2, the display device further comprises a second base substrate 20 opposite the first base substrate 10, and a black matrix 21 is provided on a side of the second base substrate 20 facing the first base substrate 10 to shield the data line 11. Fig. Figure 2 only schematically shows the black matrix on the second base substrate. For example, a side of the second base substrate facing the first base substrate could also be coated with a colored film layer. For example, a liquid crystal layer is provided between the first and second base substrates.

[0033] As in Fig. 1 and Fig. As shown in Figure 2, taking into account the control power and the process capacity of the data line 11, the line width of the data line 11 can be between 4 micrometers and 10 micrometers. A line width of less than 3 micrometers can lead to a risk of etching and breakage, and a line width of more than 10 micrometers can affect the transmittance of the display device. For example, the line width of the data line 11 can be between 5 and 8 micrometers, so that the transmittance is within a required range while simultaneously meeting the control requirements, and the display device can be an 8K resolution display device, as shown in Figure 2. Fig. Figure 2 shows. For example, the screen of the display device can be 65 inches in size and the line width of the data line 11 can be 7 micrometers.

[0034] As in Fig. 1 and Fig. As shown in Figure 2, the distance between the second electrode 14 and the data line 11 in the X-direction is 2 to 6 micrometers, for example, 2.5 micrometers. If the distance between the second electrode 14 and the data line 11 in the X-direction is less than 2 micrometers, the second electrode 14 may overlap the data line 11, taking process variations into account, resulting in a large capacitance of the data line 11. If the distance between the second electrode 14 and the data line 11 in the X-direction is greater than 6 micrometers, the display device may exhibit a high transmission loss. Furthermore, when designing the distance between the second electrode and the data line in the X-direction, any parasitic capacitance arising between the second electrode and the data line must also be considered.The larger the capacitance, the more electric field the second electrode absorbs from the data line, the lower the coupling of the data line to the first electrode, and the lower the risk of line mura.

[0035] As in Fig. 1 and Fig. As shown in Figure 2, the distance between the first electrode 13 and the data line 11 in the X-direction is 2 to 7 micrometers, for example, 5 micrometers or 6.5 micrometers. If the distance between the first electrode and the data line in the X-direction is small, the first electrode may overlap the data line. If the distance between the first electrode and the data line in the X-direction is large, the display device will have a high transmission loss.

[0036] As in Fig. 1 and Fig. As shown in Figure 2, the distance of a single side of the black matrix 21 beyond an edge of the data line 11 in the X direction can be from 2 micrometers to 8 micrometers, for example, 2 micrometers. Since there is a slope along the width of the data line 11, and the liquid crystal molecules have an angle of inclination at this slope, the above-mentioned quantity accounts for the fact that the black matrix 21 must cover the slope of the data line 11 to prevent light leakage. If, for example, a liquid crystal molecule is a negative liquid crystal, there is almost no problem with light leakage because the direction of the short axis of the power supply coincides with the direction of the electric field. The black matrix extends 2 micrometers beyond the edge of the data line in the width direction of the data line, thus preventing light leakage.

[0037] In the study, an inventor of the present application found that the invention described in Fig. 1 and Fig. The ADS display mode used in the two display devices shown is limited by the pixel structure, and the width of a dark-field area at the location of the data line is approximately 12 micrometers, which impairs the transmittance of the display device. To reduce the width of a dark-field area, the display device can use an HADS display mode in which the width of the dark-field area is less than 12 micrometers, and if the process limits of the black matrix are taken into account, the width of the dark-field area can be reduced to 8 micrometers.

[0038] The embodiments of the present disclosure provide a display substrate and a display device. The display substrate comprises a base substrate and a plurality of data lines, a plurality of gate lines, a first electrode layer, and a plurality of transistors located on the base substrate. The plurality of data lines are arranged in a first direction, the plurality of gate lines are arranged in a second direction, and the second direction intersects the first direction. The first electrode layer is located on a side of a film layer on which the plurality of data lines are located, opposite the base substrate. Each transistor comprises a gate electrode, a first electrode, and a second electrode.The gate electrodes of the plurality of transistors are electrically connected to the plurality of gate lines, the first electrodes of the plurality of transistors are electrically connected to the plurality of data lines, and the second electrodes of the plurality of transistors are electrically connected to the first electrode layer. The plurality of gate lines are located on the side of the plurality of data lines furthest from the base substrate. The gate electrodes of the plurality of transistors are arranged on the same layer as the plurality of data lines, and an orthographic projection of the gate electrode of at least one transistor on the base substrate is spaced apart from an orthographic projection of the gate line on the base substrate that is electrically connected to the gate electrode of the at least one transistor.

[0039] In the display substrate provided in the present disclosure, the data line is located between the gate line and the base substrate, and the orthographic projection of the gate electrode of the at least one transistor is spaced apart from the orthographic projection of the gate line, so that the flatness of the film layer in the display substrate can be improved to enhance the uniformity of the film layer used for alignment and the film layer with spacers, and the transmittance of the display substrate can be improved while keeping the complexity of the manufacturing process unchanged.

[0040] The display substrate and the display device provided in the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0041] Fig. Figure 3 is a schematic diagram of a sub-level structure of a display substrate provided according to an embodiment of the present disclosure. Fig. 4 is a schematic diagram of a partial cross-sectional structure along a line in Fig. 3 shown line BB'. Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. Figure 11 are schematic diagrams of different film layers in a display substrate. Fig. 12 is a partially enlarged view of the in Fig. 3 display substrates shown. Fig. 13 is a partially enlarged view of the in Fig. 8 film layers shown. Fig. 14A is a partially enlarged view of the in Fig. 12 displayed display substrates.

[0042] Fig. 5 is a film layer in which the data line is located, Fig. Figure 6 is a partial schematic diagram of a film layer containing an active layer. Fig. 7 is a film containing the first electrode layer, Fig. 8 is a film in which the Gate line is located, Fig. Figure 9 is a partial schematic diagram of through holes, Fig. 10 is a film layer in which the second electrode layer is located, and Fig. 11 is a film layer in which the spacer is located.

[0043] As in Fig. 3 and Fig. As shown in Figure 4, the display substrate comprises a base substrate 01 and a plurality of data lines 100, a plurality of gate lines 200, a first electrode layer 310, and a plurality of transistors 400 located on the base substrate 01. The plurality of data lines 100 are arranged in a first direction, for example, an X direction, and the plurality of gate lines 200 are arranged in a second direction, for example, a Y direction, with the first direction intersecting the second direction. For example, the first direction is interchangeable with the second direction. For example, the first direction is perpendicular to the second direction. For example, the angle between the first direction and the second direction can be 80 degrees to 100 degrees.

[0044] In some examples, such as in Fig. As shown in Figure 3, the multitude of data lines 100 and the multitude of gate lines 200 intersect to define multiple pixel areas, each containing a subpixel 500. For example, the display substrate comprises a multitude of subpixels 500. These multitude of subpixels 500 are arranged in an array in the first and second directions.

[0045] As in Fig. 3 and Fig. As shown in Figure 4, the first electrode layer 310 is located on a side of a film layer furthest from the base substrate 01, on which the plurality of data lines 100 are located. For example, the first electrode layer 310 can consist of a material containing a transparent conductive material such as indium tin oxide (ITO).

[0046] In some examples, such as in Fig. 2 and Fig. As shown in Figure 7, the first electrode layer 310 comprises several spaced-apart first electrodes 311, and each of the subpixels 500 comprises one of the first electrodes 311. For example, each first electrode 311 can be a block electrode. For example, each subpixel 500 can comprise two domains. For example, the first electrode 311 can be a pixel electrode. For example, in the X direction, the distance between the first electrode 311 and the data line 100 is greater than 3 micrometers to prevent them from overlapping.

[0047] As in Fig. 3, Fig. 5, Fig. 8 and Fig. As shown in Figures 12 to 14A, each transistor 400 comprises a gate electrode 403, a first electrode 401, and a second electrode 402, wherein the gate electrodes 403 of the plurality of transistors 400 are electrically connected to the plurality of gate lines 200, the first electrodes 401 of the plurality of transistors 400 are electrically connected to the plurality of data lines 100, and the second electrodes 402 of the plurality of transistors 400 are electrically connected to the first electrode layer 310. For example, the gate line 200 controls the switching on or off of the transistor 400, and the data line 100 inputs a voltage signal required for a screen via the first electrode 311 of the transistor 400 to the subpixel 500 to realize the display of the display device, including the display substrate.

[0048] For example, one of the first electrodes 401 and one of the second electrodes 402 is a source electrode and the other is a drain electrode. For example, the transistor 400 can be a thin-film transistor, a field-effect transistor, or another switching device with the same properties. The source electrode and the drain electrode of the transistor can be structurally symmetrical, so that the source electrode and the drain electrode can be structurally similar. In one embodiment of the present disclosure, in order to distinguish two electrodes of the transistors other than the gate electrode, one of them is directly designated as the first electrode and the other as the second electrode. Therefore, the first electrode and the second electrode of all or some of the transistors in the embodiments of the present disclosure are interchangeable as required.For example, the first electrode of the transistor described in the embodiments of this disclosure can be the source electrode, and the second electrode can be the drain electrode. Alternatively, the first electrode of the transistor is the drain electrode, and the second electrode is the source electrode. Furthermore, the transistors can be classified as N-type or P-type transistors according to their characteristics. The transistors provided in the embodiments of this disclosure can be either N-type or P-type transistors, as required.

[0049] For example, in Fig. 3 and Fig. As shown in Figure 6, the transistor 400 further comprises an active layer 404 that overlaps the gate electrode 403, the first electrode 401, and the second electrode 402 of the transistor 400. In the display substrate provided in the present disclosure, the gate electrode of the transistor is located on the same layer as the data line, and the data line and the gate line are interchangeable film layers, giving the transistor a bottom-gate structure.

[0050] In some examples, such as in Fig. 3 and Fig. As shown in Figure 8, the first electrode 401 and the second electrode 402 of the transistor 400 are both located on the same layer as the multitude of gate lines 200.

[0051] As in Fig. 3 and Fig. As shown in Figure 4, the plurality of gate lines 200 are located on a side of the plurality of data lines 100 that is remote from the base substrate 01, the gate electrodes 403 of the plurality of transistors 400 are arranged on the same layer as the plurality of data lines 100, and an orthographic projection of the gate electrode 403 of the at least one transistor 400 on the base substrate 01 is spaced apart from an orthographic projection of the gate line 200 electrically connected to the gate electrode 403 of the at least one transistor 400 on the base substrate. For example, the gate electrode 403 of the at least one transistor 400 does not overlap the plurality of gate lines 200 in a direction perpendicular to the base substrate 01. For example, the gate electrode 403 of at least one transistor 400 in other transistors 400 besides the at least one transistor 400 mentioned above does not overlap parts of the plurality of gate lines 200.For example, an orthographic projection of the gate electrode of at least one of the other transistors 400, with the exception of the at least one transistor 400 mentioned above, on the substrate overlaps the orthographic projection of the gate line on the substrate.

[0052] In the display substrate provided in the present disclosure, the data line is arranged between the gate line and the base substrate, and the gate electrode of the at least one transistor is adjusted so that it does not overlap with an orthographic projection of the gate line, thereby improving the flatness of the film layer in the display substrate without increasing the complexity of the manufacturing process, which in turn increases the uniformity of a film layer used for alignment and the uniformity of a film layer provided with a spacer, and improves the transmittance of the display substrate.

[0053] In a display substrate that typically employs the HADS display mode, an organic insulating layer (ITO) is located between the data line and the electrode on the side of the data line furthest from the base substrate to increase the distance between the data line and the electrode. However, compared to the display substrate that employs the ADS display mode, the HADS display substrate increases the complexity of the organic insulating layer fabrication process.

[0054] In comparison to display devices that typically use the ADS display mode, the display substrate described in the present disclosure offers not only a large distance between the data line and the gate line film layer by replacing the data line film layer and the gate line film layer, in order to reduce the coupling capacitance between them and reduce the load on the data line, but also allows the same manufacturing process to be retained as for the display substrate that uses the ADS display mode, in order to achieve the same process complexity and improve the permeability of the display substrate.

[0055] For example, the display substrate provided in the present disclosure can be applied to a display device with a resolution of 8K. For example, a screen size of 65 inches for the display device can increase the transmittance by 24% compared to the display device using the ADS display mode. A screen size of 75 inches for the display device can increase the transmittance by 28% compared to the display device using the ADS display mode.

[0056] In some examples, such as in Fig. 3, Fig. 4, Fig. 10, Fig. 12 and Fig. As shown in Figure 14A, the display substrate further comprises a plurality of first interconnect sections 610 located on a side of the plurality of gate lines 200 remote from the base substrate 01, and the first interconnect sections 610 are configured to connect the gate electrodes 403 of the plurality of transistors 400 to the plurality of gate lines 200. At least one of the gate lines 200 comprises a plurality of protrusion structures 201. For example, each gate line 200 comprises a plurality of protrusion structures 201. For example, the plurality of protrusion structures 201 in each gate line 200 are provided in a one-to-one correspondence to a row of subpixels 500 corresponding to the gate line 200.

[0057] For example, as in Fig. Figure 13 shows that the protrusion structure 201 in the gate line 200 is part of the gate line 200, the gate line 200 comprises a linear structure extending in the X direction and protrusion structures 201 associated with the linear structure, and the protrusion structure 201 is a part that projects forward of the second electrode 402 of the transistor with respect to the linear structure. For example, in the at least one gate line 200, the plurality of protrusion structures 201 are located on the same side of the linear structure.

[0058] In some examples, such as in Fig. 3, Fig. 4, Fig. 10, Fig. 12 and Fig. As shown in Figure 14A, each protrusion structure 201 is configured to be electrically connected to the gate electrode 403 of the corresponding transistor 400 via at least one of the first connection sections 610. The embodiments of the present disclosure schematically show that a protrusion structure is electrically connected to the gate electrode of the transistor via one of the first connection sections, but are not limited thereto, and a protrusion structure can also be electrically connected to the gate electrode of a transistor via two or more of the first connection sections.

[0059] For example, as in Fig. Figure 8 shows a straight line in the X direction through the protrusion structure 201 and the first electrode 401 and the second electrode 402 of the transistor to create a compact structure. For example, the first electrode 401 and the second electrode 402 of the same transistor are located between two adjacent protrusion structures 201.

[0060] For example, in Fig. 13 and Fig. As shown in Figure 14A, the first electrode 401 of the transistor is H-shaped. For example, the first electrode 401 of the transistor comprises a first section and a second section extending in the Y direction, and a third section connecting the first and second sections, wherein at least a portion of the first section overlaps the second connecting section 620 (as described below), and at least a portion of the second section overlaps the active layer 404. The size of the first section in the Y direction is larger than the size of the second section in the Y direction, and the size of the first section in the X direction is larger than the size of the second section in the X direction. For example, the size of the first section in the X direction can be more than ten micrometers, and the size of the first section in the Y direction is larger than its size in the X direction.Configuring a small size for the second section and a large size for the first section can facilitate the reduction of parasitic capacitance while also improving the conduction effect between the first section and a through-hole.

[0061] For example, in Fig. As shown in Figure 14A, the second electrode 402 of the transistor includes a fourth section extending in the X direction and a fifth section extending in the Y direction to form a T-shaped shape.

[0062] For example, the gate electrode overlaps 403, as shown in Fig. 3 and Fig. Figure 12 shows that the protrusion structure 201 does not extend in the direction perpendicular to the base substrate 01 in order to improve the flatness of the display substrate and to prevent the uneven alignment of the film layer located on a side of the protrusion structure and the gate electrode located away from the base substrate from affecting the liquid crystal deflection during the alignment process. For example, in response to the fact that the at least one gate electrode does not overlap the protrusion structure, at least one gate electrode can be configured to overlap the protrusion structure by a larger size in order to achieve flatness at different positions of the gate electrode in order to adjust the position of the spacer.

[0063] In some examples, such as in Fig. 3 and Fig. As shown in Figure 12, the plurality of protrusion structures 201 comprise at least one first protrusion structure 210 and one second protrusion structure 220, the plurality of subpixels 500 comprise at least one first subpixel 510 and one second subpixel 520, the transistor 400, which is electrically connected to the first electrode 311 of the first subpixel 510, is a first transistor 410, and the transistor 400, which is electrically connected to the first electrode 311 of the second subpixel 520, is a second transistor 420. The gate electrode 403 of the first transistor 410 is electrically connected to the first protrusion structure 210, the gate electrode 403 of the second transistor 420 is electrically connected to the second protrusion structure 220, and the shape of the first protrusion structure 210 differs from the shape of the second protrusion structure 220.

[0064] The display substrate provided in the present disclosure is configured such that the shape of the first protrusion structure and the second protrusion structure differ in order to match the shape of the spacer.

[0065] In some examples, such as in Fig. 3 and Fig. 11, Fig. 12 to Fig. As shown in Figure 13, the first protrusion structure 210 has a larger area than the second protrusion structure 220.

[0066] In some examples, such as in Fig. 3 and Fig. As shown in Figure 12, the display substrate further comprises a spacer (PS) 700 located on a side of the first electrode layer 310 away from the base substrate 01, wherein an orthographic projection of the spacer 700 on the base substrate 01 overlaps an orthographic projection of the first protrusion structure 210 and an orthographic projection of the gate electrode 403 on the base substrate 01, which is electrically connected to the first protrusion structure 210, and the dimensions of the spacer 700 are larger than those of the second protrusion structure 220 in both the first and second directions.

[0067] For example, as in Fig. 3 and Fig. Figure 12 shows that more than 50 percent of the area of ​​the orthographic projection of the spacer 700 on the base substrate 01 falls within the orthographic projection of the first protrusion structure 210 and the gate electrode 403 on the base substrate 01. For example, more than 80 percent of the orthographic projection of the spacer 700 on the base substrate 01 falls within the orthographic projection of the first protrusion structure 210 and the gate electrode 403 on the base substrate 01. For example, more than 90 percent of the orthographic projection of the spacer 700 on the base substrate 01 falls within the orthographic projection of the first protrusion structure 210 and the gate electrode 403 on the base substrate 01. For example, less than 50 percent of the orthographic projection of the spacer 700 on the base substrate 01 falls within the orthographic projection of the gate electrode 403 onto the base substrate 01.For example, less than 40 percent of the orthographic projection of the spacer 700 on the base substrate 01 coincides with the orthographic projection of the gate electrode 403 on the base substrate 01. For example, the orthographic projection of the spacer 700 on the base substrate 01 does not overlap the orthographic projection of the second protrusion structure 220 on the base substrate 01.

[0068] Due to the large size of the spacer, by setting the first protrusion structure with a larger area than that of the second protrusion structure, a large part of the spacer can overlap with the first protrusion structure, and a small part of the spacer can overlap with the gate electrode, thereby improving the flatness of the film layer between the spacer and the base substrate without affecting transistor performance and color rendering.

[0069] For example, in Fig. As shown in Figure 3, the multitude of subpixels 500 comprises a red subpixel, a green subpixel, and a blue subpixel, where the first subpixel 510 can be a red subpixel and the second subpixel 520 can be either a green or a blue subpixel to comprehensively accommodate the aperture rate and color temperature of the display substrate. For example, the gate electrodes of the transistors of subpixels of the same color do not overlap with the gate trace. For example, the gate electrodes of the transistors of the red subpixels do not overlap with the gate trace. For example, the gate electrodes of the transistors of the respective subpixels do not overlap with the gate trace.

[0070] For example, as in Fig. Figure 11 shows a plurality of spacers 700, and each red subpixel is provided with a spacer, and the plurality of spacers 700 are evenly spaced from each other. For example, the plurality of spacers 700 can have the same shape, but they are not limited to this, and the plurality of spacers can also include spacers of different shapes, for example, primary and auxiliary spacers, where the primary spacer has a larger volume than the auxiliary spacer and the number of primary spacers is less than the number of auxiliary spacers.

[0071] In some examples, such as in Fig. 13 and Fig. As shown in Figure 14A, the first projection structure 210 comprises a first subprojection structure 211 and a second subprojection structure 212, and the first subprojection structure 211 and the second projection structure 220 have substantially the same shape and are substantially the same size. For example, the first subprojection structure 211 and the second subprojection structure 212 are integrated structures. For example, the first subprojection structure 211 and the second projection structure 220 have a polygonal shape. For example, both the first subprojection structure 211 and the second projection structure 220 have a rectangular shape, such as a standard rectangle, a rounded rectangle, a chamfered rectangle, or the like.

[0072] For example, the first connecting section overlaps 610, as shown in Fig. Figure 14A shows the second undercut structure 212 not in the direction perpendicular to the base substrate 01 in order to improve the flatness of the film layer between the spacer and the base substrate.

[0073] For example, the second underprojection structure 212 has a different shape than the first underprojection structure 211. For example, the second underprojection structure 212 has a polygonal shape. For example, the second underprojection structure 212 has a rectangular shape, such as a standard rectangle, a rounded rectangle, a chamfered rectangle, or the like.

[0074] In some examples, such as in Fig. As shown in Figure 14A, the second sub-protrusion structure 212 is located on a side of the first sub-protrusion structure 211 that is remote from the gate electrode 403, which is electrically connected to the first sub-protrusion structure 211. For example, the second sub-protrusion structure 212 is located between the first sub-protrusion structure 211 and the data line 100, which is closest to the first sub-protrusion structure 211.

[0075] In some examples, such as in Fig. As shown in Figure 14A, in the second direction the size of the second underprotrusion structure 212 is larger than that of the first underprotrusion structure 211.

[0076] As in Fig. As shown in Figure 14A, for example, a straight line runs in the X direction through the gate electrode 403 and the second subprotrusion structure 212. For example, the size of the first protrusion structure 210 in the X direction is larger than the size of the spacer 700 in the X direction, and the size of the second subprotrusion structure 212 in the Y direction is larger than the size of the spacer 700 in the Y direction.

[0077] In the display substrate provided in the present disclosure, adjusting the size ratio and position ratio of the first protrusion structure and the spacer facilitates the improvement of the flatness of the film layer between the spacer and the base substrate without affecting the transistor performance and the display color.

[0078] For example, in Fig. 3 and Fig. As shown in Figure 12, the distance D4 between the gate electrode 403 of the first transistor 410 and the data line 100, located to its right, is greater than the distance D5 between the gate electrode 403 of the second transistor 420 and the data line 100, located to its right. Therefore, the second sub-projection structure 212 is positioned between the gate electrode 403 of the first transistor 410 and the data line 100, and a spacer is placed on the first sub-projection structure. The arrow in the X direction points to the right, and the arrow in the Y direction points upwards.

[0079] In some examples, such as in Fig. 3 and Fig. As shown in Figure 12, in the first direction, the ratio of the distance between the first protrusion structure 210 and its nearest data line 100 to the distance between the second protrusion structure 220 and its nearest data line 100 lies in the range of 0.8 to 1.2. For example, in the first direction, the ratio of the distance between the first protrusion structure 210 and its nearest data line 100 to the distance between the second protrusion structure 220 and its nearest data line 100 lies in the range of 0.9 to 1.1. In the first direction, the distance between the first protrusion structure 210 and its nearest data line 100 is equal to the distance between the second protrusion structure 220 and its nearest data line 100.For example, the data line 100 closest to the first protrusion structure 210 can be the data line 100 on a side of the first protrusion structure furthest from the corresponding gate electrode 403, and the data line 100 closest to the second protrusion structure 220 can be the data line 100 on a side of the second protrusion structure furthest from the corresponding gate electrode 403.

[0080] In the display substrate provided in the present disclosure, the first protrusion structure and the second protrusion structure are of different sizes in the first direction, but the distance between the first protrusion structure and the data line is approximately equal to the distance between the second protrusion structure and the data line, which helps to minimize the influence of the difference in the protrusion structure on the subpixels of different colors.

[0081] In some examples, such as in Fig. As shown in Figure 3, the data line 100 closest to the first protrusion structure 220 is shaped differently than the data line 100 closest to the second protrusion structure 220. For example, the data line 100 closest to the first protrusion structure 210 is a first sub-data line 1001, and the data line 100 closest to the second protrusion structure 220 is a second sub-data line 1002.The subpixels 500 provided in the X direction form a row of subpixels, wherein the shape of a section between two adjacent subpixels 500 in the same row of the first subdata line 1001 corresponds approximately to the shape of a section between two adjacent subpixels 500 in the same row of the second subdata line 1002, and the shape of a section between subpixels 500 in adjacent rows of the first subdata line 1001 differs from the shape of a section between subpixels 500 in adjacent rows of the second subdata line 1002 in order to adapt the shape of the data line to the shapes of the first protrusion structure and the second protrusion structure without affecting the opening rate.

[0082] In some examples, such as in Fig. 5 and Fig. Figure 12 shows two data lines 100 located on either side of the first protrusion structure 210, a first data line 110 and a second data line 120, two data lines 100 located on either side of the second protrusion structure 220, the second data line 120 and a third data line 130 or the first data line 110 and a third data line 130, and the first data line 110 or the second data line 120 is located between the first protrusion structure 210 and the second protrusion structure 220, and the first data line 110, the second data line 120 and the third data line 130 have different shapes.

[0083] For example, as in Fig. 3 and Fig. Figure 5 shows that the shape of a section 111 of the first data line 110, which is located between two adjacent subpixels 500 in the same row, the shape of a section 121 of the second data line 120, which is located between two adjacent subpixels 500 in the same row, and the shape of a section 131 of the third data line 130, which is located between two adjacent subpixels 500 in the same row, are all approximately the same, and the shape of a section 112 of the first data line 110, which is located between subpixels 500 in adjacent rows, the shape of a section 122 of the second data line 120, which is located between adjacent subpixels 500 in adjacent rows, and the shape of a section 132 of the third data line 130, which is located between adjacent subpixels 500 in adjacent rows, are all different.so that the shape of the data line adapts to the shapes of the first protrusion structure and the second protrusion structure without affecting the open rate.

[0084] In some examples, such as in Fig. 5 and Fig. As shown in Figure 12, the first data line 110 and the second data line 120 are bent away from the first protrusion 210 on both sides at positions corresponding to the first protrusion structure 210. For example, the segments of the first data line 110 and the segments of the second data line 120 between subpixels 500 in adjacent rows are each bent away from the first protrusion structure 210 on both sides. For example, data line 100, located to the right of the first protrusion structure 210, is bent to the right, and data line 100, located to the left of the first protrusion structure 210, is bent to the left. By bending the segments of the first and second data lines between adjacent rows of subpixels away from the first protrusion structure on both sides, the first protrusion structure and the spacer can be bypassed.

[0085] In some examples, such as in Fig. As shown in Figure 12, the distance between the first data line 110 and the gate electrode 403 nearest to the first data line 110 is a first distance D1, the distance between the second data line 120 and the gate electrode 403 nearest to the second data line 120 is a second distance D2, the distance between the third data line 130 and the gate electrode 403 nearest to the third data line 130 is a third distance D3, and the ratio of the first distance D1, the second distance D2, and the third distance D3 is (0.8 - 1.2):(0.8 - 1.2):(0.8 - 1.2). For example, the ratio of the first distance D1, the second distance D2, and the third distance D3 is (0.9 - 1.1):(0.9 - 1.1):(0.9 - 1.1). For example, the first distance D1, the second distance D2 and the third distance D3 are essentially the same.

[0086] In the display substrate provided in the present disclosure, the first data line, the second data line and the third data line are shaped differently, but the configuration of the first spacing, the second spacing and the third spacing as being substantially equal can help to minimize the influence of the difference in the protrusion structure on the subpixels of different colors.

[0087] In some examples, such as in Fig. 3, Fig. 5, Fig. 8 and Fig. As shown in Figure 12, the shape of the gate electrode 403 of the first transistor 410 is approximately the same as that of the gate electrode 403 of the second transistor 420, the shape of the first electrode 401 of the first transistor 410 is approximately the same as that of the first electrode 401 of the second transistor 420, and the shape of the second electrode 402 of the first transistor 410 is approximately the same as that of the second electrode 402 of the second transistor 420. Configuring the shapes of the respective electrodes of the first and second transistors to be approximately the same does not increase the complexity of the process.

[0088] In some examples, such as in Fig. As shown in Figure 12, the ratio of the distance between the gate electrode 403 of the first transistor 410 and the data line 100 electrically connected to the first transistor 410 to the distance between the gate electrode 403 of the second transistor 420 and the data line 100 electrically connected to the second transistor 420 lies in the range of 0.8 to 1.2. For example, the ratio of the second distance D2 to the first distance D1 lies in the range of 0.8 to 1.2, or the ratio of the second distance D2 to the third distance D3 lies in the range of 0.8 to 1.2. For example, the ratio of the distance between the gate electrode 403 of the first transistor 410 and the data line 100 electrically connected to the first transistor 410 to the distance between the gate electrode 403 of the second transistor 420 and the data line 100 electrically connected to the second transistor 420 is in a range of 0.9 to 1.1.The distance between the gate electrode 403 of the first transistor 410 and the data line 100, which is electrically connected to the first transistor 410, is approximately equal to the distance between the gate electrode 403 of the second transistor 420 and the data line 100, which is electrically connected to the second transistor 420.

[0089] In the display substrate provided in the present disclosure, the shape of the respective electrodes of the first transistor and the second transistor are set to be approximately the same, and the shape of the data line electrically connected to the first transistor is set differently from the shape of the data line electrically connected to the second transistor. Setting the distance between the gate electrode of the first transistor and the data line to be approximately the same as the distance between the gate electrode of the second transistor and the data line can facilitate the minimization of the influence of the difference in the protrusion structure on the subpixels of different colors.

[0090] For example, in Fig. 5 and Fig. As shown in Figure 12, the first data line 110, the second data line 120, and the third data line 130 are arranged cyclically in the X direction. For example, the distance L1 between two sections of the first data line 110 and the second data line 120 arranged between subpixels 500 in adjacent rows is greater than the distance L2 between two sections of the first data line 110 and the third data line 130 arranged between subpixels 500 in adjacent rows, and greater than the distance L3 between two sections of the second data line 120 and the third data line 130 arranged between subpixels 500 in adjacent rows. For example, L2 and L3 are essentially equal. The ratio of L1 to L2 should not be too large to prevent at least one of the first data line and the second data line from having excessively high resistance.For example, the ratio of L1 to L2 is not greater than 1.5, for example, not greater than 1.4, for example, not greater than 1.3, and for example, not greater than 1.2. The distances L1, L2, and L3 are the distances between the edges of two data lines that are close together.

[0091] For example, as in Fig. Figure 5 shows a plurality of gate electrodes 403 of the plurality of transistors arranged unevenly to adapt the positions of the gate electrode, the protrusion structure and the data line.

[0092] In some examples, such as in Fig. 3, Fig. 4 and Fig. As shown in Figure 10, the display substrate further comprises a second electrode layer 320, wherein the second electrode layer 320 is located on the same layer as the plurality of first interconnect sections 610. For example, the second electrode layer 320 can be made of a transparent conductive material such as indium tin oxide (ITO). For example, the second electrode layer 320 comprises a second electrode located in each subpixel and an interconnect section that is connected to adjacent second electrodes, wherein the second electrode is located in an emitting region of the subpixel and the interconnect section is located in a non-emitting region.

[0093] In some examples, such as in Fig. 3, Fig. 4 and Fig. As shown in Figure 10, the multitude of subpixels 500 share the second electrode layer 320, and the second electrode layer 320 can be a common electrode.

[0094] In some examples, such as in Fig. 3, Fig. 4 and Fig. As shown in Figure 10, the second electrode layer 320 comprises a plurality of strip electrodes that overlap the first electrode layer 310 in the direction perpendicular to the base substrate 01. For example, the second electrode layer 320 is stacked with the first electrode layer 310 to form a capacitor. The first electrode layer 310 is located between the film layer containing the plurality of gate lines 200 and the film layer containing the plurality of data lines 100, and the data lines 100 overlap the second electrode layer 320 in the direction perpendicular to the base substrate 01.

[0095] For example, in Fig. 3, Fig. 4 and Fig. As shown in Figure 10, the second electrode layer 320 comprises a strip electrode with a conductor width of 2.2 micrometers, and adjacent strip electrodes can be spaced 5.4 micrometers apart. For example, the size of the second electrode layer 320 extending beyond an edge of the data line 100 can be greater than 1.5 micrometers to ensure that the second electrode layer 320 can still cover the data line 100 even under process variations. For example, the shortest distance between an edge of a section where the second electrode layer 320 covers the data line 100 and an edge of the data line 100 is similar to the conductor width of the strip electrode. For example, the ratio between these two values ​​can be 0.9 to 1.1.For example, the shortest distance can be 2.1 micrometers, which not only allows for the best lighting design but also avoids the problem of color overlap at oblique angles below the minimum size of the black matrix. For example, the width of a shading section between adjacent openings in the black matrix can be 8 micrometers.

[0096] By placing the data line between the gate line and the base substrate, the parasitic capacitance between the data line and the second electrode layer can be reduced.

[0097] For example, in Fig. 3, Fig. 8 and Fig. As shown in Figure 9, the display substrate further comprises a common electrode 910, wherein the common electrode 910 is electrically connected to the second electrode layer 320 via a through-hole 804. For example, the common electrode 910 is located on the same layer as the gate line 200. For example, the common electrode 910 and the gate lines 200 are arranged alternately in the Y direction.

[0098] In some examples, such as in Fig. 3, Fig. 10 and Fig. As shown in Figure 14A, the display substrate further comprises a plurality of second interconnect sections 620, wherein the plurality of second interconnect sections 620 are arranged on the same layer as the plurality of first interconnect sections 610 and are configured to connect the first electrodes 401 of the plurality of transistors 400 to the corresponding data lines 100. For example, the second interconnect section 620 does not overlap the gate electrode 403 of the transistor in the direction perpendicular to the base substrate 01 in order to improve the flatness of the base substrate. For example, the size of the first interconnect section 610 in the Y direction is larger than the size of the second interconnect section 620 in the Y direction.

[0099] In some examples, such as in Fig. 3, Fig. 4, Fig. 9 and Fig. As shown in Figure 14A, the display substrate further comprises an insulating layer 800, wherein the insulating layer 800 is located between the plurality of second interconnection sections 620 and the base substrate 01, for example between the second electrode layer 320 and the base substrate 01. The insulating layer 800 comprises a plurality of first through-holes 801, and the first electrode 401 of the transistor 400 and the data line 100 electrically connected thereto are connected to the same second interconnection section 620 via the same first through-hole 801.

[0100] Fig. 14B is a sectional view along the in Fig. Line DD' shown in 14A. As for example in Fig. As shown in Figure 14B, the first electrode 401 of the transistor 400 does not overlap the data line 100 in the direction perpendicular to the base substrate 01, in order to prevent the second connection section 620 from rising in the first through-hole 801, which could impair electrical conductivity. Of course, the embodiments of the present disclosure are not limited to this, and the first electrode of the transistor and the data line can be electrically connected via two different through-holes. Alternatively, the first electrode of the transistor overlaps the data line in the direction perpendicular to the base substrate, and they are electrically connected via a through-hole that penetrates the intermediate insulating layer.

[0101] For example, in Fig. As shown in Figure 14A, taking into account the overlap resistance of the first via 801, the size of an overlap section between the first via 801 and the data line 100 is greater than 3 micrometers, for example, greater than 4 micrometers. For example, the size of the first via 801 can be 8 micrometers. If the first via 801 is a circular hole, the diameter of the circular hole is 8 micrometers, and if the first via 801 is a strip hole, the length of the strip hole is 8 micrometers. For example, the size of the second interconnect section 620 extending beyond an edge of the first via 801 can be 3 micrometers, for example, 4 micrometers, and so on.

[0102] For example, the first connecting section comprises 610, as in Fig. Figure 14A shows two edges extending in the second direction, wherein the first connecting section 610 covers an edge of the gate line 403 extending in the second direction, one of the two edges of the first connecting section 610 protrudes with respect to the edge of the gate electrode 403, the first connecting section 610 covers an edge of the first subprojection structure 211 extending in the second direction, and the other of the two edges of the first connecting section 610 protrudes opposite the edge of the first subprojection structure 211.For example, an edge extending in the Y direction on the right side of the first connecting section 610 is further from the geometric center of the gate electrode 403 than an edge extending in the Y direction on the right side of the gate electrode 403, and an edge extending in the Y direction on the left side of the first connecting section 610 is further from the geometric center of the first underprojection structure 211 than an edge extending in the Y direction on the left side of the first underprojection structure 211, in order to ensure the electrical interconnection effect of a second through hole and a third through hole.

[0103] In some examples, such as in Fig. 3, Fig. 4, Fig. 9 and Fig. As shown in Figure 14A, the display substrate further comprises an insulating layer 800, wherein the insulating layer 800 is located between the plurality of first connection sections 610 and the base substrate 01, for example between the second electrode layer 320 and the base substrate 01. The insulating layer 800 comprises a second through-hole 802 and a third through-hole 803, wherein the first connection section 610 is connected to the gate electrode 403 of the transistor 400 via the second through-hole 802 and the first connection section 610 is connected to the protrusion structure 201 via the third through-hole 803.

[0104] For example, the insulating layer comprises 800, as in Fig. Figure 4 shows a first insulating layer 810 located between the first electrode layer 310 and the data line 100, a second insulating layer 820 located between the gate line 200 and the first electrode layer 310, and a third insulating layer 830 located between the second electrode layer 320 and the gate line 200. The first connecting section 610 is electrically connected to the gate electrode 403 of the transistor via the second through-hole 802, which penetrates the first insulating layer 810, the second insulating layer 820, and the third insulating layer 830, and the first connecting section 610 is electrically connected to the gate line 200 via the third through-hole 803, which penetrates the third insulating layer 830.For example, part of the second connection section 620 is electrically connected to the data line 100 via a portion of the first through-hole 801, which penetrates the first insulating layer 810, the second insulating layer 820, and the third insulating layer 830. Another portion of the second connection section 620 is electrically connected to the first electrode 401 of the transistor via another portion of the first through-hole 801, which also penetrates the third insulating layer 830. The dimensions of the second and third through-holes can be determined with reference to the dimensions of the first through-hole.

[0105] Fig. Figure 15 is a schematic block diagram of a display device provided according to an embodiment of the present disclosure.

[0106] As in Fig.Figure 15 shows a display device which, in another embodiment of the present disclosure, comprises the display substrate provided in one of the above examples.

[0107] In some examples, the display device has a resolution of 8k. However, this is not limited, and the display device can also have other resolutions, such as a resolution of 16k or the like.

[0108] For example, the display device can be a liquid crystal display device. For example, the display substrate described above can be an array substrate, and the display device can further comprise an opposing substrate provided opposite the display substrate. For example, the opposing substrate can comprise a black matrix as well as a color film layer. For example, the display device can also comprise a liquid crystal layer located between the array base substrate and the opposing substrate.

[0109] The following statements should be noted: (1) The accompanying drawings relate only to the structure(s) associated with the embodiment(s) of the present disclosure, and other structures may refer to common designs. (2) If there are no conflicts, features of one embodiment or of different embodiments may be combined.

[0110] The above-described embodiments are only specific embodiments of the present disclosure; the scope of protection of the present disclosure is not limited thereto. The scope of protection of the present disclosure should be based on the scope of protection of the claims. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] CN 202310594994.3

[0001]

Claims

[1] Display substrate, comprising: a base substrate; a plurality of data lines located on the base substrate, wherein the plurality of data lines are arranged in a first direction; a multitude of gate lines located on the base substrate, wherein the multitude of gate lines are arranged in a second direction, and the second direction intersects the first direction; a first electrode layer located on a side of a film layer away from the base substrate, on which the multitude of data lines are located; a plurality of transistors located on the base substrate, each of the plurality of transistors comprising a gate electrode, a first electrode and a second electrode, with gate electrodes of the plurality of transistors being electrically connected to the plurality of gate lines, first electrodes of the plurality of transistors being electrically connected to the plurality of data lines and second electrodes of the plurality of transistors being electrically connected to the first electrode layer; wherein the plurality of gate lines are located on a side of the plurality of data lines away from the base substrate, wherein the gate electrodes of the plurality of transistors are arranged on the same layer as the plurality of data lines, and an orthographic projection of the gate electrode of at least one transistor on the base substrate is spaced apart from an orthographic projection of a gate line electrically connected to the gate electrode of the at least one transistor on the base substrate. [2] Display substrate according to claim 1, further comprising: a plurality of subpixels, wherein the first electrode layer comprises a plurality of first electrodes spaced at intervals, and each subpixel comprises one of the plurality of first electrodes; a multitude of first interconnect sections located on a side of the multitude of gate lines away from the base substrate, and configured to connect the gate electrodes of the multitude of transistors to the multitude of gate lines; wherein at least one gate line comprises a plurality of protrusion structures, each protrusion structure being configured to be electrically connected to the gate electrode of a corresponding transistor via at least one of the plurality of first connection sections, and the plurality of protrusion structures comprising at least one first protrusion structure and one second protrusion structure; The plurality of subpixels comprises at least a first subpixel and a second subpixel, wherein a transistor electrically connected to the first electrode of the first subpixel is a first transistor, a transistor electrically connected to the first electrode of the second subpixel is a second transistor, the gate electrode of the first transistor is electrically connected to the first protrusion structure, the gate electrode of the second transistor is electrically connected to the second protrusion structure, and the shape of the first protrusion structure differs from the shape of the second protrusion structure. [3] Display substrate according to claim 2, wherein the area of ​​the first projection structure is larger than that of the second projection structure. [4] Display substrate according to claim 2 or 3, wherein the first projection structure comprises a first sub-projection structure and a second sub-projection structure, and the first sub-projection structure and the second projection structure have substantially the same shape and size. [5] Display substrate according to claim 4, wherein the second sub-projection structure is located on a side of the first sub-projection structure that is remote from the gate electrode electrically connected to the first sub-projection structure. [6] Display substrate according to claim 5, wherein in the second direction the size of the second subprojection structure is larger than the size of the first subprojection structure. [7] Display substrate according to one of claims 2 to 6, wherein in the first direction the ratio of a distance between the first protrusion structure and a data line nearest to the first protrusion structure to a distance between the second protrusion structure and a data line nearest to the second protrusion structure is in a range of 0.8 to 1.

2. [8] Display substrate according to any one of claims 2 to 7, wherein the data line closest to the first protrusion structure has a different shape than the data line closest to the second protrusion structure. [9] Display substrate according to claim 8, wherein two data lines located on both sides of the first protrusion structure comprise a first data line and a second data line, two data lines located on both sides of the second protrusion structure comprise the second data line and a third data line or the first data line and a third data line, and the second data line or the first data line is located between the first protrusion structure and the second protrusion structure, and the first data line, the second data line and the third data line have different shapes. [10] Display substrate according to claim 9, wherein the first data line and the second data line are bent away from the first protrusion structure to two sides at positions corresponding to the first protrusion structure. [11] Display substrate according to claim 9 or 10, wherein a distance between the first data line and one of the gate electrodes nearest to the first data line is a first distance, a distance between the second data line and one of the gate electrodes nearest to the second data line is a second distance, a distance between the third data line and one of the gate electrodes nearest to the third data line is a third distance, and the ratio of the first distance, the second distance and the third distance is (0.8~1.2): (0.8~1.2): (0.8~1.2). [12] Display substrate according to claim 2, wherein the shape of the gate electrode of the first transistor is substantially the same as the shape of the gate electrode of the second transistor, the shape of the first electrode of the first transistor is substantially the same as the shape of the first electrode of the second transistor, and the shape of the second electrode of the first transistor is substantially the same as the shape of the second electrode of the second transistor; and the ratio of a distance between the gate electrode of the first transistor and a data line electrically connected to the first transistor to a distance between the gate electrode of the second transistor and a data line electrically connected to the second transistor is in the range of 0.8 to 1.

2. [13] Display substrate according to any one of claims 2 to 12, further comprising: a spacer located on a side of the first electrode layer furthest from the base substrate, wherein an orthographic projection of the spacer on the base substrate overlaps orthographic projections of the first protrusion structure and the gate electrode electrically connected to the first protrusion structure on the base substrate, and the sizes of the spacer are larger than those of the second protrusion structure in both the first and second directions. [14] Display substrate according to any one of claims 1 to 13, wherein the first electrodes and the second electrodes of the plurality of transistors are arranged on the same layer as the plurality of gate lines. [15] Display substrate according to any one of claims 2 to 13, further comprising: a second electrode layer located on the same layer as the plurality of first interconnect sections, wherein the plurality of subpixels share the second electrode layer, and the second electrode layer comprises a plurality of strip electrodes that overlap the first electrode layer in a direction perpendicular to the base substrate, wherein the first electrode layer is located between a film layer containing the plurality of gate lines and the film layer containing the plurality of data lines, and the plurality of data lines overlap the second electrode layer in a direction perpendicular to the base substrate. [16] Display substrate according to any one of claims 2 to 13, further comprising: a multitude of second interconnect sections located on the same layer as the multitude of first interconnect sections and configured to connect the first electrodes of the multitude of transistors to corresponding data lines. [17] Display substrate according to claim 16, further comprising: an insulating layer located between the multitude of second connection sections and the base substrate, wherein the insulating layer comprises a plurality of first through-holes, and the first electrode of the transistor and a data line electrically connected to the first electrode of the transistor are connected to the same second connecting section via the same first through-hole. [18] Display substrate according to claim 2, further comprising: an insulating layer located between the multitude of first connection sections and the base substrate, wherein the insulating layer comprises a second through-hole and a third through-hole, the first connecting section is connected to the gate electrode of the transistor via the second through-hole, and the first connecting section is connected to the protrusion structure via the third through-hole. [19] Display device comprising the display substrate according to any one of claims 1 to 18. [20] Display device according to claim 19, wherein the display device has a resolution of 8k.

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