ARRAY SUBSTANT, DISPLAY FIELD AND DISPLAY DEVICE

Abstract

An array substrate. The array substrate comprises a substrate, multiple pixel circuits, a first wiring layer, a bridge wire layer, and a second wiring layer. The first wiring layer includes a first initialization signal line, a second initialization signal line, and a third initialization signal line. Each row of pixel circuits is electrically connected to a first initialization signal line, a second initialization signal line, and a third initialization signal line. The bridge wire layer includes multiple columns of adapter blocks and multiple first fan-out lines. The second wiring layer includes multiple interconnect lines, multiple data lines, and multiple second fan-out lines.Each connecting line is electrically connected via a column of adapter blocks to at least one of the multiple first initialization signal lines, one of the multiple second initialization signal lines, and one of the multiple third initialization signal lines. The multiple data lines comprise multiple first data lines, with the first data lines located in the display area and one end of the second fan-out line extending into the fan-out area. Each first fan-out line is electrically connected to one first data line and one second fan-out line.

Description

[0001] This application claims priority over Chinese patent application No. 202310629298.1, filed on May 30, 2023, the full contents of which are hereby incorporated by reference. Technical field

[0002] The present disclosure relates to the field of display technology and in particular to an array substrate, a display field and a display device. State of the art

[0003] Organic light-emitting diode (OLED) displays have gradually become a mainstream product in the display field due to their outstanding performance, including self-illuminating properties, no backlighting required, high contrast, low profile, wide viewing angle, fast response time, compatibility with flexible panels, wide operating temperature range, and simple structure and manufacturing processes. OLED displays are widely used in end-user products such as smartphones, tablets, televisions, and wearable devices (like watches). High pixel density (pixels per inch, PPI) and narrow bezels are currently key development trends for OLED displays. Disclosure of the invention

[0004] In one aspect of the present disclosure, an array substrate is provided. The array substrate has a display area and a fan-out area, the fan-out area being adjacent to a side edge of the display area. The array substrate comprises a substrate, multiple pixel circuits, a first wiring layer, a bridge wire layer, and a second wiring layer. The multiple pixel circuits are arranged on the substrate in multiple rows and columns. The first wiring layer is located on the side of the multiple pixel circuits facing away from the substrate and comprises multiple first initialization signal lines, multiple second initialization signal lines, and multiple third initialization signal lines extending along a first direction, the first direction being the row direction in which the multiple subpixels are arranged.Each row of pixel circuits is electrically connected to one of the first initialization signal lines, one of the second initialization signal lines, and one of the third initialization signal lines. The bridge wire layer is located on the side of the first wiring layer facing away from the substrate and comprises multiple columns of adapter blocks and multiple first fan-out lines. Each column of adapter blocks comprises multiple adapter blocks spaced along a second direction. The multiple first fan-out lines run along the first direction, with the second direction being the row direction in which the multiple pixel circuits are arranged. The second wiring layer is located on the side of the bridge wire layer facing away from the substrate and comprises multiple interconnect lines, multiple data lines, and multiple second fan-out lines extending along the second direction.Each of the interconnect lines is electrically connected via a column of adapter blocks to at least one of the multiple first initialization signal lines, one of the multiple second initialization signal lines, and one of the multiple third initialization signal lines. Each of the data lines is electrically connected to a column of pixel circuits. The multiple data lines comprise multiple first data lines, with the fan-out endpoints of the first data lines located within the display area. The fan-out endpoints of the second fan-out lines extend into the fan-out area. Each of the first fan-out lines is electrically connected to one of the first data lines and to one of the second fan-out lines.

[0005] In some embodiments, both ends of at least one of the adapter blocks are electrically connected along the first direction to the first initialization signal line, the second initialization signal line, or the third initialization signal line.

[0006] In some embodiments, at least one of the adapter blocks is arranged symmetrically around the connecting line to which it is electrically connected. The adapter block comprises a first, a second, and a third subsection. The orthographic projection of the first subsection on the substrate partially overlaps with the orthographic projection of the connecting line on the substrate, and the first subsection is electrically connected to the connecting line. The second subsection extends along the first direction, is connected to the first subsection, and is arranged symmetrically around a center line of the first subsection along the first direction. The third subsection is connected to the end of the second subsection opposite the first subsection. The third subsection is larger than the second subsection along the second direction.The third subsection is electrically connected to the first initialization signal line, the second initialization signal line, or the third initialization signal line.

[0007] In some embodiments, the multiple adapter blocks comprise multiple columns of first adapter blocks, multiple columns of second adapter blocks, and multiple columns of third adapter blocks spaced apart along the first direction. Each column of first adapter blocks comprises multiple first adapter blocks spaced apart along the second direction, with each of the multiple first adapter blocks in the column being electrically connected to the multiple first initialization signal lines. Each column of second adapter blocks comprises multiple second adapter blocks spaced apart along the second direction, with each of the multiple second adapter blocks in the column being electrically connected to the multiple second initialization signal lines.Each column of third adapter blocks comprises multiple third adapter blocks spaced along the second direction, with each of the multiple third adapter blocks in the column electrically connected to the multiple third initialization signal lines. The multiple connection lines comprise multiple first connection lines, multiple second connection lines, and multiple third connection lines. Each of the first connection lines is electrically connected to a column of first adapter blocks, each of the second connection lines is electrically connected to a column of second adapter blocks, and each of the third connection lines is electrically connected to a column of third adapter blocks.

[0008] In some embodiments, the dimension of the first adapter block is larger along the first direction than the dimension of the second adapter block, and the dimension of the second adapter block is larger along the first direction than the dimension of the third adapter block.

[0009] In some embodiments, the first adapter blocks, the second adapter blocks and the third adapter blocks are arranged periodically along the first direction, and the first, second and third connecting lines are arranged periodically along the first direction.

[0010] In some embodiments, the array substrate further comprises a first source-drain conductive layer. The first source-drain conductive layer is located between the first wiring layer and the bridge wire layer and comprises multiple first connection patterns, multiple second connection patterns, and multiple third connection patterns.

[0011] Each of the first connection patterns comprises a first and a second subpattern. The first subpattern is electrically connected to the first initialization signal line and the pixel circuit; the second subpattern is electrically connected to the first adapter block. Each of the second connection patterns comprises a third and a fourth subpattern. The third subpattern is electrically connected to the second initialization signal line and the pixel circuit; the fourth subpattern is electrically connected to the second adapter block. Each of the third connection patterns comprises a fifth and a sixth subpattern. The fifth subpattern is electrically connected to the third initialization signal line and the pixel circuit; the sixth subpattern is electrically connected to the third adapter block.

[0012] In some embodiments, the first source-drain conductive layer additionally comprises a fourth, a fifth, and a sixth interconnection pattern. The fourth interconnection pattern has the same shape and dimensions as the first subpattern and is electrically connected to the first initialization signal line and the pixel circuit. The fifth interconnection pattern has the same shape and dimensions as the third subpattern and is electrically connected to the second initialization signal line and the pixel circuit. The sixth interconnection pattern has the same shape and dimensions as the fifth subpattern and is electrically connected to the third initialization signal line and the pixel circuit.

[0013] In some embodiments, the second fan-out conduit includes a first opening that divides the second fan-out conduit into a first and a second wiring segment. One end of the first wiring segment extends to the fan-out area, and the other end extends to and is electrically connected to the first fan-out conduit. The second wiring segment is located on the side of the first wiring segment facing away from the fan-out area and is electrically insulated from the first wiring segment.

[0014] In some embodiments, the second fan-out line comprises several first widened sections and several first extended sections arranged alternately along the second direction. The first widened sections are offset relative to the first fan-out line along the second direction. The bridge wire layer also comprises a first connecting segment, one end of which is electrically connected to the first fan-out line and the other end of which is electrically connected to the first widened section of the first wiring segment that is closest to the first fan-out line.

[0015] In some embodiments, the connecting cable comprises several second widened sections and several second extended sections arranged alternately along the second direction. Along the first direction, the second widened section is larger than the second extended section, and the second widened section is electrically connected to the adapter block.

[0016] In some embodiments, the first fan-out line comprises a second and a third opening. The second opening is located on the side of the first interconnect segment facing away from the first data line, which is electrically connected to the first fan-out line. The orthographic projection of the second opening on the substrate overlaps at least partially with the orthographic projection of one of the data lines on the substrate. The third opening is located on the side of the first data line facing away from the second fan-out line, which is electrically connected to the first fan-out line. The orthographic projection of the third opening on the substrate overlaps partially with the orthographic projection of one of the interconnect lines on the substrate.

[0017] In some embodiments, the bridge wire layer also includes multiple columns of matching patterns and a second interconnect segment. Each column contains multiple matching patterns spaced along the second direction. Each of the multiple matching patterns in the column is electrically connected to the multiple pixel circuits in that column and also electrically to a data line. One end of the second interconnect segment is electrically connected to the first fan-out line, and the other end is electrically connected to a target matching pattern. The target matching pattern is the matching pattern located on the fan-out side of the first fan-out line and closest to the first fan-out line.

[0018] In some embodiments, the multiple matching patterns and the multiple adapter blocks are offset along the second direction, and at least one of the adapter blocks is located between the first fan-out line and the target matching pattern.

[0019] In some embodiments, the multiple first data lines comprise at least one first sub-data line. The orthographic projection of the first sub-data line on the substrate does not overlap with the orthographic projection of the adapter block on the substrate. The orthographic projection of the second connection segment, which is connected to the first sub-data line, on the substrate lies within the orthographic projection of the first sub-data line on the substrate.

[0020] In some embodiments, the multiple first data lines comprise at least one second sub-data line; the orthographic projection of the second sub-data line on the substrate partially overlaps with the orthographic projection of a column of adapter blocks on the substrate. The column of adapter blocks electrically connected to the second sub-data line includes a destination adapter block located on the fan-out side closest to the first fan-out line. The orthographic projection of the destination adapter block on the substrate does not overlap with the orthographic projection of the second sub-data line on the substrate. The second connection segment electrically connected to the second sub-data line is a destination connection segment.The orthographic projection of the target link segment on the substrate lies within the orthographic projection of the second sub-data line on the substrate, and the target link segment extends along the second direction and is spaced from the target adapter block; and / or the target link segment is a zigzag line, the orthographic projection of the target link segment on the substrate does not overlap, at least partially, with the orthographic projection of the second sub-data line on the substrate, and the target link segment is spaced from the target adapter block.

[0021] In some embodiments, two adjacent columns of pixel circuits are arranged symmetrically. The multiple data lines are divided into several groups, each group comprising two data lines. There is a first gap between the two data lines of a group, and a second gap exists between two adjacent groups of data lines, the first gap being smaller than the second gap. Each of the interconnect lines is located between the two data lines of a group, and the two data lines of the group are arranged symmetrically around the interconnect line. Each of the second fan-out lines is located between the two data lines of a group, and the two data lines of the group are arranged symmetrically around the second fan-out line.

[0022] In some embodiments, there are 1 to 10 connecting lines between two adjacent second fan-out lines.

[0023] In some embodiments, a first, a second, and a third connecting line are located between two adjacent second fan-out lines. Between two adjacent second fan-out lines, the second, the third, and the first connecting line are arranged sequentially along the first direction X, pointing from one side edge of the display area AA to the other. Alternatively, between two adjacent second fan-out lines, the second, the first, and the third connecting line are arranged sequentially along the first direction X, pointing from one side edge of the display area AA to the other. Alternatively, between two adjacent second fan-out lines, the first, the second, and the third connecting line are arranged sequentially along the first direction X, pointing from one side edge of the display area AA to the other.Alternatively, between two adjacent second fan-out lines, the first, third, and second connecting lines are arranged sequentially along the first direction X, pointing from one side edge of the display area AA to the other. Alternatively, between two adjacent second fan-out lines, the third, second, and first connecting lines are arranged sequentially along the first direction X, pointing from one side edge of the display area AA to the other. Alternatively, between two adjacent second fan-out lines, the third, first, and second connecting lines are arranged sequentially along the first direction X, pointing from one side edge of the display area AA to the other.

[0024] In some embodiments, the second wiring layer further comprises several first voltage signal lines spaced apart along the first direction, each first voltage signal line extending along the second direction. Two adjacent first voltage signal lines comprise a group of data lines. The bridge wire layer also comprises several first voltage signal adapter lines spaced apart along the second direction. Each first voltage signal adapter line extends along the first direction and is electrically connected to a row of pixel circuits. Each of the first voltage signal lines is electrically connected to the multiple first voltage signal adapter lines.

[0025] In a further aspect, a display field is provided. The display field comprises several light elements and the array substrate described in one of the embodiments mentioned above. The several light elements are arranged on the side of the array substrate facing away from the substrate and are each electrically connected to a pixel circuit.

[0026] In another aspect, a display device is provided. The display device comprises the aforementioned display panel and a driver board. The driver board is electrically connected to the fan-out area of ​​the display panel's array substrate and serves to transmit control signals to the array substrate. Brief description of the drawings

[0027] To more clearly illustrate the technical solutions of this disclosure, the drawings required for some embodiments of this disclosure are briefly described below. The drawings described below naturally represent only some embodiments of this disclosure, and those skilled in the art can derive further drawings from them. Furthermore, the drawings described below are schematic representations and are not intended to limit the actual dimensions, signal timing, or other aspects of the products contained in the embodiments of this disclosure. Fig. Figure 1 shows a circuit diagram of a display device according to some embodiments; Fig. Figure 2 shows another circuit diagram of a display device according to some embodiments; Fig. Figure 3 shows a cross-sectional circuit diagram of a display field according to some embodiments; Fig. Figure 4 shows a circuit diagram of a pixel circuit according to some embodiments; Fig. Figure 5 shows a circuit diagram from a first semiconductor layer to a first wiring layer according to some embodiments; Fig. Figure 6 shows a circuit diagram from the first semiconductor layer to a first source-drain conductive layer according to some embodiments; Fig. Figure 7 shows an equivalent circuit diagram of a pixel circuit according to some embodiments; Fig. Figure 8 shows a circuit diagram from the first semiconductor layer to a second source-drain conductive layer according to some embodiments; Fig. Figure 9 shows a circuit diagram from the first semiconductor layer to a third source-drain conductive layer according to some embodiments; Fig. Figure 10 shows a circuit diagram of a bridge wire layer and a third source-drain conductive layer according to some embodiments. Fig. Figure 11 shows a circuit diagram of an array substrate according to some embodiments; Fig. Figure 12 shows a circuit diagram of the first semiconductor layer, the first wiring layer and the first source-drain conductive layer according to some embodiments; Fig. Figure 13 shows a circuit diagram of the first source-drain conductive layer and the second source-drain conductive layer; Fig. Figure 14 shows a circuit diagram of the bridge wire layer and the third source-drain conductive layer according to some embodiments; Fig. Figure 15 shows a circuit diagram of the bridge wire layer according to some embodiments; Fig. Figure 16 shows a circuit diagram of the bridge wire layer and a second wiring layer according to some embodiments; Fig. Figure 17 shows another circuit diagram of the bridge wire layer according to some embodiments; Fig. Figure 18 shows another circuit diagram of the bridge wire layer and the second wiring layer according to some embodiments; Fig. Figure 19 shows another circuit diagram of the bridge wire layer according to some embodiments; Fig. Figure 20 shows another circuit diagram of the bridge wire layer and the second wiring layer according to some embodiments; Fig. 21 shows another circuit diagram of the bridge wire layer according to some embodiments; Fig. Figure 22 shows another circuit diagram of the bridge wire layer and the second wiring layer according to some embodiments; Fig. 23 shows another circuit diagram of the bridge wire layer according to some embodiments; Fig. Figure 24 shows another circuit diagram of the bridge wire layer and the second wiring layer according to some embodiments; Fig. 25 shows an enlarged partial view of area C in Fig. 11. Embodiments of the invention

[0028] The following section, together with the accompanying drawings, clearly and completely describes the technical solutions of some embodiments of the present disclosure. The described embodiments obviously represent only some, and not all, embodiments of the present disclosure. All further embodiments derived by those skilled in the art based on the embodiments provided in the present disclosure fall within the scope of protection of the present disclosure.

[0029] Unless the context otherwise requires, the term "comprise" and its alternative forms, such as the third-person singular "comprises" and the present participle "comprising," are to be understood throughout the description and claims as open and inclusive, i.e., "including but not limited to." Throughout the description, terms such as "an embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are intended to indicate that certain features, structures, materials, or properties associated with that embodiment or example are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example.Furthermore, the specific features, structures, materials or properties may be appropriately included in one or more embodiments or examples.

[0030] In the following, the terms “first” and “second” are used for descriptive purposes only and should not be interpreted as indicating a relative meaning or implicitly specifying the number of the technical features mentioned. Therefore, features designated as “first” or “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of this disclosure, “several” means two or more unless otherwise specified.

[0031] In describing certain embodiments, the terms "coupled" and "connected," as well as their derivatives, may be used. The term "connected" is to be understood broadly. For example, "connected" can mean a fixed, a detachable, or an integral connection. It can be a direct or indirect connection via an intermediate element. The term "coupled," for example, indicates that two or more components are in direct physical or electrical contact.

[0032] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C and a combination of A, B and C.

[0033] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0034] The use of “suitable for” or “configured for” is to be understood herein as open and inclusive and does not exclude devices that are suitable or configured to perform additional tasks or steps.

[0035] Furthermore, the use of "based on" is to be understood as open and inclusive, since a process, step, calculation or other action that is "based on" one or more specified conditions or values ​​may in practice be based on additional conditions or values ​​beyond those specified.

[0036] For the purposes of this agreement, “about”, “approximately” or “approximately” includes the stated value and an average value within an acceptable range of deviation from the stated value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with measuring the stated quantity (i.e., the limitations of the measuring system).

[0037] For the purposes of this agreement, “parallel”, “perpendicular”, and “equal” encompass the specified conditions and conditions similar to the specified conditions within an acceptable range of deviation, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with measuring the specified quantity (i.e., the limitations of the measuring system). For example, “parallel” encompasses both absolute and approximate parallelism, with the permissible range of deviation for approximate parallelism being, for instance, within 5°.

[0038] "Perpendicular" encompasses both absolute and approximate perpendicularity, with the permissible deviation range for approximate perpendicularity also being, for example, within 5°. "Equal" encompasses both absolute and approximate equality, with the permissible deviation range for approximate equality being, for example, that the difference between the two values ​​is less than or equal to 5% of the respective value.

[0039] When a layer or element is described as lying on top of another layer or substrate, this can mean that the layer or element is located directly on top of the other layer or substrate, or that there may be intermediate layers between the layer or element and the other layer or substrate.

[0040] Exemplary embodiments are described here with reference to cross-sections and / or top views of idealized drawings. For the sake of clarity, layer thicknesses and surface dimensions are exaggerated in the drawings. Therefore, deviations in shape compared to the drawings are to be expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the exemplary embodiments are not limited to the shapes of the areas shown here, but include deviations that are, for example, due to the manufacturing process. For instance, an etched area depicted as a rectangle typically exhibits curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of areas of a device, nor are they intended to limit the scope of the exemplary embodiments.

[0041] Referring to Fig. 1 Some embodiments of the present disclosure provide a display device 1000. The display device 1000 can be any device that displays either moving (e.g., videos) or stationary (e.g., still images) content, including both text and images.

[0042] For example, the display device 1000 could be a television, a laptop, a tablet, a mobile phone, a personal digital assistant (PDA), a navigation system, a portable device, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle display, an aircraft display, or any other product or component with a display function. As in Fig. As shown in 1, the display device 1000 could, for example, be a mobile phone.

[0043] Regarding the type of light emitted by the display device 1000, it can be an organic light-emitting diode (OLED) display, a quantum dot light-emitting diode (QLED) display, or a mini / micro light-emitting diode (MLED) display, etc. The form of the display device 1000 can be flat, curved, or foldable. Regarding its morphology, the display device 1000 can be a flat display device, a curved display device, or a foldable display device, etc. Regarding its shape, the display device 1000 can be rectangular or circular, etc. The embodiments of the present disclosure are not specifically limited thereto. In the following, a rectangular, flat OLED display device is used as an example to illustrate some embodiments of the present disclosure.However, the embodiments of the present disclosure are not limited thereto, and any other display device may also be considered, as long as the same technical concepts are applied.

[0044] In some embodiments, such as in Fig. As shown in Figure 2, the display device 1000 comprises a display panel 1100 and a driver board 1200. The driver board 1200 may, for example, contain a timing control controller (TCON), a DC / DC power management chip, and an adjustable resistor divider circuit (for generating Vcom), as well as other driver circuitry. The driver board 1200 may also contain other circuit structures not listed here. The driver board is electrically connected to the display panel 1100 and serves to transmit control signals to the display panel 1100, thereby controlling the display panel 1100 to display the image. Furthermore, the display device 1000 may also include an under-display camera and an under-display fingerprint sensor, etc., which enable various functions such as photo and video recording, as well as fingerprint or facial recognition, though these are not expressly limited here.

[0045] Referring to Fig. 2. The display field 1100 has a display area AA and a peripheral area BB. The peripheral area BB is located on at least one side of the display area AA. For example, the peripheral area BB surrounds the display area AA. The display area AA is the area of ​​the display field 1100 used for image display. The display area AA is equipped with several subpixels P, which represent the smallest light-emitting units on the display field 1100 and are used for image display.

[0046] The multiple subpixels P can emit light of the same color, for example, white or blue. The display field also has a color filter layer on the display side; that is, the display field uses a COE (CF on Encapsulation) structure. Alternatively, the multiple subpixels P can emit light of different colors. For example, the multiple subpixels P include red subpixels that emit red light, green subpixels that emit green light, and blue subpixels that emit blue light.

[0047] Referring to Fig. 2. The peripheral area BB can be used, for example, to accommodate gate driver circuits (such as Gate on Array GOA), control signal lines (such as clock signal lines and supply voltage lines), and to bond driver chips (such as source driver ICs). The functions of the peripheral area BB are not limited to these, and undisclosed embodiments are not described further.

[0048] The peripheral area BB includes a fan-out area BB1 on one side of the display area. Fan-out area BB1 is the portion of peripheral area BB located on the side of display area AA. Fan-out area BB1 can be used to route signal lines from the peripheral area and connect them to a driver board or driver chip. Fan-out area BB1 is adjacent to a side edge of display area AA. For example, fan-out area BB1 is adjacent to the bottom edge of display area AA.

[0049] Referring to Fig. 3. The display panel 1100 comprises an array substrate 100, several light-emitting elements 200, and an encapsulation layer 300, arranged one above the other. The display panel 1100 may also include functional laminate layers arranged on the side of the encapsulation layer 300 facing away from the array substrate. These functional laminate layers may, for example, include one or more of the following: a touch-sensitive functional layer, an anti-reflective layer, a hardening layer, a color filter layer (for the display panel with a COE structure), and an anti-fingerprint layer, enabling the display panel to perform its functions. The embodiments of this disclosure do not expressly limit the type and number of functional laminate layers.

[0050] Continue with Fig. 3. For example, a light-emitting element 200 can comprise an anode 201, a light-emitting functional layer 202, and a cathode layer 203 arranged one above the other. The display field 1100 can also contain a pixel definition layer (PDL). The pixel definition layer (PDL) is located on the side of the anode 201 facing away from the array substrate 100 and has multiple openings, with each light-emitting element 200 located in the region of one opening.

[0051] The encapsulation layer 300 is configured to reduce the risk of moisture and oxygen from the environment penetrating the luminaire elements 200, thus increasing the service life of the display panel 1100. The encapsulation layer 300 can be an encapsulation film or an encapsulation substrate. As shown in Fig. As shown in Figure 3, the encapsulation layer 300 can, for example, be an encapsulation film. In this case, the encapsulation layer 300 can comprise a first inorganic encapsulation layer 301, an organic encapsulation layer 302, and a second inorganic encapsulation layer 303, stacked one after the other.

[0052] Array substrate 100 has a display area AA and a fan-out area BB1. The display area AA of array substrate 100 and the display area AA of display field 1100 are identical. The fan-out area BB1 of array substrate 100 and display field 1100 is the same area. That is, array substrate 100 has a display area AA and a fan-out area BB1 that borders a side edge of display area AA.

[0053] According to Fig. In section 2, the array substrate 100 comprises multiple pixel circuits 120. The multiple pixel circuits 120 are arranged in multiple rows and columns. Each row of pixel circuits 120 comprises multiple pixel circuits 120 spaced along a first direction X, and the multiple rows of pixel circuits 120 are arranged along a second direction Y. Each column of pixel circuits 120 comprises multiple pixel circuits 120 arranged along the second direction Y, and the multiple columns of pixel circuits 120 are arranged along the first direction X. That is, the first direction X is the row direction in which the multiple pixel circuits 120 are arranged, and the second direction Y is the column direction in which the multiple pixel circuits 120 are arranged. The first direction X and the second direction Y intersect. For example, the first direction X and the second direction Y are perpendicular to each other.

[0054] As in Fig. As shown in Figure 3, the array substrate 100 also includes a substrate 110 on which the multiple pixel circuits are arranged. The substrate 110 can be a rigid substrate, for example made of glass. Alternatively, the substrate 110 can be a flexible substrate whose material includes, for example, polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0055] As in Fig. As shown in Figure 3, the array substrate 100 further comprises a first semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a first dielectric intermediate layer ILD1, a second semiconductor layer ACT2, a third gate insulating layer GI3, a third gate conductive layer GT3, a second dielectric intermediate layer ILD2, a first source-drain conductive layer SD1, a first planarization layer PLN1, a second source-drain conductive layer SD2, a second planarization layer PLN2, a third source-drain conductive layer SD3 and a third planarization layer PLN4, which are arranged successively perpendicular to and facing away from the substrate 110.

[0056] The pixel circuit 120 comprises several thin-film transistors (TFTs) and at least one capacitor Cst. For example, the pixel circuit 120 can be a "3T1C" circuit, a "7T1C" circuit, or an "8T1C" circuit, where "T" represents one TFT and the number preceding "T" indicates the number of TFTs; and "C" represents one capacitor Cst and the number preceding "C" indicates the number of capacitors Cst. In the following embodiments of this disclosure, the pixel circuit 120 is presented as an "8T1C" circuit. However, the embodiments of this disclosure are not limited to this, and any other pixel circuit 120 can also be considered, provided the same technical concepts are applied.

[0057] As in Fig. As shown in Figure 3, the thin-film transistors can comprise a first thin-film transistor TFT1 and a second thin-film transistor TFT2. The first thin-film transistor TFT1 can include a first active layer 121 in the first semiconductor layer ACT1, a gate electrode 122 in the first gate conductive layer GT1, and a source electrode 123 and a drain electrode 124 in the first source-drain conductive layer SD1. The second thin-film transistor TFT2 can include a second active layer 125 in the second semiconductor layer ACT2, a gate electrode 126 in the second gate conductive layer GT2 and the third gate conductive layer GT3, and a source electrode 123 and a drain electrode 124 in the first source-drain conductive layer SD1. The source electrodes 123 and the drain electrodes 124 can be structurally identical and thus interchangeable.

[0058] For example, the first thin-film transistor TFT1 can be a low-temperature polysilicon thin-film transistor, meaning that low-temperature polycrystalline silicon is used for the first semiconductor layer ACT1. The second thin-film transistor TFT2 can be an oxide thin-film transistor, meaning that a metal oxide is used for the second semiconductor layer ACT2, for example, indium gallium zinc oxide or indium gallium tin oxide.

[0059] Based on the advantages of low-temperature polysilicon thin-film transistors (LTPS), such as high mobility and fast charging time, and of oxide thin-film transistors, such as low leakage current, LTPS and oxide thin-film transistors are integrated on a single array substrate 100. This means that the pixel circuits 120 incorporate both LTPS and oxide thin-film transistors to leverage the advantages of both, reduce the power consumption of the array substrate 100, and improve the display quality of the display array 1100.

[0060] According to Fig. The array substrate 100 also includes multiple scan signal lines GL and multiple emission control signal lines EML. For example, the multiple scan signal lines GL can include multiple first scan signal lines GL1, multiple second scan signal lines GL2, multiple third scan signal lines GL3, and multiple fourth scan signal lines GL4. A row of pixel circuits 120 is electrically connected to one of the first scan signal lines GL1, one of the second scan signal lines GL2, one of the third scan signal lines GL3, one of the fourth scan signal lines GL4, and one of the emission control signal lines EML. The first scan signal lines GL1, the second scan signal lines GL2, the third scan signal lines GL3, and the emission control signal lines EML are located in the first gate conductive layer GT1, and the fourth scan signal lines GL4 are located in the second gate conductive layer GT2.

[0061] It is understood that the first gate layer GT1 can comprise several structures, such as the gates of the first thin-film transistors TFT1, the first scan signal lines GL1, the second scan signal lines GL2, the third scan signal lines GL3, and the emission control signal lines EML. The gate of the first thin-film transistor TFT1 is part of the pixel circuit 120. The pixel circuit 120 comprises structures within the first gate layer GT1, although the first gate layer GT1 does not completely constitute the pixel circuit 120. Similarly, the pixel circuit 120 comprises structures within the second gate layer GT2, although the second gate layer GT2 does not completely constitute the pixel circuit 120.

[0062] In some embodiments, further with Fig. 4. The pixel circuit 120 comprises a driver transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor Cst. Each of the transistors (driver transistor DT and the first through seventh transistors) comprises a gate, a first electrode, and a second electrode. The first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. For example, the first electrode is the source of the transistor and the second electrode is the drain of the transistor.

[0063] The first scan signal line GL1 forms the gate of the first transistor T1, the second scan signal line GL2 the gates of the second transistor T2 and the third transistor T3, the third scan signal line GL3 the gate of the fourth transistor T4, the fourth scan signal line GL4 the gate of the fifth transistor T5 and the emission control signal line EML the gates of the sixth transistor T6 and the seventh transistor T7.

[0064] The disclosed embodiments further comprise a first wiring layer, a bridge wire layer, and a second wiring layer. The first wiring layer is located on the side of the multiple pixel circuits 120 facing away from the substrate 110, the bridge wire layer is located on the side of the first wiring layer facing away from the substrate, and the second wiring layer is located on the side of the bridge wire layer facing away from the substrate. For example, the first wiring layer can be arranged on the same layer as the third gate conductive layer GT3, the bridge wire layer on the same layer as the second source-drain conductive layer SD2, and the second wiring layer on the same layer as the third source-drain conductive layer SD3. This helps to reduce the number of film layers in the array substrate 100 and lower the production costs of the array substrate 100.

[0065] It is understood that in further embodiments, the first wiring layer and the third gate conductive layer GT3 can also be independent film layers. For example, the first wiring layer can be arranged between the third gate conductive layer GT3 and the first source-drain conductive layer SD1. Likewise, the bridge wire layer and the second source-drain conductive layer SD2 can be independent film layers, and the second wiring layer and the third source-drain conductive layer SD3 can also be independent film layers. All subsequent embodiments of the present disclosure are described by reference to the example "the first wiring layer is arranged on the same layer as the third gate conductive layer GT3, the bridge wire layer is arranged on the same layer as the second source-drain conductive layer SD2, and the second wiring layer is arranged on the same layer as the third source-drain conductive layer SD3."Thus, the first wiring layer and the third gate layer GT3 are the same film layer, the bridge wire layer and the second source-drain layer SD2 are the same film layer, and the second wiring layer and the third source-drain layer SD3 are the same film layer. Therefore, the first wiring layer is designated "GT3", identical to the third gate layer GT3, the bridge wire layer is designated "SD2", identical to the second source-drain layer SD2, and the second wiring layer is designated "SD3", identical to the third source-drain layer SD3.

[0066] Fig. Figure 5 shows the structure of the array substrate 100 after adding the first wiring layer GT3 to Fig. 4. According to Fig. 5 the first wiring layer GT3 includes several first initialization signal lines Vinitl, several second initialization signal lines Vinit2 and several third initialization signal lines Vinit3, which extend along the first direction X. Fig. Figure 5 shows only a portion (one or two) of the first initialization signal lines Vinit1, the second initialization signal lines Vinit2, and the third initialization signal lines Vinit3. The multiple first initialization signal lines Vinit1, the multiple second initialization signal lines Vinit2, and the multiple third initialization signal lines Vinit3 are spaced apart along the second direction Y. Each row of pixel circuits 120 is electrically connected to one of the first initialization signal lines Vinit1, one of the second initialization signal lines Vinit2, and one of the third initialization signal lines Vinit3.

[0067] In some embodiments (see Fig. 4 and Fig. 5) The orthographic projection of the first initialization signal line Vinit1 on substrate 110 overlaps at least partially with the orthographic projection of the second scan signal line GL2 on substrate 110. The orthographic projection of the second initialization signal line Vinit2 on substrate 110 overlaps at least partially with the orthographic projection of the first scan signal line GL1 on substrate 110. The orthographic projection of the third initialization signal line Vinit3 on substrate 110 overlaps at least partially with the orthographic projection of the emission control signal line EML on substrate 110.In this way, the second scan signal line GL2 can shield the electric field generated by the first initialization signal line Vinit1, the first scan signal line GL1 can shield the electric field generated by the second initialization signal line Vinit2, and the emission control signal line EML can shield the electric field generated by the third initialization signal line Vinit3, thereby reducing the effects of the first, second, and third initialization signal lines Vinit1, Vinit2, and Vinit3 on the first and second semiconductor layers ACT1 and ACT2, and thus reducing the effects on the pixel circuit 120.

[0068] In some embodiments, the fourth transistor T4 can be a dual-gate transistor. As in Fig. As shown in Figure 5, the first wiring layer GT3 can also include several fourth scan signal lines GL4. It is understood that the orthographic projection of the fourth scan signal line GL4 in the second gate conductive layer GT2 on substrate 110 overlaps at least partially with the orthographic projection of the fourth scan signal line GL4 in the first wiring layer GT3 on substrate 110, and both transmit the same scan signal. Therefore, both are referred to as the fourth scan signal line GL4.

[0069] Fig. Figure 6 shows the structure of the array substrate 100 after adding the first source-drain conductive layer SD1 to Fig. 5. The first source-drain conductive layer SD1 comprises several source and drain structures for electrically connecting the transistors of the pixel circuit 120 to the first initialization signal line Vinit1, the second initialization signal line Vinit2 and the third initialization signal line.

[0070] Referring to the Fig. 4, Fig. 6 and Fig. 7. The gate of the first transistor T1 is electrically connected to the first scan signal line GL1, the first electrode to the first initialization signal line Vinit1, and the second electrode to the gate of the driver transistor DT. The gate of the second transistor T2 is electrically connected to the second scan signal line GL2, the first electrode to the second initialization signal line Vinit2, and the second electrode to a first node N1. The gate of the third transistor T3 is electrically connected to the second scan signal line GL2, the first electrode to the third initialization signal line Vinit3, and the second electrode to the first electrode of the driver transistor DT.The fourth transistor, T4, has a gate electrically connected to the third scan signal line, GL3; a first electrode electrically connected to the third initialization signal line, Vinit3; and a second electrode electrically connected to the first electrode of the driver transistor, DT. The fifth transistor, T5, has its gate electrically connected to the fourth scan signal line, GL3; its first electrode to the second electrode of the driver transistor, DT; and its second electrode to the gate of DT. The sixth transistor, T6, has its gate electrically connected to the emission control signal line, EML; its first electrode to the first voltage signal line, VDD; and its second electrode to the first electrode of the driver transistor, DT.The seventh transistor, T7, is electrically connected via its gate to the emission control signal line EML, its first electrode to the second electrode of the driver transistor DT, and its second electrode to the first node N1. The capacitor Cst is connected via its first plate to the first voltage signal line VDD and its second plate to the gate of the driver transistor DT.

[0071] The fifth transistor, T5, is an oxide thin-film transistor that reduces the gate leakage current of the driver transistor DT, thus ensuring consistent brightness of the driver transistor DT within a display frame. The driver transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are low-temperature polysilicon thin-film transistors that improve the response speed of the Pixel 120 circuit.

[0072] Fig. Figure 8 shows the structure of the array substrate 100 after the addition of the bridge wire layer SD2 to Fig. 6. According to Fig. In Figure 8, the bridge wire layer SD2 comprises multiple adapter blocks 21, multiple first fan-out lines 22, and multiple columns of matching patterns 23. The multiple adapter blocks 21 are arranged in multiple columns, each column containing multiple adapter blocks 21 arranged along the second direction Y. The multiple first fan-out lines 22 (each of the multiple first fan-out lines 22) extend along the first direction X, and the multiple first fan-out lines 22 are spaced apart along the second direction Y.

[0073] Fig. Figure 9 shows the structure of the array substrate 100 after adding a second wiring layer SD3 to the one shown in Fig. Structure 8 shown. Referring to Fig. 9 is the second wiring layer SD3 located on the side of the bridge wire layer SD2 facing away from the substrate 110, and includes several connecting lines 31 and several data lines DL, both extending along the second direction Y. Fig. Figure 10 shows a stacked structure of the bridge wire layer SD2 and the second wiring layer SD3. According to Fig. 10 The second wiring layer SD3 also includes several second fan-out lines 32.

[0074] At the same time in the Fig. 9 and Fig. 10 Each connecting line 31 is electrically connected via a column of adapter blocks 21 to one of the multiple first initialization signal lines Vinitl, one of the multiple second initialization signal lines Vinit2, and one of the multiple third initialization signal lines Vinit3. The multiple connecting lines 31 can be electrically connected to at least one of the multiple first initialization signal lines Vinitl, one of the multiple second initialization signal lines Vinit2, and one of the multiple third initialization signal lines Vinit3. In this way, the connecting lines 31 can connect at least one of the multiple first initialization signal lines Vinitl, one of the multiple second initialization signal lines Vinit2, and one of the multiple third initialization signal lines Vinit3 to form a horizontally and vertically intersecting grid structure.This reduces the power consumption of the array substrate 100 and improves the display quality of the display field.

[0075] For example, each of the connecting lines 31 is electrically connected to the multiple first initialization signal lines Vinit1. Alternatively, each of the connecting lines 31 is electrically connected to the multiple second initialization signal lines Vinit2. Alternatively, each of the connecting lines 31 is electrically connected to the multiple third initialization signal lines Vinit3. Alternatively, some of the connecting lines 31 are electrically connected to the multiple first initialization signal lines Vinit1 and some to the multiple second initialization signal lines Vinit2. Alternatively, some of the connecting lines 31 are electrically connected to the multiple first initialization signal lines Vinit1 and some of the connecting lines 31 are electrically connected to the multiple third initialization signal lines Vinit3.Alternatively, some of the connecting lines 31 are electrically connected to the multiple second initialization signal lines Vinit2 and some of the connecting lines 31 are electrically connected to the multiple third initialization signal lines Vinit3. Alternatively, some of the connecting lines 31 are electrically connected to the multiple first initialization signal lines Vinitl, some of the connecting lines 31 are electrically connected to the multiple second initialization signal lines Vinit2 and some of the connecting lines 31 are electrically connected to the multiple third initialization signal lines Vinit3.

[0076] For example, if we consider the electrical connection of the multiple connecting lines 31 with the multiple first initialization signal lines Vinit1, the multiple connecting lines 31 and the multiple first initialization signal lines Vinit1 form a grid structure, which corresponds to a parallel connection of the multiple first initialization signal lines Vinit1 via the multiple connecting lines 31. This can reduce the resistance of the multiple first initialization signal lines Vinit1 and the voltage drop occurring on the multiple first initialization signal lines Vinit1 during voltage signal transmission, thus reducing the power consumption of the array substrate 100.Likewise, the multiple connecting lines 31 can reduce the resistance and voltage drop of at least one of the multiple first initialization signal lines Vinitl, the multiple second initialization signal lines Vinit2 and the multiple third initialization signal lines Vinit3, thereby reducing the power consumption of the array substrate 100 and improving the image quality of the display field.

[0077] In some embodiments (see Fig. 6 and Fig. 9) The connecting line 31 is successively connected via the adapter block 21 of the bridge wire layer SD2 to the connection patterns of the first source-drain conductive layer SD1 (the first connection pattern 41, the second connection pattern 42 and the third connection pattern 43, see the following for details) with the first initialization signal line Vinit1, the second initialization signal line Vinit2 or the third initialization signal line Vinit3.

[0078] For example, the multiple connecting lines 31 are electrically connected to the multiple first initialization signal lines Vinit1, or the multiple connecting lines 31 are electrically connected to the multiple second initialization signal lines Vinit2, or the multiple connecting lines 31 are electrically connected to the multiple third initialization signal lines Vinit3, or the multiple connecting lines 31 are electrically connected to the multiple first initialization signal lines Vinit1 and to the multiple second initialization signal lines Vinit2, or the multiple connecting lines 31 are electrically connected to the multiple first initialization signal lines Vinit1 and to the multiple third initialization signal lines Vinit3.or the multiple connecting lines 31 are electrically connected to the multiple second initialization signal lines Vinit2 and to the multiple third initialization signal lines Vinit3, or the multiple connecting lines 31 are electrically connected to the multiple first initialization signal lines Vinitl, to the multiple second initialization signal lines Vinit2 and to the multiple third initialization signal lines.

[0079] It is understood that the present application also includes additional or reduced types of initialization signal lines based on the embodiments described above. For example, the array substrate additionally includes several fourth initialization signal lines, and the multiple interconnect lines can also be electrically connected to the fourth initialization signal lines. Alternatively, the array substrate can include only several first and second initialization signal lines, with the multiple interconnect lines being electrically connected to the first and / or second initialization signal lines.

[0080] As in Fig. As shown in Figure 9, each of the data lines DL is electrically connected to a column of pixel circuits 120. For example, each of the data lines DL is electrically connected to a column of matching patterns 23, and the multiple matching patterns 23 of a column are each electrically connected to the multiple pixel circuits of a column.

[0081] Referring to Fig. 11. The multiple data lines DL can comprise multiple first data lines DL1 and multiple second data lines DL2. The first data lines DL1 are located in the display area AA, meaning they do not extend into the fan-out area BB1. The second fan-out lines 32 extend into the fan-out area BB1. The first data line DL1, the first fan-out line 22, and the second fan-out line 32 are connected sequentially, with each of the first fan-out lines 22 electrically connected to one of the first data lines DL1 and to one of the second fan-out lines 32. In other words, the first data line DL1 is the data line DL in the array substrate 100, which must be routed sequentially via the first and second fan-out lines 22 and 32 to the fan-out area BB1. The second data lines DL2 run directly into the fan-out area BB1. This arrangement is called FIAA (Fanout in AA) or FIP (Fanout in Panel).It helps to reduce the dimensions of the fan-out area BB1 along the second direction Y, thereby reducing the frame width of the array substrate 100 and enabling a narrow frame for the display device.

[0082] For example, the data line DL must be in accordance with Fig. 11. The cable must traverse at least part of the fan-out area BB1 and extend to the side of the fan-out area BB1 facing away from the display area AA1, for example, to the bond area BB2 of the fan-out area BB1. The bond area BB2 can be bound to a driver board or driver chip. This electrically connects the driver board or driver chip to the data line DL, and data signals are transmitted to the data line DL, enabling the pixel circuit to control the light source.

[0083] As in Fig. As shown in Figure 11, the bond area BB2 along the first direction X is smaller than the display area AA. In the second direction Y, the bond area BB2 is located opposite the central area of ​​the display area AA. The data lines DL on both lateral edges of the display area AA along the first direction are designated as first data lines DL1, while the data lines DL in the central area of ​​the display area AA along the first direction X are designated as second data lines DL2. For example, the second data lines DL2 along the second direction Y are located opposite the bond area BB2, while the first data lines DL1 are located on both sides of the second data lines DL2 along the first direction X.In this way, along the first direction X, the first data lines DL1, located on both sides of the bonding area BB2, are routed out via the first fan-out lines 22 and the second fan-out lines 32, while the second data lines DL2, located opposite the bonding area BB2, are routed directly out. This helps to reduce the dimensions of the fan-out area BB1 along the second direction Y, thus achieving a narrow frame.

[0084] It is understood that the array substrate can comprise multiple fan-out areas BB1 and multiple bond areas BB2. For example, in large-format display devices (such as televisions and computers), the array substrate can comprise multiple fan-out areas BB1 and multiple bond areas BB2. The data lines DL opposite bond area BB2 along the second direction Y can be considered second data lines DL2, while the remaining data lines DL can be considered first data lines DL1. Of course, the distinction between first data lines DL1 and second data lines DL2 is not limited to this, and the first data lines DL1 and second data lines DL2 can be arranged in other regions if required.

[0085] As described above, the embodiments described herein use a bridge wire layer SD2 and a second wiring layer SD3. This allows at least one of the first initialization signal lines Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3 to be connected in parallel (via connecting lines 31 and adapter blocks 21) to form a grid structure. This reduces the power consumption of the array substrate 100. Furthermore, the first data lines DL1 can be routed out of the display area AA at the edge of the display area AA (via first and second fan-out lines 22 and 32), thereby reducing the width (the dimension along the second direction Y) of the fan-out area BB1.In other words, this simultaneously reduces the resistance of the first, second and third initialization signal lines Vinit1, Vinit2 and Vinit3, and decreases the width of the fan-out area BB1.

[0086] The following embodiments of this application use an example in which several connecting lines 31 are electrically connected via several adapter blocks 21 to several first initialization signal lines Vinitl, several second initialization signal lines Vinit2, and several third initialization signal lines Vinit3. That is, the several connecting lines 31 simultaneously connect the several first initialization signal lines Vinitl, the several second initialization signal lines Vinit2, and the several third initialization signal lines Vinit3 in parallel to form three independent grid structures, with each pair of the first initialization signal lines Vinitl, the second initialization signal lines Vinit2, and the third initialization signal lines Vinit3 being electrically isolated from each other.

[0087] In some embodiments, such as in Fig. As shown in Figure 10, the multiple connecting lines 31 comprise multiple first connecting lines 311, multiple second connecting lines 312, and multiple third connecting lines 313 extending along the second direction Y. The multiple first connecting lines 311, the multiple second connecting lines 312, and the multiple third connecting lines 313 are spaced apart from each other along the first direction X. The multiple adapter blocks 21 comprise multiple columns of first adapter blocks 211, multiple columns of second adapter blocks 212, and multiple columns of third adapter blocks 213, spaced apart from each other along the first direction X.Each column of first adapter blocks 211 comprises several first adapter blocks 211 spaced apart along the second direction Y; each column of second adapter blocks 212 comprises several second adapter blocks 212 spaced apart along the second direction Y; and each column of third adapter blocks 213 comprises several third adapter blocks 213 spaced apart along the second direction Y. Each of the first connecting lines 311 is electrically connected via a column of several first adapter blocks 211 to several (all) first initialization signal lines Vinit1. Each of the second connecting lines 312 is electrically connected via a column of several second adapter blocks 212 to several (all) second initialization signal lines Vinit2.Each of the third connecting lines 313 is electrically connected via a column of several third adapter blocks 213 to several (all) third initialization signal lines Vinit3.

[0088] In some embodiments, see Fig. 12 The first source-drain conductive layer SD1 comprises several first connection patterns 41, several second connection patterns 42, several third connection patterns 43, several fourth connection patterns 44, several fifth connection patterns 45, and several sixth connection patterns 46. It should be noted that in Fig. 12 To facilitate the identification of the structure of the first source-drain conductive layer SD1 and the connection between the first source-drain conductive layer SD1 and the first wiring layer GT3, only the first semiconductor layer ACT1 is used to represent the pixel circuit 120, while other film layers between the first semiconductor layer ACT1 and the first wiring layer GT3 are omitted.

[0089] As in Fig. As shown in Figure 12, the first connection pattern 41 comprises a first subpattern 411 and a second subpattern 412. The first subpattern 411 is electrically connected to the first initialization signal line Vinit1 and to the pixel circuit 120. Fig. 12 represents the first semiconductor layer ACT, the pixel circuit 120. Fig. Figure 13 shows the stacked structure of the first source-drain conductor layer SD1 and the bridge wire layer SD2. Fig. 12 and Fig. 13 the orthographic projection of the second subpattern 412 on the substrate 110 is located within the orthographic projection of the first adapter block 211 on the substrate 110, and the second subpattern 412 is electrically connected to the first adapter block 211.

[0090] As in Fig. As shown in Figure 12, the first connection pattern 41, for example, extends along the second direction Y. The first subpattern 411 is closer to the first initialization signal line Vinit1 than the second subpattern 412. Furthermore, the dimension of the first subpattern 411 along the first direction X is smaller than that of the second subpattern 412. This contributes, as shown in Fig. Figure 13 illustrates this, contributing to an increase in the overlap area between the second subpattern 412 and the first adapter block 211, thereby increasing the contact area between the second subpattern 412 and the first adapter block 211. This reduces the contact resistance between the second subpattern 412 and the first adapter block 211.

[0091] As in Fig. As shown in Figure 13, for example, each of the first adapter blocks 211 is electrically connected to two first connection patterns 41. As in Fig. As shown in Figure 13, the first two connection patterns 41, which are electrically connected to the same first adapter block 211, are arranged symmetrically.

[0092] As in Fig. As shown in Figure 12, the fourth connection pattern 44 has the same shape and dimensions as the first subpattern 411. The fourth connection pattern 44 is electrically connected to the first initialization signal line Vinit1 and to the pixel circuit 120 (first semiconductor layer ACT1).

[0093] With reference to the Fig. 12 and Fig. The fourth connection pattern 44 is essential for connecting the first initialization signal line Vinit1 to the pixel circuit 120. That is, regardless of whether the first connection line 311 and the first adapter block 211 are present, the first source-drain conductive layer SD1 contains the fourth connection pattern 44. The first connection pattern 41 can be considered the fourth connection pattern 44 with the additional second subpattern 412. In other words, the second subpattern 412 is provided in the first source-drain conductive layer SD1, and the second subpattern 412 is connected to the first subpattern 411 (the first connection pattern 41). In this way, the second subpattern 412 can be connected to the first initialization signal line Vinit1 via the first subpattern 411.This simplifies the structure of the first interconnection pattern 41, minimizes the structural changes to the first source-drain conductive layer SD1, and helps to simplify the preparation of the first source-drain conductive layer SD1.

[0094] In further embodiments, the fourth connection pattern 44 in the first source-drain conductive layer SD1 can be wholly or partially replaced by the first connection pattern 41 to improve the pattern consistency of the first source-drain conductive layer SD1. In this case, only a portion of the first connection pattern 41 is used for the electrical connection with the first adapter block 211, while the other portion of the first connection pattern 41 is used only for connecting the first initialization signal line Vinit1 to the pixel circuit 120.

[0095] As in Fig. As shown in Figure 12, the second connection pattern 42 comprises a third subpattern 421 and a fourth subpattern 422. The third subpattern 421 is electrically connected to the second initialization signal line Vinit2 and to the pixel circuit 120 (of the first semiconductor layer ACT1). As shown in Fig. As shown in Figure 13, the orthographic projection of the fourth subpattern 422 on the substrate 110 is located within the orthographic projection of the second adapter block 212 on the substrate 110, and the fourth subpattern 422 is electrically connected to the second adapter block 212.

[0096] For example, as in Fig. As shown in Figure 13, each of the second adapter blocks 212 is electrically connected to two second connection patterns 42. As shown in Fig. As shown in Figure 12, the two second connection patterns 42, which are electrically connected to the same second adapter block 212, are arranged symmetrically. The fourth subpattern 422 is connected to the inside (the side facing the axis of symmetry between the two second connection patterns 42) of the third subpattern 421 and has a larger dimension along the first direction X than the third subpattern 421. This increases the overlap area between the fourth subpattern 422 and the second adapter block 212, thereby increasing the contact area between the fourth subpattern 422 and the second adapter block 212 and reducing the contact resistance between the fourth subpattern 422 and the second adapter block 212.

[0097] As in Fig. As shown in Figure 12, the shape and dimensions of the fifth connection pattern 45 are identical to those of the third subpattern 421. In other words, the fifth connection pattern 45 has the same shape and dimensions as the third subpattern 421. The fifth connection pattern 45 is electrically connected to the second initialization signal line Vinit2 and to the pixel circuit 120.

[0098] Referring to Fig. 12 and Fig. The fifth connection pattern 45 is essential for connecting the second initialization signal line Vinit2 to the pixel circuit 120 (of the first semiconductor layer ACT1). The second connection pattern 42 can be considered the fifth connection pattern 45 with the additional fourth subpattern 422. This allows the fourth subpattern 422 to be connected to the second initialization signal line Vinit2 via the third subpattern 421. This simplifies the structure of the second connection pattern 42, contributes to reducing the degree of structuring of the first source-drain conductive layer SD1, and decreases the difficulty of fabricating the first source-drain conductive layer SD1.

[0099] In further embodiments, the fifth connection pattern 45 in the first source-drain conductive layer SD1 can be wholly or partially replaced by the second connection pattern 42 to improve the pattern consistency of the first source-drain conductive layer SD1. In this case, only part of the second connection pattern 42 is used for the electrical connection with the second adapter block 212, while the other part of the second connection pattern 42 is used only for connecting the second initialization signal line Vinit2 to the pixel circuit 120.

[0100] As in Fig. As shown in Figure 12, the third connection pattern 43 comprises a fifth subpattern 431 and a sixth subpattern 432. The fifth subpattern 431 is electrically connected to the third initialization signal line Vinit3 and to the pixel circuit 120 (of the first semiconductor layer ACT1). As shown in Fig. As shown in Figure 13, the orthographic projection of the sixth subpattern 432 on the substrate 110 overlaps at least partially with the orthographic projection of the third adapter block 213 on the substrate 110, and the sixth subpattern 432 is electrically connected to the third adapter block 213.

[0101] As in Fig. As shown in Figure 12, the fifth subpattern 431, for example, can be an axisymmetric pattern arranged symmetrically around an axis extending along the second direction Y. For example, the fifth subpattern 431 has an approximately C-shaped structure and comprises two first sections 4311. The orthographic projections of the two first sections 4311 on the substrate 110 each partially overlap with the orthographic projection of the first initialization signal line Vinit1 on the substrate 110, and the two first sections 4311 are electrically connected to the first initialization signal line Vinit1. The third connection pattern 43 comprises two sixth subpatterns 432 arranged symmetrically around the axis of symmetry of the fifth subpattern 431. As shown in Figure 12, the fifth subpattern 431 is approximately C-shaped and comprises two sixth subpatterns 432 arranged symmetrically around the axis of symmetry of the fifth subpattern 431. Fig. As shown in Figure 13, the two sixth sub-patterns 432 are each electrically connected to the third adapter block 213.

[0102] As in Fig. As shown in Figure 12, the shape and dimensions of the sixth connection pattern 46 are identical to those of the fifth subpattern 431. In other words, the sixth connection pattern 46 has the same shape and dimensions as the fifth subpattern 431. The sixth connection pattern 46 is electrically connected to the third initialization signal line Vinit3 and to the pixel circuit 120.

[0103] As in Fig. 12 and Fig. As shown in Figure 13, the sixth connection pattern 46 is essential for connecting the third initialization signal line Vinit3 to the pixel circuit 120. The third connection pattern 43 can be considered the sixth connection pattern 46 with the additional sixth subpattern 432. In this way, the sixth subpattern 432 can be connected to the third initialization signal line Vinit3 via the fifth subpattern 431, which simplifies the structure of the third connection pattern 43 and facilitates the preparation of the first source-drain conductive layer SD1.

[0104] In other embodiments, the sixth connection pattern 46 in the first source-drain conductive layer SD1 can be wholly or partially replaced by the third connection pattern 43 to improve the pattern consistency of the first source-drain conductive layer SD1. In this case, only part of the third connection pattern 43 is used for the electrical connection with the second adapter block 212, while the other part of the third connection pattern 43 is used only for connecting the third initialization signal line Vinit3 to the pixel circuit 120.

[0105] In some embodiments (see Fig. 12) The first source-drain conductive layer SD1 also contains a seventh connection pattern 47, an eighth connection pattern 48, and a ninth connection pattern 49. The seventh connection pattern 47 is electrically connected to the pixel circuit (the first semiconductor layer ACT1) and is configured to transmit a first voltage signal (e.g., a supply voltage signal). The eighth connection pattern 48 is electrically connected to the pixel circuit and is configured to transmit a data signal. The ninth connection pattern 49 is configured to electrically connect the pixel circuit 120 to the light source.

[0106] Fig. Figure 13 shows the bridge wire layer SD2 with multiple adapter blocks 21 in multiple columns. Each column contains multiple adapter blocks 21 spaced along the second direction Y. The adapter blocks 21 of a column are each electrically connected to the multiple first initialization signal lines Vinitl, the multiple second initialization signal lines Vinit2, or the multiple third initialization signal lines Vinit3. As shown in Fig. As shown in Figure 14, a connecting line 31 is electrically connected to the several adapter blocks 21 of a column. Thus, each connecting line 31 can be connected to one of the several first initialization signal lines Vinitl, the several second initialization signal lines Vinit2, or the several third initialization signal lines Vinit3.

[0107] As in Fig. As shown in Figure 13, the multiple adapter blocks 21 comprise, for example, multiple columns of first adapter blocks 211, multiple columns of second adapter blocks 212, and multiple columns of third adapter blocks 213, spaced apart along the first direction X. Each column of first adapter blocks 211 comprises multiple first adapter blocks 211, spaced apart along the second direction Y. Each column of second adapter blocks 212 comprises multiple second adapter blocks 212, spaced apart along the second direction Y. Each column of third adapter blocks 213 comprises multiple third adapter blocks 213, spaced apart along the second direction Y. Fig. Figure 13 shows only one column of first adapter blocks 211, one column of second adapter blocks 212 and one column of third adapter blocks 213, and in one column of first adapter blocks 211 only two first adapter blocks 211 are shown, spaced apart from each other along the second direction Y.

[0108] For example, the multiple connecting lines comprise 31, as in Fig. Figure 14 shows several first connection lines 311, several second connection lines 312, and several third connection lines 313. Each of the first connection lines 311 is electrically connected via a column of several (all) first adapter blocks 211 to several (all) first initialization signal lines Vinit1. Each of the second connection lines 312 is electrically connected via a column of several (all) second adapter blocks 212 to several (all) second initialization signal lines Vinit2. Each of the third connection lines 313 is electrically connected via a column of several (all) third adapter blocks 213 to several (all) third initialization signal lines Vinit3. Fig. Figure 14 shows only a first connecting line 311, a second connecting line 312 and a third connecting line 313.

[0109] As in Fig. As shown in Figure 13, at least one adapter block 21 is electrically connected at both ends along the first direction X to the first initialization signal line Vinit1, the second initialization signal line Vinit2, or the third initialization signal line Vinit3. In this way, the other end can remain electrically connected to the initialization signal line even if the connection between one end of the adapter block 21 and the initialization signal line (first initialization signal line Vinit1, second initialization signal line Vinit2, or third initialization signal line Vinit3) fails, thereby improving the reliability of the connection between the adapter block 21 and the initialization signal line.

[0110] For example, several columns of first adapter blocks 211 are electrically connected at both ends along the first direction X to the first initialization signal line Vinit1, several columns of second adapter blocks 212 are electrically connected at both ends along the first direction X to the second initialization signal line Vinit2, and several columns of third adapter blocks 213 are electrically connected at both ends along the first direction X to the third initialization signal line Vinit3. This helps to improve the reliability of the connection between the adapter block 21 and the initialization signal line.

[0111] In some embodiments (see Fig. 13 and Fig. 14) At least one adapter block 21 is arranged symmetrically around the connecting line 31 to which it is electrically connected. This enables uniform signal transmission on both sides of a first subsection 214. The adapter block 21 can comprise the first subsection 214, a second subsection 215, and a third subsection 216.

[0112] The orthographic projection of the first subsection 214 onto the substrate 110 partially overlaps with the orthographic projection of the connecting line 31 onto the substrate 110. For example, the orthographic projection of the first subsection 214 onto the substrate 110 lies within the orthographic projection of the connecting line 31 onto the substrate 110. The first subsection 214 is electrically connected to the connecting line 31. The second subsection 215 extends along the first direction X and is connected to the first subsection 214. The second subsection 215 is arranged symmetrically to the center line L1 of the first subsection 214 along the first direction X. The center line L1 of the first subsection 214 along the first direction X refers to the line connecting the midpoints of the first subsections 214 along the first direction. As shown in Fig. As shown in Figure 14, the center line L1 of the first subsection 214 runs along the first direction X along the second direction Y, and the first subsection 214 is symmetrical about the center line L1.

[0113] The third subsection 216 is connected to both ends of the second subsection 215 along the first direction X. Along the second direction Y, the dimension of the third subsection 216 is larger than that of the second subsection 215. The third subsection 216 is electrically connected to the first initialization signal line Vinit1 (via the first connection pattern 41), to the second initialization signal line Vinit2 (via the second connection pattern 42), or to the third initialization signal line Vinit3 (via the third connection pattern 43). The dimension of the third subsection 216 along the second direction Y is larger than that of the second subsection 215 along the second direction Y, thus allowing the third subsection 216 to more easily make contact with the first connection pattern 41, the second connection pattern 42, or the multiple third connection patterns 43.

[0114] For example, if the adapter block 21 is arranged symmetrically around the connecting line 31, which is electrically connected to the adapter block 21, the second subsection 215 of the adapter block 21 is arranged symmetrically around the center line L1 of the first subsection 214 along the first direction X. The adapter block 21 comprises two third subsections 216, each of which is connected to two ends of the second subsection 215 along the first direction X.

[0115] For example, the first adapter block is 211 (see Fig. 13 and Fig. 14) arranged symmetrically around the first connecting line 311, which is electrically connected to the first adapter block 211. The first adapter block 211 comprises a first adapter section 2141, a second adapter section 2151, and a third adapter section 2161. The orthographic projection of the first adapter section 2141 onto the substrate 110 corresponds to the orthographic projection of the first connecting line 311 onto the substrate 110, and the first connecting line 311 is electrically connected to the first adapter section 2141.

[0116] Continue with Fig. 13: The second adapter section 2151 extends along the first direction X and is connected to one side (the top) of the first adapter section 2141 along the second direction Y. The second adapter section 2151 is arranged symmetrically around the center line L11 of the first adapter section 2141 along the first direction X. In other words, the second adapter section 2151 is located on one side of the first adapter section 2141 along the second direction Y.

[0117] Two third adapter sections 2161 are each connected to the two ends of the second adapter section 2151 along the first direction X. The third adapter sections 2161 are electrically connected to the first initialization voltage signal line Vinit1 via the first connection pattern 41. For example, the third adapter sections 2161 are connected to the second subpattern 412 of the first connection pattern 41 in the first source-drain conductive layer SD1 and to the first initialization voltage signal line Vinit1 via the first subpattern 411 of the first connection pattern 41.

[0118] Along the second direction Y, the third adapter section 2161 is larger than the second adapter section 2151. This helps to increase the overlap area between the third adapter section 2161 and the first connection pattern 41, thereby increasing the contact area between the third adapter section 2161 and the first connection pattern 41 and reducing the contact resistance between the third adapter section 2161 and the first connection pattern 41.

[0119] As in Fig. As shown in Figure 14, the second adapter block 212 is, for example, arranged symmetrically around the second connecting line 312, which is electrically connected to the second adapter block 212. As shown in Fig. As shown in Figure 13, the second adapter block 212 comprises a fourth adapter section 2142, two fifth adapter sections 2152, and two sixth adapter sections 2162. As shown in Fig. As shown in Figure 14, the orthographic projection of the fourth adapter section 2142 on the substrate 110 corresponds to the orthographic projection of the second connecting line 312 on the substrate 110, and the fourth adapter section 2142 is electrically connected to the second connecting line 312.

[0120] As in Fig. As shown in Figure 13, the two fifth adapter sections 2152 are each connected to the two ends of the fourth adapter section 2142 along the first direction X and are arranged symmetrically around the fourth adapter section 2142. That is, the two fifth adapter sections 2152 are spaced apart along the first direction X, with the fourth adapter section 2142 located between and connected to the two fifth adapter sections 2152. Along the second direction Y, the fourth adapter section 2142 is larger than the fifth adapter section 2152. This increases the overlap area between the fourth adapter section 2142 and the second connecting line 312, thereby increasing the contact area between the fourth adapter section 2142 and the second connecting line 312 and reducing the contact resistance between the fourth adapter section 2142 and the second connecting line 312.

[0121] The two sixth adapter sections 2162 are each connected to the ends of the two fifth adapter sections 2152 that are furthest from the fourth adapter section 2142. The sixth adapter sections 2162 are electrically connected to the second initialization voltage signal line Vinit2 via the second connection pattern 42. For example, each of the sixth adapter sections 2162 is electrically connected to the fourth subpattern 422 of a second connection pattern 42 in the first source-drain conductive layer SD1 and to the second initialization voltage signal line Vinit2 via the third subpattern 421 of the second connection pattern 42.

[0122] Along the second direction Y, the sixth adapter section 2162 is larger than the fifth adapter section 2152. This increases the overlap area between the sixth adapter section 2162 and the second connection pattern 42, thereby increasing the contact area between the sixth adapter section 2162 and the second connection pattern 42 and reducing the contact resistance between the sixth adapter section 2162 and the second connection pattern 42.

[0123] For example, how in Fig. As shown in Figure 14, the third adapter block 213 is arranged symmetrically around the third connecting line 313, which is electrically connected to the third adapter block 213. The third adapter block 213 comprises a seventh adapter section 2143, an eighth adapter section 2153, and two ninth adapter sections 2163. The orthographic projection of the seventh adapter section 2143 onto the substrate 110 corresponds to the orthographic projection of the third connecting line 313 onto the substrate 110, and the seventh adapter section 2143 is electrically connected to the third connecting line 313.

[0124] In Fig. 13 The eighth adapter section 2153 extends along the first direction X and is connected to one side of the seventh adapter section 2143 along the second direction Y. The eighth adapter section 2153 is arranged symmetrically around the center line of the seventh adapter section 2143 along the first direction X. The third connecting line 313 is electrically connected to the seventh adapter section 2143 and the eighth adapter section 2153.

[0125] The two ninth adapter sections 2163 are each connected to the end of the eighth adapter section 2153 furthest from the seventh adapter section 2143. The ninth adapter sections 2163 are electrically connected to the third initialization voltage signal line Vinit3. As shown in the Fig. 12 and Fig. As shown in Figure 13, for example, the ninth adapter section 2163 is electrically connected to the sixth subpattern 432 of the third connection pattern 43 in the first source-drain conductive layer SD1 and is connected to the third initialization voltage signal line Vinit3 via the fifth subpattern 431 of the third connection pattern 43.

[0126] Along the second direction Y, the ninth adapter section 2163 is larger than the eighth adapter section 2153, which helps to increase the contact area between the ninth adapter section 2163 and the third connection pattern 43 and to reduce the contact resistance between the ninth adapter section 2163 and the third connection pattern 43.

[0127] In some embodiments, as in Fig. As shown in Figure 13, the first adapter block 211, the second adapter block 212, and the third adapter block 213 are arranged along the first direction X. In other words, the first adapter block 211, the second adapter block 212, and the third adapter block 213 are arranged side by side along the first direction X. This helps to improve the space utilization of the bridge wire layer SD2 and facilitates the placement of other structures on the bridge wire layer SD2 (such as a first fan-out line 22, a shielding pattern 27, and a first signal transmission line 28).

[0128] In some embodiments, according to Fig. 13 along the first direction X, the distance between two first connection patterns 41 connected to the same first adapter block 211 is greater than the distance between two second connection patterns 42 connected to the same second adapter block 212. Furthermore, the distance between two second connection patterns 42 connected to the same second adapter block 212 is greater than the distance between two sixth subpatterns 432 of the third connection pattern 43 connected to the same third adapter block 213. Based on this, as in Fig. Figure 13 shows that along the first direction X the dimension D3 of the first adapter block 211 is larger than the dimension D4 of the second adapter block 212, and the dimension D4 of the second adapter block 212 is larger than the dimension D5 of the third adapter block 213.

[0129] In some embodiments, the first adapter blocks 211, the second adapter blocks 212, and the third adapter blocks 213 are arranged periodically along the first direction X. That is, the first adapter blocks 211, the second adapter blocks 212, and the third adapter blocks 213 that are adjacent are arranged in the same sequence. For example, the sequence along the first direction X is: second adapter block 212, third adapter block 213, first adapter block 211, second adapter block 212, third adapter block 213, first adapter block 211, and so on. However, the present application does not restrict the arrangement sequence of the first adapter blocks 211, the second adapter blocks 212, and the third adapter blocks 213.

[0130] Along the first direction X, the first adapter blocks 211, the second adapter blocks 212, and the third adapter blocks 213 are arranged periodically. Thus, along the first direction X, the distance between two adjacent first adapter blocks 211, two adjacent second adapter blocks 212, and two adjacent third adapter blocks 213 is equal. This contributes to improving the uniformity of the grid structure formed by the first initialization signal line Vinit1 and the first connecting line 311, the second initialization signal line Vinit2 and the second connecting line 312, and the third initialization signal line Vinit3 and the third connecting line 313. This ensures that the resistances on the first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3 are uniform and equal.

[0131] Corresponding to the periodic arrangement of the first adapter blocks 211, the second adapter blocks 212, and the third adapter blocks 213, the first connecting lines 311, the second connecting lines 312, and the third connecting lines 313 are also arranged periodically. The arrangement sequence of the first connecting lines 311, the second connecting lines 312, and the third connecting lines 313 corresponds to the arrangement sequence of the first adapter blocks 211, the second adapter blocks 212, and the third adapter blocks 213.

[0132] As in Fig. As shown in Figure 13, the bridge wire layer SD2 also includes several first fan-out lines 22. These are spaced apart along the second direction Y, and each of the first fan-out lines 22 extends along the first direction X. For example, both ends of the first fan-out line 22 can extend along the first direction X to the edge of the display area AA to improve the pattern uniformity of the bridge wire layer SD2. Naturally, the first fan-out line 22 can be provided with openings (such as the second opening 221 and the third opening 222) to divide the first fan-out line 22 into multiple segments.

[0133] Along the second direction Y, the first fan-out lines 22 and the multiple adapter blocks 21 are offset. In other words, along the second direction Y, there is a gap between the first fan-out lines 22 and the adapter blocks 21. This helps to reduce signal interference between the first fan-out lines 22 and the adapter blocks 21 and prevents contact between the first fan-out lines 22 and the adapter blocks 21.

[0134] In some embodiments, such as in Fig. As shown in Figure 13, the bridge wire layer SD2 additionally contains several shielding patterns 27. The orthographic projections of the shielding patterns 27 on the substrate 110 cover the orthographic projections of the pixel circuits 120 on the substrate 110. The shielding patterns 27 can shield the pixel circuits 120 from interference caused by signal lines (such as data lines DL) in the second wiring layer SD3.

[0135] In some embodiments, such as in Fig. As shown in Figure 13, the bridge wire layer SD2 also contains several first signal transmission lines 28 spaced apart along the second direction Y. Each of the first signal transmission lines 28 extends along the first direction and is connected to a row of shielding patterns 27, which can reduce the resistance of the first signal transmission lines 28. As shown in Fig. As shown in Figure 13, the first signal transmission lines 28 are electrically connected to the seventh connection patterns 47 in the first source-drain conductive layer SD1 and via the seventh connection patterns 47 to the pixel circuits in order to transmit a first voltage signal to the seventh connection patterns 47 and the pixel circuits.

[0136] In some embodiments, such as in Fig. As shown in Figure 13, at least part of the first adapter block 211 is arranged opposite the shielding patterns 27 along the second direction Y. For example, the first adapter block 211 is arranged on both sides along the first direction opposite two adjacent shielding patterns 27. Along the second direction Y, at least part of the second adapter block 212 is arranged opposite the shielding pattern 27. For example, the second adapter block 212 is arranged on both sides along the first direction X opposite two adjacent shielding patterns 27. Along the first direction X, the third adapter block 213 is offset from the shielding pattern 27. That is, no part of the third adapter block 213 is arranged opposite the shielding pattern 27 along the second direction Y.

[0137] In some embodiments, such as in Fig. As shown in Figure 13, the bridge wire layer SD2 also contains several tenth connection patterns 29 which are electrically connected to the ninth connection pattern 49 to electrically connect the pixel circuit 120 to the light-emitting element 200.

[0138] As in Fig. As shown in Figure 14, the second wiring layer SD3 contains several data lines DL. The data lines DL are divided into several groups, with each group comprising two adjacent data lines DL. There is a first distance D1 between the two data lines DL of a group, and a second distance D2 between two adjacent groups of data lines DL. The first distance D1 is smaller than the second distance D2. In other words, two adjacent data lines DL are grouped together. The data lines DL are, for example, zigzag lines. As shown in Fig. As shown in Figure 14, between two data lines DL of a group there is a first partial distance D11 and a second partial distance D12. Along the first direction X, the first partial distance D11 is larger than the second partial distance D12 and smaller than the second distance D2 between two adjacent groups of data lines DL.

[0139] Once again with reference to Fig. 14 comprises a data line DL comprising third widened sections 331 and third extended sections 332, which are arranged (alternately connected) along the second direction Y. That is, two adjacent third widened sections 331 are connected by a third extended section 332, and two adjacent third extended sections 332 are connected by a third widened section 331.

[0140] The orthographic projection of the third widened section 331 on the substrate 110 partially overlaps with the orthographic projection of the matching pattern 23 on the substrate 110. The third widened section 331 is electrically connected to the matching pattern 23. The dimension of the third widened section 331 along the first direction X is larger than the dimension of the third extended section 332 along the first direction X. This increases the overlap area between the third widened section 331 and the matching pattern 23, thereby increasing the contact area between the third widened section 331 and the matching pattern 23 and improving the reliability and stability of the connection between the third widened section 331 and the matching pattern 23.

[0141] As in Fig. As shown in Figure 14, the second wiring layer SD3 also contains several connecting lines 31. For example, the second wiring layer SD3 contains a first connecting line 311, a second connecting line 312, and a third connecting line 313. A connecting line 31 contains second widened sections 314 and second extended sections 315, which are arranged (alternately connected) along the second direction Y. That is, two adjacent second widened sections 314 are connected by a second extended section 315, and two adjacent second extended sections 315 are connected by a second widened section 314.

[0142] The orthographic projection of the second widened section 314 on the substrate 110 corresponds to the orthographic projection of the adapter block 21 on the substrate 110. The second widened section 314 serves for the electrical connection with the adapter block 21. The dimension of the second widened section 314 along the first direction X is larger than the dimension of the second extended section 315 along the first direction X. This increases the overlap area between the second widened section 314 and the adapter block 21, thereby increasing the contact area between the second widened section 314 and the adapter block 21 and improving the reliability and stability of the connection between the second widened section 314 and the adapter block 21.

[0143] As in Fig. As shown in Figure 14, the third widened section 331 and the second widened section 314 are offset along the second direction Y. In other words, there is a distance between the third widened section 331 and the second widened section 314 along the second direction Y. In other words, the third widened section 331 and the second widened section 314 do not lie on a straight line along the first direction X. This helps to increase the distance between the third widened section 331 and the second widened section 314. Put another way, this helps to increase the distance between a data line and a connection line 31, thereby reducing the risk of signal interference between the data line DL and the connection line 31.

[0144] As in Fig. As shown in Figure 14, each of the connecting lines 31 is located between two data lines DL of a group. The two data lines DL of a group are arranged symmetrically around the central data line 31. This helps to improve the space utilization of the second wiring layer SD3, increase the wiring density of the data lines DL and the connecting lines 31, and thereby improve the PPI of the display panel. For example, the second widened section 314 is located within the second partial spacing D12 between the two data lines DL of a group.

[0145] In some embodiments, such as in Fig. As shown in Figure 14, the second wiring layer SD3 also contains several first voltage signal lines VDD. The first voltage signal lines VDD run along the second direction Y and are spaced apart along the first direction X. The orthographic projection of the first voltage signal line VDD on the substrate 110 partially overlaps with the orthographic projection of the first signal transmission line 28 in the bridge wire layer SD2 on the substrate 110. Each of the first voltage signal lines VDD is electrically connected to several (all) first signal transmission lines 28. In other words, the first voltage signal line VDD is sequentially electrically connected to the first signal transmission line 28, the seventh connection pattern 47, and the pixel circuit.The multiple first voltage signal lines VDD and the multiple first signal transmission lines 28 are interconnected in a grid structure, which helps to reduce the resistance of the first voltage signal lines VDD and the multiple first signal transmission lines 28.

[0146] As in Fig. As shown in Figure 14, for example, a first voltage signal line VDD is located between each pair of adjacent groups of data lines DL. The first voltage signal line VDD serves, for example, to transmit a supply voltage signal. Along the first direction X, the width of the first voltage signal line VDD is greater than that of the data line DL and greater than that of the connecting line 31.

[0147] As in Fig. As shown in Figure 14, the second wiring layer SD3 also contains several eleventh connection patterns 34. The orthographic projection of the eleventh connection pattern 34 on the substrate 110 overlaps with the orthographic projection of the tenth connection pattern 29 in the bridge wire layer SD2 on the substrate 110, and the eleventh connection pattern 34 is electrically connected to the tenth connection pattern 29. In other words, the eleventh connection pattern 34 is successively electrically connected to the tenth connection pattern 29, the ninth connection pattern, and the pixel circuit.

[0148] In some embodiments (see Fig. 15) The bridge wire layer SD2 also contains first connection segments 24 and connection blocks 25. One end of a first connection segment 24 is connected to a first fan-out line 22, and the other end is connected to a connection block 25. Each of the first connection segments 24 is connected to only one first fan-out line 22 and one connection block 25. The connection block 25 is used to establish an electrical connection with the second fan-out line 32. As shown in Fig. As shown in Figure 15, the dimension of the connecting block 25 along the first direction X is larger than the width of the first connecting segment 24. This helps to increase the overlap area between the connecting block 25 and the second fan-out line 32, thereby increasing the contact area between the connecting block 25 and the second fan-out line 32 and reducing the contact resistance between the connecting block 25 and the second fan-out line 32.

[0149] As in Fig. As shown in Figure 15, of several connection blocks 25 in a column, only one connection block 25 is electrically connected to a first fan-out line 22 via a first connection segment 24, so that a second fan-out line 32 can be electrically connected to a single first fan-out line 22. The fabrication of several connection blocks 25 in a column contributes to improving the pattern uniformity of the bridge wire layer SD2.

[0150] According to Fig. 16 The second wiring layer SD3 also contains second fan-out lines 32. In some embodiments, the structure of the second fan-out line 32 is identical to that of the connecting line 31, thereby improving the pattern uniformity of the second wiring layer SD3 and reducing the manufacturing difficulties of the second wiring layer SD3.

[0151] As in Fig. As shown in Figure 16, a second fan-out line 32 comprises several first widened sections 324 and several first extended sections 325 arranged (alternately connected) along the second direction Y.

[0152] The first widened sections 324 and the second widened section 314 of the connecting line 31 are arranged along the first direction X, i.e., the first widened sections 324 and the second widened section 314 lie side by side along the first direction X. This ensures that the shape and structure of the second fan-out line 32 are essentially identical to those of the connecting line 31. This improves the pattern uniformity of the second wiring layer SD3 and simplifies the fabrication of the second wiring layer SD3.

[0153] The first widened section 324 is offset from the first fan-out line 22 along the second direction Y. That is, the orthographic projection of the first widened section 324 on substrate 110 does not overlap with the orthographic projection of the first fan-out line 22 on substrate 110. In other words, there is a gap between the first widened section 324 and the first fan-out line 22 along the second direction Y.

[0154] The orthographic projection of the first widened section 324 on the substrate 110 overlaps with the orthographic projection of the connecting block 25 on the substrate 110, and the first widened section 324 is electrically connected to the connecting block 25. Along the first direction X, the dimension of the first widened section 324 is larger than that of the first extended section 325, which helps to increase the contact area between the first widened section 324 and the connecting block 25 and to improve the connection stability between the first widened section 324 and the connecting block 25.

[0155] As in Fig. As shown in Figure 16, each of the second fan-out lines 32, similar to the connecting line 31, is located between two data lines DL of a group. For example, the first widened section 324 of the second fan-out line 32 can also be located within the second partial spacing D12 between the two data lines DL. This helps to improve the space utilization of the second wiring layer SD3, increase the wiring density of the data lines DL, the connecting lines 31, and the second fan-out lines 32, and thus improve the PPI of the display panel.

[0156] In some embodiments, such as in Fig. As shown in Figure 16, the second fan-out line 32 extends through the display area AA along the second direction Y. That is, within the display area AA, the length of the second fan-out line 32 in the second direction Y is approximately equal to the length of the connecting line 31 in the second direction Y. Furthermore, the shape and structure of the second fan-out line 32 within the display area AA are approximately the same as those of the connecting line 31. This helps to improve the pattern uniformity of the second wiring layer SD3 and simplifies the fabrication of the second wiring layer SD3.

[0157] As in Fig. As shown in Figure 16, the second fan-out line 32 also includes a first opening 321, which divides the second fan-out line 32 into a first wiring segment 322 and a second wiring segment 323. One end (e.g., the lower end) of the first wiring segment 322 extends to the fan-out area BB1 (not shown), and the other end extends to a first fan-out line 22, which is electrically connected to the second fan-out line 32. The second wiring segment 323 is located on the side of the first wiring segment 322 facing away from the fan-out area BB1 and is electrically insulated from the first wiring segment.

[0158] The first opening 321 divides the second fan-out line 32 into the first wiring segment 322 and the second wiring segment 323, which are electrically isolated from each other. The first fan-out line 32 is electrically connected to the first wiring segment 322 and runs through the first wiring segment 322 to the fan-out area BB1. The second wiring segment 323 can also be used, for example, to transmit other signals. For instance, the array substrate 100 additionally contains a second voltage signal line VSS, which is located within the peripheral area BB and at least partially surrounds the display area AA. The second voltage signal line VSS can, for example, be electrically connected to a cathode layer of the light-emitting element. The second wiring segment 323 can be electrically connected to both the second voltage signal line VSS and the cathode layer.In other words, the second wiring segment 323 is arranged parallel to the cathode layer, which helps to reduce the resistance of the cathode layer. This helps to shorten the transmission path of the data signal on the second fan-out line 32 and thus reduce the voltage drop on the second fan-out line 32 during the transmission of the data signal.

[0159] The multiple first widened sections 324 include a first widened target section 324A. This first widened target section 324A is the first widened section 324 of the multiple first widened sections 324 in the first wiring segment 322 that is closest to the first fan-out line 22. The first connecting segment 24 connects the first fan-out line 22 and the first widened target section 324A. This allows the first wiring segment 322 to be electrically connected to the first fan-out line 22 sequentially via the first widened target section 324A and the first connecting segment 24. This eliminates the need for a widened area directly above the first fan-out line 22 in the first wiring segment 322, thereby simplifying the structure of the first wiring segment 322 and improving the uniformity of the second wiring layer SD3.

[0160] Referring to Fig. 15 The bridge wire layer SD2 also includes a second connection segment 26 and several columns of matching patterns 23. Each column of the multiple columns of matching patterns 23 contains multiple matching patterns 23 spaced apart along the second direction Y. The multiple matching patterns 23 in a column are each electrically connected to multiple pixel circuits (not shown) in a column, and the multiple matching patterns 23 in a column are also electrically connected to a data line DL. For example, the data line DL is sequentially electrically connected to the multiple matching patterns 23 in a column, the multiple eighth connection patterns 48 in a column, and the multiple pixel circuits in a column, thereby transmitting the data signal carried by the data line DL to the pixel circuits.That is, the multiple matching patterns 23 in a column are each electrically connected to the multiple eighth connection patterns 48 in a column in the first source-drain conductive layer SD and electrically connected via the multiple eighth connection patterns 48 in the column to the multiple pixel circuits in a column.

[0161] As in Fig. As shown in Figure 15, one end of the second connection segment 26 is electrically connected to the first fan-out line 22, and the other end is connected to the target matching pattern 23. The target matching pattern 23A is the matching pattern 23 in the column of matching patterns 23 that are electrically connected to the first data line DL1, located on the side of the first fan-out line 22 facing the fan-out area BB1, and closest to the first fan-out line 22. It is understood that a first fan-out line 22 is only electrically connected to a matching pattern 23 via a second connection segment 26.

[0162] In other words, the first data line DL1 is electrically connected to the target matching pattern 23A, the second link segment 26, the first fan-out line 22, the first link segment 24, the link block 25, and the second fan-out line 32, in that order. Furthermore, the first data line DL1 is also electrically connected to the target matching pattern 23A, the eighth matching pattern 48, and the pixel circuit, in that order. This eliminates the need for additional connection structures between the first data line DL1 and the first fan-out line 22 (e.g., additional through-holes in the second planarization layer), thus simplifying the connection structure between the first data line DL1 and the first fan-out line 22.

[0163] As in Fig. As shown in Figure 15, the first fan-out line 22 also has a second opening 221. The second opening 221 is located on the side of the first connection segment 24 facing away from the first data line DL1, which is electrically connected to the first fan-out line 22. The second opening 221 divides the first fan-out line 22 into two sections, which shortens the data signal propagation path on the first fan-out line 22 and reduces the voltage drop of the data signal across the first fan-out line 22.

[0164] As in Fig. As shown in Figure 16, the orthographic projection of the second opening 221 on the substrate 110 coincides with the orthographic projection of the data line DL on the substrate 110 that is closest to the first connection segment 24. This minimizes the propagation path of the data signal on the first fan-out line 22 and prevents the second opening 221 from separating the first connection segment 24. This improves the stability of the signal transmission between the first connection segment 24 and the first fan-out line 22.

[0165] As in Fig. As shown in Figure 15, the first fan-out line 22 also has a third opening 222. The third opening 222 is located on the side of the first data line DL11, which is electrically connected to the first fan-out line 22, opposite the second fan-out line 32. In other words, the third opening 222 is located on the side of the second connection segment 26 opposite the second fan-out line 32. The third opening 222 divides the first fan-out line 22 into two sections, thereby further shortening the propagation path of the data signal on the first fan-out line 22 and reducing the voltage drop of the data signal on the first fan-out line 22.

[0166] As in Fig. As shown in Figure 16, the orthographic projection of the third aperture 222 on the substrate 110 corresponds to the orthographic projection of the connecting line 31, which is closest to the second connecting segment 26, or the first voltage signal line VDD (the first voltage signal line VDD in Fig. 16) on the substrate 110. This minimizes the propagation path of the data signal on the first fan-out line 22 and prevents the second opening 221 from separating the second connection segment 26, thereby improving the stability of the signal transmission between the second connection segment 26 and the first fan-out line 22.

[0167] For example, the first fan-out line 22 includes both the second opening 221 and the third opening 222. The section of the first fan-out line 22 between the second opening 221 and the third opening 222 serves to transmit the data signal. This minimizes the propagation path of the data signal on the first fan-out line 22 and reduces data signal loss on the first fan-out line 22. In other embodiments, the first fan-out line 22 can, of course, also include only the second opening 221 or the third opening 222, which will not be discussed in detail here.

[0168] In some embodiments (see Fig. 15 and Fig. 16) The multiple first data lines DL1 include at least one first sub-data line DL11. The orthographic projection of the first sub-data line DL11 on substrate 110 does not overlap with the orthographic projection of an adapter block 21 on substrate 110. The orthographic projection of the second extended section 26, which is electrically connected to the first sub-data line DL11, on substrate 110 lies within the orthographic projection of the first sub-data line DL11 on substrate 110. Thus, the second extended section 26, which is electrically connected to the first sub-data line DL11, does not interfere with the adapter block 21. In other words, there is no adapter block 21 between the matching pattern 23, which is electrically connected to the first sub-data line DL11, and the first fan-out line 22, which is electrically connected to the first sub-data line DL11.

[0169] In some embodiments (see Fig. 17 to 24) the several first data lines DL1 also include at least one second sub-data line DL12. The orthographic projection of the second sub-data line DL12 on the substrate 110 partially overlaps with the orthographic projection of a column of adapter blocks 21 on the substrate 110.

[0170] The column of adapter blocks 21, which are electrically connected to the second sub-data line DL12, includes a destination adapter block 21A. The destination adapter block 21A is located on the side of the first fan-out line 22, which is electrically connected to the second sub-data line DL12 and is closest to the first fan-out line 22, which is electrically connected to the second sub-data line DL12, facing the fan-out area BB1. The orthographic projection of the target adapter block 21A on the substrate 110 does not overlap with the orthographic projection of the second sub-data line DL12 on the substrate 110. For example, in the case of multiple adapter blocks 21, the orthographic projections of all adapter blocks 21 on the substrate 110, with the exception of the target adapter block 21A, partially overlap with the orthographic projection of the connecting line 31 on the substrate 110, which is electrically connected to the adapter blocks 21.Furthermore, all adapter blocks 21, with the exception of the target adapter block 21A, are arranged symmetrically around the connecting line 31, which is electrically connected to the adapter blocks 21.

[0171] The second connection segment 26, which is electrically connected to the second sub-data line DL12, is the destination connection segment 26A. The orthographic projection of the destination connection segment 26A on substrate 110 lies within the orthographic projection of the second sub-data line DL12 on substrate 110. The destination connection segment 26A extends along the second direction Y and is spaced from the destination adapter block 21A, and / or the destination connection segment 26A is a zigzag line, and the orthographic projection of the destination connection segment 26A on substrate 110 does not overlap, at least partially, with the orthographic projection of the second sub-data line DL12 on substrate 110. There is a distance between the destination connection segment 26A and the destination adapter block 21A.

[0172] In some embodiments (see Fig. 17 and Fig. 18) includes at least one second sub-data line DL12, a first destination data line DL121, and the orthographic projection of the first destination data line DL121 on the substrate 110 partially overlaps with the orthographic projection of a column of first adapter blocks 211 on the substrate 110.

[0173] As in Fig. As shown in Figure 17, a matching pattern for connecting the first destination data line DL121 and the first fan-out line 22 is a first destination matching pattern 231A. Along the second direction Y, at least part of the first adapter block 211 is arranged opposite the shielding pattern 27. For example, both ends of the first adapter block 211 are arranged along the first direction X opposite the shielding pattern 27. The destination adapter block 21A includes a first destination adapter block 211A. A first adapter block 211 is located between the first destination matching pattern 231A and the first fan-out line 22. This first adapter block 211 is a first destination adapter block 211A.

[0174] In other words: As in Fig. As shown in Figure 17, the first destination adapter block 211A is contained in a column of several first adapter blocks 211, which are electrically connected to the second sub-data line DL12. The first destination adapter block 211A is located between the first fan-out line 22, which is electrically connected to the first destination data line DL121, and the first destination matching pattern 231A.

[0175] As in Fig. As shown in Figure 17, the first destination adapter block 211A has a fourth opening 2111. The destination connection segment 26A, electrically connected to the first destination data line DL121, extends along the second direction Y. The destination connection segment 26A passes through the fourth opening 2111, and an avoidance gap exists between the destination connection segment 26A and the first destination adapter block 211A. Thus, a fourth opening 2111 is provided in the first destination adapter block 211A. This fourth opening 2111 serves to bypass the destination connection segment 26A, which is electrically connected to the first destination data line DL121, thereby preventing a short circuit between the first destination adapter block 211A and the destination connection segment 26A and ensuring that the data signal and the first initialization signal do not interfere with each other.

[0176] As in Fig. As shown in Figure 18, the orthographic projection of the target connection segment 26A, which is electrically connected to the first target data line DL121, is located on the substrate 110 within the orthographic projection of the first target data line DL121 on the substrate 110.

[0177] In some embodiments, such as in Fig. 19 and Fig. Figure 20 shows that at least one second sub-data line DL12 includes a second destination data line DL122, and the orthographic projection of the second destination data line DL122 on the substrate 110 partially overlaps with the orthographic projection of a column of second adapter blocks 212 on the substrate 110.

[0178] As in Fig. As shown in Figure 19, the target matching pattern 23A also includes a second target matching pattern 232A, which is used to connect the second target data line DL122 and the first fan-out line 22. The target adapter block 21A includes a second target adapter block 212A. A column of several second adapter blocks 212, electrically connected to the second target data line DL122, includes the second target adapter block 212A. Along the second direction Y, the second target adapter block 212A is located between the first fan-out line 22, which is electrically connected to the second target data line DL122, and the second target matching pattern 232A.

[0179] Along the second direction Y, at least part of the second adapter block 212 is located opposite the shielding pattern 27. For example, both ends of the second adapter block 212 are located along the first direction X opposite the shielding pattern 27. In other words, a second adapter block 211 is located between the second target matching pattern 232A and the first fan-out line 22. This second adapter block 211 serves as the second target adapter block 212A.

[0180] In other words, as in Fig. As shown in Figure 19, a column of several first adapter blocks 211, which are electrically connected to the second destination data line DL122, comprises a first destination adapter block 211A. The first destination adapter block 211A is located between the first fan-out line 22, which is electrically connected to the second destination data line DL122, and the second destination matching pattern 232A.

[0181] For example, the orthographic projection of the second destination data line DL122 on substrate 110 partially overlaps with the orthographic projections of all second adapter blocks 212 in a column of second adapter blocks 212 on substrate 110, with the exception of the second destination adapter block 212A.

[0182] As in Fig. As shown in Figure 19, the second adapter block 212, with the exception of the second target adapter block 212A, comprises a first subsection 214, a second subsection 215, and two third subsections 216. The two third subsections 216 are located on opposite sides of the first subsection 214 along the first direction X. The second subsection 215 connects the first subsection 214 and the two third subsections 216.

[0183] As in Fig. As shown in Figure 19, the destination connection segment 26A, which is electrically connected to the second destination data line DL122, extends along the second direction Y. As shown in Fig. As shown in Figure 20, the orthographic projection of the target connection segment 26A on substrate 110 is located within the orthographic projection of the third sub-data line on substrate 110.

[0184] As in Fig. As shown in Figure 19, the second destination adapter block 212A comprises a first subsection 214, a fourth subsection 217, and a third subsection 216. The third subsection 216 is located on the side of the first subsection 214 facing away from the destination connection segment 26A. The fourth subsection 217 is located between the first subsection 214 and the third subsection 216, connecting the first and third subsections 214 and 216. That is, compared to other second adapter blocks 212, the second destination adapter block 212A lacks the third subsection 216 facing the destination connection segment 26A and the part of the second subsection 215 that connects the first subsection 214 to the third subsection 216 on the right side (facing the destination connection segment 26A).The portion of the second target adapter block 212A facing the target connection segment 26A is removed (compared to the other second adapter blocks 212) to prevent a short circuit between the second target adapter block 212A and the target connection segment 26A, thus ensuring that the data signal and the second initialization signal do not interfere with each other. In a further embodiment of the present disclosure, the target connection segment 26A can also be configured as a zigzag line or curve, such that the third subsection 216 lies half within the area of ​​the target connection segment 26A enclosed by the zigzag line or curve, without any part of the third subsection 216 being removed.

[0185] In some embodiments, such as in the Fig. 21 and Fig. As shown in Figure 22, the multiple first data lines DL1 include at least one third destination data line DL123. The orthographic projection of the third destination data line DL123 on substrate 110 partially overlaps with the orthographic projection of a column of third adapter blocks 213 on substrate 110.

[0186] As in Fig. As shown in Figure 21, the target matching pattern 23A also includes a third target matching pattern 233A, which serves to connect the third target data line DL123 to the first fan-out line 22. The target adapter block 21A further includes a third target adapter block 213A. A column of third adapter blocks 212, which are electrically connected to the third target data line DL123, contains the third target adapter block 213A. Along the second direction Y, the third target adapter block 213A is located between the first fan-out line 22, which is electrically connected to the second sub-data line DL12, and the second target matching pattern 232A.

[0187] As in Fig. As shown in Figure 21, the third adapter block 213 and the shielding pattern 27 are offset along the first direction X. This means that along the second direction Y, no part of the third adapter block 213 is opposite the shielding pattern 27. This allows a wiring space to remain between the third adapter block 213 and the shielding pattern 27.

[0188] For example, the orthographic projection of the third destination data line DL123 on substrate 110 partially overlaps with the orthographic projections of all third adapter blocks 213 in a column of third adapter blocks 213 on substrate 110, with the exception of the third destination adapter block 213A.

[0189] In some embodiments, such as in the Fig. 21 and Fig. As shown in Figure 22, the target connection segment 26A, electrically connected to the third target data line DL123, extends along the second direction Y. Furthermore, the orthographic projection of the second extended section 26, which is electrically connected to the third target data line DL123, lies on substrate 110 within the orthographic projection of the third target data line DL123 on substrate 110.

[0190] As in Fig. As shown in Figure 21, the other third adapter blocks 213, with the exception of the third destination adapter block 213A, comprise a first subsection 214, a second subsection 215, and two third subsections 216. The two third subsections 216 are located on opposite sides of the first subsection 214 along the first direction X, and the second subsection 215 connects the first subsection 214 and the two third subsections 216.

[0191] With reference to Fig. The third destination adapter block 213A comprises a first subsection 214, a fifth subsection 218, and a third subsection 216. The second subsection 215 is located on the side of the first subsection 214 facing away from the destination connection segment 26A. The fifth subsection 218 is located between and connects the first and second subsections 214 and 215. In other words, compared to other third adapter blocks 213, the third destination adapter block 213A lacks the third subsection 216 facing the destination connection segment 26A and the portion of the second subsection 215 that connects the first subsection 214 to the third subsection 216 on the right side (facing the destination connection segment 26A).In other words, the part of the third destination adapter block 213A facing the destination link segment 26A (compared to other third adapter blocks 213) is removed to prevent a short circuit between the second destination adapter block 212A and the destination link segment 26A, and thus interference between the data signal and the second initialization signal.

[0192] In other embodiments, such as in Fig. 23 and Fig. As shown in Figure 24, the second connection segment 26, which is electrically connected to the third destination data line DL123, is the destination connection segment 26A. The destination connection segment 26A is zigzag-shaped and spaced apart from the third adapter block 213. The orthographic projection of the destination connection segment 26A on the substrate 110 does not overlap, at least partially, with the orthographic projection of the third destination data line DL123 on the substrate 110.

[0193] As in Fig. As shown in Figure 23, the third adapter block 213 is offset from the shielding pattern 27 along the first direction X. This means that along the second direction Y, no part of the third adapter block 213 is located opposite the shielding pattern 27. This allows a wiring space to remain between the third adapter block 213 and the shielding pattern 27. The destination connection segment 26A, electrically connected to the third destination data line DL123, is located within this wiring space.

[0194] In some embodiments, one to ten connecting lines 31 may be provided between two adjacent second fan-out lines 32. For example, one, three, six, or ten data lines may be provided between two adjacent second fan-out lines 32, although this is not a limitation in the present disclosure.

[0195] As in Fig.As shown in Figure 25, for example, three connecting lines 31 are provided between two adjacent second fan-out lines 32. These three connecting lines 31 are a first connecting line 311, a second connecting line 312, and a third connecting line 313. In some embodiments, the wiring density of the first connecting lines 311, the second connecting lines 312, and the third connecting lines 313 is the same.

[0196] In some embodiments, three adjacent connecting lines 31 comprise a first connecting line 311, a second connecting line 312, and a third connecting line 313. The order of these adjacent first connecting lines 311, second connecting line 312, and third connecting line 313 can be chosen arbitrarily.

[0197] In some embodiments, there are three connecting lines 31 between two adjacent second fan-out lines 32: a first connecting line 311, a second connecting line 312 and a third connecting line 313.

[0198] For example, along the first direction X, pointing from one side edge of the display area AA to the other side edge (e.g., from left to right), the second connecting line 312, the third connecting line 313, and the first connecting line 311 are arranged successively between two adjacent second fan-out lines 32. Alternatively, along the first direction X, pointing from one side edge of the display area AA to the other side edge (e.g., from left to right), the second connecting line 312, the first connecting line 311, and the third connecting line 313 are arranged successively between two adjacent second fan-out lines 32. Alternatively, the first connecting line 311, the second connecting line 312, and the third connecting line 313 are arranged along the first direction X, from one side edge of the display area AA to the other side edge (e.g., from left to right).The first connecting line 311, the third connecting line 313, and the second connecting line 312 are arranged successively between two adjacent second fan-out lines 32 along the first direction X, pointing from one side edge of the display area AA to the other side edge (e.g., from left to right). Alternatively, the first connecting line 311, the third connecting line 313, and the second connecting line 312 are arranged successively between two adjacent second fan-out lines 32 along the first direction X, pointing from one side edge of the display area AA to the other side edge (e.g., from left to right). Alternatively, the third connecting line 313, the second connecting line 312, and the first connecting line 311 are arranged successively between two adjacent second fan-out lines 32 along the first direction X, pointing from one side edge of the display area AA to the other side edge (e.g., from left to right).(from left to right) the third connecting line 313, the first connecting line 311 and the second connecting line 312 are arranged successively between two adjacent second fan-out lines 32.

[0199] The above description is merely one specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any modifications or substitutions that a person skilled in the art might conceive within the scope of this disclosure shall be covered by the scope of protection of this disclosure. Therefore, the scope of protection of the present disclosure is subject to the scope of protection of the claims. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] CH 202310629298.1

[0001]

Claims

[1] Array substrate with a display area and a fan-out area, wherein the fan-out area is adjacent to a side edge of the display area, the array substrate comprising: a substrate; multiple pixel circuits on the substrate, arranged in multiple rows and columns; a first wiring layer on the side of the multiple pixel circuits facing away from the substrate, comprising multiple first initialization signal lines, multiple second initialization signal lines, and multiple third initialization signal lines extending along a first direction, the first direction being the row direction in which the multiple subpixels are arranged, with each row of pixel circuits being electrically connected to a first initialization signal line, a second initialization signal line, and a third initialization signal line; a bridge wire layer on the side of the first wiring layer facing away from the substrate, comprising multiple columns of adapter blocks and multiple first fan-out lines, each column of adapter blocks comprising multiple adapter blocks spaced apart along a second direction, the multiple first fan-out lines running along the first direction, the second direction being the row direction in which the multiple pixel circuits are arranged; a second wiring layer on a side of the bridge wire layer facing away from the substrate, comprising multiple interconnect lines, multiple data lines, and multiple second fan-out lines extending along the second direction, each interconnect line being electrically connected via a column of adapter blocks to one of the multiple first initialization signal lines, one of the multiple second initialization signal lines, and one of the multiple third initialization signal lines, each of the data lines being electrically connected to a column of pixel circuits, the multiple data lines comprising multiple first data lines, with one fan-out end of each of the first data lines being located in the display area, and with one fan-out end of each of the second fan-out lines extending into the fan-out area;and wherein each of the first fan-out lines is electrically connected to one of the first data lines and to one of the second fan-out lines. [2] Array substrate according to claim 1, wherein both ends of at least one of the adapter blocks are electrically connected along the first direction to the first initialization signal line, the second initialization signal line or the third initialization signal line. [3] Array substrate according to claim 2, wherein at least one of the adapter blocks is arranged symmetrically around the connecting line electrically connected to the adapter block and the adapter block comprises the following: a first subsection, wherein the orthographic projection of the first subsection on the substrate partially overlaps the orthographic projection of the connecting line on the substrate; wherein the first subsection is electrically connected to the connecting line; a second subsection, wherein the second subsection extends along the first direction, is connected to the first subsection and is arranged symmetrically around a center line of the first subsection along the first direction; and a third subsection connected to an end of the second subsection opposite the first subsection, wherein the third subsection has a larger dimension along the second direction than the second subsection and the third subsection is electrically connected to the first initialization signal line, the second initialization signal line or the third initialization signal line. [4] Array substrate according to any one of claims 1 to 3, wherein the multiple adapter blocks comprise multiple columns of first adapter blocks, multiple columns of second adapter blocks and multiple columns of third adapter blocks spaced apart along the first direction; each column of first adapter blocks comprises multiple first adapter blocks spaced apart along the second direction, and the multiple first adapter blocks in the column are each electrically connected to the multiple first initialization signal lines; each column of second adapter blocks comprises multiple second adapter blocks spaced apart along the second direction, and the multiple second adapter blocks in the column are each electrically connected to the multiple second initialization signal lines;Each column of third adapter blocks comprises multiple third adapter blocks spaced apart along the second direction, and the multiple third adapter blocks in the column are each electrically connected to the multiple third initialization signal lines; and wherein the multiple connecting lines comprise multiple first connecting lines, multiple second connecting lines, and multiple third connecting lines; wherein each of the first connecting lines is electrically connected to a column of first adapter blocks, each of the second connecting lines is electrically connected to a column of second adapter blocks, and each of the third connecting lines is electrically connected to a column of third adapter blocks. [5] Array substrate according to claim 4, wherein along the first direction the dimension of the first adapter block is larger than the dimension of the second adapter block and the dimension of the second adapter block is larger than the dimension of the third adapter block. [6] Array substrate according to claim 4 or 5, wherein along the first direction the first adapter blocks, the second adapter blocks and the third adapter blocks are arranged periodically and the first connecting lines, the second connecting lines and the third connecting lines are arranged periodically. [7] Array substrate according to any one of claims 4 to 6, further comprising: a first source-drain conductive layer located between the first wiring layer and the bridge wire layer, comprising multiple first connection patterns, multiple second connection patterns, and multiple third connection patterns; wherein the first connection pattern comprises a first and a second subpattern, wherein the first subpattern is electrically connected to the first initialization signal line and to the pixel circuit, and the second subpattern is electrically connected to the first adapter block; wherein the second connection pattern comprises a third and a fourth subpattern, the third subpattern being electrically connected to the second initialization signal line and to the pixel circuit, and the fourth subpattern being electrically connected to the second adapter block; and wherein the third connection pattern comprises a fifth and a sixth subpattern, wherein the fifth subpattern is electrically connected to the third initialization signal line and to the pixel circuit, and the sixth subpattern is electrically connected to the third adapter block. [8] Array substrate according to claim 7, wherein the first source-drain conductive layer further comprises: a fourth connection pattern, wherein the fourth connection pattern has the same shape and dimensions as the first subpattern and is electrically connected to the first initialization signal line and to the pixel circuit; a fifth connection pattern, wherein the fifth connection pattern has the same shape and dimensions as the third subpattern and is electrically connected to the second initialization signal line and to the pixel circuit; and a sixth connection pattern, wherein the sixth connection pattern has the same shape and dimensions as the fifth subpattern and is electrically connected to the third initialization signal line and to the pixel circuit. [9] Array substrate according to any one of claims 1 to 8, wherein the second fan-out line has a first opening that divides the second fan-out line into a first and a second wiring segment; wherein one end of the first wiring segment extends to the fan-out area, and the other end extends to the first fan-out line and is electrically connected to it; The second wiring segment is located on a side of the first wiring segment facing away from the fan-out area and is electrically isolated from the first wiring segment. [10] Array substrate according to claim 9, wherein the second fan-out line comprises several first widened sections and several first extended sections arranged alternately along the second direction, the first widened sections and the first fan-out lines being offset along the second direction; and the bridge wire layer further comprises a first connecting segment, wherein one end of the first connecting segment is connected to the first fan-out line and the other end is electrically connected to the first widened section in the first wiring segment that is closest to the first fan-out line. [11] Array substrate according to claim 10, wherein the connecting line comprises several second widened sections and several second extended sections arranged alternately along the second direction, wherein the second widened section along the first direction is larger than the second extended section and the second widened section is electrically connected to the adapter block. [12] Array substrate according to claim 10 or 11, wherein the first fan-out line comprises: a second opening, wherein the second opening is located on the side of the first connection segment facing away from the first data line, which is electrically connected to the first fan-out line, and wherein the orthographic projection of the second opening on the substrate partially overlaps with the orthographic projection of a data line on the substrate; and a third opening, wherein the third opening is located on the side of the first data line that is electrically connected to the first fan-out line that is opposite the second fan-out line that is electrically connected to the first fan-out line, and wherein the orthographic projection of the third opening on the substrate partially overlaps with the orthographic projection of a connecting line on the substrate. [13] Array substrate according to any one of claims 9 to 12, wherein the bridge wire layer further comprises: multiple columns of matching patterns, each column comprising multiple matching patterns spaced along the second direction, the multiple matching patterns in the column being electrically connected to the multiple pixel circuits in a column, and the multiple matching patterns in the column being electrically connected to a data line; and a second connecting segment, wherein one end of the second connecting segment is electrically connected to the first fan-out line and the other end is electrically connected to a target matching pattern, wherein the target matching pattern is the matching pattern that is located on the side of the first fan-out line facing the fan-out area and is closest to the first fan-out line. [14] Array substrate according to claim 13, wherein the multiple matching patterns and the multiple adapter blocks are offset along the second direction and at least one of the adapter blocks is located between the first fan-out line and the target matching pattern. [15] Array substrate according to claim 13 or 14, wherein the multiple first data lines include at least one first sub-data line, wherein the orthographic projection of the first sub-data line on the substrate does not overlap with the orthographic projection of the adapter block on the substrate; and the orthographic projection of the second connection segment, which is connected to the first sub-data line on the substrate, lies within the orthographic projection of the first sub-data line on the substrate. [16] Array substrate according to claim 13 or 14, wherein the multiple first data lines include at least one second sub-data line, wherein the orthographic projection of the second sub-data line on the substrate partially overlaps with the orthographic projection of a column of adapter blocks on the substrate; the column of adapter blocks that is electrically connected to the second sub-data line includes a target adapter block, wherein this target adapter block is located on the side of the first fan-out line facing the fan-out area and is closest to it; the orthographic projection of the target adapter block on the substrate does not overlap with the orthographic projection of the second sub-data line on the substrate; and the second connection segment, which is electrically connected to the second sub-data line, is a target connection segment, wherein the orthographic projection of the target connection segment on the substrate lies within the orthographic projection of the second sub-data line on the substrate, and the target connection segment extends along the second direction and is spaced from the target adapter block; and / or the target connection segment is a zigzag line, the orthographic projection of the target connection segment on the substrate does not overlap at least partially with the orthographic projection of the second sub-data line on the substrate, and the target connection segment is spaced from the target adapter block. [17] Array substrate according to any one of claims 1 to 16, wherein two adjacent columns of pixel circuits are arranged symmetrically; the multiple data lines are divided into multiple groups, each group comprising two data lines, with a first distance provided between the two data lines of a group and a second distance provided between two adjacent groups of data lines, the first distance being smaller than the second distance; and Each connecting line lies between the two data lines of a group and the two data lines of the group are arranged symmetrically around the connecting line; each second fan-out line lies between the two data lines of a group and the two data lines of the group are arranged symmetrically around the second fan-out line. [18] Array substrate according to claim 17, wherein 1 to 10 connecting lines are provided between two adjacent second fan-out lines. [19] Array substrate according to claim 17 or 18, wherein a first, a second and a third connecting line are provided between two adjacent second fan-out lines; between the two adjacent second fan-out lines along the first direction and from one side edge of the display area to the other side edge, the second connecting line, the third connecting line and the first connecting line are arranged sequentially; or between the two adjacent second fan-out lines along the first direction and from one side edge of the display area to the other side edge, the second connecting line, the first connecting line and the third connecting line are arranged successively; or between the two adjacent second fan-out lines along the first direction and from one side edge of the display area to the other side edge, the second connecting line, the first connecting line and the third connecting line are arranged successively; or between the two adjacent second fan-out lines along the first direction and from one side edge of the display area to the other side edge, the first connecting line, the second connecting line and the third connecting line are arranged sequentially; or between the two adjacent second fan-out lines along the first direction and from one side edge of the display area to the other side edge, the first connecting line, the third connecting line and the second connecting line are arranged sequentially; or between the two adjacent second fan-out lines along the first direction and from one side edge of the display area to the other side edge, the third connecting line, the second connecting line and the first connecting line are arranged successively; or The third connecting line, the first connecting line and the second connecting line are arranged successively between the two adjacent second fan-out lines along the first direction and from one side edge of the display area to the other side edge. [20] Array substrate according to any one of claims 17 to 19, wherein the second wiring layer further comprises several first voltage signal lines spaced apart along the first direction, each of the first voltage signal lines running along the second direction, with two adjacent first voltage signal lines comprising a group of data lines; the bridge wire layer further comprises several first voltage signal transmission lines spaced apart along the second direction, each of the first voltage signal transmission lines running along the first direction and electrically connected to a row of pixel circuits; and Each of the first voltage signal lines is electrically connected to the several first voltage signal transmission lines. [21] Display field, comprising: an array substrate according to any one of claims 1 to 20; multiple light elements arranged on a side of the array substrate facing away from the substrate, each light element being electrically connected to a pixel circuit. [22] Display device, comprising: a display field according to claim 21, comprising an array substrate; a driver board that is electrically connected to a fan-out area of ​​the array substrate and transmits control signals to the array substrate.

Images