INITIALIZATION OF DATABASE PARTICIPANTS

Description

1. Field of the invention

[0001] The invention relates in general to the initialization of data bus participants and in particular to the programming of data bus participants of a ring bus using instruction lists. 2. State of the art

[0002] Data bus devices are most commonly found in automation systems. A data bus device serves to control or monitor a process within an automation system. This is accomplished by outputting control signals, e.g., to actuators, and / or by receiving measurement signals, e.g., from sensors within the automation system.

[0003] Automation systems are used primarily for controlling industrial plants, buildings, and means of transport. Controlling an automation system typically requires several sensors and actuators. These monitor and control the process performed by the system. The various sensors and actuators of an automation system are often also referred to as automation devices.

[0004] These automation devices can either be connected directly to the controller of the automation system, or they can first be connected to input and output modules, often also called I / O modules. These can then, in turn, be connected directly to the controller. The automation devices can either be integrated directly into the I / O modules or connected to them via cables or wirelessly.

[0005] The control of an automation system is typically achieved using one or more programmable logic controllers (PLCs). PLCs can be arranged hierarchically or decentrally within the system. PLCs come in different performance classes, allowing them to perform various control and regulation tasks depending on their processing and memory capacity. In its simplest form, a PLC has inputs, outputs, an operating system (firmware), and an interface through which a user program can be loaded. The user program defines how the outputs should be switched based on the inputs. The inputs and outputs can be connected to automation devices and / or I / O modules, and the logic defined in the user program allows the PLC to monitor and control the processes performed by the automation system.The process is monitored by sensors and controlled by actuators. The controller, also known as the central controller or central unit, takes over control of at least one automation device or I / O module connected to it.

[0006] However, directly connecting the automation devices to the at least one controller, or the I / O modules to the at least one controller, via parallel wiring—that is, running a separate line from each automation device or I / O module to the higher-level controller—is very complex. The cabling effort increases significantly with parallel wiring, especially as the level of automation in an automation system increases. This results in considerable effort during the planning, installation, commissioning, and maintenance phases.

[0007] Therefore, bus systems are predominantly used in modern automation technology to connect automation devices or I / O modules to the controller. The participants in a bus system are also called bus participants. Because data is exchanged on the bus system, the bus participants are also frequently referred to as data bus participants. To further simplify the connection of individual automation devices or I / O modules to the bus system, groups of automation devices or I / O modules are often first interconnected using a specialized local bus to form a local bus system. Subsequently, at least one participant in this local bus is connected to the bus system that is connected to the controller.

[0008] The local bus system may differ from the bus system used to establish the connection with the controller.

[0009] The device connected to the controller's bus system within a group of local bus participants is often referred to as the local bus master. Alternatively, it is also called the head station of the local bus system. This local bus master may contain additional logic, circuitry, or functionalities compared to other local bus participants, which are necessary for connecting to the controller's bus system. The local bus master itself may also contain a PLC. Furthermore, this device may have logic and circuitry for conversion between the two bus systems. The local bus master can therefore also be configured as a gateway or bus converter, ensuring the conversion of data in the format of one bus system to the format of the local bus system and vice versa. Usually, but not always, the local bus master is specialized in connecting the local bus to the higher-level bus.

[0010] The local buses used are usually tailored to the specific operational requirements of the automation devices or I / O modules, or take into account their specific hardware design. The groups of automation devices or I / O modules within the local bus system typically form a subgroup of the automation system, responsible for executing a specific task within the process being carried out by the automation system. The data exchanged on the buses for the process is also frequently referred to as local bus data or process data, because this data contains information for regulating or controlling the process being executed by the automation system. This data can include, among other things, measurement data, control data, status data, and / or other information. Depending on the bus protocol used, other data can be prepended to this information ( English header) or appended ( EnglishThis other data can contain information about the data itself, or information about internal communication on the local bus. A wide variety of different information is known to be included, which can be prepended to or appended to the data depending on the bus protocol used.

[0011] An example of a local bus is a ring bus, which is a specialized form of the local bus, as described, for example, in US 5,472,347A. In a ring bus, the data bus participants, such as automation devices or I / O modules, are each connected to their directly adjacent data bus participants, and data is forwarded sequentially from one data bus participant to the next. Thus, data is not sent to all data bus participants simultaneously, but rather sequentially, with each data bus participant receiving data from the preceding data bus participant and forwarding it to the following data bus participant. Between receiving the data and forwarding it, the data bus participant can process the received data. When the data reaches the last data bus participant in the sequence, the data is forwarded from the last data bus participant back to the first data bus participant in the sequence.The return flow can either pass through all data bus participants or bypass them using a bypass line. The ring bus therefore has a downward and an upward flow of data. Data in a ring bus is usually transmitted in the form of data packets that pass through all data bus participants.

[0012] In such a ring bus configuration, or indeed in any other local bus, programming the data bus participants is complex. For example, programming the data bus participants requires interrupting the transmission on the bus, or programming the data bus participant via an external interface, during which time the data bus participant cannot participate in communication on the local bus.

[0013] Further state of the art is disclosed in US 2007 / 081473 A1, WO 02 / 15517 A2 and US 2015 / 110126 A1.

[0014] Based on this, the object of the present invention is to provide an improved method and an improved data bus participant with which programming of the data bus participants is possible even during the operation of the local bus, so that the data bus participant can process process data immediately after programming during the operation of the local bus. 3. Summary of the invention

[0015] This problem is solved by a method and a data bus participant according to the independent claims. Advantageous embodiments are described in the dependent claims. The inventive method for operating a data bus participant of a local bus, in particular a ring bus, comprises the steps of receiving a first data packet via the local bus, wherein the first data packet contains an address of the data bus participant to which it is addressed and at least one instruction list with a set of instructions for processing process data. "Addressed" in this case means that the instruction list contained in the data packet is intended for a specific data bus participant in the local bus. The instructions in the instruction list can specify a wide variety of processing steps to be carried out on the process data.At least one instruction list contains, for example, instructions that define a set of rules for processing the process data. This rule set defines, for instance, which process data a data bus participant should select from a data stream circulating on the local bus, which data should be read, at which points the data bus participant should write process data, and / or which process data the data bus participant should manipulate in other ways. Accordingly, the instruction lists define the behavior of the data bus participant with respect to the process data to be processed. The data bus participant to which the instruction list is addressed can store the instruction list in memory and use it to process process data at a later time. The instruction list can be stored in such a way that it can be easily retrieved.Storage can encompass all methods of retaining the instruction list. The only requirement is that the data bus participant has access to the received instruction list, i.e., access to the memory. Accordingly, the instruction list can be stored within the data bus participant itself, for example, in its own memory or in a memory connected to it. The connection between the data bus participant and the memory can be wired or wireless. It is also conceivable that the memory is an add-on module that can be connected to the data bus participant. The memory can be configured in any way.

[0016] The first data packet can also be called a communication data packet and preferably does not contain any process data. Advantageously, a communication data packet contains data, in particular for programming and / or controlling and / or monitoring and / or identifying at least one data bus participant. Advantageously, the communication data packet has an address that is assigned to at least one data bus participant. Preferably, the data bus participant is configured to evaluate the address and read the communication data packet, so that the data bus participant can be programmed with the information contained in the communication data packet, for example, the instruction list, or rather, stores this information and is thus programmed.

[0017] Furthermore, the method according to the invention includes receiving a second data packet via the local bus, wherein the second data packet contains process data. This received process data can then be processed by executing instructions from the at least one instruction list received in the first data packet.

[0018] The second data packet, also known as the process data packet, contains process data that is sent and / or received by the data bus participants on the local bus. Advantageously, the process data packet does not contain an address for transmitting the process data to or from a data bus participant on the local bus. Within the process data packet, the process data is arranged, for example, in such a way that data bus participants can identify the process data belonging to their respective data bus participant based on the position of the process data within the packet, such as one or more bits within an assigned contiguous data block (1 byte). Advantageously, the process data packet has an identifier (IDE) that is assigned to the type of data packet, i.e., the process data packet, and is identifiable by the data bus participant. The process data can also be referred to as local bus data.

[0019] By using an initial data packet, which is sent to a data bus participant via local bus-compliant communication, the participant can be programmed without requiring external programming. The programming for the data bus participant therefore takes place during the operation of the local bus. Once the data bus participant has stored the instruction list contained in the initial data packet, its programming is complete, and it can process the process data contained in subsequent local bus-compliant communication.

[0020] In a preferred embodiment of the method according to the invention, the method further includes comparing the address received in the first data packet with the address of the data bus participant. Only if the addresses match does the data bus participant store the instruction list following in the first data packet, so that only the data bus participant to which the instruction list is addressed is programmed. For example, the address can also be a group address, meaning that several data bus participants will detect a match with the address, so that several data bus participants can be programmed. This is advantageous, for example, if several data bus participants perform the same task in the automation system and are therefore equipped with the same sensors and / or actuators, but occupy different positions in the automation process.

[0021] In a preferred embodiment of the method according to the invention, the first and second data packets are received in a cycle frame compliant with the local bus. This means that the programming and the process data to be processed with the programming can be sent in the same cycle frame. However, it is also possible for the first and second data packets to be received in different cycle frames. A cycle frame can be defined, for example, as a recurring (cyclic), preferably equidistant, time interval in which data can be transmitted on the local bus. The cycle frame has, for example, at least one start identifier (SOC) and a time range for data transmission. Advantageously, several start identifiers (SOCs) of successive cycle frames are equidistant from one another in time. The aforementioned time range is provided for the transmission of the data packets.The start identifier (SOC) and the data packets are transmitted via the local bus and pass through all data bus participants. The start identifier (SOC) can be transmitted separately, i.e., as an independent symbol, or, advantageously, contained within a start data packet (SOC packet).

[0022] Within the time frame of the cycle, no, one, or several data packets are transmitted. Advantageously, idle data is inserted into a cycle frame, particularly adjacent to at least one data packet. Advantageously, the transmission of the data packets and / or the idle data creates a continuous signal on the local bus. This signal allows the data bus participants to synchronize with it. Advantageously, the cycle frame also includes a trailer. The trailer has a variable length and follows the data transmission time frame, preferably until the next start identifier (SOC) of the next cycle frame. Advantageously, the trailer contains idle data.

[0023] Preferably, the cycle frame is generated by a local bus master. This local bus master can predefine the programming based on the process data to be processed. This has the advantage that there is no interruption of communication. Furthermore, the additional effort is reduced. (engl. The overhead for the local bus master is very low because it does not need to use extra communication for programming or have to elaborately adapt the local bus-compliant communication; instead, the local bus master can integrate the programming into the normal process data communication.

[0024] In a further preferred embodiment of the method according to the invention, the second data packet further comprises an instruction list index (ILI). This instruction list index is used to select an instruction list for processing the received process data. The instruction list index informs the data bus participant which stored instruction list is to be used. An instruction list index is thus assigned to an instruction list, or vice versa, so that the instruction list to be used can be identified with the help of the instruction list index. For this purpose, the instruction list index preferably has a value that is assigned to an instruction list; for example, the value indicates a specific instruction list or its memory location.The value itself can be the memory address where the instruction list is stored in the data bus participant, or where at least the first instruction of the instruction list is stored. Alternatively or additionally, the value can also point to a memory area in which the corresponding instruction list is stored. In the aforementioned cases, one can also speak of a direct mapping. The value of the instruction list index can also be used, for example, as input to a conversion table. (engl.(Lookup table, LUT). The value of the instruction list index is the input value of the conversion table. The output value of the conversion table can be the memory address of the first instruction in the associated instruction list or otherwise identify the instruction list. The instruction list index preferably has a value from a fixed range. For example, the instruction list index can be from the bit range between 0000 and 1111. However, it is clear to those skilled in the art that other value ranges can also be used. The conversion table can be implemented in software or hardware, for example, in the form of logic, and can specify a one-to-one conversion from an input value to an output value, where the output value indicates the instruction list to be used.The relationship between the instruction list index and the instruction list depends on the mapping table. When using a mapping table, this can also be described as an indirect mapping. However, with both direct and indirect mapping, the instruction list index allows the data bus participant to uniquely identify, i.e., locate, the instruction list to be used. The data bus participant then executes the instruction list found via the index to process the process data in the second data packet. In other words, the set of instructions from the selected instruction list is processed. If the instruction list index contains a reference to an instruction list that is not present at the data bus participant, the data bus participant can report an error.The data bus participant can also ignore the instruction list index and not process any instruction list for the process data.

[0025] In a further preferred embodiment of the method according to the invention, the first and second data packets comprise a number of symbols, each symbol having a number of bits, for example, 8 bits, i.e., 1 byte. However, it is known to those skilled in the art that the data packets can also be divided into other units comprising more or less than 8 bits. The data packets traverse the local bus in the form of these symbols, i.e., unit by unit, piece by piece, or part by part. Such a part of the data packets is hereinafter also referred to as a piece or unit. This means that the data bus participants only ever have a portion of the data packets available at any given time. A data bus participant receives the first and second data packets symbol by symbol.After processing a symbol, the data bus participant forwards the processed portion to the downstream data bus participant and simultaneously receives a new portion of the data packet from the upstream data bus participant. Processing a portion of a data packet can also involve the data bus participant skipping that portion. For example, all data bus participants not addressed to the first data packet can skip at least one instruction list contained within that packet, and only the data bus participant to which the first data packet is addressed can store the instruction list. To ensure deterministic processing time, each portion of the data packet remains with a data bus participant for the same amount of time, regardless of whether processing takes place or not.This is necessary to give the other data bus participants sufficient time to perform their processing on the portions of the data packets already present before a new portion of the data packets is received. The processing of the portions of the first data packet can consist either of skipping them (i.e., not processing them, provided they contain at least one instruction list) or storing them if the first data packet is addressed to the data bus participant receiving those portions. Processing the portions of the second data packet can consist of performing a bitwise operation on the received data. In this case, the processing can also be described as bit-granular.The bit operations that can be performed are based, for example, on a reduced set of instructions that the data bus participant can execute, such as "SKIP", "MOVE", "NEGATION", "INCREMENT", "AND", and "OR", or a combination thereof. Which bit operations are to be executed is stored in the data bus participant using instruction lists. An instruction list can be sent to the respective data bus participant in an initial data packet and represents the programming of the data bus participant. These instruction lists contain at least one instruction for each part of the second data packet or for each bit of the second data packet; that is, an operation to be performed with the corresponding bit. There can be a fixed number or a predetermined number of instructions for each symbol in the instruction list.Each data bus participant executes a certain number of instructions per symbol within the time available for processing. For example, if a data bus participant is not supposed to process a particular bit, the corresponding instruction list for that bit can be empty or contain a "SKIP" instruction. The instruction list can also specify the number of repetitions for a particular instruction. For instance, the instruction list might contain a "SKIP" instruction with the instruction to repeat it twice. In this case, the next two bits are skipped instead of being processed. Parameters can also be specified for the "MOVE," "NEGATION," "INCREMENT," "AND," and "OR" instructions.

[0026] In a further preferred embodiment of the method according to the invention, the address in the first data packet is a unique address of the data bus participant to which the first data packet is addressed. In this case, "directed" means that the instruction list contained in the first data packet is stored only by the data bus participant whose address matches the unique address in the first data packet. That is, programming is performed only on the data bus participant whose address matches the address in the first data packet. Accordingly, the first data packet can also be referred to as a directed or specific data packet because it is intended for only one data bus participant or a specific group of data bus participants, whereas the second data packet does not contain an address and can therefore be referred to as an undirected or indeterminate data packet.The second data packet is undefined because it carries the process data for all data bus participants on the local bus. It can also be said that the first data packet represents asynchronous communication, whereas the second data packet represents synchronous communication. The communication of the first data packet is asynchronous because it does not need to be resent in every cycle frame, but is only used once for programming a data bus participant. The communication of the second data packet is synchronous because it is repeated cyclically. The process data does not always have to have the same value, but it is clear to those skilled in the art that in automation, the same process steps are repeated again and again, which necessitates the presence of cyclically recurring process data.

[0027] The aforementioned problem is also solved by a data bus participant of a local bus, in particular a ring bus, wherein the data bus participant has means for receiving a first data packet via the local bus, the first data packet containing an address of the data bus participant to which it is addressed and at least one instruction list with a set of instructions for processing process data. The data bus participant according to the invention further has means for receiving a second data packet via the local bus, the second data packet containing process data. The means for receiving can be a receiver circuit or a transceiver circuit. The circuits are, for example, integrated in an application-specific integrated circuit. (engl. ASIC) or in a field-programmable (logic) gate arrangement (engl. FPGA) implemented.

[0028] The data bus participant according to the invention further comprises a means for executing instructions from at least one instruction list for processing the received process data. The execution means can be a microcontroller or a computing circuit, which can in particular be formed from gate elements of an integrated circuit. The computing circuit can be designed as digital logic, which is in particular implemented as at least part of a semiconductor chip. The circuits can be implemented in an ASIC or an FPGA.

[0029] In a preferred embodiment of the data bus participant according to the invention, it further comprises a means for sending the received second data packet to another data bus participant via the local bus. The data bus participant can send the second data packet symbolically to another data bus participant via the local bus. This other data bus participant can be a data bus participant that directly follows the sending data bus participant. The transmission of the data can be synchronized among all data bus participants, for example, according to a schedule specified by the local bus master, or it can be triggered by the receipt of further data packets.

[0030] The above-mentioned task is also solved by a method for operating a local bus master of a local bus, in particular a ring bus, wherein the method comprises generating at least one instruction list with a set of instructions for processing process data for a data bus participant, generating a first data packet, wherein the first data packet contains an address of the data bus participant to which the first data packet is addressed, and containing at least one instruction list, generating a second data packet, wherein the second data packet contains process data, and sending the first and second data packets to the data bus participant via the local bus.

[0031] In a preferred embodiment of the method according to the invention, the first and second data packets each comprise a number of symbols, each symbol comprising a number of bits, and the data packets are sent symbol by symbol to the data bus participant. The local bus master accordingly sends a first and second data packet at regular intervals, and these successively traverse all data bus participants in a downward direction, i.e., away from the local bus master. The last data bus participant on the local bus then sends the packets back to the local bus master one after the other in an upward direction, i.e., towards the local bus master. The returned packets either traverse all data bus participants again or are routed past them to the local bus master.

[0032] The aforementioned problem is also solved by a local bus master of a local bus, in particular a ring bus, with a data bus participant. The local bus master comprises means for generating at least one instruction list with a set of instructions for processing process data for the data bus participant, as well as means for generating a first data packet, wherein the first data packet includes an address of the data bus participant to which the first data packet is addressed and the at least one instruction list. Furthermore, the local bus master according to the invention comprises means for generating a second data packet, wherein the second data packet contains process data. The means for generating the data packet can be a processor, a microcontroller, or a computing circuit, which can in particular be formed from gate elements of an integrated circuit.The computing circuitry can be implemented as digital logic, which is typically implemented as at least part of a semiconductor chip. The circuitry can be implemented in an ASIC or an FPGA.

[0033] Furthermore, the local bus master according to the invention includes means for sending the first and second data packets to the data bus participant via the local bus. The two data packets can be sent within a single cycle frame that the sending means can generate. Alternatively, the sending means can send the two data packets within different cycle frames and generate the corresponding cycle frames. The sending means can be a transmitter circuit or a transceiver circuit. These circuits are implemented, for example, in an ASIC or FPGA. 4. Brief description of the drawings

[0034] The invention is explained in more detail below with reference to exemplary embodiments and the accompanying drawings. Further details, features, and advantages of the subject matter of the invention will become apparent from the described exemplary embodiments. The drawings show: Fig. 1 a schematic block diagram of an exemplary automation system with a programmable logic controller and an exemplary ring bus; Fig. 2 a schematic representation of a first data packet for programming a data bus participant; Fig. 3 a schematic representation of a second data packet for sending process data to data bus participants; Fig. 4 an exemplary timing diagram showing the traversal of the data in the Figs. 2 and 3 The data packets shown are transmitted by the exemplary data bus participants of the in Fig. 1 shown ring bus; and Fig. 5 a schematic representation of instruction lists for processing the in Fig. 2 shown process data of the second data package. 5. Description of preferred embodiments

[0035] Figure 1 Figure 1 shows a schematic block diagram of an automation system. It will be understood by those skilled in the art that the automation system shown is only an example and that all elements, modules, components, participants, and units belonging to the automation system may be configured differently but can nevertheless fulfill the basic functionalities described here.

[0036] The in Figure 1The automation system shown has a higher-level control unit 1, which can be implemented, for example, with a programmable logic controller (PLC). Such a PLC 1 is fundamentally used to control and regulate the process executed by the automation system. Nowadays, however, PLCs 1 in automation systems also perform more advanced functions, such as visualization, alarm generation, and recording of all process-related data, and as such, the PLC 1 acts as a human-machine interface. PLCs 1 are available in different performance classes, offering varying resources (computing capacity, storage capacity, number and type of inputs and outputs, and interfaces) that enable the PLC 1 to control and regulate the automation system's process. A PLC 1 typically has a modular design and consists of individual components, each fulfilling a different task.A PLC (Programmable Logic Controller) typically consists of a central processing unit (with one or more main processors and memory modules) and several modules with inputs and outputs. Such modular PLCs can be easily expanded by adding modules. The specific modules required depend on the complexity of the process and the overall design of the automation system. In modern automation systems, the PLC is usually no longer an independent system, but rather connected to the internet or intranet via interfaces (not shown here). This means the PLC is part of a network from which it can receive information, instructions, programming, and so on.For example, PLC 1 can receive information about materials supplied to the process via a connection to a computer located on the intranet or internet. This allows for optimal process control, for instance, by knowing the quantity or properties of these materials. It is also conceivable that PLC 1 can be controlled by a user via access from the intranet or internet. For example, a user can access PLC 1 using a computer, also called a master computer, and check, modify, or correct its user programming. Accordingly, access to PLC 1 is possible from one or more remote control centers or monitoring stations. The master computers may, if necessary, have visualization capabilities to display process sequences.

[0037] To control the automation system's processes, PLC 1 is connected to automation devices. To minimize wiring effort, bus systems are used for these connections. In the Figure 1 In the illustrated embodiment, the PLC 1 is connected to a local bus master 3 of a subordinate local bus system via a higher-level bus 2, which in this embodiment can be a fieldbus. However, not only a local bus master 3 of a local bus, as in this embodiment, can be connected to the higher-level bus 2, but also any other devices – not shown here – that are configured for communication with the PLC 1.

[0038] In the embodiment shown here, the higher-level bus 2 is connected to the local bus master 3. For this purpose, the local bus master 3 has a first interface 4 designed to connect to the higher-level bus 2. The interface 4 can, for example, have a socket, and the higher-level bus 2 can have a plug that can be received by the socket. The plug and socket can, for example, be modular plugs and sockets, meaning that each wire of the higher-level bus 2 is electrically or optically connected to a connection in the modular socket. However, those skilled in the art are also aware of other ways in which an interface 4 can be designed so that the local bus master 3 can be electrically or optically connected to the higher-level bus 2.Experts are familiar with screw, twist, click, or plug connections, which can be used to establish an electrical or optical connection. In most cases, a male connector is inserted into a female counterpart. This insertion usually not only establishes the electrical or optical connection but also ensures that the two parts are mechanically coupled and can only be separated by applying a certain force. However, it is also conceivable that the higher-level bus 2 is hardwired to interface 4.

[0039] In the embodiment shown here, the local bus master 3 has a second interface for connecting it to the local bus. Data bus participants 7a, 7b, ..., 7n are connected to or form the local bus. Advantageously, the local bus is configured such that a data packet sent by the local bus master 3 is transmitted through all data bus participants 7a, 7b, ..., 7n connected to the local bus and back to the local bus master 3. Each data bus participant 7a, 7b, ..., 7n receives only a portion of the data packet from the preceding data bus participant 7a, 7b, ..., 7n. After a period of time in which the data contained in this part can be processed by the data bus participant 7a, 7b, ..., 7n, the part is forwarded to the downstream data bus participant 7a, 7b, ..., 7n and at the same time a new part of the data packet is received by the upstream data bus participant 7a, 7b, ..., 7n.In this way, all parts of the data packet sequentially pass through all data bus participants 7a, 7b, ..., 7n. The local bus is advantageously configured in a ring-shaped structure. Such local buses can also be referred to as ring buses 6. Alternatively, the local bus can also be configured in a branch or star topology, or as a combination or hybrid of the aforementioned configurations. The sending and receiving of the data packets is accomplished via the second interface of the local bus master 3. In the embodiment shown here, the second interface is divided into a first part 5a and a second part 5b. The first part 5a of the second interface establishes the downward connection in the ring bus 6, and the second part 5b of the second interface establishes the upward connection in the ring bus 6.

[0040] The Ringbus 6, whose data transmission direction is indicated by arrows in the Figure 1The embodiment shown in the example shown here has several data bus participants 7a, 7b, ..., 7n. In this embodiment, each of these data bus participants 7a, 7b, ..., 7n has an interface 8 for receiving data from an upstream or preceding data bus participant 7a, 7b, ..., 7n. In the case of data bus participant 7a, it receives data via interface 8 from the upstream local bus master 3. Furthermore, in this embodiment, each of the data bus participants 7a, 7b, ..., 7n has an interface 9 for forwarding data to a downstream or subsequent data bus participant 7a, 7b, ..., 7n. In the case of data bus participant 7a, it sends data to the downstream data bus participant 7b via interface 9. Interfaces 8 and 9 serve to propagate data downwards along the ring bus 6, i.e., away from the local bus master 3.Furthermore, in this embodiment, data bus participants 7a, 7b, ..., 7n also have interfaces 10 and 11 for propagating data upwards along the ring bus 6, i.e., towards the local bus master 3. In the case of data bus participant 7a, interface 10 is designed to receive data from the downstream data bus participant 7b, and interface 11 is designed to forward data to the upstream data bus participant, here the local bus master 3. It can therefore also be said that interfaces 9 and 11 are transmitter interfaces, whereas interfaces 8 and 10 are receiver interfaces.

[0041] In the embodiment shown here, the connections between the interfaces and the PLC 1 or the data bus participants 7a, 7b, ..., 7n are implemented using cables or circuit boards for direct or indirect contact via electrical contacts. Alternatively, the individual connections can be made wirelessly, with the interfaces providing the necessary conversions to the radio standards used.

[0042] Even though the local bus master 3 and the individual data bus participants 7a, 7b, ..., 7n are shown spaced apart from each other in the embodiment shown here, i.e., the local bus master 3 is arranged decentrally from the data bus participants 7a, 7b, ..., 7n, it is known to those skilled in the art that the data bus participants 7a, 7b, ..., 7n and the local bus master 3 – which also represents a data bus participant of the ring bus 6 – can also be directly connected to each other. For example, contacts of one data bus participant can engage corresponding receptacles or receiving contacts of a directly adjacent data bus participant to establish an electrical connection between the data bus participants so that data can be sent in the downward and upward directions. For example, the data bus participants 7a, 7b, ..., 7n can have receptacles on the side facing away from the master and contacts on the side facing the master. If the data bus participants 7a, 7b, ...If the data bus participants 7a, 7b, ..., 7n are arranged in a corresponding sequence, the contacts of each data bus participant 7a, 7b, ..., 7n engage with the corresponding contacts of the other data bus participant 7a, 7b, ..., 7n, thus establishing an electrical connection. The local bus master 3 then has corresponding contacts on its side that engage with the corresponding contacts of the first data bus participant 7a, thereby establishing an electrical connection between interfaces 5a and 8 or interfaces 5b and 11. However, other methods are also known to those skilled in the art, such as push contacts or knife-and-fork contacts, for establishing an electrical or optical connection between two directly adjacent data bus participants 7a, 7b, ..., 7n.

[0043] If the data bus participants 7a, 7b, ..., 7n and the local bus master 3 are to be directly connected, they can also have mechanical mounts or fasteners with which the individual data bus participants 7a, 7b, ..., 7n and the local bus master 3 can be connected to each other. For example, a data bus participant 7a, 7b, ..., 7n can have a projection on one side and an undercut on the other. If the data bus participants 7a, 7b, ..., 7n are then connected in series, one projection engages with an undercut of the other data bus participant 7a, 7b, ..., 7n, thus creating a mechanical connection. For easy connection of the data bus participants 7a, 7b, ..., 7n, they can also be arranged on a common mount, for example, a DIN rail. The data bus participants 7a, 7b, ..., 7n have corresponding mounting means. Alternatively or additionally, the data bus participants 7a, 7b, ..., 7n can also have, for example, detachably connectable mounting means with which the data bus participants 7a, 7b, ..., 7n can be attached either to the DIN rail or to another mounting surface. The detachably connectable mounting means can be interchangeable, and a corresponding mounting means for the desired mounting surface can be connected to the data bus participants 7a, 7b, ..., 7n so that they can be attached to the desired mounting surface.

[0044] Furthermore, the data bus participants 7a, 7b, ..., 7n in the Figure 1The illustrated embodiment also includes a processing unit 12. This processing unit 12 can be an arithmetic logic unit or another type of arithmetic unit with which data can be processed. The processing unit 12 is preferably an integral part of the data bus participant 7a, 7b, ..., 7n in order to ensure particularly fast and time-synchronized data processing.

[0045] The processing unit 12 can also be described as the complete circuit of the data bus participant. This means that the processing unit 12 receives data via inputs 8 and 10 and outputs data on outputs 9 and 11. Furthermore, the processing unit 12 can receive and output data from inputs and outputs 13 and 14. Additionally, the processing unit 12 has access to a memory – not shown here – of the data bus participant 7a, 7b, ..., 7n, in which, for example, data, process data, or instruction lists are stored.

[0046] The processing unit 12 can be configured to process received data and output data. Data to be processed can be received either from an upstream data bus participant or from inputs 13 of data bus participant 7a, 7b, ..., 7n. The inputs 13 of data bus participant 7a, 7b, ..., 7n can be connected to sensors 15 that send, for example, measurement data, status data, etc. Processed data can be output either to a downstream data bus participant or to outputs 14 of data bus participant 7a, 7b, ..., 7n. The outputs 14 of data bus participant 7a, 7b, ..., 7n can be connected to actuators 16 that, for example, perform a specific action using the data addressed to them. If data processing is also required in the upstream direction, data can also be received from a downstream data bus participant 7a, 7b, ..., 7n are received and processed data is sent to an upstream data bus participant 7a, 7b, ..., 7n.

[0047] For the sake of simplicity, in the embodiment shown here, the data bus participants 7a, 7b, ..., 7n are shown with only one input 13 and one output 14, and only data bus participant 7b is connected to sensor 15 and actuator 16. However, it is known to those skilled in the art that the data bus participants 7a, 7b, ..., 7n can have a plurality of inputs and outputs 13 and 14, and can be connected to a plurality of different sensors 15 and actuators 16. The defining characteristic of the sensors 15 is that they receive data or signals and send them to the data bus participants 7a, 7b, ..., 7n, whereas actuators 16 receive data or signals from the data bus participants 7a, 7b, ..., 7n and perform an action based on this data or these signals.

[0048] Alternatively, interfaces 8, 9, 10, and 11 can be integrated into a module unit, and data bus participants 7a, 7b, and 7n can be plugged into this module unit. These module units can also be referred to as the basic elements of the ring bus 6. The ring bus infrastructure is built using these module units, and the data bus participants 7a, 7b, ..., 7n are interchangeable, allowing the ring bus 6 to be configured with any number of data bus participants 7a, 7b, ..., 7n. The module units also ensure that even if a data bus participant 7a, 7b, ..., 7n is removed, communication between the remaining data bus participants 7a, 7b, ..., 7n is not interrupted, as communication continues via the remaining module units.

[0049] The data bus participants 7a, 7b, ..., 7n shown in this embodiment are also frequently referred to as I / O modules due to their inputs and outputs 13, 14, which can be connected to sensors 15 and actuators 16, respectively. Although the data bus participants 7a, 7b, ..., 7n are shown as spatially separated from the sensors 15 and actuators 16 in this embodiment, the sensors 15 and actuators 16 can also be integrated into the I / O module.

[0050] The ring bus 6 shown in the embodiment presented here is based on a cyclically repeating sequence of data packets or telegrams, often called cycle frame communication. The local bus master 3, for example, generates data packets that have a header, a process data part or information data part, and a checksum part. The process data part or information data part of the data packet can contain user data, control data, and process data – as shown in the Figures 2 and 3As shown, the data packet(s) are sent downwards by the local bus master 3 to the first data bus participant 7a of the ring bus 6. This participant receives the first part of the data packet via interface 8. Such a part of the data packet is subsequently referred to as a piece or unit. Data bus participant 7a then processes the part and forwards it to the next data bus participant 7b via interface 9. Simultaneously, the first data bus participant 7a receives a second part of the data packet, and so on. The size of the data packet parts, i.e., the segmentation, depends on the storage capacity of the data bus participants 7a, 7b, ..., 7n. For example, a fixed number of bits, such as 8 bits of the data packet, can be available for processing simultaneously at data bus participants 7a, 7b, ..., 7n.

[0051] The data packets traverse the data bus participants 7a, 7b, ..., 7n accordingly, unit by unit, in chunks, or parts by part, for example, in segments or symbols of 8 bits. The data packets processed by the last data bus participant, in this embodiment data bus participant 7n, then traverse the ring bus 6 upwards, so that the parts originating from the last data bus participant 7n are sent back upwards towards the local bus master 3 through all data bus participants 7a, 7b, ..., 7n. For this purpose, the last data bus participant 7n either has a switchable bridge that connects interface 9 with interface 10, or a switchable bridge – not shown here – is connected to the last data bus participant 7n, which performs the function of routing the parts of the cycle frame from interface 9 to interface 10.Alternatively, interface 10 of data bus participant 7n can also be connected directly to interface 5b of local bus master 3 using a bypass line - not shown here.

[0052] In the upward direction, the data packets can be looped back to the local bus master 3 by the individual data bus participants 7a, 7b, ..., 7n, as in the embodiment shown here, without further processing. However, it is also conceivable that the data packets are processed again in the upward direction, so that the data packets are processed twice: once in the downward direction to the last data bus participant 7n and once in the upward direction to the local bus master 3. For example, processing in the upward direction could involve signal refresh and / or phase shifting.

[0053] When processing data packets downwards, i.e., away from local bus master 3, or upwards, i.e., towards local bus master 3, processing is accomplished using instruction lists. These instruction lists contain sets of instructions that can be executed by the processing unit 12 of the data bus participants 7a, 7b, ..., 7n. The instruction lists themselves can be sent to the individual data bus participants 7a, 7b, ..., 7n by local bus master 3 during an initialization phase, or, advantageously, sent to the data bus participants 7a, 7b, ..., 7n during ongoing communication, so that programming of the data bus participants 7a, 7b, ..., 7n takes place without interrupting communication.

[0054] Figure 2Figure 1 shows a schematic representation of a first data packet 17 for programming a data bus participant 7a, 7b, ..., 7n without interrupting the ongoing communication. The first data packet 17 can be embedded in a sequence of data packets of the ongoing cyclic communication and used to program a data bus participant 7a, 7b, ..., 7n. The programming of the data bus participant 7a, 7b, ..., 7n takes place using instruction list information, which is sent to the data bus participant 7a, 7b, ..., 7n to be programmed in the first data packet 17.

[0055] The first data packet 17 consists of a general header, an information section, and a checksum section. The header contains a field 18, which contains a unique bit pattern MWR, also known as a codeword or identifier. Data bus participants 7a, 7b, ..., 7n know that when the bit pattern MWR occurs, data is made available to them. This data can be instruction lists for programming data bus participants 7a, 7b, ..., 7n. The header of the first data packet 17 can also contain further information necessary for control or error detection – not shown here.

[0056] The information section of the first data packet 17 contains a field 19 in which the address of the data bus participant 7a, 7b, ..., 7n to be addressed is stored. Only the data bus participant 7a, 7b, ..., 7n whose address matches the address stored in field 19 reads the instruction list data 21 of the information section of the first data packet 17. The information section may also contain a further field 20, which can be used by the corresponding data bus participant 7a, 7b, ..., 7n whose address is stored in field 19 for error detection, error propagation, or this field 20 can contain instructions on where the instruction list data 21 should be stored. The instruction list data 21 can contain at least one instruction list or several instruction lists. After saving the instruction lists in the respective data bus participants 7a, 7b, ..., 7n can also be said to have completed the programming of the data bus participant 7a, 7b, ..., 7n. The instruction lists contain sets of instructions that define the processing to be carried out by the data bus participants 7a, 7b, ..., 7n. Furthermore, the first data packet 17 can also contain a checksum component with which a cyclic redundancy check can be performed.

[0057] After a data bus participant 7a, 7b, ..., 7n has been programmed using the first data packet 17, i.e., as soon as the instruction list has been stored in the data bus participant 7a, 7b, ..., 7n, this data bus participant 7a, 7b, ..., 7n is ready to process process data. This process data can already be received in the same cycle frame that accomplished the programming of the data bus participant 7a, 7b, ..., 7n, namely in a second data packet that follows the first data packet in the cycle frame. Such a second data packet is in Figure 3 shown. However, the second data packet 22 can also be received in a different cycle frame.

[0058] Figure 3Figure 1 shows a schematic representation of a second data packet 22 for sending process data to the data bus participants 7a, 7b, ..., 7n of the ring bus 6. The second data packet 22 can be embedded in a cycle frame of the ongoing communication, e.g. as part of the process data portion.

[0059] The second data packet 22 consists of a general header, an information section, and a checksum section. The header contains a field 23, which holds a unique bit pattern IDE, also known as a codeword or identifier. Data bus participants 7a, 7b, ..., 7n know that when the bit pattern IDE occurs, a process data packet is transmitted. The header of the second data packet 22 can also contain other information that can be used for control and / or troubleshooting. The information section of the second data packet 22 can begin with an instruction list index field, ILI, 24, which specifies which instruction list the data bus participants 7a, 7b, ..., 7n should use. For example, in normal operation of the ring bus 6, it may be intended that all data bus participants 7a, 7b, ..., 7n use their first instruction list, whereas in case of an error, the second instruction list should be used. It is also conceivable that a first instruction list comprises instructions for process data in a first process data package within a cycle frame, and a second instruction list can comprise a second set of instructions for process data in a second process data package within a cycle frame. The first arrangement can differ from the second arrangement. For example, when changing tools on an actuator connected to a data bus participant 7a, 7b, ..., 7n, different processing may be necessary because, in this case, other process data specific to the new tool, i.e., bits, are also transmitted in a data package within the cycle frame.The first instruction list can be used, for example, before the tool change, whereas the second instruction list is used after the tool change. The instruction list index 24 can directly point to the memory location of the instruction list stored in the data bus participant 7a, 7b, ..., 7n, or the instruction list index can have a value that allows the data bus participant 7a, 7b, ..., 7n to locate the corresponding instruction list, for example, via a conversion table, so that, depending on the instruction list index 24, either a first, a second, or another instruction list indicated by the instruction list index 24 can be used.

[0060] The information portion of the second data packet 22 further contains the actual process data 25a, 25b, 25c, ... . The process data 25a, 25b, 25c, ... are used by the data bus participants 7a, 7b, ..., 7n to perform control, regulation, or evaluation. For example, the process data 25a, 25b, 25c, ... can be sent to actuators to trigger a positioning movement. The process data 25a, 25b, 25c, ... can therefore represent control signals or be converted into corresponding control signals by the data bus participants 7a, 7b, ..., 7n. The process data 25a, 25b, 25c, ... can, for example, also represent measured values ​​acquired by sensors connected to the data bus participants 7a, 7b, ..., 7n and can be used as limit or setpoint values ​​to control actuators accordingly. That is, the data bus participants 7a, 7b, ..., 7n set the process data 25a, 25b, 25c, ...accordingly into control signals and / or measurement signals or vice versa.

[0061] Furthermore, the second data packet 22 contains a counter value 26, which is incremented or decremented by each data bus participant 7a, 7b, ..., 7n through which the second data packet 22 passes. This allows the second data packet to determine, upon its return to the local bus master 3, or rather, upon its return to the local bus master 3, whether all data bus participants 7a, 7b, ..., 7n have processed the cycle frame. This inherently also reveals whether a data bus participant 7a, 7b, ..., 7n has encountered an error and has not performed any processing. Additionally, the second data packet 22 can also contain a checksum component, which can be used to perform a cyclic redundancy check.

[0062] Figure 4Figure 1 shows an exemplary timing diagram of the forwarding of the first and second data packets 17, 22 by corresponding data bus participants 7a, 7b, ..., 7n of a ring bus 6. In the embodiment shown here, the second data bus participant 7b is programmed using the first data packet 17.

[0063] At time τ = 1, only data bus participant 7a has received the bit pattern MWR of the first data packet 17 from the local bus master 3 in a first symbol. In this case, data bus participant 7a knows that the subsequent symbols of the first data packet 17 contain instruction list data 21. However, at this point, data bus participant 7a does not know whether this instruction list data 21 is intended for itself or for another data bus participant 7b, ..., 7n in the ring bus 6. Upon receiving the symbol with the bit pattern MWR, data bus participant 7a can be put into receive mode. This means that data bus participant 7a expects instruction list data 21 that can be stored in an accessible memory. To ensure deterministic behavior of the ring bus 6, the symbol remains with data bus participant 7a for a certain period of time before it forwards it to the downstream data bus participant, in this case, data bus participant 7b.

[0064] At time τ = 2, data bus participant 7a has forwarded the first symbol to the second data bus participant 7b and received another symbol from the local bus master 3. At this time τ = 2, the second data bus participant 7b is also switched to receive mode, namely by receiving the symbol with the bit pattern MWR. Upon forwarding the symbol carrying the MWR bit pattern, all data bus participants 7a, 7b, ..., 7n are switched to receive mode.

[0065] At time τ = 3, the first data bus participant 7a receives a symbol of the first data packet 17 from the local bus master 3. This symbol contains a unique address of the data bus participant 7a, 7b, ... 7n to which the instruction list data 21 are directed. In the embodiment shown here, this symbol contains the information that the instruction list data 21 are intended for the second data bus participant 7b. That is, if the first data bus participant 7a compares its unique address with the unique address in the received symbol, it will find that its address and the address specified in the symbol do not match. In this case, the data bus participant 7a can exit its receive mode because it is known that the following instruction list data 21 are not intended for this data bus participant 7a.For the first data bus participant 7a, it is not relevant for whom the instruction list data 21 are intended, but only that they are not intended for him, as can be seen from the comparison.

[0066] In the embodiment shown here, at time τ = 4, the first data bus participant 7a forwarded the symbol with the address to the second data bus participant 7b. The latter compared the unique address indicated in the symbol with its own unique address and found a match. This means that the following instruction list data 21 is intended for data bus participant 7b. As soon as data bus participant 7b receives the instruction list data 21 in the following symbols, it is stored in an accessible memory. This means that the second data bus participant 7b is programmed.

[0067] The other data bus participants 7n through which the first data packet 17 passes symbolically are indeed put into receive mode by the symbol with the MWR bit pattern, but a comparison with the following symbol carrying the address shows that the instruction list data 21 are not intended for these data bus participants 7n, so that they can leave receive mode again.

[0068] In the embodiment shown here, the first data packet 17 is followed by the second data packet 22. This data packet 22 also traverses the ring bus 6, i.e., the data bus participants 7a, 7b, ..., 7n symbolically.

[0069] At an assumed time τ = n, the first data bus participant 7a receives a symbol with the bit pattern IDE, which puts data bus participant 7a into a processing mode because this bit pattern indicates that the following symbols carry process data 25a, 25b, 25c, ... The received symbol with the bit pattern IDE is then passed on to data bus participants 7b, ..., 7n to put them into processing mode. The symbol with the IDE bit pattern is followed by a symbol with an instruction list index, ILI. The instruction list index tells data bus participant 7a which stored instruction list it should use to process the following process data 25a, 25b, 25c, ... This instruction list index is also passed on to all data bus participants 7b, ..., 7n.For the second data bus participant 7b, this instruction list index can, for example, point to the instruction list that was just saved and received via the instruction list data 21 of the first data packet 17. It is therefore possible to program data bus participant 7b within the same cycle frame and then immediately use this programming to process process data 25a, 25b, 25c, ...

[0070] Even if in the Figures 2 to 4 In the discussed embodiment of first and second data packets 17, 22, which are sent in the same cycle frame, it is clear to the person skilled in the art that the first and second data packets 17, 22 can also be sent in different cycle frames, and that a cycle frame can also contain only one of the data packets 17, 22 shown.

[0071] Processing of process data 25a, 25b, 25c, ... using the instruction list index and the stored instruction lists is in Figure 5 shown.

[0072] Figure 5Figure 1 shows an exemplary processing of process data 25a, 25b, 25c, ... using instruction lists 27a, 27b, 27n. In the embodiment shown here, the instruction lists 27a, 27b, 27n are represented as tables. Instruction list 27a is stored in data bus participant 7a, instruction list 27b in data bus participant 7b, and instruction list 27n in data bus participant 7n. In this embodiment, each row of the tables contains two instructions that can be executed with the symbol of the data packet currently attached to data bus participant 7a, 7b, ..., 7n. However, those skilled in the art are aware that even though only two instructions for two work cycles are shown here as an example, a different number of instructions per symbol can also be executed. Furthermore, it is clear to the person skilled in the art that the instruction lists 27a, 27b, 27n also apply to each bit in the process data symbols 25a, 25b, 25c, ...Each bit may have its own instruction. For the sake of simplicity and clarity, we have omitted specifying instructions for each bit here.

[0073] As soon as the first data bus participant 7a receives the symbol with the instruction list index 24, it searches for the appropriate instruction list according to the instruction list index 24. In the embodiment shown here, the data bus participant 7a has stored two instruction lists, namely instruction list 27a' and 27a". In this embodiment, the instruction list index 24 refers to instruction list 27a', for example, to the memory location of the first instruction in the corresponding instruction list 27a'. Upon receiving the next symbol, which carries the process data 25a, the first instructions in instruction list 27a' are executed. The first line of instruction list 27a' of data bus participant 7a is empty, which is indicated by "---". This means that data bus participant 7a does not perform any processing with the first received symbol because no instruction is present.Instead of empty instructions, the instruction list 27a' can also contain "SKIP" instructions at this point. The data bus participant 7a also has no instructions in its instruction list 27a' for the next symbol, which carries the process data 25b. This means that this process data 25b is also not processed by the data bus participant 7a, but remains with it only for a certain time, for example, two cycles, to ensure deterministic behavior of the ring bus 6, so that each data bus participant 7a, 7b, ..., 7n has the same amount of time available for each symbol currently present. Only for the third symbol reaching the data bus participant 7a does it contain instructions, namely Read "R". (engl. Read) the process data 25c and write "W" (engl. Write) the process data 25c to output 14, which can be connected to an actuator 16, for example, to trigger an actuating movement there.

[0074] The data bus participant 7b in the embodiment shown here also has two instruction lists stored, namely instruction list 27b' and 27b". At least one instruction list 27b', 27b" can be one that was previously communicated to the data bus participant 7b via the instruction list data 21 of the first data packet 17. That is, it can be one with which the data bus participant 7b was programmed directly before receiving the process data 25a, 25b, 25c, ... In the embodiment shown here, the first line of instruction list 27b' contains the instruction "Read "R", specifically the process data 25a from the first symbol reaching the data bus participant 7b after the symbol bearing the instruction list index 24. The second instruction is to write "W", specifically the process data 25a just read, to memory at memory position oxoo.For the second symbol reaching data bus participant 7b, the instruction list specifies processing steps that are not directly related to the process data 25b carried by this symbol, but rather utilize the time available to data bus participant 7b before it must forward the symbol. In the embodiment shown here, the instruction list 27b' contains the instructions to read input 13 of data bus participant 7b, which is marked with "R", and to read the previously stored process data 25a from memory. Reading the input could, for example, consist of reading a sensor value from a sensor 15 connected to input 13. For the third symbol reaching data bus participant 7b, instruction list 27b' instructs the user to create a bitwise "AND" combination of the value read from input 13 and the process data 25a and to write this combination into the symbol, i.e.The process data 25c can be overwritten. This is because the process data 25c has already been read by the first data bus participant 7a and is no longer needed by any further data bus participants 7b, ..., 7n. In this way, the calculated value can be forwarded to the local bus master 3 or the controller 1. It is understood by those skilled in the art that other calculations or bit operations can also be performed here, and the bit operations given are for illustrative purposes only and are not to be understood as limiting.

[0075] Data bus participant 7n can also have two instruction lists 27n' and 27n"", with the instruction list index 24 indicating which instruction list 27n' or 27n' is to be used. In the embodiment shown here, the instruction list index 24 instructs all data bus participants 7a, 7b, ..., 7n to use their first instruction list; that is, data bus participant 7n also uses its first instruction list, namely instruction list 27n'. In this embodiment, instruction list 27n' contains only one instruction for the second symbol reaching this data bus participant 7n after instruction list index 24, and this instruction is: Read "R" process data 25b.

[0076] Those skilled in the art are aware that the examples of instruction lists shown here are not to be understood as restrictive and that any type of instruction list and any combination of instructions may occur in the implementation of the invention without departing from the inventive idea.

[0077] The methods described herein can also be implemented as a computer-readable medium containing code that causes a computer to execute at least one of the described methods. The computer-readable medium can be implemented in any way and provided on a storage medium such as a DVD, CD, hard drive, or other storage media. Reference symbol list

[0078] 1 Programmable Logic Controller (PLC) 2 Higher-level bus 3 Local bus master 4 First interface 5a, b Second interface 6 Ring bus 7a, b, n Data bus participants 8 First down data interface 9 Second down data interface 10 First up data interface 11 Second up data interface 12 Processing unit 13, 14 Inputs / outputs 15 Sensor 16 Actuator 17 First data packet 18 MWR code word 19 Address 20 Additional field 21 Instruction list data 22 Second data packet 23 IDE code word 24 Instruction list index 25a, b, c Process data 26 Counter value 27a, b, c Instruction lists

Claims

1. A method for operating a data bus subscriber (7a, 7b, ..., 7n) of a local bus (6), the method comprising: receiving a first data packet (17) via the local bus (6), wherein the first data packet (17) comprises an address (19) of the data bus subscriber (7a, 7b, ..., 7n) to which it is directed and at least one instruction list (27a, 27b, 27n) with a set of instructions for processing process data (25a, 25b, 25c); receiving a symbol of a second data packet (22) via the local bus (6), the second data packet (22) having process data (25a, 25b, 25c), the second data packet (22) comprising a number of symbols; executing instructions of the at least one instruction list (27a, 27b, 27n) for processing the received process data (25a, 25b, 25c) symbol-by-symbol; the method characterized by: forwarding the processed symbol of the second data packet (22) to a further data bus subscriber (7a, 7b, ..., 7n) via the local bus (6) and simultaneously receiving a further symbol of the second data packet (22), wherein the forwarding is delayed so long that each symbol always remains for the same duration at the data bus subscriber (7a, 7b, ..., 7n).

2. The method according to claim 1, wherein the first and second data packets (17, 22) are payload data of a cycle frame or two cycle frames.

3. The method according to one of the preceding claims, wherein the first data packet (17) comprises a number of symbols.

4. The method according to one of the preceding claims, wherein each symbol is processed with a fixed number of instructions of the instruction list (27a, 27b, 27n).

5. The method according to claim 4, wherein the symbol-by-symbol processing of the received process data (25a, 25b, 25c) comprises bit-granular processing of the received process data (25a, 25b, 25c).

6. The method according to claim 5, wherein the bit-granular processing comprises: performing a bit operation on at least one bit of the received symbol to obtain at least one processed process datum.

7. The method according to one of the preceding claims, wherein the address is a biunique address used for addressed communication with the data bus subscriber (7a, 7b, ..., 7n).

8. A data bus subscriber (7a, 7b, ..., 7n) of a local bus (6), the data bus subscriber (7a, 7b, ..., 7n) comprising: means for receiving a first data packet (17) via the local bus (6), wherein the first data packet (17) comprises an address (19) of the data bus subscriber (7a, 7b, ..., 7n) to which it is directed, and at least one instruction list (27a, 27b, 27n) with a set of instructions for processing process data (25a, 25b, 25c); means for receiving a symbol of a second data packet (22) via the local bus (6), wherein the second data packet (22) comprises process data (25a, 25b, 25c), the second data packet (22) comprising a number of symbols; means for executing instructions of the at least one instruction list (27a, 27b, 27n) for processing the received process data (25a, 25b, 25c); the data bus subscriber characterized by: means for forwarding the processed symbol of the second data packet (22) to a further data bus subscriber (7a, 7b, ..., 7n) via the local bus (6) and simultaneously receiving a further symbol of the second data packet (22) with the means for receiving, wherein the forwarding is delayed so long that each symbol always remains for the same duration at the data bus subscriber (7a, 7b, ..., 7n).