ELECTRONIC SYSTEM OF A MOTOR VEHICLE WITH AT LEAST TWO CONTROL UNITS, EACH HAVING ITS OWN CLOCK GENERATOR, AND METHOD FOR CONTROLLING SUCH A SYSTEM

Description

[0001] The invention relates to an electronic system for a motor vehicle with at least two control units that communicate with each other, each designed to send and receive signal information and each having its own processor with its own clock generator for clocking the respective control unit. The invention further relates to a method for controlling such a system. In particular, the invention relates to an electronic system with three or more control units, each having its own processors that, due to their design, are not clocked at exactly the same rate. This is particularly the case with processors with clock generators in the form of quartz crystals. This leads to the clock generators contained in the individual processors running slightly asynchronously, which in turn means that the calculation results of the processors are not available exactly simultaneously, but rather with a time delay depending on the asynchronicity.

[0002] The invention particularly relates to electronic systems in the form of steer-by-wire steering systems, especially those having a force feedback actuator (FFA) connected directly or indirectly, in particular via a transmission, to a control element. A control element within the meaning of the invention is understood in particular to be a steering wheel or other steering instrument, in particular a steering instrument of a vehicle.

[0003] Steer-by-wire steering systems do not require a direct mechanical connection between a steering wheel or other steering instrument and the steerable wheels. Therefore, no intermediate steering shaft is required. The steering feel, such as haptic feedback on the steering wheel in response to the wheels touching a curb, is provided by the aforementioned force feedback actuator. To control the force feedback actuator, signals from wheel actuators (RWA) are transmitted to the force feedback actuator, particularly via a so-called BUS system.

[0004] Steer-by-wire steering systems, particularly those designed for dual-track vehicles, typically feature at least two wheel actuators (RWA). This is due to the high safety requirements placed on such steering systems - and other electronic systems in motor vehicles - which require control units for particularly safety-relevant elements, such as a wheel actuator, to be designed redundantly. Typically, two control units are provided for the two wheel actuators, which are interconnected with the wheel actuators in such a way that each control unit can control both wheel actuators. This ensures that, in the event of one control unit failing, the other control unit continues to reliably control the vehicle.

[0005] The force feedback actuator and the at least two wheel actuators of such steer-by-wire steering systems are typically each functionally connected to a processor, in particular a microprocessor, so that the described steering systems involve three processors or microprocessors with independent clock generators. This results in a steering system in which two wheel actuators also contribute to the generation of a steering feel by means of the force feedback actuator, so that a total of three processors—in particular microprocessors—are involved in generating the steering feel.

[0006] The processors of the steering systems or electronic systems described above are usually functionally connected to at least one further element that can be controlled by the processors to carry out specific processes. Such a further element can be, for example, an electric motor, particularly if the electronic system is a steer-by-wire steering system. In particular, reference is made to a connection to a 6-phase electric motor, which is controlled via the three processors using pulse width modulation, with three phases being assigned to each processor. The asynchronicity explained above leads to instabilities, inaccuracies, and insufficient efficiency in the delivered motor torque. This leads to a suboptimal steering feel and / or suboptimal steering positioning accuracy.

[0007] DE 100 02 522 C1 discloses a method for providing consistent input values ​​and a multi-computer system, which are intended to be used in particular in conjunction with motor vehicles. This document teaches how to operate processors approximately synchronously at the same clock frequency in conjunction with safety-relevant multi-processor systems in motor vehicles, such as brake-by-wire or steer-by-wire. Reference is made to synchronization of the computer units using the TTP bus protocol, with which deviation values ​​of less than 100 µs can be achieved. In response to the problem described at the beginning that processors - particularly processors clocked with the aid of quartz crystals - are not clocked exactly synchronously, it is taught how to prevent overwriting of a stored value in order to avoid the effects of slightly differing time bases.In other words, according to this document, the memory is temporarily "frozen." It is described as advantageous that no complex synchronization mechanisms are required at the computer level. The disadvantage of this method and multi-computer system is that asynchronous processor clocking is simply ignored, which can lead to qualitatively inferior results that deviate from reality, especially when several events occur in close succession in connection with steering systems.

[0008] DE 10 2007 051 173 discloses a method and a device for operating a circuit arrangement with a clock signal generator and a reference clock signal generator. According to these methods, the circuit arrangement is clocked by means of the clock signal generator and is designed to either increment or decrement counters depending on a predetermined sensor signal. Particular reference is made to oscillators or quartz crystals used as clock signal generators. The document teaches, among other things, monitoring the frequency of the clock signal generator and, if the ratio lies outside a predetermined ratio range, recognizing and signaling counter readings as invalid. The method and device do not lead to a qualitative improvement in the results, but merely to the elimination of obviously unusable results.

[0009] WO 2005 / 114419 A2 discloses a method for fault-tolerant data processing, which particularly also applies to systems with three interconnected processors. Reference is made not only to steer-by-wire and brake-by-wire systems, but also to problems resulting from asynchronous clocking of the processors in such systems. According to this method, it is proposed to regularly compare and synchronize the processor times. A disadvantage is that the synchronization is always performed in the same way according to a predefined scheme.

[0010] DE 10 2019 211 021 A1 discloses a method for detecting a time offset between a first control unit and a second control unit, wherein the control units are each connected to an identical voltage source. Within the scope of the method, the control units are supplied with voltage by means of the voltage source, which is subject to a stochastic process. The voltage is digitized, and a first stamp is generated by the first control unit based on the stochastic voltage curve of the digitized voltage. Furthermore, a second stamp is generated by the second control unit based on the stochastic voltage curve of the digitized voltage. The first and / or the second stamp are transmitted to an evaluation device and compared. A time offset between the first control unit and the second control unit is then determined if the first stamp differs from the second stamp.By using one voltage source for both control units, the control units cannot be considered redundant.

[0011] The invention is based on the object of providing an electronic system with at least two control units, each having its own processor with its own clock generator, which has an optimized synchronization of the clock generators.

[0012] The object is achieved according to the invention with the features of the independent claims. Further practical embodiments and advantages of the invention are described in conjunction with the dependent claims.

[0013] An electronic system of a motor vehicle according to the invention comprises at least two control units communicating with one another, each of which is designed to send and receive signal information and each having its own processor with its own clock generator for clocking the respective control unit, wherein one control unit is defined as the master control unit and the control loop is designed to determine the time difference of the at least one other control unit compared to the master control unit in order to reduce or eliminate the asynchronicity of the clock generators by influencing the control loop on the clock generator of the at least one other control unit.In this case, each control unit not defined as a master control unit is designed to create, in addition to signal information, a time stamp with the time of generation of a signal, wherein the signal provided with the time stamp corresponds to a clock signal generated by the clock generator and wherein at least one control element is provided which is designed such that a time difference between two time stamps which relate to the same signal information is taken into account as a size of a control loop for reducing the asynchronicity of the clock generators in order to reduce or eliminate an asynchronicity of the clock generators.The control loop comprises a comparison module, the clock generator and the control element. The control loop is designed such that, upon receipt of a signal, the time at which the signal is generated is compared with the corresponding clock signal generated by the clock generator. The comparison module determines a time difference from the time difference between the time at which the signal is generated and the next clock signal and sends a corresponding time difference signal to the control element. The control element provides a correction signal for the clock generator based on the time difference signal. In other words, the general idea of ​​the invention is to synchronise or correct the clocking of the clock generators, which in practice differs slightly, using a control loop.To modify the clock deviations using a control loop in such a way that the differences between (two or more) clock generators are reduced as much as possible or completely eliminated. This allows for (optimized) synchronization and – especially in connection with safety-relevant functions of a motor vehicle – greater stability and accuracy of electronic systems.

[0014] In a first practical embodiment of an electronic system according to the invention, one control unit is defined as the master control unit. In this case, the control loop is designed to determine the time difference between the at least one other control unit and the master control unit in order to reduce or eliminate the asynchronicity of the clock generators by influencing the control loop on the clock generator of the at least one other control unit. This embodiment is relatively simple and cost-effective to implement and has the advantage that the control unit to be defined as the master control unit can be determined during the system design phase.If the electronic system according to the invention is an electronic steering system of the steer-by-wire type and the control units provided are a control unit for a force feedback actuator and two—in particular redundant—control units for wheel actuators, it is preferable in connection with this embodiment to define the control unit assigned to the force feedback actuator as the master control unit. This has the advantage that if one of the control units of the wheel actuator fails, the control loop continues to function with the master control unit and the still-functioning control unit of the other wheel actuator, so that the functionality of the control loop is not jeopardized if a control unit for the wheel actuator fails.

[0015] An embodiment of an electronic system is also known in which three control units are provided and are designed to create, in addition to signal information, a time stamp with the time of generation of a signal and to receive time stamps from the other control units, wherein each control unit is designed to compare its own time stamp with the associated time stamps of the other control units and wherein at least one decision module is provided which is designed to make a binding decision for all control units on the basis of the time differences determined by each control unit in order to reduce or eliminate asynchronicity of the clock generators with the least possible control effort. In this case, there is no need for a premature determination or definition of a (constantly constant) master control unit.Instead, each control unit determines the time differences to the other control units. This makes it possible, based on the then determined time stamp deviations, to make a (temporary) decision binding for all control units with the help of the decision module as to which two control units should adapt to which other control unit using the control loop. The control unit to which the other control units should adapt according to the (temporary) decision can therefore be regarded as the temporary master control unit. In this case, it is therefore a prerequisite that each control unit can adapt to the other two control units. This can lead to a change in the temporary master control unit, especially after a restart of the electronic system.

[0016] In another practical embodiment of an electronic system according to the invention, a continuous linear controller is provided as the control element. In particular, reference is made in this context to a PI controller. Such control elements are available relatively inexpensively, not only as standard components. It has also been shown that such control elements can also achieve relatively efficient and precise control for the described application, which can significantly reduce asynchrony in the short term.

[0017] The above applies in particular to electronic systems with PI controllers, whose P element is designed for dynamic adjustment of the clocks and whose I element is designed for the compensation of constant synchronicity deviations.

[0018] In another embodiment of an electronic system according to the invention, at least two control elements are provided, which are interconnected to form a cascade control system. Such a somewhat more complex structure allows the control to be further optimized in individual cases, particularly if the previously described PI controller does not achieve a satisfactory reduction in asynchrony and / or if the control duration is too long.

[0019] When an electronic system, particularly a steer-by-wire steering system, includes at least two control units within a redundant control system, reducing asynchrony has a particularly significant impact on improving the system's accuracy. In particular, haptic inaccuracies in the steering system, such as a false, delayed response of a force feedback actuator, can be avoided in this case.

[0020] The above applies in particular to electronic systems with two control units, which are redundant control units for wheel actuators of an electronic steering system of the steer-by-wire type and a further control unit which is assigned to a force feedback actuator, wherein the control units are all functionally connected to one another.

[0021] In a preferred embodiment, a start-delay module is provided, which enables a time-delayed start of the control loop and / or makes the start of the control loop dependent on the occurrence of one or more conditions. The background to this embodiment is that after the start of an electronic system, a time-delayed start of the individual elements, in particular the control units with their associated clock generators, can occur. If no start-delay module is provided, this can lead to very large differences between individual time stamps or to no corresponding time stamps being generated due to the control unit or its clock generator not having started yet. Without a start-delay module, this would lead to an unnecessarily long control process, especially in the case of large differences.Accordingly, it is preferable to start the control loop with a time delay, for example, after 10, 50, 100, 500, or 1,000 signals. This number is preferably chosen to ensure that all control units are reliably fully started and their clocks are already running at their standard timing.

[0022] The invention also relates to the following method.

[0023] In the method according to the invention for controlling an electronic system, one of the control units is defined as the master control unit, and each control unit not defined as a master control unit sends cyclic signal information with a time stamp and a fixed cycle time. This signal information is taken into account as a control loop variable for reducing the asynchronicity of the clock generators in order to reduce or eliminate asynchronicity of the clock generators. It is advantageous if, in addition to the time stamp, a value for the delay that has elapsed between the start of a task and the actual transmission of the signal information is also transmitted. If the value of this delay is to be taken into account, only the value of the last determined delay can be used, not the current value.From the (last determined) value of the delay, the time at which a task started and the time at which the last signal information was received, the time offset of the clock generators of different control units can be determined exactly.

[0024] If the hardware of an electronic system allows it, the processor clock can be adjusted (manipulated) based on the determined time offset in order to synchronize the clocks of the control units.

[0025] If the hardware doesn't allow manipulation of the processor clock, the call timing of the tasks to be synchronized must be adjusted so that the control unit clocks are synchronized. The tasks, especially in steer-by-wire steering systems, are often directly related to specific PWM cycles. In this case, it is also necessary to adjust the PWM cycle time.

[0026] In another known method for controlling an electronic system according to variant b), each control unit sends cyclic signal information with a time stamp and a fixedly defined cycle time, wherein each control unit is designed to compare its own time stamp with the corresponding time stamps of the other control units, and wherein at least one decision module is provided and designed to make a binding decision for all control units based on the time differences determined by each control unit in order to reduce or eliminate asynchronicity of the clock generators with the least possible control effort. In this case, the control units are of equal status insofar as it is not predetermined which of the control units specifies the clock to which the other control units adapt.With the help of the decision module, it can be determined which of the control units sets the clock, depending on the state of the electronic system, whereby the other control units or the tasks on the other control units are then adapted as far as possible so that the clock times of the control units are synchronized as far as possible.

[0027] In connection with the known variant b), the following two embodiments of the implementation are known.

[0028] Either the control elements of the control loop are designed in such a way that they do not completely compensate for the time offset and still try to implement their own clock to a small extent.

[0029] Or the control elements of the control loop are designed to fully compensate for the time offset. In this case, means are required to communicate the cycle time adjustments of each control unit to the other control units. The control loop must then be designed so that the sum of the adjustments tends toward zero.

[0030] In both of the last-described embodiments of the method according to the known variant b), the aim is for the cycle time of the tasks to assume a value which corresponds as closely as possible to the average of the respectively originally desired cycle times.

[0031] Further practical embodiments of the invention are described below in conjunction with the drawings. They show: Fig. 1 a schematic representation of a steering system of the steer-by-wire type in an isometric view, Fig. 2 a schematic representation of control units for the steering according toFig. 1 , Fig. 3 a schematic representation of a control circuit for reducing the asynchronicity of the clock generators of the control units from Fig. 2 , Fig. 4 a graphic representation of an electronic system with the control units according to Fig. 2 and the control loop according to Fig. 3 , according to which the force feedback actuator is defined as the master control unit and Fig. 5 shows an illustration of an electronic system according to Fig. 4 with visualization of the wiring of the two electric motors and corresponding power electronics.

[0032] Figure 1shows a steering system 10 of the steer-by-wire design with a steering wheel 14 serving as a steering instrument 12, a steering shaft 16 coupled in a rotationally fixed manner to the steering wheel 14 and a force feedback actuator (FFA) 18 with an FFA electric motor 20. Two steerable wheels 22 are coupled via a road wheel actuator (RWA) 24 and functionally connected steering rods 26. The road wheel actuator (RWA) 24 has an RWA electric motor 28 which is designed such that two Figure 1 RWA control units (not shown) can each access half the power of the RWA electric motor. This allows each of the RWA control units (not shown) to control the electric motor of the force feedback actuator (FFA) 18, creating a redundant electronic system for the road wheel actuator (RWA).

[0033] The road wheel actuator (RWA) 24 calculates and / or measures the steering forces that occur. The force feedback actuator (FFA) 18 then adjusts a steering feel based on the calculation or measurement results.

[0034] Figure 2 shows a schematic representation of the control units for the steering in the form of a system architecture with three microprocessors, namely an FFA control unit 30 with an FFA microprocessor 32, an RWA control unit 34 with a first RWA microprocessor 36 and a second RWA microprocessor 38. The microprocessors 32, 36, 38 are connected to one another via a bus line 40 of a bus system.

[0035] Figure 3shows a control loop as it can be implemented in an electronic system according to the invention. At a comparison module 42, upon receipt of a signal 44, the time at which the signal 44 is generated is compared with the corresponding clock signal 46, which is generated by a clock generator 48. The corresponding clock signal 46 can arrive earlier or later. The comparison module 42 determines a time difference from the time difference between the time at which the signal 44 is generated and the next clock signal 46 and sends a corresponding time difference signal 50 to a control element 52. The control element 52 then provides a correction signal 54 for the clock generator 48 based on the time difference signal 50. The control element 52 is designed such that a minimization of the time difference signal 50 is desired.

[0036] Figure 4 shows a graphical representation of an electronic system 56 with the control units from Fig. 2 and two control circuits according to Fig. 3 . In this system, the FFA microprocessor 32 of the FFA control unit 30, i.e., the control unit of the force feedback actuator, is defined as the master control unit. A signal sent by the FFA microprocessor 32 of the FFA control unit 30 is provided with a time stamp and, together with the time stamp, arrives as an input signal at the first RWA microprocessor 36 and the second RWA microprocessor 38. This signal is - as in connection with Figure 3 described - are aligned with the corresponding clock signals 46a, 46b generated by the respective clock generators 48a, 48b. Through the described interaction with the respective control element 52a, 52b, the asynchronicity of the clock generators 48a, 48b can be individually reduced with the help of the respective control loop, thereby improving the precision of the electronic system.

[0037] Figure 5shows an extension of the representation from Figure 2 The FFA control unit 30 includes the FFA microprocessor 32 and an FFA power electronics unit 58. This FFA power electronics unit 58 is connected to a three-phase electric motor 60 via three lines.

[0038] The first RWA microprocessor 36 and the second RWA microprocessor 38 are connected to a 6-phase electric motor 66 via a first RWA power electronics unit 62 and a second RWA power electronics unit 64, each via three lines.

[0039] The communication between the described control units 30, 34 takes place in the Fig. 5The illustrated embodiment has at least two bus systems A, B, wherein the bus system A establishes a direct connection between the FFA control unit 30 and the RWA control unit 34. Bus system B establishes a connection to the vehicle bus system (not shown) and thus to other control units assigned to the vehicle.

[0040] A further direct communication connection, not shown here, can exist between the first RWA microprocessor 36 and the second RWA microprocessor 38, so that data can optionally also be exchanged directly here. List of reference symbols

[0041] 10Steering 12Steering instrument 14Steering wheel 16Steering shaft 18Force feedback actuator (FFA) 20FFA electric motor 22Steerable wheel 24Road wheel actuator (RWA) 26Steering rod 28RWA electric motor 30FFA control unit 32FFA microprocessor 34RWA control unit 36First RWA microprocessor 38Second RWA microprocessor 40Bus line 42Comparison module 44Signal 46Clock signal 48Clock generator 50Time difference signal 52Control element 54Correction signal 56Electronic system 58FFA power electronics 603-phase electric motor 62First RWA power electronics 64Second RWA power electronics 666-phase electric motor

Claims

1. Electronic system of a motor vehicle, comprising at least two control units (30, 34) which communicate with each other, each designed to send and receive signal information and each having its own processor (32, 36, 38) with its own clock generator (48) for clocking the particular control unit (30, 34), characterized by each control unit (30, 34) being designed to create, in addition to signal information, a time stamp with the time of generation of a signal (44), the signal (44) provided with the time stamp corresponding to a clock signal generated by the clock generator (48); of the at least two control units (30, 34) which communicate with each other, one control unit being defined as a master control unit and the other of the two control units being defined as a non-master control unit; the control unit defined as a non-master control unit comprising a control loop; the control loop comprising a comparison module (42), the clock generator (48) and a control element (52), the control element (52) being designed such that a time difference between two time stamps which relate to the same signal information is taken into account as a size of a control loop for reducing the asynchronicity of the clock generators (48) in order to reduce or eliminate an asynchronicity of the clock generators (48), the control loop being designed such that, at the comparison module (42), upon receiving a signal (44), the time at which the signal (44) was generated is compared with the corresponding clock signal (46) generated by the clock generator (48), and the comparison module (42) determines a time gap from the time difference between the time at which the signal (44) was generated and the next clock signal (46) and sends a corresponding time difference signal (50) to the control element (52), and the control element (52) providing a correction signal (54) for the clock generator (48) based on the time difference signal (50).

2. Electronic system according to the preceding claim, characterized in that a PI controller is provided as the control element (52).

3. Electronic system according to the preceding claim, characterized in that the P element of the PI controller is designed for dynamic adjustment of the clock cycles and the I element of the PI controller is designed for compensation of constant synchronicity deviations.

4. Electronic system according to any of the preceding claims, characterized in that at least two control elements (52) are provided which are connected to form a cascade control.

5. Electronic system according to any of the preceding claims, characterized in that at least two control units (30, 34) are part of a redundant control system.

6. Electronic system according to the preceding claim, characterized in that two control units (30, 34) are redundant control units (30, 34) for wheel actuators of an electronic steering system (10) of the steer-by-wire type and one control unit (30, 34) is assigned to a force feedback actuator (18), the control units (30, 34) being functionally connected to one another.

7. Electronic system according to any of the preceding claims, characterized in that a start delay module is provided which allows a time-delayed start of the control loop and / or makes the start of the control loop dependent on the occurrence of one or more conditions.

8. Method for controlling an electronic system (56) according to any of the preceding claims, characterized in that one of the control units (30, 34) is defined as a master control unit and each control unit (30, 34) not defined as a master control unit sends cyclic signal information with a time stamp and a fixedly defined cycle time, this signal information being taken into account as a size of the control loop for reducing the asynchronicity of the clock generators (48) in order to reduce or eliminate an asynchronicity of the clock generators (48).