TFT array substrate and manufacturing process therefor and display device

Description

BACKGROUND Technical Field

[0001] Embodiments of the present disclosure generally relate to a field of display technology, and more particularly, to a TFT array substrate capable of improving a resolution of a display panel, a method for manufacturing the same, and a display device comprising such a TFT array substrate.Description of the Related Art

[0002] A TFT (Thin Film Transistor) array substrate is widely used in a display panel of a display device. In particular, a low-temperature polysilicon array substrate is gradually favored as an array substrate used in the display panel in recent years and is increasingly used in an organic electroluminescent displays or a liquid crystal display panel having high resolution and high picture quality, since it has advantages such as a high mobility and a high response speed. In the high resolution display panel, a number of small-sized thin film transistors are required, thus it demands higher requirements for process implementation, electrical performance and reliability of the thin film transistor array substrate. In particular, when a conventional low-temperature polysilicon thin film transistor array substrate is used in an organic electroluminescent diode display technology, it is generally necessary to provide a longer channel so as to drive the thin film transistor, thereby occupying a larger substrate area and restricting a high resolution design. US 2013 / 140569 discloses a semiconductor device which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. US 2013 / 240886 discloses an active device and an active device array substrate, wherein the active device array substrate includes a substrate and a plurality of active devices being located on the substrate, and at least one of the active devices includes a first thin film transistor and a second thin film transistor. KR 2015 / 0101417 discloses a display device including: a first semiconductor layer prepared on a substrate; a first insulating layer prepared on the substrate to cover the first semiconductor layer; a gate electrode prepared on the first insulating film to overlap the first semiconductor layer; a second insulating layer prepared on the first insulating layer to cover the gate electrode; and a second semiconductor layer prepared on the second insulating layer to overlap the first semiconductor layer and the gate electrode. JPH06291269A discloses a first semiconductor layer forming a field-effect transistor of a first conductive channel and a second semiconductor layer forming a field-effect transistor of a second conductive channel being laminated via an insulation layer. First and second insulation gate electrodes are formed on the surface in the mutual reverse side of the first and second semiconductor layers in a mutual opposed location. A common third insulation gate electrode with respect to both transistors is disposed between the first and second semiconductor layers and opposed to each of the first and second insulation gate electrodes. JPH08148693A discloses stacked TFT transistors for display applications, in which a channel region of a first semiconductor layer and a channel region of a second semiconductor layer are controlled by means of a common gate electrode layer. Between the first semiconductor layer and the second semiconductor layer, at least on electrical connection is made and the first semiconductor layer and the second semiconductor layer are connected in parallel or in series.SUMMARY

[0003] The present disclosure has been proposed out in order to overcome at least one of the above and other issues and defects existing in the prior art.

[0004] According to an aspect of the present disclosure, there is provided a TFT array substrate, comprising: a base substrate; and two thin film transistors located on the base substrate, the two thin film transistors each comprising an active layer having a source region and a drain region, the two active layers of the two thin film transistors being superposed with each other in a direction perpendicular to the base substrate, wherein the drain region of one of the two active layers is electrically connected to the source region of the other one of the two active layers via a through hole so that the two thin film transistors are connected in series wherein the two active layers comprise a first active layer formed on the base substrate and a second active layer positioned above the first active layer, and the second active layer comprises a connecting portion for electrically connecting the drain region of the first active layer to the source region of the second active layer, and a portion of the second active layer forms the connecting portion, wherein the connecting portion comprises a portion formed of a same material as the second active layer and doped, wherein one of the two thin film transistors comprises a first gate located on the base substrate, a first gate insulation layer covering the first gate, and a first active layer located on the first gate insulation layer, the other one of the two thin film transistors comprises a second active layer located above the first active layer, a second gate insulation layer covering the second active layer and a second gate located on the second gate insulation layer, and the source region of the second active layer is electrically connected to the drain region of the first active layer.

[0005] In an embodiment, the above-described TFT array substrate further comprises an interlayer insulation layer covering the one of the two thin film transistors, wherein the second active layer is located on the interlayer insulation layer.

[0006] In an embodiment, the TFT array substrate is provided with the through hole extending through the interlayer insulation layer so as to expose the drain region of the first active layer, and the connecting portion is located in the through hole.

[0007] The above-described TFT array substrate further comprises a source electrode layer electrically connected to the source region of the first active layer and a pixel electrode layer electrically connected to the drain region of the second active layer.

[0008] In an embodiment, the active layers each comprises a low-temperature polysilicon layer.

[0009] According to still another aspect of the present disclosure, there is provided a display device, comprising the TFT array substrate according to any one of the above-described embodiments.

[0010] According to the embodiments of the present disclosure, there is provided a TFT array substrate, and a display device. The TFT array substrate comprises two active layers superposed with each other in a direction perpendicular to the base substrate, and these two active layers are electrically connected to each other, wherein the drain region of one active layer is electrically connected to the source region of the other active layer, so as to form two thin film transistors superposed with each other in a vertical direction and connected in series. Thus, it is possible to reduce or save an area occupied by each thin film transistor on the substrate while maintaining a total effective channel length constant, thereby facilitating a high resolution design of a display panel, to meet the need for sensitivity to the channel length in an application of the thin film transistor in a high resolution display panel.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The features and advantages of the present disclosure will become more apparent from the following description with reference to the accompanying drawings, and the drawings are schematic and are not to be construed as limiting the present disclosure. In the drawings: Fig. 1 is a cross sectional view showing a structure of a portion of a TFT array substrate, not falling within the scope of the claimed invention; Fig. 2 is a cross sectional view showing a structure of a portion of a TFT array substrate according to an exemplary embodiment of the present disclosure, not falling within the scope of the claimed invention; Fig. 3 is a cross sectional view showing a structure of a portion of a TFT array substrate according to an exemplary embodiment of the present invention; and Figs. 4a-4d are schematic views showing steps of a method for manufacturing a TFT array substrate according to an exemplary embodiment of the present disclosure, not falling within the scope of the claimed invention. DETAINED DESCRIPTION OF PREFERRED EMBODIMENTS

[0012] Embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. In the present specification, the same or similar parts are indicated by the same or similar reference numerals. The following description of the various embodiments of the present disclosure with reference to the accompanying drawings is intended to illustrate a general concept of the present disclosure, but should not be construed as limiting the present disclosure.

[0013] Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it will be apparent that one or more embodiments may also be carried out without these specific details. In other instances, well known structures and devices are schematically illustrated to simplify the drawings.

[0014] Fig. 1 is a schematic view for showing a structure of a low-temperature polysilicon thin film transistor array substrate including a substrate 1, an active layer 2, a gate insulation layer 3, a gate layer 4, an intermediate insulation layer 5, a via hole penetrating through the intermediate insulation layer and the gate insulation layer, source and drain electrode layers 6, 7, a planarization layer 8 and a pixel electrode layer 9. In order to achieve such array substrate, it requires at least six masks for forming the active layer, the gate layer, the via hole, the source and drain electrode layers, the planarization layer and the pixel electrode layer. In a preparation process of a high resolution array substrate, channel length becomes is a key factor, especially for driving the thin film transistors of the organic electroluminescent diode display device, in which the channel length 2L may reach up to tens of microns, resulting in occupying a larger area and further adversely affecting implementation of high resolution.

[0015] According to a general inventive concept of the present disclosure, it provides a TFT array substrate, comprising two active layers superposed with each other in a direction perpendicular to a base substrate, and these two active layers are electrically connected to each other, for example, a drain region of one active layer is electrically connected to a source region of the other active layer, so as to form two thin film transistors superposed with each other in a vertical direction and connected in series. Thus, it is possible to reduce or save an area occupied by each thin film transistor on the substrate while maintaining a total effective channel length constant, thereby facilitating a high resolution design of a display panel, to meet the need for sensitivity to the channel length in an application of the thin film transistor in a high resolution display panel. In one example, the TFT array substrate is a low-temperature polysilicon array substrate.

[0016] Fig. 2 shows a structure of a portion of a TFT array substrate according to an exemplary embodiment of the present disclosure not falling within the scope of the claimed invention. As shown in Fig. 2, the TFT array substrate comprises a base substrate 100, a first active layer 102 formed on the base substrate 100, a first gate insulation layer 103 covering the first active layer 102, a gate 104 formed on the first gate insulation layer 103, a second gate insulation layer 105 at least covering the gate 104 and a second active layer 107 at least partially disposed on the second gate insulation layer 105. The first active layer 102, the first gate insulation layer 103 and the gate 104 form a portion of a first thin film transistor, while the gate 104, the second gate insulation layer 105 and the second active layer 107 form a portion of a second thin film transistor. Moreover, the second active layer 107 is electrically connected to the first active layer 102, so that the first thin film transistor is connected in series to the second thin film transistor.

[0017] In the embodiment, the first thin film transistor and the second thin film transistor superposed with each other share the gate 104, each of them has a channel length of L, and their total effective channel length is 2L, which is equal to the channel length of the conventional thin film transistor. However, on one hand, the area occupied on the substrate is reduced, thereby facilitating both an array substrate and a display panel having a high resolution; on the other hand, these two thin-film transistors connected in series can effectively reduce off-state leakage current and increase stability of the thin film transistors.

[0018] In an example, the drain region of one of these two active layers 102, 107 is electrically connected to the source region of the other of these two active layers, so as to achieve the series connection of the two thin film transistors. For example, in Fig. 2, a source electrode layer 101 is formed on the base substrate 100, and the source region of the first active layer 102 partially covers or makes contact with the source electrode layer 101, so as to realize the electrical connection of the source region of the first active layer 102 to the source electrode layer 101. Moreover, the drain region of the first active layer 102 is electrically connected to the source region of the second active layer 107, and the drain region of the second active layer 107 may be electrically connected to a pixel electrode layer 109. As shown in Fig. 2, the pixel electrode layer 109 may be disposed on a planarization layer 108 covering the second active layer 107 and the second gate insulation layer 105.

[0019] In one example, the TFT array substrate is provided with a through hole 106 extending through the first gate insulation layer 103 and the second gate insulation layer 105 so as to expose the drain region of the first active layer 102 (see Fig. 4c), and the second active layer 107 may comprise a connecting portion 1071 located in the through hole 106 so as to electrically connect the drain region of the first active layer 102 to the source region of the second active layer 107. In an example, the connecting portion 1071 may be formed of the same material as the second active layer 107, and alternatively, the connecting portion 1071 is doped to increase carrier concentration therein, and reduce on-resistance between the active layers in an on state.

[0020] Fig. 3 shows a structure of a portion of a TFT array substrate according to an embodiment of the claimed invention. As shown in Fig. 3, the TFT array substrate comprises a base substrate 200, a first gate 201 formed on the base substrate 200, a first gate insulation layer 202 covering the first gate 201, a first active layer 204 disposed on the first gate insulation layer 202, an interlayer insulation layer 205 covering the first active layer 204, a second active layer 206 formed on the interlayer insulation layer 205, a second gate insulation layer 207 covering the second active layer 206 and a second gate 209 disposed on the second gate insulation layer 207. The first gate 201, the first gate insulation layer 202 and the first active layer 204 form a portion of a first thin film transistor, while the second active layer 206, the second gate insulation layer 207 and the second gate 209 form a portion of a second thin film transistor. Moreover, the second active layer 206 is electrically connected to the first active layer 204, so that the first thin film transistor is connected in series to the second thin film transistor.

[0021] In the embodiment, the first thin film transistor and the second thin film transistor superposed with each other each has a channel length of L, and their total effective channel length is 2L, which is equal to the channel length of the conventional thin film transistor. However, on the one hand, the area occupied on the substrate is reduced, thereby facilitating an array substrate and a display panel to be of a high resolution; on the other hand, these two thin-film transistors connected in series can effectively reduce off-state leakage current and increase stability of the thin film transistors.

[0022] In an example, the drain region of one of these two active layers 204, 206 is electrically connected to the source region of the other one of these two active layers, so as to achieve the series connection of the two thin film transistors. For example, in Fig. 3, a source electrode layer 203 is formed on the first gate insulation layer 202, and the source region of the first active layer 204 is partially superposed or made contact with the source electrode layer 203, so as to realize the electrical connection of the source region of the first active layer 204 to the source electrode layer 203. Moreover, the drain region of the first active layer 204 is electrically connected to the source region of the second active layer 206, and the drain region of the second active layer 206 may be electrically connected to a pixel electrode layer 210. As shown in Fig. 3, the pixel electrode layer 210 may be disposed on a planarization layer 208 covering the second gate 209 and the second gate insulation layer 207.

[0023] In one example, the TFT array substrate is provided with a through hole extending through the interlayer insulation layer 205 so as to expose the drain region of the first active layer 204, and the second active layer 206 may comprise a connecting portion located in the through hole 106 so as to electrically connect the drain region of the first active layer 204 to the source region of the second active layer 206, for example, a vertical portion extending from the source region of the second active layer 206 to the drain region of the first active layer 204 as shown in the figure. In an example, the connecting portion may be formed of the same material as the second active layer 206, and alternatively, the connecting portion is doped to increase carrier concentration therein, and reduce on-resistance between the active layers in an on state.

[0024] According to another aspect, an embodiment of the present disclosure also provides a method for manufacturing a TFT array substrate, comprising steps of: providing a base substrate; and forming two thin film transistors on the base substrate, the thin film transistors each comprising an active layer having a source region and a drain region, the two active layers of the two thin film transistors being superposed with each other in a direction perpendicular to the base substrate, wherein the drain region of one of the two active layers is electrically connected to the source region of the other of the two active layers so that the two thin film transistors are connected in series.

[0025] Next, a method for manufacturing a TFT array substrate according to an exemplary embodiment of the present disclosure will be described in detail by way of example with reference to Figs. 4a to 4d.

[0026] Firstly, a base substrate 100 is provided. The base substrate may be a transparent substrate, such as a glass substrate or the like, which is cleaned in advance, and a buffer layer formed of silicon oxide, silicon nitride, or a stacked combination of both may be applied on the base substrate, to prevent adversely affecting operating characteristics of the thin film transistor due to the diffusion of metal ion impurities in the transparent substrate into the active layer.

[0027] As shown in Fig. 4a, a first semiconductor material layer is formed on the base substrate 100, and the first semiconductor material layer is patterned with a first mask to form a first active layer 102.

[0028] As shown in Fig. 4b, a first gate insulation layer 103 covering the first active layer 102 is formed, and a gate material layer is formed on the first gate insulation layer 103 and the gate material layer is patterned with a second mask to form a gate 104 located above the first active layer 102. The gate may have a structure of a single layer, two or more layers, and may be made of metal or metal alloy, such as molybdenum, aluminum, molybdenum tungsten or the like, and the thickness thereof may be in a range of 1000Å to 5000Å, alternatively in a range of 1500Å to 4000Å.

[0029] As shown in Fig. 4c, a second gate insulation layer 105 covering the gate 104 and the first gate insulation layer 103 is formed. In one example, the first and / or second gate insulation layer may be a single layer of silicon oxide, silicon nitride, or a stacked combination of both, and the present disclosure is not limited thereto. The first and / or second gate insulation layer may be deposited by PECVD, LPCVD, APCVD or ECR-CVD and the like, with a deposition thickness of 500Å to 2000Å. Further, a suitable thickness, for example 600Å to 1500Å, can be selected according to the specific design requirements.

[0030] Next, a through hole 106 extending through the second gate insulation layer 105 and the first gate insulation layer 103 is formed by using a third mask to expose the drain region of the first active layer 102.

[0031] Then, as shown in Fig. 4d, a second semiconductor material layer is formed on the second gate insulation layer 105 and the second semiconductor material layer is patterned with the first mask as described above to form a second active layer 107. A portion of the second active layer is located in the through hole to form a connecting portion 1071 for electrically connecting the drain region of the first active layer 102 to the source region of the second active layer 107. In an example, the first and / or second active layer may be a polysilicon layer, which is transformed by an amorphous silicon layer by means of a process of excimer laser crystallization, metal induced crystallization or solid phase crystallization or the like, thereby forming a low-temperature polysilicon array substrate. It should be noted that depending on different crystallization methods, specific processes and structures of the thin film transistors will be different. For example, in the preparation process, it is possible to incorporate heat treatment dehydrogenation, deposition of induced metal, heat treatment crystallization, excimer laser illumination crystallization, doping of source and drain regions (P-type or N-type doping), activation of doped impurities and the like, without affecting implementation of the present disclosure. In such a situation, the present disclosure will also have a beneficial effect. Exemplarily, the thickness of the first and / or second active layer may be 100Å to 3000Å, specifically 500Å to 1000Å, and the forming method thereof may be PECVD, LPCVD or a sputtering method, and the deposition temperature is below 600°C.

[0032] In an embodiment, still as shown in Fig. 4a, before the step of forming the first active layer 102, or after the step of forming the first active layer 102 but before the step of forming the first gate insulation layer 103, the method further comprises a step of forming an electrically conductive material layer on the base substrate and patterning the electrically conductive material layer by using a fourth mask to obtain a source electrode layer 101, wherein a portion of the first active layer 102 is superposed with a portion of the source electrode layer 101.

[0033] Further, after forming the gate 104 but before forming the second gate insulation layer 105, a first ion implantation process may be implemented by using the gate 104 as a shielding mask, so as to implement an ion doping process to the source region and the drain region of the first active layer 102; after forming the second active layer 107, a second ion implantation process may be implemented by using the above-described second mask as another shielding mask, so as to implement an ion doping process to the source region and the drain region of the second active layer 107. Alternatively, after forming the second active layer 107, an ion implantation process may be implemented by using the above-described second mask as a shielding mask, so as to implement an ion doping process to the source regions and the drain regions of the first active layer 102 and the second active layer 107. It will be appreciated that the connecting portion of the second active layer located in the through hole may also be doped when the ion doping process is implemented to the second active layer, so as to increase carrier concentration therein, and reduce on-resistance between the active layers in an on state.

[0034] The ion implantation process may be an ion implantation method with a mass spectrometer, an ion cloud-type implantation method without a mass spectrometer, a plasma implantation method, a solid state diffusion implantation method or the like. For example, if a popular ion cloud-type implantation method is used, then a mixed gas including Boron such as B 2 H 6 / H 2 or Phosphorus such as PH 3 / H 2 may be implanted according to the design requirements, and the ion implantation energy may be 10 to 200keV, specifically 40 to 100keV. The implantation dose may be in a range of 1×10 11< ~1×10 20< atoms / cm 3< , specifically 1×10 14< ~1×10 18< atoms / cm 3< .

[0035] As shown in Fig. 2, a planarization layer 108 covering the second active layer 107 and the second gate insulation layer 105 may be formed by using a fifth mask; and a pixel electrode layer 109 may be formed on the planarization layer 108 by using a sixth mask, wherein the pixel electrode layer 109 is electrically connected to the drain region of the second active layer 107. The planarization layer may be made of an organic material, specifically an organic photoresist material such as polyimide, acrylic or the like, with a thickness of 8000 Å to 20000 Å. The pixel electrode layer may be a structure of a single layer, two or more layers, and is composed of a transparent conductive material such as indium tin oxide, indium zinc oxide or the like, or metal, metal alloy, for example silver, silver alloy or the like, with a thickness of 1000Å to 5000Å, specifically 1500Å to 4000Å.

[0036] It can be seen that the method according to the embodiments of the present disclosure also uses six masks to manufacture the TFT array substrate, without increasing the number of masks compared to the conventional processes. Therefore, the method does not incorporate additional processes and increase process complexity in process realization, and the manufactured device has a better property.

[0037] Further, in an embodiment of the present disclosure, it is provided a display device, comprising the TFT array substrate according to any one of the above-described embodiments, or the TFT array substrate manufactured by the method according to any one of the above-described embodiments. Such a display device may be a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a notebook computer, a tablet computer, a display, a digital photo frame, a navigator, an identification device, or any other products or components having a display function.

Claims

1. A TFT array substrate, comprising: a base substrate (100); and two thin film transistors located on the base substrate (100), the two thin film transistors each comprising an active layer having a source region and a drain region, the two active layers of the two thin film transistors being superposed with each other in a direction perpendicular to the base substrate (100), wherein the drain region of one (102) of the two active layers is electrically connected to the source region of the other one (107) of the two active layers via a through hole (106) so that the two thin film transistors are connected in series, wherein the two active layers comprise a first active layer (102) formed on the base substrate (100) and a second active layer (107) positioned above the first active layer (102), and the second active layer (107) comprises a connecting portion (1071) for electrically connecting the drain region of the first active layer (102) to the source region of the second active layer (107), and a portion of the second active layer (107) forms the connecting portion (1071), wherein the connecting portion (1071) comprises a portion formed of a same material as the second active layer (107) and doped, wherein one of the two thin film transistors comprises a first gate (201) located on the base substrate (200), a first gate insulation layer (202) covering the first gate (201), and a first active layer (204) located on the first gate insulation layer (202), wherein the other one of the two thin film transistors comprises a second active layer (206) located above the first active layer (204), a second gate insulation layer (207) covering the second active layer (206) and a second gate (209) located on the second gate insulation layer (207), wherein the source region of the second active layer (206) is electrically connected to the drain region of the first active layer (204), and wherein the TFT array substrate further comprises a source electrode layer (101) electrically connected to the source region of the first active layer (102) and a pixel electrode layer (109) electrically connected to the drain region of the second active layer (107).

2. The TFT array substrate according to claim 1, further comprising an interlayer insulation layer (205) covering the one of the two thin film transistors, wherein the second active layer (206) is located on the interlayer insulation layer (205).

3. The TFT array substrate according to claim 2, wherein the TFT array substrate is provided with the through hole extending through the interlayer insulation layer (205) so as to expose the drain region of the first active layer (204), and the connecting portion is located in the through hole.

4. The TFT array substrate according to any one of claims 1-3, wherein the active layers each comprises a low-temperature polysilicon layer.

5. A display device, comprising the TFT array substrate according to any one of claims 1-4.