DISPLAY DEVICE

Description

[TECHNICAL FIELD]

[0001] The present invention relates to a display device and a method of driving the same.[BACKGROUND]

[0002] In general, a display device includes a display panel and a display panel driver. The display panel includes a plurality of pixels, a plurality of gate lines, a plurality of data lines, and a plurality of emission control lines. The display panel driver includes a gate driver configured to provide a gate signal to the gate lines, a data driver configured to provide a data voltage to the data lines, an emission controller configured to provide an emission control signal to the emission control lines, and a driving controller configured to generate control signals for controlling the gate driver, the data driver, and the emission controller.

[0003] Recently, when an image displayed on the display panel is a still image, or the display panel is driven in an always-on-display (AOD) mode, a method for reducing power consumption through low-frequency driving has been researched.

[0004] EP 3193323 A2 describes an organic light emitting display device which may include a display panel, a power supply, and a display driver, The display panel may comprise a plurality of scan lines, a plurality of data lines, and a plurality of pixels connected to the scan lines and to the data lines. The power supply may supply a first pixel voltage and a second pixel voltage to the pixels. The display driver may control the display panel. The display panel may display a first image in a first frame frequency during a first driving mode, and display a second image in a second frame frequency that is lower than the first frame frequency during a second driving mode, according to a control by the display driver

[0005] US 2015 / 243203 A1 describes a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide semiconductor) while at least one of the TFTs implementing the driving circuit next to the active area is a LTPS TFT (i.e., TFT with poly-Si semiconductor).

[0006] EP 2743910 A1 describes a display device including a display panel including a gate line, a data line, and a pixel connected to the gate line and the data line, a data driver connected to the data line, a gate driver connected to the gate line, and a signal controller controlling the data driver and the gate driver, wherein a circuits powering power source voltage that is normally used for driving the data driver is selectively not applied during a new-image blanking time when the signal controller is not supplying image data to the data driver.

[0007] US 2018 / 226029 A1 describes a pixel including first to fourth transistors and a driving transistor. The first transistor is connected between a data line and a first node and has a gate electrode to receive a scan signal. The driving transistor is connected between the first node and a second node and has a gate electrode connected to a third node. The second transistor is connected between the second and third nodes and has a gate electrode to receive the scan signal. The third transistor is connected between first power and the first node and has a gate electrode to receive an emission signal. The fourth transistor is connected between the first and second nodes and has a gate electrode to receive an initialization signal. An organic light emitting diode is connected between the second node and second power. A storage capacitor is connected between the first power and third node.

[0008] US 2018 / 006099 A1 describes a pixel. The pixel includes a pixel circuit and an organic light emitting diode. The pixel circuit has first, second, third, and fourth transistors. The first transistor controls an amount of current flowing from a first driving power supply coupled to a first node to a second driving power supply through the organic light emitting diode. The turns on when a scan signal is supplied to a first scan line. The third transistor turns on when a scan signal is supplied to a second scan line. The fourth transistor turns on when a scan signal is supplied to a third scan line. The first transistor is a p-type Low Temperature Poly-Silicon thin film transistor and the third transistor and the fourth transistor are n-type oxide semiconductor thin film transistors.

[0009] US 2018 / 090073 A1 describes an organic light-emitting display device including an organic light-emitting display panel having a plurality of subpixels connected to data lines and gate lines; a data driver driving the data lines; and a gate driver driving the gate lines, wherein the organic light-emitting display device has a first mode having a first refresh rate and a second mode having a second refresh rate that is lower than the first refresh rate, the second mode having a first period and a second period that is subsequent to the first period, and wherein, in the first period of the second mode, the data driver subsequently supplied data voltages to at least two of the plurality of subpixels, and in the second period of the second mode, the data driver supplies a specific voltage to the plurality of subpixels, the specific voltage being the same as one of at least two of the data voltages sequentially supplied to the at least two subpixels.

[0010] US 2017 / 004766 A1 describes an organic light emitting display which can reduce flicker, along with power consumption, and a driving method thereof. In a low-power operation mode of the organic light emitting display, at least one holding frame is placed between writing frames in which image data is written, the output of the source driver is enabled during the writing frames, the output of the source driver is disabled during the holding frames, and the emission driver is controlled during the holding frames to increase the toggle frequency of the emission signal to be higher than or equal to N times the frame frequency (N is a positive integer greater than or equal to 2). The driving method can reduce the perceived flicker.

[0011] US 2019 / 180689 A1 describes a method for driving a display device is provided. The display device includes a first driving circuit and a pixel array. The driving method includes the following step. In a first mode, by using the first driving circuit, a first light emission start signal is received to drive the pixel array. The first light emission start signal includes a plurality of first pulses, and duration of each of the first pulses is respectively overlapped with at least a part of a period of each of a first frame and at least one second frame. In a second mode, by using the first driving circuit, a second light emission start signal is received to drive the pixel array. The second light emission start signal includes a second pulse. Duration of the second pulse is overlapped with at least a part of a period of the first frame, and the second light emission start signal remains at a first level in a period of the at least one second frame.[CONTENT OF THE INVENTION][PROBLEM TO BE SOLVED]

[0012] One object of the present invention is to provide a display device capable of reducing power consumption of a display panel.

[0013] However, the object of the present invention is not limited thereto. Thus, the object of the present invention may be extended without departing from the scope of the present invention.[MEANS FOR SOLVING THE PROBLEM]

[0014] According to embodiments, a display device includes a display panel including a pixel including switching elements of a first type and switching elements of a second type, wherein the switching elements of the first type are poly-silicon thin film transistors and the switching elements of the second type are oxide thin film transistors, a gate driver configured to generate a gate signal based on a gate clock signal and to provide the gate signal to the display panel, a data driver configured to provide a data voltage to the display panel, an emission controller configured to provide an emission control signal to the display panel, and a driving controller configured to generate control signals for controlling the gate driver, the data driver, and the emission controller. Here, in a low-frequency driving mode, the driving controller provides the gate clock signal that swings between a high level and a low level to the gate driver during a writing frame for writing data to the pixel and may provide the gate clock signal having a direct current voltage to the gate driver during a holding frame for holding the data written in the pixel. The driving controller comprises a voltage generator configured to generate an analog voltage for operating the data driver to generate a gamma reference based on the analog driving voltage (AVDD), and a sustaining voltage for constantly maintaining a driving current of the pixel. In the low-frequency driving mode, the driving controller is configured to provide: the analog voltage (AVDD) having a first voltage level to the data driver during the writing frame; the analog driving voltage (AVDD) having a second voltage level that is lower than the first voltage level to the data driver (130) during the holding frame; and the sustaining voltage having the first voltage level to the pixel during the holding frame.

[0015] The pixel includes: a first switching element including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second switching element including a gate electrode to which a first data write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the second node; a third switching element including a gate electrode to which a second data write gate signal is applied, a first electrode connected to the first node, and a second node connected to the third node; a fourth switching element including a gate electrode to which a data initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the first node; a fifth switching element including a gate electrode to which the emission control signal is applied, a first electrode to which a high power supply voltage is applied, and a second electrode connected to the second node; a sixth switching element including a gate electrode to which the emission control signal is applied, a first electrode connected to the third node, and a second electrode connected to an anode electrode of an organic light emitting diode; a seventh switching element including a gate electrode to which an organic light emitting diode initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode electrode of the organic light emitting diode; a storage capacitor including a first electrode to which the high power supply voltage is applied and a second electrode connected to the first node; the organic light emitting diode including the anode electrode and a cathode electrode to which a low power supply voltage is applied; and an eighth switching element including a gate electrode to which a sustaining voltage enable signal is applied, a first electrode to which the sustaining voltage is applied, and a second electrode connected to the first electrode of the second switching element.

[0016] The first switching element, the second switching element, the fifth switching element, the sixth switching element and the eighth switching elements are poly-silicon thin film transistors; the third switching element, the fourth switching element, and the seventh switching element are oxide thin film transistors.

[0017] During the holding frame, the display device is configured to turn the eighth switching element on, to transmit the sustaining voltage to the first electrode of the second switching element through the eighth switching element.

[0018] In embodiments, in the low-frequency driving mode, the gate clock signal may swing between the high level and the low level during the writing frame and may be maintained at the low level during the holding frame.

[0019] In embodiments, in the low-frequency driving mode, the gate clock signal may swing between the high level and the low level during the writing frame and may be maintained at the high level during the holding frame.

[0020] In embodiments, the switching element of the first type may be a P-type transistor. In addition, the switching element of the second type may be an N-type transistor.

[0021] In embodiments, in the low-frequency driving mode, the second switching element, the fifth switching element, and the sixth switching element may be driven at a first driving frequency, and the third switching element may be driven at a second driving frequency that is lower than the first driving frequency.

[0022] In embodiments, the driving controller may include a gate controller configured to generate the gate clock signal.

[0023] According to examples, a display device includes a display panel including a pixel including a switching element of a first type and a switching element of a second type that is different from the first type, a gate driver configured to provide a gate signal to the display panel, a data driver configured to provide a data voltage to the display panel, an emission controller configured to provide an emission control signal to the display panel, and a driving controller configured to generate control signals for controlling the gate driver, the data driver, and the emission controller. The driving controller includes a voltage generator configured to generate an analog voltage provided to the data driver and the pixel. Here, in a low-frequency driving mode, the driving controller may provide an analog driving voltage for operating the data driver to the data driver during a writing frame for writing data to the pixel and may provide the analog driving voltage that does not operate the data driver to the data driver during a holding frame for holding the data written in the pixel.

[0024] In examples, in the low-frequency driving mode, the driving controller may provide the analog driving voltage having a first voltage level to the data driver during the writing frame and may provide the analog driving voltage having a second voltage level that is lower than the first voltage level to the data driver during the holding frame.

[0025] The switching element of the first type is a poly-silicon thin film transistor. In addition, the switching element of the second type is an oxide thin film transistor.

[0026] In embodiments, the switching element of the first type may be a P-type transistor. In addition, the switching element of the second type may be an N-type transistor.

[0027] The pixel includes a first switching element including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, a second switching element including a gate electrode to which a first data write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the second node, a third switching element including a gate electrode to which a second data write gate signal is applied, a first electrode connected to the first node, and a second node connected to the third node, a fourth switching element including a gate electrode to which a data initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the first node, a fifth switching element including a gate electrode to which the emission control signal is applied, a first electrode to which a high power supply voltage is applied, and a second electrode connected to the second node, a sixth switching element including a gate electrode to which the emission control signal is applied, a first electrode connected to the third node, and a second electrode connected to an anode electrode of an organic light emitting diode, a seventh switching element including a gate electrode to which an organic light emitting diode initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode electrode of the organic light emitting diode, a storage capacitor including a first electrode to which the high power supply voltage is applied and a second electrode connected to the first node, and the organic light emitting diode including the anode electrode and a cathode electrode to which a low power supply voltage is applied.

[0028] In embodiments, the first switching element, the second switching element, the fifth switching element, and the sixth switching element may be the poly-silicon thin film transistors. In addition, the third switching element, the fourth switching element, and the seventh switching element may be the oxide thin film transistors.

[0029] In embodiments, in the low-frequency driving mode, the second switching element, the fifth switching element, and the sixth switching element may be driven at a first driving frequency, and the third switching element may be driven at a second driving frequency that is lower than the first driving frequency.

[0030] In the low-frequency driving mode, the driving controller provides the analog driving voltage to the data driver during the writing frame and may provide the sustaining voltage to the pixel during the holding frame.

[0031] In embodiments, the driving controller may include a voltage generator configured to generate a voltage provided to the data driver and the pixel.[EFFECTS OF THE INVENTION]

[0032] According to embodiments of the present invention, in the low-frequency driving mode of the display device including the pixel including the switching element of the first type and the switching element of the second type, the display device provides the gate clock signal having the direct current voltage to the gate driver during the holding frame, so that power consumption can be reduced.

[0033] According to embodiments of the present invention, in the low-frequency driving mode of the display device including the pixel including the switching element of the first type and the switching element of the second type, the display device does not operate the data driver during the holding frame, so that the power consumption can be reduced.

[0034] In addition, according to embodiments of the present invention, in the low-frequency driving mode of the display device including the pixel including the switching element of the first type and the switching element of the second type, the display device supplies the sustaining voltage to the pixel during the holding frame, so that a leakage current can be prevented from being generated, and luminance of the pixel can be constantly maintained.[BRIEF DESCRIPTION OF THE DRAWINGS]

[0035] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present invention. FIG. 2 is a circuit diagram illustrating an example of a pixel included in the display device of FIG. 1. FIG. 3 is a timing diagram illustrating input signals applied to the pixel of FIG. 2. FIG. 4 is a timing diagram illustrating an example of signals applied to the pixel of FIG. 2 in a low-frequency driving mode. FIG. 5 is a timing diagram illustrating another example of signals applied to the pixel of FIG. 2 in a low-frequency driving mode. FIG. 6 is a circuit diagram illustrating another example of a pixel included in the display device of FIG. 1. FIG. 7 is a timing diagram illustrating an example of signals applied to the pixel of FIG. 6 in a low-frequency driving mode. FIG. 8 is a block diagram illustrating an electronic device including the display device of FIG. 1. FIG. 9 is a diagram illustrating an example in which the electronic device of FIG. 8 is implemented as a smart phone. [PARTICULAR CONTENTS FOR IMPLEMENTING THE INVENTION]

[0036] Hereinafter, embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

[0037] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present invention.

[0038] Referring to FIG. 1, a display device 100 may include a display panel 110 and a display panel driver. The display panel driver may include a gate driver 120, a data driver 130, an emission controller 140, and a driving controller 150.

[0039] The display panel 110 may include a plurality of gate lines GWPL, GWNL, GIL, and GBL, a plurality of data lines DL, a plurality of emission control lines EML, sustaining voltage supply lines VsusL, and a plurality of pixels PX electrically connected to the gate lines GWPL, GWNL, GIL, and GBL, the data lines DL, the emission control lines EML, and the sustaining voltage supply lines VsusL. The gate lines GWPL, GWNL, GIL, and GBL, the emission control lines EML, and the sustaining voltage supply lines VsusL may extend in a first direction D1, and may be arranged in a second direction D2 perpendicular to the first direction D1. The data lines DL may extend in the second direction D2, and may be arranged in the first direction D1. The first direction D1 may be parallel to a long side of the display panel 110, and the second direction D2 may be parallel to a short side of the display panel 110. Each of the pixels PX may be formed in a region where the gate lines intersect the data lines DL.

[0040] The driving controller 150 may receive input image data IMG and an input control signal CON from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CON may include a master clock signal and a data enable signal. The input control signal CON may further include a vertical synchronization signal and a horizontal synchronization signal.

[0041] The driving controller 150 may generate control signals CTL1, CTL2, and CTL3 for controlling the gate driver 120, the data driver 130, and the emission controller 140 based on the input image data IMG and the input control signal CON.

[0042] The driving controller 150 may generate a first control signal CTL1 for controlling an operation of the gate driver 120 based on the input control signal CON. The driving controller 150 may output the first control signal CTL1 to the gate driver 120. For example, the first control signal CTL1 may include a vertical start signal and a gate clock signal. In one embodiment, in a low-frequency driving mode, the driving controller 150 may provide a gate clock signal that swings between a high level and a low level to the gate driver 120 during a writing frame for writing data to the pixel PX, and provide a gate clock signal having a direct current voltage to the gate driver 120 during a holding frame for holding the data written in the pixel PX. For example, the driving controller 150 may include a gate controller configured to generate the gate clock signal.

[0043] The driving controller 150 may generate a second control signal CTL2 for controlling an operation of the data driver 130 based on the input control signal CON. The driving controller 150 may output the second control signal CTL2 to the data driver 130. For example, the second control signal CTL2 may include a horizontal start signal and a load signal.

[0044] The driving controller 150 may generate a data signal DATA based on the input image data IMG. For example, the driving controller 150 may convert the input image data IMG into the data signal DATA by applying an algorithm for compensating for image quality of the input image data IMG. The driving controller 150 may output the data signal DATA to the data driver 130.

[0045] In addition, the driving controller 150 may generate an analog driving voltage AVDD for operating the data driver 130. The driving controller 150 may output the analog driving voltage AVDD to the data driver 130. Further, the driving controller 150 may generate a sustaining voltage Vsus for constantly maintaining a driving current of the pixel PX. The driving controller 150 may provide the sustaining voltage Vsus to the pixel PX. For example, the driving controller 150 may include a voltage generator configured to generate a voltage provided to the data driver 130 and the pixel PX. In one embodiment, in the low-frequency driving mode, the driving controller 150 may provide an analog driving voltage AVDD having a first voltage level to the data driver 130 during the writing frame, and provide an analog driving voltage AVDD having a second voltage level (e.g., 0V) to the data driver 130 during the holding frame. In another embodiment, in the low-frequency driving mode, the driving controller 150 may provide the analog driving voltage AVDD having the first voltage level to the data driver 130 during the writing frame, and provide a sustaining voltage Vsus having a third voltage level to the pixel PX during the holding frame. For example, the third voltage level may be equal to or different from the first voltage level.

[0046] The driving controller 150 may generate a third control signal CTL3 for controlling an operation of the emission controller 140 based on the input control signal CON. The driving controller 150 may output the third control signal CTL3 to the emission controller 140.

[0047] The gate driver 120 may generate gate signals GWP, GWN, GI, and GB in response to the first control signal CTL1 supplied from the driving controller 150. The gate driver 120 may output the gate signals GWP, GWN, GI, and GB to the gate lines GWPL, GWNL, GIL, and GBL.

[0048] The data driver 130 may generate a data voltage Vd based on the second control signal CTL2, the analog driving voltage AVDD, and the data signal DATA supplied from the driving controller 150. The data driver 130 may generate a gamma reference voltage based on the second control signal CTL2 and the analog driving voltage AVDD received from the driving controller 150. The gamma reference voltage may have a value corresponding to each data signal DATA. For example, the data driver 130 may generate the gamma reference voltage by distributing the analog driving voltage AVDD supplied from the driving controller 150. The data driver 130 may convert the data signal DATA into an analog data voltage Vd by using the gamma reference voltage. The data driver 130 may output the data voltage Vd to the data line DL.

[0049] The emission controller 140 may generate an emission control signal in response to the third control signal supplied from the driving controller 150. The emission controller 140 may output emission control signals to the emission control lines EML.

[0050] FIG. 2 is a circuit diagram illustrating an example of a pixel included in the display device of FIG. 1, and FIG. 3 is a timing diagram illustrating input signals applied to the pixel of FIG. 2.

[0051] Referring to FIGS. 1 to 3, the display panel may include a plurality of pixels PX, and each of the pixels PX may include an organic light emitting diode OLED.

[0052] The pixels PX receive data write gate signals GWP and GWN, a data initialization gate signal GI, an organic light emitting diode initialization gate signal GB, and an emission control signal EM to emit light from the organic light emitting diode OLED according to a level of the data voltage Vd, so that an image may be displayed.

[0053] According to embodiments of the present invention, each of the pixels PX may include a switching element of a first type and a switching element of a second type that is different from the first type. For example, the switching element of the first type may be a poly-silicon thin film transistor. For example, the switching element of the first type may be a low-temperature poly-silicon (LTPS) thin film transistor. For example, the switching element of the second type may be an oxide thin film transistor. For example, the switching element of the first type may be a P-type transistor, and the switching element of the second type may be an N-type transistor.

[0054] For example, the data write gate signals GWP and GWN may include a first data write gate signal GWP and a second data write gate signal GWN. The first data write gate signal GWP may be applied to the P-type transistor, and may have a low-level activation signal at a data write timing. The second data write gate signal GWN may be applied to the N-type transistor, and may have a high-level activation signal at the data write timing.

[0055] According to embodiments of the present invention, each of the pixels PX may include first to seventh switching elements T1, T2, T3, T4, T5, T6, and T7, a storage capacitor CST, and an organic light emitting diode OLED.

[0056] The first switching element T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. For example, the first switching element T1 may be a poly-silicon thin film transistor. The first switching element T1 may be a P-type thin film transistor. The first electrode of the first switching element T1 may be a source electrode, and the second electrode of the first switching element T1 may be a drain electrode.

[0057] The second switching element T2 may include a gate electrode to which the first data write gate signal GWP is applied, a first electrode to which the data voltage Vd is applied, and a second electrode connected to the second node N2. For example, the second switching element T2 may be a poly-silicon thin film transistor. The second switching element T2 may be a P-type thin film transistor. The first electrode of the second switching element T2 may be a source electrode, and the second electrode of the second switching element T2 may be a drain electrode.

[0058] The third switching element T3 may include a gate electrode to which the second data write gate signal GWN is applied, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. For example, the third switching element T3 may be an oxide thin film transistor. The third switching element T3 may be an N-type thin film transistor. The first electrode of the third switching element T3 may be a source electrode, and the second electrode of the third switching element T3 may be a drain electrode.

[0059] The fourth switching element T4 may include a gate electrode to which the data initialization gate signal GI is applied, a first electrode to which an initialization voltage VI is applied, and a second electrode connected to the first node N1. For example, the fourth switching element T4 may be an oxide thin film transistor. The fourth switching element T4 may be an N-type thin film transistor. The first electrode of the fourth switching element T4 may be a source electrode, and the second electrode of the fourth switching element T4 may be a drain electrode.

[0060] The fifth switching element T5 may include a gate electrode to which the emission control signal EM is applied, a first electrode to which a high power supply voltage ELVDD is applied, and a second electrode connected to the second node N2. For example, the fifth switching element T5 may be a poly-silicon thin film transistor. The fifth switching element T5 may be a P-type thin film transistor. The first electrode of the fifth switching element T5 may be a source electrode, and the second electrode of the fifth switching element T5 may be a drain electrode.

[0061] The sixth switching element T6 may include a gate electrode to which the emission control signal EM is applied, a first electrode connected to the third node N3, and a second electrode connected to an anode electrode of the organic light emitting diode OLED. For example, the sixth switching element T6 may be a poly-silicon thin film transistor. The sixth switching element T6 may be a P-type thin film transistor. The first electrode of the sixth switching element T6 may be a source electrode, and the second electrode of the sixth switching element T6 may be a drain electrode.

[0062] The seventh switching element T7 may include a gate electrode to which the organic light emitting diode initialization gate signal GB is applied, a first electrode to which the initialization voltage VI is applied, and a second electrode connected to the anode electrode of the organic light emitting diode OLED. For example, the seventh switching element T7 may be an oxide thin film transistor. The seventh switching element T7 may be an N-type thin film transistor. The first electrode of the seventh switching element T7 may be a source electrode, and the second electrode of the seventh switching element T7 may be a drain electrode.

[0063] The storage capacitor CST may include a first electrode to which the high power supply voltage is applied, and a second electrode connected to the first node N1.

[0064] The organic light emitting diode OLED may include the anode electrode, and a cathode electrode to which a low power supply voltage ELVSS is applied.

[0065] Referring to FIG. 3, the pixel PX may operate in a first period P1 to a fourth period P4. During the first period P1, the fourth switching element T4 may be turned on in response to the initialization gate signal GI, so that the first node N1 and the storage capacitor CST may be initialized. During the second period P2, the second switching element T2 and the third switching element T3 may be turned on in response to the first data write gate signal GWP and the second data write gate signal GWN, respectively, so that a threshold voltage of the first switching element T1 may be compensated, and the data voltage Vd for which the threshold voltage is compensated may be written in the first node N1. During the third period P3, the seventh switching element T7 may be turned on in response to the organic light emitting diode initialization gate signal GB, so that the anode electrode of the organic light emitting diode OLED may be initialized. During the fourth period P4, the fifth switching element T5 and the sixth switching element T6 may be turned on in response to the emission control signal EM, so that the organic light emitting diode OLED may emit light.

[0066] During the first period P1, the data initialization gate signal GI may have an activation level. For example, the activation level of the data initialization gate signal GI may be a high level. When the data initialization gate signal GI having the activation level is supplied, the fourth switching element T4 may be turned on, so that the initialization voltage VI may be applied to the first node N1.

[0067] During the second period P2, each of the first data write gate signal GWP and the second data write gate signal GWN may have an activation level. For example, the activation level of the first data write gate signal GWP may be a low level, and the activation level of the second data write gate signal GWN may be a high level. When the first data write gate signal GWP and the second data write gate signal GWN having the activation levels are supplied, the second switching element T2 and the third switching element T3 may be turned on. In addition, the first switching element T1 may be turned on by the initialization voltage VI. The data voltage Vd supplied to the first electrode of the second switching element T2 along a path formed as the first to third switching elements T1, T2, and T3 are turned on may be set to the first node N1. In this case, since the third switching element T3 is turned on, the first switching element T1 is diode-connected, so that the data voltage Vd for which the threshold voltage of the first switching element T1 is compensated (i.e., a voltage obtained by subtracting the threshold voltage from the data voltage) may be set to the first node N1.

[0068] During the third period P3, the organic light emitting diode initialization gate signal GB may have an activation level. For example, the activation level of the organic light emitting diode initialization gate signal GB may be a high level. When the organic light emitting diode initialization gate signal GB having the activation level is supplied, the seventh switching element T7 may be turned on, so that the initialization voltage VI may be applied to the anode electrode of the organic light emitting diode OLED.

[0069] During the fourth period P4, the emission control signal EM may have an activation level. For example, the activation level of the emission control signal EM may be a low level. When the emission control signal EM having the low level is supplied, the fifth switching element T5 and the sixth switching element T6 may be turned on. In addition, the first switching element T1 may be turned on by the data voltage Vd. The first switching element T1 may generate a driving current based on the data voltage Vd. The driving current may be supplied to the anode electrode of the organic light emitting diode OLED through the sixth switching element T6, so that the organic light emitting diode OLED may emit the light.

[0070] FIG. 4 is a timing diagram illustrating an example of signals applied to the pixel of FIG. 2 in a low-frequency driving mode.

[0071] Referring to FIGS. 1 to 4, the display device may be driven in a normal driving mode for operating at a normal driving frequency, and in a low-frequency driving mode for operating at a frequency lower than the normal driving frequency. For example, when the input image data is a moving image, the display panel may operate in the normal driving mode. For example, when the input image data is a still image, the display panel may operate in the low-frequency driving mode. For example, when the display device is driven in an always-on-display (AOD) mode, the display panel may operate in the low-frequency driving mode.

[0072] The display panel may be driven by a unit of frames, and may be refreshed every frame in the normal driving mode. Therefore, the normal driving mode may include only a writing frame WRITING FRAME for writing data to a pixel. In the low-frequency driving mode, the display panel may be refreshed at a frequency of the low-frequency driving mode. Therefore, the low-frequency driving mode may include a writing frame WRITING FRAME for writing data to a pixel, and a holding frame HOLDING FRAME for holding the data written in the pixel. For example, when a frequency of the normal driving mode is 60 Hz, and the frequency of the low-frequency driving mode is 1 Hz, the low-frequency driving mode may include one writing frame WRITING FRAME and 59 holding frames HOLDING FRAME during 1 second. When the frequency of the normal driving mode is 60 Hz, and the frequency of the low-frequency driving mode is 1 Hz, 59 consecutive holding frames HOLDING FRAME may be disposed between two adjacent writing frames WRITING FRAME. In this case, in the pixel of FIG. 2, the second switching element T2, the fifth switching element T5, and the sixth switching element T6 may operate at 60 Hz, and the third switching element T3 may operate at 1 Hz. For example, when the frequency of the normal driving mode is 60 Hz, and the frequency of the low-frequency driving mode is 10 Hz, the low-frequency driving mode may include 10 writing frames WRITING FRAME and 50 holding frames HOLDING FRAME during 1 second. When the frequency of the normal driving mode is 60 Hz, and the frequency of the low-frequency driving mode is 10 Hz, five consecutive holding frames HOLDING FRAME may be disposed between two adjacent writing frames WRITING FRAME. In this case, in the pixel of FIG. 2, the second switching element T2, the fifth switching element T5, and the sixth switching element T6 may operate at 60 Hz, and the third switching element T3 may operate at 10 Hz.

[0073] Referring to FIG. 4, gate clock signals CLK1 and CLK2 may include a first gate clock signal CLK1 and a second gate clock signal CLK2. For example, the second gate clock signal CLK2 may be a signal obtained by allowing the first gate clock signal CLK1 to be delayed. For example, the second gate clock signal CLK2 may be an inversion signal of the first gate clock signal CLK1. Although the first gate clock signal CLK1 and the second gate clock signal CLK2 have been shown in FIG. 4, the gate clock signal is not limited thereto. For example, the gate driver may further receive a gate clock signal according to a configuration of a stage that generates a gate signal.

[0074] The driving controller of the display device according to embodiments of the present invention may provide a gate clock signal having a direct current voltage to the gate driver during the holding frame HOLDING FRAME. In one embodiment, in the low-frequency driving mode, the gate clock signals CLK1 and CLK2 may swing between a high level and a low level during the writing frame WRITING FRAME, and may be maintained at the low level during the holding frame HOLDING FRAME. In another embodiment, in the low-frequency driving mode, the gate clock signals CLK1 and CLK2 may swing between the high level and the low level during the writing frame WRITING FRAME, and may be maintained at the high level during the holding frame HOLDING FRAME. For example, the high level may have a gate-on voltage level, and the low level may have a gate-off voltage level.

[0075] Referring to FIG. 4, the first gate clock signal CLK1 may swing between the high level and the low level during the writing frame WRITING FRAME, and may be maintained at the low level during the holding frame HOLDING FRAME. In addition, the second gate clock signal CLK2 may swing between the high level and the low level during the writing frame WRITING FRAME, and may be maintained at the high level during the holding frame HOLDING FRAME. In the display device according to embodiments of the present invention, the gate clock signals CLK1 and CLK2 may be maintained as a direct current voltage having a high level or a low level without swinging during the holding frame HOLDING FRAME in the low-frequency driving mode, so that power consumption may be reduced.

[0076] FIG. 5 is a timing diagram illustrating another example of signals applied to the pixel of FIG. 2 in a low-frequency driving mode.

[0077] Referring to FIGS. 1, 2, 3, and 5, the display device may be driven in a normal driving mode for operating at a normal driving frequency, and in a low-frequency driving mode for operating at a frequency lower than the normal driving frequency. For example, when the input image data is a moving image, the display panel may operate in the normal driving mode. For example, when the input image data is a still image, the display panel may operate in the low-frequency driving mode. For example, when the display device is driven in an AOD mode, the display panel may operate in the low-frequency driving mode.

[0078] The display panel may be driven by a unit of frames, and may be refreshed every frame in the normal driving mode. Therefore, the normal driving mode may include only a writing frame WRITING FRAME for writing data to a pixel. In the low-frequency driving mode, the display panel may be refreshed at a frequency of the low-frequency driving mode. Therefore, the low-frequency driving mode may include a writing frame WRITING FRAME for writing data to a pixel, and a holding frame HOLDING FRAME for holding the data written in the pixel. The driving controller of the display device may not operate the data driver during the holding frame HOLDING FRAME.

[0079] Referring to FIG. 5, in the low-frequency driving mode, the driving controller of the display device may provide an analog driving voltage AVDD having a first voltage level to the data driver during the writing frame WRITING FRAME, and provide an analog driving voltage AVDD having a second voltage level LV2 that is lower than the first voltage level LV1 to the data driver during the holding frame HOLDING FRAME. The second voltage level may have a voltage level (e.g., 0V) that does not operate the data driver. The data driver may generate a gamma reference voltage based on the analog driving voltage AVDD having the first voltage level LV1 during the writing frame WRITING FRAME. The data driver may convert the data signal supplied from the driving controller into the analog data voltage Vd by using the gamma reference voltage, and output the data voltage Vd to the data line. The data driver may receive the analog driving voltage AVDD having the second voltage level LV2 during the holding frame HOLDING FRAME. The data driver may not operate during the holding frame HOLDING FRAME based on the analog driving voltage AVDD having the second voltage level LV2. Therefore, in the display device according to embodiments of the present invention, the data driver may not operate during the holding frame HOLDING FRAME in the low-frequency driving mode, so that the power consumption may be reduced.

[0080] FIG. 6 is a circuit diagram illustrating another example of a pixel included in the display device of FIG. 1, and FIG. 7 is a timing diagram illustrating an example of signals applied to the pixel of FIG. 6 in a low-frequency driving mode.

[0081] Referring to FIG. 6, according to embodiments of the present invention, each of pixels PX may include first to eighth switching elements T1, T2, T3, T4, T5, T6, T7, and T8, a storage capacitor CST, and an organic light emitting diode OLED. The pixel PX of FIG. 6 according to embodiments of the present invention may have substantially the same structure as the pixel PX of FIG. 2 except that the pixel PX of FIG. 6 includes the eighth switching element T8.

[0082] The eighth switching element T8 may include a gate electrode to which a sustaining voltage enable signal Vsus_en is applied, a first electrode to which a sustaining voltage Vsus is applied, and a second electrode connected to the first electrode of the second switching element T2. For example, the eighth switching element T8 may be a poly-silicon transistor. The eighth switching element T8 may be a P-type thin film transistor. The first electrode of the eighth switching element T8 may be a source electrode, and the second electrode of the eighth switching element T8 may be a drain electrode.

[0083] Referring to FIG. 7, in the low-frequency driving mode, the driving controller of the display device may provide the analog driving voltage AVDD to the data driver during the writing frame WRITING FRAME, and provide the sustaining voltage Vsus to the pixel PX during the holding frame HOLDING FRAME. For example, the driving controller may include a voltage generator configured to generate the analog driving voltage AVDD and the sustaining voltage Vsus.

[0084] The driving controller may generate a voltage having a first voltage level and provide the generated voltage to the data driver as the analog driving voltage AVDD during the writing frame WRITING FRAME, and may generate a voltage having a voltage level equal to or different from the first voltage level and provide the generated voltage to the pixel as the sustaining voltage Vsus during the holding frame HOLDING FRAME. Since the voltage is not supplied to the data driver during the holding frame HOLDING FRAME, the data driver may not operate.

[0085] In addition, the driving controller may provide the sustaining voltage enable signal Vsus_en to the pixel. Referring to FIGS. 6 and 7, the sustaining voltage enable signal Vsus_en may be activated during the holding frame HOLDING FRAME and supplied to the gate electrode of the eighth switching element T8. The eighth switching element T8 may be turned on in response to the sustaining voltage enable signal Vsus_en during the holding frame HOLDING FRAME. Therefore, the sustaining voltage Vsus may be supplied to the first electrode of the second switching element T2 through the eighth switching element T8 during the holding frame HOLDING FRAME.

[0086] In the pixel of FIG. 6, a leakage current may be generated through the second switching element T2 connected to the first switching element T1 during the holding frame HOLDING FRAME. When the voltage of the first electrode of the first switching element T1 is changed by the leakage current generated due to the second switching element T2, the driving current may be changed, so that luminance of the pixel PX may be changed. Since the pixel PX of the display device according to embodiments of the present invention supplies the sustaining voltage Vsus to the first electrode of the second switching element T2 through the eighth switching element T8 during the holding frame HOLDING FRAME, the leakage current may be prevented from being generated due to the second switching element T2. Therefore, the pixel PX may emit light with constant luminance.

[0087] As described above, since the driving controller of the display device according to embodiments of the present invention provides the analog driving voltage AVDD to the data driver during the writing frame WRITING FRAME, and does not provide the analog driving voltage AVDD to the data driver during the holding frame HOLDING FRAME, the data driver may be prevented from operating during the holding frame HOLDING FRAME. Therefore, the power consumption of the display device may be reduced during the holding frame HOLDING FRAME. In addition, since the driving controller of the display device according to embodiments of the present invention provides the sustaining voltage Vsus to the pixel PX during the holding frame HOLDING FRAME, the driving current may be prevented from being changed due to the leakage current.

[0088] FIG. 8 is a block diagram illustrating an electronic device including the display device of FIG. 1, and FIG. 9 is a diagram illustrating an example in which the electronic device of FIG. 8 is implemented as a smart phone.

[0089] Referring to FIGS. 8 and 9, the electronic device 200 may include a processor 210, a memory device 220, a storage device 230, an input / output (I / O) device 240, a power supply 250, and a display device 260. Here, the display device 260 may be the display device 100 of FIG. 1. In addition, the electronic device 200 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like. In an embodiment, as illustrated in FIG. 9, the electronic device 200 may be implemented as a smart phone 300. However, the electronic device 200 is not limited thereto.

[0090] The processor 210 may perform various computing functions. The processor 210 may be a micro-processor, a central processing unit (CPU), and the like. The processor 210 may be coupled to other components via an address bus, a control bus, a data bus, and the like. Further, the processor 210 may be coupled to an extended bus such as a peripheral component interconnection (PCI) bus. The memory device 220 may store data for operations of the electronic device 200. For example, the memory device 220 may include a non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and the like and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, and the like. The storage device 230 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, and the like.

[0091] The I / O device 240 may include an input device such as a keyboard, a keypad, a mouse device, a touch-pad, a touch-screen, and the like and an output device such as a printer, a speaker, and the like. In some embodiments, the display device 260 may be included in the I / O device 240. The power supply 250 may provide power for operations of the electronic device 200. The display device 260 may be coupled to other components via the buses or other communication links.[ABILITY OF INDUSTRIAL UTILITY]

[0092] The present invention may be applied to an electronic device including a display device. For example, the present invention may be applied to a television, a computer monitor, a laptop, a digital camera, a smart phone, a cellular phone, a smart pad, a tablet PC, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a car navigation system, a video phone, a head mounted display (HMD) device, and the like.

Claims

1. A display device (100, 260) comprising: a display panel (110) including a pixel (PX) including switching elements of a first type and switching elements of a second type, wherein the switching elements of the first type are poly-silicon thin film transistors and the switching elements of the second type are oxide thin film transistors; a gate driver (120) configured to generate a gate signal (GWP, GWN, GI, GB) based on a gate clock signal (CLK1, CLK2) and to provide the gate signal GWP, GWN, GI, GB) to the display panel (110); a data driver (130) configured to provide a data voltage (Vd) to the display panel (110); an emission controller (140) configured to provide an emission control signal (EM) to the display panel (110); and a driving controller (150) configured to generate control signals (CLT1, CLT2, CLT3) for controlling the gate driver (120), the data driver (130), and the emission controller (140), wherein, in a low-frequency driving mode, the driving controller (150) is configured to provide the gate clock signal (CLK1, CLK2) that swings between a high level and a low level to the gate driver (120) during a writing frame (WRITING FRAME) for writing data to the pixel (PX) and to provide the gate clock signal (CLK1, CLK2) having a direct current voltage to the gate driver (120) during a holding frame (HOLDING FRAME) for holding the data written in the pixel (PX); wherein the driving controller comprises a voltage generator configured to generate: - an analog driving voltage (AVDD) for operating the data driver to generate a gamma reference based on the analog driving voltage (AVDD), and - a sustaining voltage (Vsus) for constantly maintaining a driving current of the pixel, and wherein, in the low-frequency driving mode, the driving controller is configured to provide: - the analog driving voltage (AVDD) having a first voltage level to the data driver (130) during the writing frame; - the analog driving voltage (AVDD) having a second voltage level that is lower than the first voltage level to the data driver (130) during the holding frame (HOLDING FRAME); and - the sustaining voltage (Vsus) having the first voltage level to the pixel during the holding frame; wherein the pixel includes: - a first switching element (T1) including a gate electrode connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3); - a second switching element (T2) including a gate electrode to which a first data write gate signal (GWP) is applied, a first electrode to which the data voltage (Vd) is applied, and a second electrode connected to the second node (N2); - a third switching element (T3) including a gate electrode to which a second data write gate signal (GWN) is applied, a first electrode connected to the first node (N1), and a second electrode connected to the third node (N3); - a fourth switching element (T4) including a gate electrode to which a data initialization gate signal (GI) is applied, a first electrode to which an initialization voltage (VI) is applied, and a second electrode connected to the first node (N1); - a fifth switching element (T5) including a gate electrode to which the emission control signal (EM) is applied, a first electrode to which a high power supply voltage (ELVDD) is applied, and a second electrode connected to the second node (N2); - a sixth switching element (T6) including a gate electrode to which the emission control signal (EM) is applied, a first electrode connected to the third node (N3), and a second electrode connected to an anode electrode of an organic light emitting diode (OLED); - a seventh switching element (T7) including a gate electrode to which an organic light emitting diode initialization gate signal (GB) is applied, a first electrode to which the initialization voltage (VI) is applied, and a second electrode connected to the anode electrode of the organic light emitting diode (OLED); - a storage capacitor (CST) including a first electrode to which the high power supply voltage (ELVDD) is applied and a second electrode connected to the first node (N1); - the organic light emitting diode (OLED) including the anode electrode and a cathode electrode to which a low power supply voltage (ELVSS) is applied; and - an eighth switching element (T8) including a gate electrode to which a sustaining voltage enable signal (Vsus_en) is applied, a first electrode to which the sustaining voltage is applied, and a second electrode connected to the first electrode of the second switching element (T2); the first switching element, the second switching element, the fifth switching element, the sixth switching element and the eighth switching elements are poly-silicon thin film transistors; the third switching element, the fourth switching element, and the seventh switching element are oxide thin film transistors, during the holding frame (HOLDING FRAME), the display device (100, 260) is configured to turn the eighth switching element (T8) on, to transmit the sustaining voltage (Vsus) to the first electrode of the second switching element (T2) through the eighth switching element (T8).

2. The display device (100, 260) of claim 1, wherein, in the low-frequency driving mode, the gate clock signal (CLK1, CLK2) swings between the high level and the low level during the writing frame (WRITING FRAME) and is maintained at the low level during the holding frame (HOLDING FRAME).

3. The display device (100, 260) of claim 1 or claim 2, wherein, in the low-frequency driving mode, the gate clock signal (CLK1, CLK2) swings between the high level and the low level during the writing frame (WRITING FRAME) and is maintained at the high level during the holding frame (HOLDING FRAME).

4. The display device of any preceding claim, wherein the driving controller (150) includes a gate controller configured to generate the gate clock signal (CLK1, CLK2).

5. The display device (100, 260) of any preceding claim, wherein the switching element of the first type is a P-type transistor, and wherein the switching element of the second type is an N-type transistor.

6. The display device (100, 260) of any preceding claim, wherein, in the low-frequency driving mode, the second switching element (T2), the fifth switching element (T5), and the sixth switching element (T6) are driven at a first driving frequency, and the third switching element (T3) is driven at a second driving frequency that is lower than the first driving frequency.