PROVIDING A DIGITAL RAMP SIGNAL

Description

[0001] This patent application claims priority from French patent applications FR2301359 and FR2300946. Technical field

[0002] This description relates generally to circuits for providing digital ramp signals. Prior art

[0003] For certain applications, we want to obtain an electronic circuit capable of providing a digital signal corresponding to a succession of ramps.

[0004] US 2009 / 231479 A1 discloses a DAC that outputs ramp signals corresponding to the pixels of an image sensor. An example application relates to the control of quantum bit storage cells by an analog control signal obtained by digital-to-analog conversion of the digital signal. For such applications, it may be desirable to be able to modify the succession of ramps of the digital signal in a simple manner. It may further be desirable for the digital signal to be supplied at high frequency, i.e. with fine time precision.

[0005] However, it may be desirable to use an electronic circuit clocked by a clock signal at a frequency lower than the desired granularity of the digital signal. Summary of the invention

[0006] One embodiment overcomes all or part of the drawbacks of known ramp digital signal supply circuits.

[0007] An embodiment provides an electronic circuit for providing a digital signal comprising a succession of ramps, the electronic circuit being clocked by a clock signal, the electronic circuit being configured to provide a number Nout of digital values ​​of the digital signal at each cycle of the clock signal, Nout being strictly greater than 1, the electronic circuit comprising a first memory in which are stored, for each ramp, first data comprising a start value of the ramp, the slope of the ramp, and a remaining duration of the ramp in the last cycle of the clock signal in which the ramp extends, and a second memory in which are stored second data relating to the numbers of cycles of the clock signal over which some of the ramps extend,and a first circuit configured to read from the first memory the first data relating to several successive ramps and from the second memory the second data associated with said several successive ramps, and to provide said digital values ​​from the first and second data read.,

[0008] According to one embodiment, the first circuit is configured to read in parallel in the first memory the first data relating to Nout successive ramps, to read in the second memory the second data associated with said Nout successive ramps, and to provide, at a cycle of the clock signal, Nout digital values ​​of the digital signal forming part of one to Nout ramps among said Nout ramps

[0009] According to one embodiment, the first circuit comprises Nout interpolation circuits in parallel, each interpolation circuit being configured to calculate, at one cycle of the clock signal, one of the Nout digital values ​​of the digital signal forming part of one to Nout ramps among said successive Nout ramps.

[0010] According to one embodiment, the first data stored in the first memory comprise, for each ramp, coefficients of a polynomial of degree greater than or equal to 2, the slope of the ramp being the coefficient of degree 1 of the polynomial, the first circuit being configured to provide said digital ramp values ​​corresponding to polynomial functions.

[0011] According to one embodiment, Nout is a power of two, in particular 2, 4, 8, or 16.

[0012] According to one embodiment, the first circuit is configured to read, in the first memory, simultaneously the first data of successive Nout ramps.

[0013] According to one embodiment, the first circuit is configured to read, in the second memory, simultaneously the second data of successive Nout ramps.

[0014] According to one embodiment, the first circuit comprises a first module configured to provide, at each cycle of the clock signal, sets of data, each set comprising a ramp start value, the slope of the ramp, and a delay, the delay varying from one set to another, and a second module configured, for each set, to provide a digital value of the digital signal equal to the sum of the ramp start value and the product of the slope of the ramp and the delay.

[0015] According to one embodiment, the first memory comprises Nout memory blocks in parallel.

[0016] According to one embodiment, the electronic circuit comprises a third memory in which are stored, for each ramp of the succession of ramps, third data comprising the start value of the ramp, the end value of the ramp, and the duration of the ramp, the electronic circuit further comprising a second circuit configured to provide, from the third data, the first data and the second data, and to write the first data in the first memory and to write the second data in the second memory.

[0017] According to one embodiment, the second circuit is configured to process the third data in batches of successive Nout ramps.

[0018] According to one embodiment, the second circuit comprises a third module configured to determine, for each ramp, the slope of the ramp, and a fourth module configured to determine the total duration elapsed from the start of the succession of ramps to the end of the ramp and the number of cycles of the clock signal contained in said total duration.

[0019] An embodiment also provides a system comprising the electronic circuit as defined above, a digital-to-analog converter configured to convert the digital signal into an analog signal, and quantum bit storage cells receiving the analog signal.

[0020] An embodiment also provides a method for providing a digital signal comprising a succession of ramps comprising the provision, at each cycle of a clock signal, of a number Nout of digital values ​​of the digital signal, Nout being strictly greater than 1, the method comprising the provision of a first memory in which are stored, for each ramp, first data comprising a start value of the ramp, the slope of the ramp, and a remaining duration of the ramp in the last cycle of the clock signal in which the ramp extends, the provision of a second memory in which are stored second data relating to the numbers of cycles of the clock signal over which some of the ramps extend, the reading, in the first memory, of the first data relating to several successive ramps and, in the second memory, of the second data associated with said several successive ramps,and providing said digital values ​​from the first and second data read., Brief description of the drawings

[0021] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there Figure 1 represents a quantum bit control and measurement system; Figure 2 , there Figure 3 , there Figure 4 , there Figure 5 , and the Figure 6 represent examples of waveforms; the Figure 7 represents the waveform of the Figure 6 on which the waveform data parameters have been indicated; figure 8 represents the waveform of the Figure 7 on which the waveform control parameters have been indicated; figure 9schematically represents an embodiment of an electronic circuit configured to execute a waveform; the Figure 10 represents a more detailed embodiment of the electronic circuit of the figure 9 ; there Figure 11 illustrates an embodiment of a finite automaton of the electronic circuit of the Figure 10 ; there Figure 12 represents an embodiment of a division module of the electronic circuit of the Figure 10 ; there figure 13 illustrates an embodiment of a method for managing a memory of the electronic circuit of the Figure 10 ; there Figure 14 represents an embodiment of a module for calculating the duration of the electronic circuit of the Figure 10 ; there Figure 15 illustrates an embodiment of another finite automaton of the electronic circuit of the Figure 10 ; there figure 16 illustrates an embodiment of a method of operating the finite state machine of the Figure 15 ; there Figure 17represents an embodiment of a module for interpreting the electronic circuit of the Figure 10 ; and the figure 18 illustrates an embodiment of a method for managing a memory of the electronic circuit of the Figure 10 ; there figure 19 illustrates another embodiment of a method for managing a memory of the electronic circuit of the Figure 10 ; there figure 20 schematically represents another embodiment of an electronic circuit configured to execute a waveform; the figure 21 represents an embodiment of a system for providing a digital signal; and the figure 22 , there figure 23 , and the figure 24 represent examples of waveforms obtained by testing. Description of the embodiments

[0022] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed.

[0023] Unless otherwise specified, the expressions "approximately", "approximately", and "substantially" mean within 10%, preferably within 5%.

[0024] In the remainder of the description, a ramp is a signal corresponding to a polynomial function starting from a starting value Start_val to arrive at an end value End_val in a duration Duration, and a waveform is a set of successive ramps. In particular, the ramp is called a linear ramp when the signal starting from the starting value Start_val to arrive at the end value End_val is linear, and the ramp is called a non-linear ramp when the signal starting from the starting value Start_val to arrive at the end value End_val is not linear.

[0025] An electronic circuit is said to execute or play a waveform when it provides a succession of digital values ​​of a digital signal which, after a digital-to-analog conversion, leads to an analog signal whose graphical representation corresponds to the waveform.

[0026] There Figure 1represents an embodiment of a system 1 comprising: quantum bit storage cells 2 (Qubits); a cold enclosure 3 containing the quantum bit storage cells 2; a processing device 4 configured to provide a digital signal Sn; a digital-to-analog converter 6 (DAC) which receives the digital signal Sn and provides an analog signal Sa for exciting the quantum bit storage cells 2; and an analog-to-digital converter 7 (ADC) which receives an analog measurement signal Sma from the quantum bit storage cells 2 and converts it into a digital measurement signal Sna transmitted to the processing device 4.

[0027] The processing device 4 comprises an electronic circuit 10 configured to execute a waveform and provide the digital signal Sn. For example, the electronic circuit 10 corresponds to a programmable logic circuit, in particular a field-programmable gate array (FPGA), or to an application-specific integrated circuit (ASIC).

[0028] The electronic circuit 10 configured to execute a waveform is clocked by a clock signal having a frequency fhard and a period Thard. According to one embodiment, the electronic circuit 10 provides, at each clock cycle of duration Thard, called a hardware cycle hereinafter, a number Nout of successive digital values ​​of the digital signal Sn corresponding to the waveform. Nout is an integer greater than or equal to 1, and is called the oversampling factor. According to one embodiment, Nout is a power of 2. The frequency equal to the product of the frequency fhard and the oversampling factor Nout is called fdac, and the duration equal to the ratio between the period Thard and the oversampling factor Nout is called Tdac. In the embodiment illustrated in Figure 1, the digital values ​​of the digital signal Sn corresponding to the waveform are supplied to the digital-to-analog converter 6 which is clocked by a clock signal having the frequency fdac and the period Tdac.

[0029] Each ramp in the waveform is defined by its start value Start_val, its end value End_val, and its duration Duration which is expressed in number of periods Tdac. The set of data Start_val, End_val, and Tdac of the ramps in the waveform are called raw parameters of the waveform. Each ramp in the waveform can extend over less than one hardware cycle, over more than one hardware cycle, start in one hardware cycle and end in another hardware cycle, etc. This means, among other things, that for each ramp, the start of the ramp can coincide with the start of a hardware cycle or be within a hardware cycle and that the end of the ramp can coincide with the end of a hardware cycle or be within a hardware cycle. In addition, the hardware cycle of the start of the ramp can be the same as the hardware cycle of the end of the ramp or can be different from the hardware cycle of the end of the ramp.

[0030] Examples of waveforms will now be described for linear ramps. Figure 2 , there Figure 3 , there Figure 4 , there Figure 5 , and the Figure 6 represent examples of waveforms, for example curves of the evolution of the amplitude Amp of a voltage as a function of time t. On the Figure 2 , there Figure 3 , there Figure 4 , the waveform comprises three successive ramps R0, R1, and R2, and, on the Figure 6 , the waveform comprises four successive ramps R0, R1, R2, and R3. On the figures 2 to 6 , the hardware operating cycles of the electronic circuit 10 are shown in dotted lines.

[0031] The raw parameters of the waveforms represented on the figures 2 to 6 are grouped respectively in tables Table 1 to Table 5 below. For the figures 2 to 5 , Nout is equal to 16. For the Figure 6 , Nout is equal to 4. The raw waveform parameters have been added on the Figure 6. [Table 1] Raw parameters Ramp Start_val End_val Duration R0 -4500 4500 16 R1 4500 -4500 16 R2 -4600 -4600 8 [Table 2] Raw parameters Ramp Start_val End_val Duration R0 -4500 4500 1 R1 4500 -4500 1 R2 -4600 -4600 24 [Table 3] Raw parameters Ramp Start_val End_val Duration R0 -4500 4500 8 R1 4500 -4500 3 R2 -4600 -4600 7 [Table 4] Raw parameters Ramp Start_val End_val Duration R0 -4500 4500 18 R1 4500 -4500 15 R2 -4600 -4600 7 [Table 5] Raw parameters Ramp Start_val End_val Duration R0 0 4192 11 R1 4192 1290 2 R2 1290 2902 1 R3 2902 0 7

[0032] We note that for the waveforms represented on the figures 3, 4, 5 , And 6 , some ramps do not start and / or end at the end of a hardware cycle. Therefore, an electronic circuit clocked by a fhard frequency signal and implementing only an interpolation algorithm cannot execute these waveforms.

[0033] According to one embodiment, two sets of data are determined from the raw parameters of the waveform, the first set of data is called data parameters of the waveform and the second set of data is called control parameters of the waveform.

[0034] The waveform data parameters include, for each ramp in the waveform, the starting value Start_val of the ramp, the slope of the ramp, called "Coeff", and the number of periods Tdac, called Rest, in the last hardware cycle over which the ramp extends since the start of this last hardware cycle. The waveform data parameters represented in Figure 6 are grouped in Table 6 below. [Table 6] Data settings Ramp Start_val Coefficient Rest R0 0 381,09 3 R1 4192 -1451 1 R2 1290 1612 2 R3 2902 -414.57 1

[0035] There Figure 7 represents the waveform of the Figure 6 on which the waveform data parameters have been indicated.

[0036] The waveform control parameters allow ramps to be grouped into successive ramp groups. When a ramp ends in the middle of a hardware cycle, it is necessary to be able to complete the current hardware cycle with a certain number of ramps. These ramps represent a group. This group will be played for a certain number of hardware cycles, which corresponds to a Cycles control parameter. When it ends, the system must obtain information on where the next ramp group to be played begins via the Index control parameter. The waveform control parameters represented in Figure 6 are grouped in Table 7 below. [Table 7] Control parameters Cycles Index 2 1 0 2 1 -

[0037] There figure 8 represents the waveform of the Figure 6 on which the waveform control parameters are illustrated.

[0038] An embodiment of an electronic circuit configured to execute a waveform from the raw parameters of the waveform will now be described in the case of a waveform comprising linear ramps.

[0039] There figure 9 schematically represents an embodiment of the electronic circuit 10 configured to execute a waveform from the raw parameters of the waveform.

[0040] The electronic circuit 10 comprises: a memory 12 (Raw memory) in which the raw parameters of the waveform Start_val, End_val, Duration are stored; a decoding circuit 20 (Decode) configured to provide the data parameters Start_val, Coeff, Rest and the control parameters Cycles, Index of the waveform from the raw parameters of the waveform stored in the memory 12; a memory 30 (Data memory), also called data memory 30, in which the data parameters Start_val, Coeff, Rest of the waveform provided by the decoding circuit 20 are stored; a memory 32 (Control memory), also called control memory 32, in which the control parameters Cycles, Index of the waveform are stored provided by the decoding circuit 20;and an execution circuit 40 (Execute) configured to determine the successive digital values ​​of the digital signal Sn corresponding to the waveform from the data parameters Start_val, Coeff, Rest stored in the data memory 30 and the control parameters Cycles, Index stored in the control memory 32. ;

[0041] According to one embodiment, the electronic circuit 10 further comprises a memory 34 (Parameter Memory) in which are stored, for each waveform, waveform configuration parameters Repeat, Taille_waveform and the reading start addresses Address_raw in the memory 12 and the reading start addresses Address_update in the memories 30 and 32.

[0042] The decoding circuit 20 comprises: a division module 22 (Division) configured to receive the raw parameters Start_val, End_val, Duration stored in the memory 12 and provide the data parameters Start_val, and Coeff; a duration calculation module 24 (Total duration) configured to receive the raw parameters Duration stored in the memory 12, determine the total duration of each ramp of the waveform and provide the data parameter Rest and the control parameters Cycles, Index; a merger module 26 (Merger) configured to receive the control parameters Cycles, Index determined by the duration calculation module 24, and provide the modified control parameters Cycles, Index; and a reorganization module 28 (Shuffler) configured to receive the control parameters Cycles, Index determined by merger module 26 and provide the modified control parameters Cycles, Index.

[0043] The execution circuit 40 includes: an interpretation module 42 (data interpreter) receiving the data parameters Start_val, Coeff, and Rest of the waveform to be executed stored in the data memory 30, and providing data Value, Coeff, Offset, and Dur; a search module 44 (Fetch) receiving the control parameters Cycles and Index stored in the control memory 32 and controlling the operation of the interpretation module 42; and an interpolation module 46 (interpolator) configured to receive the data Value, Coeff, Offset, and Dur provided by the interpretation module 42 and provide the digital values ​​of the digital signal Sn corresponding to the waveform.

[0044] An embodiment of a method for providing the data parameters Start_val, Coeff, and Rest and the control parameters Cycles and Index of a waveform by the decoding circuit 20 from the raw parameters Start_val, End_val, Duration of the waveform will now be described. According to one embodiment, the decoding circuit 20 processes the raw parameters stored in the memory 12 in batches and simultaneously reads the raw parameters relating to successive ramps of the waveform.

[0045] For each ramp of the successive Nout ramps of the waveform, the division module 22 determines the data parameter Coeff of the ramp by determining the difference between the end value End_val and the start value Start_val of the ramp and dividing this difference by the duration Duration of the ramp. The data parameters Coeff of the successive Nout ramps of the waveform are thus obtained.

[0046] For each ramp of the successive Nout ramps of the waveform, the duration calculation module 24 determines the Total data and the Rest data parameter. The Total data is equal to the number of hardware cycles fully elapsed from the start of the first ramp of the batch of Nout ramps to the end of the ramp in question. The Rest data parameter is equal to 0 in the case where the ramp in question ends at the same time as a hardware cycle and is equal to the number of periods Tdac in the last hardware cycle over which the ramp in question extends from the start of this last cycle in the case where the ramp in question does not end at the same time as a hardware cycle. In the case of the waveform represented on the Figure 6 , the duration calculation module 24 provides the data grouped in table Table 8 below: [Table 8] Duration calculation module Ramp Total Rest R0 2 3 R1 3 1 R2 3 2 R3 5 1

[0047] According to one embodiment, the determination of the control parameters Cycles and Index of the successive Nout ramps of the waveform is carried out by the fusion module 26 according to a method comprising five steps.

[0048] According to one embodiment, for each ramp in the batch of successive Nout ramps of the waveform being processed, the first step is to calculate the output hardware cycle of the ramp, i.e. the last hardware cycle where it is played and deduce the number of cycles to be played since the last ramp. This corresponds to the quotient of the total duration Total with the oversampling Nout minus the output cycle of the previous ramp. There are two exceptions to take into account, this comes from the fact that a ramp aligned with the end of a hardware cycle at its last played cycle which overlaps the next one. When the ramp ends up aligned with the end of a hardware cycle (i.e. when the data parameter Rest is equal to 0) and the last ramp was not, it is necessary to remove one hardware cycle to be played. When the previous ramp ended up aligned with a hardware cycle but this one is not, it must be played one more cycle.

[0049] According to one embodiment, in the first step, for each ramp of the successive Nout ramps of the waveform, the fusion module 26 therefore determines the control parameter Cycles of the ramp in the following manner: in the case where the Ramp Rest data parameter is equal to 0 and the Rest data parameter of the previous ramp is not equal to 0, the Ramp Cycles control parameter is equal to the difference between the Ramp Total data and the Total data of the previous ramp, all reduced by 1; in the case where the Ramp Rest data parameter is not equal to 0 and the Rest data parameter of the previous ramp is equal to 0, the Ramp Cycles control parameter is equal to the difference between the Ramp Total data and the Total data of the previous ramp, all increased by 1;and in the case where the Ramp Rest data parameter is equal to zero and the Previous Ramp Rest data parameter is equal to 0 or in the case where the Ramp Rest data parameter is different from zero and the Previous Ramp Rest data parameter is different from 0, the Ramp Cycles control parameter is equal to the difference between the Ramp Total data and the Previous Ramp Total data. ;

[0050] When processing a batch of Nout ramps, the merge module 26 stores in memory the Rest data parameter of the last ramp of the previous batch so that it can determine the Cycles control parameter of the first ramp of the new batch being processed. The first ramp of the waveform is processed like the others, only when processing the first ramp, it is considered that there is a fictitious "previous" ramp whose Rest data parameter is equal to 0.

[0051] In the case of the waveform shown in the Figure 6 , the fusion module 26 provides, at the first stage, the data grouped in table Table 9 below: [Table 9] Fusion - Step 1 Ramps Cycles R0 3 R1 1 R2 0 R3 2

[0052] In a second step, the fusion module 26 determines a Block data item for each ramp in the batch of Nout ramps. For each ramp, in the case where the Cycles control parameter of the ramp is equal to 0 and the Rest data parameter of the previous ramp is different from 0, the Block data item of the ramp is equal to 0, otherwise the Block data item is equal to 1. For the processing of the first ramp of the waveform, it is considered that there is a fictitious "previous" ramp whose Rest data parameter is equal to 0 and the Cycles control parameter is equal to 0. The second step therefore consists of indicating the beginnings of groups of ramps. If the Cycles control parameter of the ramp is equal to 0, the ramp is not the beginning of a group of ramps, otherwise it is. There is one exception: if the previous ramp ends up aligned with the end of a hardware cycle, the next ramp is necessarily in a new ramp group even if the ramp's Cycle data is 0.In the case of the waveform shown in the . Figure 6 , the fusion module 26 determines in the second step the data grouped in the table Table 10 below: [Table 10] Fusion - Step 2 Ramps Cycles Block R0 3 1 R1 1 1 R2 0 0 R3 2 1

[0053] In a third step, the fusion module 26 determines, for each ramp of the batch of Nout ramps, a Blocksum data which is equal to the sum of the Block data of all the ramps of the batch of Nout ramps since the start of the batch including the ramp considered. In the case of the waveform represented on the Figure 6 , the fusion module 26 determines in the third step the data grouped in the table Table 11 below: [Table 11] Fusion - Step 3 Ramps Cycles Block Blocksum R0 3 1 1 R1 1 1 2 R2 0 0 2 R3 2 1 3

[0054] In a fourth step, the fusion module 26 determines values ​​of the Index control parameter. For this purpose, an index is associated with each ramp of the Nout ramps processed by the fusion module 26, the first ramp of the Nout ramps having the index 0 and the last ramp of the Nout ramps having the index Nout-1. Each possible value of the Blocksum data is examined. The Blocksum data can vary between 1 and Nout. In the case where the Blocksum data of no ramp in the batch of Nout ramps has the value considered, nothing is done. In the case where the Blocksum data of a single ramp in the batch of Nout ramps has the Blocksum data value considered, the Index control parameter, with the index equal to the Blocksum data value considered reduced by one unit, is equal to the index of the ramp considered.In the case where the Blocksum data of at least two ramps has the considered Blocksum data value, the Index control parameter, at the index equal to the considered Blocksum data value reduced by one, is equal to the lowest index of these ramps. The fourth step therefore aims to determine the size of the ramp groups and their position in the set of Nout ramps processed by the fusion module 26. In the case of the waveform represented on the . Figure 6, the merge module 26 determines in the fourth step the data grouped in the table Table 12 below. In this example, Nout being equal to 4, the possible values ​​of the Blocksum data vary between 1 and 4. We look for the value 4 in the Blocksum column: it is not there. We then look for the value 3 in the Blocksum column, we find it for the ramp R3. The Index control parameter at position 2 is therefore equal to 3. We then look for the value 2 in the Blocksum column that we find for the ramps R1 and R2, we therefore retain the ramp R1. The Index control parameter at position 1 is therefore equal to 1. We then look for the value 1 in the Blocksum column that we find for the ramp R0. The Index control parameter at position 1 is therefore equal to 0. [Table 12] Fusion - Step 4 Ramps Cycles block Blocksum Index R0 3 1 1 0 R1 1 1 2 1 R2 0 0 2 3 R3 2 1 3 0

[0055] The merging module 26 determines, in a fifth step, the final version of the Cycles and Index control parameters of the batch of Nout ramps of the waveform for storage in the control memory 32. For each index of the Index control parameter obtained in the fourth step, the Cycles control parameter at the index considered is equal to the Cycles control parameter obtained in the fourth step, reduced by one unit, at the index equal to the Index control parameter obtained in the fourth step at the index considered. Furthermore, the Index control parameter at the index considered is equal to the difference between the Index control parameter obtained in the fourth step, at the index considered increased by one unit, and the Index control parameter obtained in the fourth step at the index considered. The final version of the Cycles and Index control parameters of the waveform represented in Figure 6 are grouped in Table 7 above.

[0056] The execution of the waveform is carried out by the execution circuit 40. More precisely, the interpretation module 42 reads the data parameters of the waveform in the data memory 30 and the search module 44 reads the control parameters the data parameters of the waveform in the control memory 32. At each hardware cycle, the interpretation module 42 transmits to the interpolation module 46 Nout sets of values, each set comprising a Value data, a Dur data, an Offset data, and a Coeff data.

[0057] At each hardware cycle, the interpolation module 46 determines Nout digital values ​​Point of the digital signal Sn from the Nout data sets received. Each digital value Point is obtained according to the following relationship: Point = Value + Dur + Offset ∗ Coeff

[0058] The interpolation module 46 comprises Nout interpolation sub-modules in parallel, each interpolation sub-module being configured to calculate one of the Nout digital values ​​Point of the digital signal Sn from one of the sets of values ​​comprising a Value data, a Dur data, an Offset data, and a Coeff data.

[0059] Execution of the waveform shown in the Figure 6 will now be described. during the execution of this waveform by the execution circuit 40, the interpretation module 42 reads from the data memory 30 continuously the data parameters of Nout successive ramps of the waveform. In the case of the waveform shown in the Figure 6, the execution circuit 40 therefore reads the data parameters from the table Table 6. In the first hardware cycle, the execution circuit 40 processes the data parameters of the first ramp which are stored in a data register indicated in the table Table 13 below. [Table 13] Data Log - Cycle 1 Value Coefficient Offset Rest 0 381,09 0 3

[0060] The data parameters of the following Nout ramps are read in a reading window shown in Table 14 below. [Table 14] Reading Window - Cycle 1 Start_val Coefficient Rest 4192 -1451 1 1290 1612 2 2902 -414,57 1 x x x

[0061] The waveform control parameters of the Figure 6read by the search module 44 are indicated in Table 15 below. In the first hardware cycle, the search module 44 stores in memory a Current_cycle data equal to the value of the Cycles control parameter in the first row of Table 7 and a Current_Index data equal to the value of the Index control parameter in the first row of Table 7. [Table 15] Research Module - Cycle 1 Current_cycle Current_Index 2 1

[0062] Since Nout is equal to 4, the interpretation module 42 provides the interpolation module 46 with four sets of values, each comprising the Value data equal to 0, the Coeff data equal to 381.09, the Offset data equal to 0, and the Dur data respectively equal to 0, Tdac, 2*Tdac, and 3*Tdac.

[0063] In the second hardware cycle, the interpretation module 42 adds the value Nout*Coeff to the data Value used in the first hardware cycle. This does not require multiplication because Nout is a power of two. The interpretation module 42 therefore updates the data Value as shown in Table 16 below. The window for reading Nout successive ramps by the interpretation module 42 does not move and is shown in Table 17 below. In addition, the search module 44 updates the control parameter Current_cycle as shown in Table 18 below. [Table 16] Data Register - Cycle 2 Value Coefficient Offset Rest 1524,36 381,09 0 3 [Table 17] Reading Window - Cycle 2 Start_val Coefficient Rest 4192 -1451 1 1290 1612 2 2902 -414,57 1 x x x [Table 18] Research Module - Cycle 2 Current_cycle Current _Index 1 1

[0064] The interpretation module 42 provides the interpolation module 46 with four sets of values, each comprising the Value data equal to 1524.36, the Coeff data equal to 381.09, the Offset data equal to 0, and the Dur data respectively equal to 0, Tdac, 2*Tadc, and 3*Tdac.

[0065] In the third hardware cycle, the interpretation module 42 adds the value Nout*Coeff to the data Value used in the second hardware cycle. The interpretation module 42 therefore updates the data Value as shown in Table 19 below. The window for reading Nout successive ramps by the interpretation module 42 does not move and is shown in Table 20 below. In addition, the search module 44 updates the data Current_cycle as shown in Table 21 below. [Table 19] Data Log - Cycle 3 Value Coefficient Offset Rest 3048, 72 381,09 0 3 [Table 20] Reading Window - Cycle 3 Start_val Coefficient Rest 4192 -1451 1 1290 1612 2 2902 -414,57 1 x x x [Table 21] Research Module - Cycle 3 Current_cycle Current _Index 0 1

[0066] Since the current Cycles data is equal to 0 and the Rest data is equal to 3, the interpretation module 42 provides the interpolation module 46 with four sets of values, including three sets of values ​​each comprising the Value data equal to 3048.72, the Coeff data equal to 381.09, the Offset data equal to 0, and the Dur data respectively equal to 0, Tdac, and 2*Tadc, and a fourth set of values ​​comprising the Value data equal to 4192, the Coeff data equal to -1451, the Offset data equal to 0, and the Dur data equal to 0. The fourth set of values ​​is determined with the data present in the first row of the table Table 20 designated by the value of the index Current Index of the table Table 21.

[0067] In the fourth hardware cycle, the interpretation module 42 updates the Value data, the Coeff data, the Offset data, and the Rest data as indicated in Table 22 below. The window for reading successive Nout ramps by the interpretation module 42 is shifted, as shown in Table 23 below. In addition, the search module 44 updates the Current_cycle and Current _Index data as indicated in Table 24 below, the Current_cycle data being equal to the value of the Cycles control parameter in the second row of Table 7 and the Current_Index data being equal to the value of the Index control parameter in the second row of Table 7. [Table 22] Data Log - Cycle 4 Value Coefficient Offset Rest 4192 381, 09 1 1 [Table 23] Reading Window - Cycle 4 Start_val Coefficient Rest 1290 1612 2 2902 -414,57 1 x x x x x x [Table 24] Research Module - Cycle 4 Current_cycle Current_index 0 2

[0068] Since the Current Cycles data is equal to 0, the Offset data is equal to 1 and the Rest data is equal to 1, the interpretation module 42 provides the interpolation module 46 with a set of values ​​comprising the Value data equal to 4192, the Coeff data equal to -1451, the Offset data equal to 1, and the Dur data equal to 0, then the interpretation module 42 provides the interpolation module 46 with a set of values ​​comprising the Value data equal to 1290, the Coeff data equal to 1612, the Offset data equal to 0, and the Dur data equal to 0, and finally two sets of values, each comprising the Value data equal to 2902, the Coeff data equal to -414.57, the Offset data equal to 0, and the Dur data respectively equal to 0 and Tdac.

[0069] In the fifth hardware cycle, the interpretation module 42 updates the Value data, the Coeff data, the Offset data, and the Rest data as indicated in Table 25 below. The window for reading successive Nout ramps by the interpretation module 42 is shifted, as shown in Table 26 below. In addition, the search module 44 updates the Current_cycle and Current_index data as indicated in Table 27 below, the Current_cycle data being equal to the value of the Cycles control parameter in the third row of Table 7 and the Current_Index data being equal to the value of the Index control parameter in the third row of Table 7. [Table 25] Data Log - Cycle 5 Value Coefficient Offset Rest 2902 -414,57 2 1 [Table 26] Reading Window - Cycle 5 Start_val Coefficient Rest x x x x x x x x x x x x [Table 27] Research Module - Cycle 5 Current_cycle Current _index 1 x

[0070] Since the Current Cycles data is equal to 1, the Offset data is equal to 2 and the Rest data is equal to 1, the interpretation module 42 provides the interpolation module 46 with four sets of values, each comprising the Value data equal to 2902, the Coeff data equal to -414.57, the Offset data equal to 2, and the Dur data respectively equal to 0, Tdac, 2*Tdac, and 3*Tdac.

[0071] In the sixth hardware cycle, the interpretation module 42 adds the value Nout*Coeff to the data Value used in the fifth hardware cycle. The interpretation module 42 therefore updates the data Value as shown in Table 28 below. The window for reading Nout successive ramps by the interpretation module 42 does not move and is shown in Table 29 below. In addition, the search module 44 updates the data Current_cycle as shown in Table 29 below. [Table 28] Data Log - Cycle 6 Value Coefficient Offset Rest 1243,72 -414,57 2 1 [Table 29] Fenêtre de lecture - Cycle 6 Start_val Coeff Rest x x x x x x x x x x x x [Table 30] Module de recherche - Cycle 6 Current_cycle Current _index 0 x

[0072] Since the Current Cycles data is equal to 0, the Offset data is equal to 2 and the Rest data is equal to 1, the interpretation module 42 provides the interpolation module 46 with two sets of values, each comprising the Value data equal to 1243.72, the Coeff data equal to -414.57, the Offset data equal to 2, and the Dur data respectively equal to 0 and Tdac. To complete the final hardware cycle, the interpretation module 42 can provide the interpolation module 46 with two sets of values, each comprising the Value data equal to 1243.72, the Coeff data equal to 0, the Offset data equal to 0, and the Dur data respectively equal to 2*Tdac and 3*Tdac. Alternatively, to complete the final hardware cycle, the interpretation module 42 can provide the interpolation module 46 with two sets of values ​​corresponding to determined points.

[0073] There figure 10 represents a more detailed embodiment of the electronic circuit 10 of the figure 9 .

[0074] The decoding circuit 20 configured to provide the data parameters and the control parameters of the waveform from the raw parameters comprises a finite state machine 21 configured to read, at each hardware cycle, Nout data set from the memory 12 in which the raw parameters of the waveform are stored. The finite state machine 21 is configured to distribute the Nout data set to the division module 22 and to the duration calculation module 24.

[0075] The division module 22 is adapted to implement a Newton Raphson type division algorithm. The division module 22 receives the start value Start_val, the end value End_val, and the duration Duration of each ramp. The division module 22 provides Nout data parameters Start_val and out data parameters Coeff at each hardware cycle. According to one embodiment, the division module 22 requires two hardware cycles to perform a division.

[0076] The search module 44 of the execution circuit 40 configured to determine the digital values ​​of the waveform from the data parameters and the control parameters corresponds to a finite automaton 44 configured to read, at each hardware cycle, the data parameters and the control parameters of successive ramps in the memories 30 and 32.

[0077] According to one embodiment, the raw parameters of the waveform, i.e., the data Start_val, End_val, and Duration for each ramp are each stored on a number NB of bits in the memory 12. According to one embodiment, for each ramp of the waveform, the data parameter Start_val is stored on the number NB of bits in the data memory 30, the data parameter Coeff is stored as a float on the number NB of mantissa bits and 4 exponent bits in the data memory 30, and the data parameter Rest is stored on log(Nout) bits (in base 2) in the data memory 30. According to one embodiment, the control parameter Cycles is stored on NB-log(Nout) bits in the control memory 32, and the control parameter Index is stored on log(Nout) bits (in base 2) in the control memory 32. As an example, the number NB of bits is equal to 14.

[0078] According to one embodiment, memory 12 comprises Nout BRAM memory blocks in parallel. According to one embodiment, memory 30 comprises Nout BRAM DATA memory blocks in parallel. According to one embodiment, memory 32 comprises Nout BRAM CONTROL memory blocks in parallel. According to one embodiment, the size of memory 30 is the same as the size of memory 32. According to one embodiment, memory 34 comprises Nwfm BRAM memory blocks.

[0079] There figure 11 illustrates an embodiment of the finite state machine 21. The role of the finite state machine is to read the raw parameters, namely the raw parameters Start_val, End_val, and Duration, and to provide, in the memory 12, and to transmit them to the division module 22 and to the duration calculation module 24.

[0080] The finite state machine 21 comprises three states INIT_A, START_A, and RUN_A. In the INIT_A state, the finite state machine 21 is at rest. The transition from the INI_A state to the START_A state is achieved when an update bit is set to the logic value "1" by a system external to the electronic circuit 10. This means that the determination of the data parameters and the control parameters of a new waveform is to be carried out by the decoding circuit 20 from the raw parameters of this new waveform which are stored in the memory 12. The external system also sends to the electronic circuit 10 an identifier of the waveform to be executed.In the START_A state, the state machine 21 reads, in the memory 34, from the waveform identifier, the read address of the memory 12 at which the reading of the raw parameters of the waveform will begin, the address of the data memory 30 at which the writing of the data parameters in the data memory 30 will begin and the address of the control memory 32 at which the writing of the control parameters in the control memory 32 will begin. Advantageously, the address of the data memory 30 at which the writing of the data parameters will begin is the same as the address of the control memory 32 at which the writing of the control parameters will begin. The state machine 21 then sets an end_param bit to the logic value "1" which causes the transition from the START_A state to the RUN_A state.In the RUN_A state, the finite state machine 21 will read, in the memory 12, the raw parameters, namely the raw parameters Start_val, End_val, and Duration, of Nout successive ramps of the waveform and provides, at each hardware cycle, the raw parameters Start_val, End_val, and Duration of Nout successive ramps to the division module 22 and the raw parameters Duration of these Nout successive ramps to the duration calculation module 24. When the finite state machine 21 has transmitted the raw parameters of the last Nout successive ramps of the waveform to the division module 22 and to the duration calculation module 24, it sets an end_update bit to the logic value "1" which causes the transition from the RUN_A state to the INIT_A state.

[0081] There figure 12 represents an embodiment of the division module 22.

[0082] The division module 22 receives the raw parameters Start_val, End_val, and Duration provided by the finite state machine 21. For each ramp, the determination of the data parameter Coeff requires the determination of the inverse of the duration Duration of the ramp. For this purpose, the division module 22 implements an iterative algorithm according to the following relationship: X i + 1 = X i 2 − Duration ∗ X i where X i is an estimate of 1 / Duration

[0083] The error ε i between the estimate and 1 / Duration is given by the following relation: ε i + 1 = 1 − Duration ∗ X i + 1 = ε i 2

[0084] To initialize the algorithm, X 0 is given by the following relation: X 0 = T 0 − T 1 ∗ Duration where T0 is equal to 42 / 17 and T1 is equal to 32 / 17.

[0085] According to one embodiment, the division module 22 performs two iterations of this algorithm with a precision of 15 bits. Only two loops are sufficient with rounding to 14 bits to ensure bit-wise precision and therefore an error accumulation over the maximum duration of less than 2 bits.

[0086] The division module 22 comprises a module 100 which receives the raw Duration parameter and which provides the most significant bit Dur_exponent of the raw Duration parameter. The division module 22 comprises a module 102 which receives the raw Duration parameter and which provides a Dur_mantissa signal equal to the raw Duration parameter whose bits have been shifted by one position towards the most significant bit and which therefore corresponds to the mantissa of the raw Duration parameter. The Dur_mantissa signal is thus normalized between 0.5 and 1.

[0087] The division module 22 comprises a DSP0 block carrying out the initialization of the algorithm by implementing the Math 4 relation and comprising a multiplier MUL0 receiving the signal Dur_mantissa and the signal T1 and providing the product of the signal Dur_mantissa and the signal T1 and comprising a subtractor SOUS0 receiving the signal provided by the multiplier MUL0 and the signal T1 and providing the signal X 0 .

[0088] The division module 22 comprises blocks DSP1 and DSP2 implementing a first iteration according to the relation Math 2. The block DSP1 comprises a multiplier MUL1 receiving the signal X 0 and the signal Dur_mantissa and providing the product of the signal X 0 and the signal Dur_mantissa and comprising a subtractor SOUS1 receiving the signal provided by the multiplier MUL1 and the number 2 and providing the difference between the number 2 and the signal provided by the multiplier MUL1. The block DSP2 comprises a multiplier MUL2 receiving the signal provided by the subtractor SOUS1 and the signal X 0 and providing the signal X 1 .

[0089] The division module 22 comprises blocks DSP3, DSP4 and DSP5 implementing a second iteration according to the relation Math 2. The block DSP3 comprises a multiplier MUL3 receiving the signal Amp_mantissa and the signal X 1 and providing a signal Amp*X 1 equal to the product of the signal Amp_mantissa and the signal X 1 . The block DSP4 comprises a multiplier MUL4 receiving the signal X 1 and the signal Dur_mantissa and providing the product of the signal X 1 and the signal Dur_mantissa and comprising a subtractor SOUS4 receiving the signal provided by the multiplier MUL4 and the number 2 and providing the difference between the number 2 and the signal provided by the multiplier MUL4. The block DSP5 comprises a multiplier MUL5 receiving the signal Amp*X1 and the signal provided by the subtractor SOUS4 and providing the signal Amp*X2 equal to the product of the signal X 2 and the signal Amp_mantissa.

[0090] The division module 22 comprises a subtractor 104 which receives the raw parameter Start_val and the raw parameter End_val and which determines an Amp data equal to the difference between the raw parameter End_val and the raw parameter Start_val. The division module 22 comprises a module 106 which determines whether the Amplitude data is positive and a module 108 which then provides the most significant bit Amp_exponent of the Amplitude data and a module 110 which determines whether the Amplitude data is negative and a module 112 which then provides the most significant bit Amp_exponent of the Amplitude data. The division module 22 comprises a module 114 which receives the Amplitude data and provides an Amp_mantissa signal equal to the Amplitude data whose bits have been shifted by a number of positions equal to 13-Amp-exponent towards the most significant bit. The Amp_mantissa signal therefore corresponds to the mantissa of the Amplitude data.The Amp_mantissa signal is thus normalized between 0.5 and 1.

[0091] The division module 22 includes an adder ADD1 which receives the signal Amp_exponant, the number 3, and the signal Dur_exponant and provides a signal Coeff_exponant equal to the sum between the signal Amp_exponant, the number 3, reduced by the signal Dur_exponant.

[0092] The division module 22 includes a module 116 which receives the Amp*X 2 signal and the Coeff_exponant signal and provides a Coeff_mantissa signal.

[0093] The division module 22 comprises a finite state machine 118. The role of the finite state machine 118 is to provide the write addresses of the data memory 30 for writing the data parameters Coeff_mantissa, Coeff_exponant, Start_val, and Rest in the data memory 30, the data parameters Rest being provided by the duration calculation module 24. The finite state machine 118 comprises two states INIT_B and RUN_B. In the INIT_B state, the finite state machine 118 is at rest. The transition from the INI_B state to the START_B state is achieved when the finite state machine 21 sets a start_B bit to the logic value "1".In the RUN_B state, the state machine 118 receives the start_address of the data memory 30 at which the writing of the data parameters Coeff_mantissa, Coeff_exponant, and Start_val in the data memory 30 must begin, and determines the successive write addresses of the data memory 30 to which the data parameters Coeff_mantissa, Coeff_exponant, Start_val, and Rest are written in the data memory 30 as they are supplied. The transition from the RUN_B state to the INI_B state is achieved when the state machine 21 sets the start_B bit to the logic value "0".

[0094] There figure 13 illustrates an embodiment of a method of operating the reorganization module 28. The operation of the reorganization module 28 requires two hardware cycles. The reorganization module 28 receives the Cycles and Index control parameters from the merge module 26 and stores them in a temporary memory operating according to the first-in, first-out method. At each hardware cycle, the reorganization module 28 writes the first four entries of the temporary memory into the control memory 32. When the number of data stored in the memory of the reorganization module 28 exceeds a Buffer size threshold, then the Buffer size number of data empties the first four entries of the temporary memory and shifts the other entries of the temporary memory by four positions, and the write address of the memory 32 is incremented. For example, the Buffer size threshold is equal to 4.For example, in step A), the reorganization module 28 receives three new data. The three new data 1, 2, and 3 are represented stored in memory in step B). The reorganization module 28 performs an operation of writing the data 1, 2, and 3 in the control memory 32 with the write address equal to i. Furthermore, in step B), the reorganization module 28 receives four new data. The four new data 4, 5, 6, and 7 are represented stored in memory in step C). The reorganization module 28 performs an operation of writing the data 1, 2, 3, and 4 in the control memory 32 with the write address equal to i. Since the number of stored data is greater than 4 in step C), the reorganization module 28 deletes data 1, 2, 3, and 4 as shown in step D) and shifts data 5, 6, 7 by four positions and the write address is incremented by one.Furthermore, in step C), the reorganization module 28 receives a new data item. The new data item 8 is shown stored in memory in step D). The reorganization module 28 performs a write operation of the data items 5, 6, 7, and 8 in the control memory 32 with the write address equal to i+1. Since the number of stored data items is greater than 4 in step D), the reorganization module 28 deletes the data items 5, 6, 7, and 8 in the control memory 32 as shown in step E). Furthermore, in step D), the reorganization module 28 receives three new data items. The three new data items 9, 10, and 11 are shown stored in memory in step E). The reorganization module 28 performs a write operation of the data 9, 10, and 11 in the control memory 32 with the write address equal to i+2. Furthermore, in step E), the reorganization module 28 receives three new data.The three new data 12, 13, and 14 are represented stored in memory in step F). The reorganization module 28 performs an operation of writing the data 9, 10, 11, and 12 in the control memory 32 with the write address equal to i+2.

[0095] There figure 14 represents an embodiment of the duration calculation module 24 configured to determine the total duration total_dur of the waveform. According to one embodiment, the duration calculation module 24 has a Kogge-Stone structure. According to one embodiment, the duration calculation module 24 receives Nout raw parameters Duration, denoted in figure 14 dur[0] to dur[Nout], from Nout successive ramps and determines Nout duration data total_dur[0] to total_dur[Nout-1]. According to one embodiment, each raw parameter dur[0] to dur[Nout] comprises 14 bits and each data total_dur[0] to total_dur[Nout-1] comprises 14+log(Nout) bits. For example, in figure 14 , Nout is equal to 16.

[0096] The duration calculation module 24 receives the raw Duration data of the ramps coded on 14 bits, dur[0] to dur

[15] . The duration calculation module 24 comprises first adders SUM1 j , j being an integer varying from 1 to 15. Each adder SUM1 j , j varying from 1 to 15, receives the data dur[j-1] and dur[j] and determines the data s1[j] equal to the sum between the data dur[j-1] and dur[j]. The duration calculation module 24 further comprises second adders SUM2 j , j being an integer varying from 2 to 15. Each adder SUM2 j , j varying from 2 to 15, receives the data sli[j-2] and s1[j], the data s1[0] being equal to the data dur[0]. Each adder SUM2 j , j varying from 2 to 15, determines the data s2[j] equal to the sum between the data s1[j-2] and s1[j] and therefore equal to the sum between the data dur[j-2] to dur[j]. The duration calculation module 24 further comprises third adders SUM3 j , j being an integer varying from 4 to 15.Each SUM3 adder j , j varying from 4 to 15, receives the data s2[j-4] and s2[j], the bit s2[0] being equal to dur[0] and the bit s2[1] being equal to the bit s1[1]. Each SUM3 adder j , j varying from 4 to 15, determines the data s3[j] equal to the sum between the data s2[j-4] and s2[j] and therefore equal to the sum between the data dur[j-5] to dur[j]. The duration calculation module 24 further comprises fourth SUM4 adders j , j being an integer varying from 8 to 15. Each SUM4 adder j , j varying from 8 to 15, receives the data s3[j-8] and s3[j], the bit s3[0] being equal to dur[0], the bit s3[1] being equal to the bit s1[1], the bit s3[2] being equal to the bit s2[2], and the bit s3[3] being equal to the bit s2[3]. Each SUM4 adder j , j varying from 8 to 15, determines the data s4[j] equal to the sum between the data s3[j-8] and s3[j] and therefore equal to the sum between the data dur[j-8] to dur[j].The duration calculation module 24 further comprises fifth adders SUM5 j , j being an integer varying from 0 to 15. Each adder SUM5 j , j varying from 1 to 15, determines the data total_dur[j] equal to the sum between the bit s4[j] and the previous value of total_dur[j].

[0097] There figure 15 illustrates an embodiment of the search module 44 when it corresponds to a finite automaton. The search module 44 receives instructions from the user such as starting or stopping the execution of a waveform. The role of the search module 44, during the execution of a waveform, is to determine the read addresses of the data memory 30 in which the data parameters are stored and the read addresses of the control memory 32 in which the control parameters are stored.

[0098] The search module 44 includes six states INIT_C, START_C, START1_C, START2_C, RUN_C, and REP_C.

[0099] In the INIT_C state, the search module 44 is at rest. The transition from the INI_C state to the START_C state is achieved when an update bit is set to the logic value "1" by a system external to the electronic circuit 10. This corresponds to an instruction to start the execution of a waveform. Starting the waveform costs 4 hardware cycles.

[0100] In the START_C state, the search module 44 reads waveform execution parameters from the memory 34, including in particular the size (Waveform_Size parameter) of the waveform and whether the waveform is to be executed repeatedly or not (Repeat parameter). The search module 44 further reads, from the memory 34, the read address of the data memory 30 at which to start reading the waveform data parameters. The search module 44 then sets a started bit to the logic value "1", which causes the START_C state to change to the START1_C state.

[0101] In the START1_C state, the search module 44 reads the waveform data parameters from the data memory 30 at the read address obtained in the START_C state, and reads the waveform control parameters from the control memory 32 at the read address obtained in the START_C state. The search module 44 then sets a bit enb_data to the logic value "1", which causes the START1_C state to change to the START2_C state.

[0102] In the START2_C state, the search module 44 waits for the reading step initiated in the START1_C state to have completed correctly. The transition from the START_2C state to the RUN_C state is achieved when a first_next bit is set to the logic value "1" by the search module 44.

[0103] In the RUN_C state, the search module 44 determines the next read addresses read_data_address of the data parameters in the data memory 30 and the next read addresses wr_addr of the control parameters in the control memory 32. The search module 44 can further provide a shift data item and a next_index data item used by the interpretation module 42 as described below.

[0104] The transition from the RUN_C state to the REP_C state is performed when the search module 44 has read the last data parameters and control parameters of the waveform and the waveform is to be executed repeatedly. The transition from the RUN_C state to the INIT_C state is performed when the search module 44 has read the last data parameters and control parameters of the waveform and the waveform is to be executed only once.

[0105] In state REP_C, the search module 44 resets the execution of the waveform. The search module 44 then goes to state START1_C as during the first execution of the waveform.

[0106] The transition from the START_C, START1_C, START2_C, RUN_C, and REP_C states to the INIT_C state is achieved when a stop bit is set to the logic value "1" by a system external to the electronic circuit 10. This corresponds to an instruction to stop the execution of a waveform.

[0107] There figure 16 illustrates an embodiment of a method for reading control parameters in the control memory 32 by the search module 44 in the RUN_C state.

[0108] The search module 44 must be able to analyze and read one line of control parameters in the control memory 32 per hardware cycle. Indeed, a group of ramps may only last one hardware cycle. It is therefore necessary to be able to determine the next read address in the data memory 30 in one hardware cycle to handle the case where several groups of this type are linked together. According to one embodiment, changing a read address and retrieving the data may cost more than one hardware cycle, for example two hardware cycles. Thus, the search module 44 must be able to have "advance" access to the information of the next control line. According to one embodiment, the search module 44 reads the lines two by two in the control memory 32 and stores, in a buffer memory, the odd lines (Cycles[i+1] Index[i+1]). The read address wr_addr in the control memory 32 is therefore incremented two by two.Generally, depending on the latency of the search module 44, a reading of more than two lines from the control memory 32 can be expected.

[0109] When the ramp group ends (which corresponds to the Current_cycle data equal to 0), the search module 44 updates the read addresses read_data_address, sends to the interpretation module 42 the next realignment shift shift_data as well as the size of the ramp group next_index to manage the transition to the next ramp group.

[0110] For example, the search module 44 sets the data Current_cycle equal to the control parameter Cycles[i] and sets the data Current_Index equal to the control parameter Index[i] read at the address wr_addr of the memory 32, and keeps in memory the control parameters Cycles[i+1] Index[i+1] read at the address wr_addr+1 of the memory 32. At each hardware cycle, the data Current_cycle is decreased by 1 (cycle-=1). When the value of the Current_cycle data is equal to 0 (if cycle==0) and the control parameters Cycles[i+1] Index[i+1] have not yet been used (wr_addr / 2 even), the search module 44 sets the Current_cycle data equal to the control parameter Cycles[i+1] and sets the Current_Index data equal to the control parameter Index[i+1] read at the address wr_addr+1 of the memory 32.When the value of the Current_cycle data is equal to 0 (if cycle==0) and the control parameters Cycles[i+1] Index[i+1] have already been used (wr_addr / 2 odd), the read address wr_addr in control memory 32 is incremented by 2 (wr_addr+=2), and the following two lines (Cycles[i+2] Index[i+2] and Cycles[i+3] Index[i+3]) are read into memory 32.

[0111] There figure 17 represents an embodiment of the interpretation module 42.

[0112] Interpretation module 42 includes: a first buffer memory 50; a second buffer memory 52; a finite state machine 54; a processing memory 56; an index register 58; and an output memory 60.

[0113] The state machine 54 comprises two states RUN_D and INIT_D. In the INIT_D state, the state machine 54 provides default values ​​for the data Value, Rest, Coeff, Offset. The transition from the INI_D state to the RUN_D state is achieved when the state machine 44 sets a start_D bit to the logic value "1". In the RUN_D state, the state machine 54 determines Nout points at each hardware cycle. The transition from the RUN_D state to the INIT_D state is achieved when the state machine 44 sets the start_D bit to the logic value "0".

[0114] Data memory 30 is implemented as Nout memory blocks in parallel, therefore, since we are reading with a sliding window not aligned with Nout, the data must be realigned. It is the search module 44 that determines the value of the shift _data required for realignment, described in more detail later.

[0115] When reading a new ramp at the beginning of a new hardware cycle, the state machine 54 reads the Start_val, Coeff, and Rest data stored in the second buffer 52 and stores them in the processing memory 56. The 14-bit Start_val data of the second buffer 52 is recorded in 28 bits in the processing memory 56 in the Value data. The 14-bit Coeff data parameter of the second buffer 52 is recorded in 28 fixed-point bits in the processing memory 56. The Nout lines of the first buffer 50 and second buffer 52 are then updated.

[0116] At each hardware cycle, the finite state machine 54 determines Nout points which are recorded in the output memory 60. Each point corresponds to a data set comprising the Value data, the Coeff data parameter, the Dur data, and the Offset data. The Nout points recorded in the output memory 60 are read by the interpolation module 44 to provide Nout digital values ​​of the digital signal Sn, according to the Math 1 relationship described previously. The Dur data corresponds to the duration relative to the time of the Value value and can therefore vary from 0 to (Nout-1)*Tdac. The Offset data corresponds to a duration offset and is equal to a multiple of Tdac (possibly 0).

[0117] When the hardware cycle is finished but the ramp is not completed, the Value value is updated by adding the Nout*Coeff data to it. To avoid having to perform multiplication, this can be done by shifting the bits of the Coeff data to the left Nout times and adding the resulting value to the Value data. The state machine 54 will perform this action as long as the first ramp in the group is not exhausted.

[0118] When the first ramp is exhausted, the system will start filling the Nout points with the Rest number of points from the first ramp. Knowing the size of the ramp group, it will fetch the ramps needed to complete the cycle. Each ramp has its duration encoded on the Rest data. Thus the interpretation module 42 will concatenate the Nout points needed to complete the hardware cycle. It can then fetch the first ramp of the next ramp group, and calculate the Offset value (part of the ramp played during the previous group). This Offset value avoids an additional multiplication to initialize the value of the first ramp of the next ramp group. There is an exception to handle when the group ends up aligned with a hardware cycle. There is then no offset on the first ramp of the next ramp group, which corresponds to the Offset data equal to 0.

[0119] The interpretation module 42 also manages the end of a waveform. When there are no more points to play, the interpretation module 42 will keep the last known point and play it continuously.

[0120] Even if the Coeff data parameter is stored on 28 bits in the output memory 60, it may be advantageous for the interpolation module 44 to read only the 14 most significant bits of the Coeff data parameter in the output memory 60, for example to be compatible with the fhard frequency. When the Coeff data parameter to be stored in the output memory 60 is strictly between -1 and 0, it must be rounded to 0. When the Coeff data parameter is negative greater than -1, these 14 most significant bits are rounded to -1 even if it is in reality very close to 0. To avoid bounce effects (because the value in the buffer is indeed updated with the coefficient on 28 bits) the Coeff data parameter is therefore rather rounded to 0 in this case.

[0121] For example, in the fourth hardware cycle when executing the waveform in Table 7 described above, the search module 44 indicates to the interpretation module 42 that two additional ramps will be necessary to complete the hardware cycle by providing the interpretation module 42 with the next_index data equal to the Current_index data in Table 24 described above. The interpretation module 42 therefore reads the data parameters of the next two ramps in Table 23 described above. With the data stored in the processing memory 56, which correspond to the data in Table 22 described above, the processing module 42 determines a set of values ​​comprising the Value data equal to 4192, the Coeff data equal to -1451, the Offset data equal to 1, and the Dur data equal to 0 since the Rest data parameter is equal to 1.Then, since the Rest data parameter of the first next ramp is equal to 2 (first row of Table 23), the processing module 42 determines that the first next ramp is played only once and determines a set of values ​​including the Value data equal to 1290, the Coeff data equal to 1612, the Offset data equal to 0, and the Dur data equal to 0. Since the Rest data parameter of the second next ramp is equal to 1 (second row of Table 23), the processing module 42 determines that the second next ramp is played until the end of the fourth hardware cycle and also in the following cycle. In the fourth cycle, the processing module 42 therefore determines two sets of values, each including the Value data equal to 2902, the Coeff data equal to -414.57, the Offset data equal to 0, and the Dur data equal to 0 and Tdac respectively.For the fifth cycle that follows, the processing module 42 updates the data in the processing memory 56, which corresponds to the data in the table Table 25 described previously. Since the ramp defined by the data in the processing memory 56 has already been played twice, the interpretation module has set the Offset data to 2.

[0122] There figure 18 illustrates an embodiment of a method of operating the first buffer 50 and the second buffer 52. figure 18 , Nout is taken equal to 4, so that the data memory is implemented as 4 memory blocks in parallel. Since the interpretation module 42 reads with a sliding window not aligned with the 4 memory blocks, the data must be realigned. It is the search module 44 that determines the value of the shift _data needed for the realignment. In case A), the shift value is equal to 0. In case B), the shift value is equal to 2. In case C), the shift value is equal to 3.

[0123] There figure 19 illustrates an embodiment of a method for managing memories 30 and 32. Nwfm is the number of usable waveforms and Nramp is the maximum possible number of ramps per waveform. On the left side of the figure 19 , we have very schematically represented four waveforms FO1, FO2, FO3, FO4 that we want to be able to play. In the central part of the figure 19 , we have represented the memory 12, 30 in which the data of the four waveforms FO1, FO2, FO3, FO4 are stored in a non-optimal way. The size of the memory 12, 30 is then equal to the product Nwfm*Nramp. In the central part of the figure 19 , the memory 12, 30 is represented in which the data of the four waveforms FO1, FO2, FO3, FO4 are stored optimally. The size of the memory 12, 30 can then be strictly less than the product Nwfm*Nramp.

[0124] In the embodiments described above, the decoding circuit 20 and the execution circuit 40 are each implemented by a dedicated electronic circuit. According to another embodiment, only the execution circuit 40 is implemented by a dedicated electronic circuit and the decoding circuit 20 comprises a processor, for example a microprocessor or a microcontroller, configured to execute instructions of a computer program stored in a memory.

[0125] The embodiments described above relate to waveforms comprising linear ramps. According to another embodiment, each ramp of the waveform may follow a polynomial function P(x) according to the following relationship: P x = Start_value + Coeff 1 ∗ x + Coeff 2 ∗ x 2 + ⋯ + CoeffD ∗ x D where D is the degree of the polynomial and the coefficients Coeffj, j vary from 1 to D, are the coefficients of the polynomial. When the degree of the polynomial is equal to 1, the ramp corresponds to a linear ramp. When the degree of the polynomial is greater than or equal to 2, the ramp corresponds to a non-linear ramp.

[0126] There figure 20 schematically represents another embodiment of the electronic circuit 10 configured to execute a waveform in which each ramp follows the Math 5 relationship indicated previously. In this embodiment, the data parameters stored in the memory 30 comprise, for each ramp, the data parameters Start_val and Rest described previously and, in addition, the coefficients Coeffj, j varying from 1 to D. The interpretation module 42 and the search module 44 may have the same structure as that described previously, except that the processed data are larger since there are several coefficients Coeff. The interpolation module 46 provides each digital value of the signal Sn from the data Value, Dur, Offset, Coeff1, ... CoeffD provided by the interpretation module 42 according to the following relationship. P x = Start_value + Coeff 1 ∗ x + Coeff 2 ∗ x 2 + ⋯ + CoeffD ∗ x D

[0127] In particular, when the interpolation module 46 is implemented by an FPGA circuit, the calculation of a digital value by the interpolation module 46 may take D+1 hardware cycles and require D multipliers.

[0128] In the embodiments described above, the decoding circuit 20 is configured to provide, at each hardware clock cycle, the data parameters and the control parameters of Nout successive ramps of the waveform and the execution circuit 40 is configured to provide, at each hardware clock cycle, Nout digital values ​​of the digital signal Sn. According to another embodiment, the decoding circuit 20 is configured to provide, at each hardware clock cycle, the data parameters and the control parameters of Nout1 successive ramps of the waveform and the execution circuit 40 is configured to provide, at each hardware clock cycle, Nout2 digital values ​​of the digital signal Sn, Nout1 and Nout2 being different integers. In particular, Nout1 may be strictly less than Nout2. This advantageously simplifies the production of the decoding circuit 20.

[0129] The digital signal Sn supplied by the electronic circuit 10 can be modified before its transmission to the digital-analog converter 6.

[0130] There figure 21 represents an embodiment of a system 200 for providing a digital signal Sn". The system 200 comprises the electronic circuit 10, shown in the figure 9 , which provides the digital signal Sn and a circuit 202 configured to provide a digital signal Sn'. The system 200 further comprises a circuit 204, for example a summer, which receives the digital signals Sn and Sn' and provides the digital signal Sn", for example equal to the sum of the digital signals Sn and Sn'.

[0131] Tests were carried out. For these tests, the electronic circuit 10 is implemented by an FPGA circuit. The Nwfm parameter is equal to 32, the Nramp parameter is equal to 256. The size of each memory 12, 30, and 32 is equal to 8192.

[0132] There figure 22 is a timing diagram of several four successive waveforms FO1, FO2, FO3, and FO4.

[0133] There figure 23 is a timing diagram of the fourth waveform FO4 of the figure 22 to which a digital signal of a sinusoidal waveform has been added between times t1 and t2.

[0134] There figure 24 is a timing diagram of the fourth waveform FO4 of the figure 22 to which a digital signal of a Gaussian waveform has been added between times t1 and t2.

[0135] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art without departing from the scope of the appended claims.

[0136] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above.

Claims

1. Electronic circuit (10) for providing a digital signal (Sn), an analog signal obtained by digital-to-analog conversion of the digital signal comprising a succession of ramps, the electronic circuit being clocked by a clock signal, the electronic circuit being configured to supply a number Nout of successive digital values of the digital signal at each cycle of the clock signal, Nout being greater than 1, the electronic circuit comprising a first memory (30) in which are stored, for each ramp, first data comprising a start value of the ramp, the slope of the ramp, and a remaining duration of the ramp in the last cycle of the clock signal in which the ramp extends, and a second memory (32) in which are stored second data relative to the numbers of cycles of the clock signal over which some of the ramps extend, and a first circuit (40) configured to read from the first memory the first data relative to a plurality of successive ramps and from the second memory the second data associated with said plurality of successive ramps, and to provide said digital values based on the first and second read data.

2. Electronic circuit according to claim 1, wherein the first circuit (40) is configured to read in parallel from the first memory (30) the first data relative to Nout successive ramps, to read from the second memory the second data associated with said Nout successive ramps, and to supply, at a cycle of the clock signal, Nout digital values of the digital signal forming part of from one to Nout ramps among said Nout ramps.

3. Electronic circuit according to claim 2, wherein the first circuit (40) comprises Nout interpolation circuits (46) in parallel, each interpolation circuit being configured to calculate, at a cycle of the clock signal, one of the Nout digital values of the digital signal forming part of from one to Nout ramps among said Nout successive ramps.

4. Electronic circuit according to any of claims 1 to 3, wherein the first data stored in the first memory (30) comprise, for each ramp, coefficients of a polynomial of a degree greater than or equal to 2, the slope of the ramp being the coefficient of degree 1 of the polynomial, the first circuit (40) being configured to supply said digital values of ramps corresponding to polynomial functions.

5. Electronic circuit according to any of claims 1 to 4, wherein Nout is a power of two, in particular 2, 4, 8, or 16.

6. Electronic circuit according to any of claims 1 to 5, wherein the first circuit (40) is configured to read, from the first memory (30), simultaneously the first data of Nout successive ramps.

7. Electronic circuit according to any of claims 1 to 6, wherein the first circuit (40) is configured to read, from the second memory (32), simultaneously the second data of Nout successive ramps.

8. Electronic circuit according to any of claims 1 to 7, in which the first circuit (40) comprises a first module (42) configured to supply, at each cycle of the clock signal, sets of data, each set comprising a start value of the ramp, the slope of the ramp, and a delay, the delay varying from one set to the other, and a second module (44) configured, for each set, to supply a digital value of the digital signal equal to the sum of the start value of the ramp and of the product of the slope of the ramp and of the delay.

9. Electronic circuit according to any of claims 1 to 8, wherein the first memory (30) comprises Nout memory blocks in parallel.

10. Electronic circuit according to any of claims 1 to 9, comprising a third memory (12) in which are stored, for each ramp of the succession of ramps, third data comprising the start value of the ramp, the end value of the ramp, and the duration of the ramp, the electronic circuit further comprising a second circuit (20) configured to supply, based on the third data, the first data and the second data, and to write the first data into the first memory (30) and to write the second data into the second memory (32).

11. Electronic circuit according to claim 10, wherein the second circuit (20) is configured to process the third data in batches of Nout successive ramps.

12. Electronic circuit according to claim 10 or 11, wherein the second circuit (20) comprises a third module (22) configured to determine, for each ramp, the slope of the ramp, and a fourth module (24) configured to determine the total duration elapsed from the start of the succession of ramps to the end of the ramp and the number of cycles of the clock signal contained in said total duration.

13. System (10) comprising the electronic circuit according to any of claims 1 to 12, a digital-to-analog converter (6) configured to convert the digital signal (Sn) into an analog signal (Sa), and quantum bit storage cells (2) receiving the analog signal.

14. Method of supplying a digital signal (Sn), an analog signal obtained by digital-to-analog conversion of the digital signal comprising a succession of ramps, the method comprising the supply, at each cycle of a clock signal, of a number Nout of successive digital values of the digital signal, Nout being greater than 1, the method comprising the provision of a first memory (30) in which are stored, for each ramp, first data comprising a start value of the ramp, the slope of the ramp, and a remaining duration of the ramp in the last cycle of the clock signal in which the ramp extends, the provision of a second memory (32) in which are stored second data relative to the numbers of cycles of the clock signal over which some of the ramps extend, the reading, from the first memory, of the first data relative to a plurality of successive ramps and, from the second memory, of the second data associated with said plurality of successive ramps, and the supply of said digital values based on the first and second read data.