Device for LED emissive display

Abstract

The present description relates to an elementary module (100) of a display device for displaying at least one pixel of an image, the module comprising: - a first set of N LEDs (101(i,j)) distributed in M ​​groups (G(i)), at least one of the M groups comprising at least two LEDs, where N and M are integers, with M greater than or equal to 2; and - a control circuit comprising M biasing circuits (103(i)) associated respectively with the M groups of LEDs, each biasing circuit (103(i)) being shared by the LEDs of the corresponding group (G(i)) and being adapted to successively control the LEDs of the group in emission.

Description

Domaine technique

[0001] This description relates to the production of an emissive image display device using light-emitting diodes (LEDs), for example a television screen, computer screen, smartphone screen, digital tablet screen, etc. It relates more particularly to the production of an elementary module of such a device. Technique antérieure

[0002] It has already been proposed, for example in patent application WO2017089676 or in patent applications WO2018185433 and WO2018185434, an image display device comprising a plurality of elementary electronic chips, which will hereinafter be called elementary modules, arranged in a matrix on the same transfer substrate. The modules are mounted integrally with the transfer substrate and connected to electrical connection elements of the transfer substrate for their control. Each module comprises one or more LEDs and a control circuit for said one or more LEDs and corresponds to a pixel of the device. More particularly, each module comprises a first chip called an LED chip integrating said one or more LEDs of the module, and a second chip called a control chip comprising the control circuit for said one or more LEDs of the module.The LED chip and the control chip are joined and electrically connected to each other, the assembly forming a so-called monolithic module, in other words a compact assembly, comprising connection terminals intended to be connected to corresponding connection terminals of the transfer substrate.

[0003] It would be desirable to be able to improve at least partially certain aspects of an image display device of this type.

[0004] Documents US2015 / 339998, US6317138 and US2018 / 247586 describe other examples of image display devices. Summary of the invention

[0005] The invention is set forth in the attached set of claims. Brève description des dessins

[0006] These and other features and advantages will be set forth in detail in the following description of particular embodiments in conjunction with the accompanying figures, among which: there figure 1 is an electrical circuit diagram of an example of an elementary module of a display device according to one embodiment; figure 2 is a timing diagram illustrating an example of operation of the elementary module of the figure 1 ; there figure 3 is a simplified schematic representation of another example of an elementary module of a display device according to one embodiment; the figure 4 illustrates in more detail an example of a control circuit of an elementary module according to one embodiment; the figure 5 represents an example of a characteristic curve of the quantum efficiency of an LED; the figure 6 illustrates an example of operation of an elementary module according to one embodiment; the figure 7 illustrates another example of operation of an elementary module according to an embodiment; the figure 8 illustrates in more detail another example of a control circuit of an elementary module according to one embodiment; and the figure 9 illustrates in more detail another example of a control circuit of an elementary module according to one embodiment. Description des modes de réalisation

[0007] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0008] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, the manufacture of the elementary modules of the display devices described has not been detailed, the manufacture of such modules being within the scope of those skilled in the art from the teachings of the present description. Each elementary module is intended to be mounted integrally with a transfer substrate and connected to electrical connection elements of the transfer substrate for its control. Each elementary module comprises a monolithic chip or an assembly of several electrically connected monolithic chips. Generally, an elementary module is a compact assembly of one or more electronic chips advantageously obtained according to microelectronic component manufacturing methods.A plurality of modules, for example identical or similar, can be mounted on the same transfer substrate, each module corresponding for example to a pixel of the display device. By way of example, the elementary modules of the display devices described each comprise a plurality of LEDs and a transistor-based control circuit, and can be manufactured according to methods identical or similar to those described in the aforementioned patent application WO2017089676.

[0009] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements.

[0010] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0011] There figure 1 is an electrical circuit diagram of an example of a pixel 100 of a display device according to one embodiment. In this example, the module 100 is a monolithic module consisting of an assembly of a control chip and an LED chip. The LED chip is for example arranged on and in contact with the control chip. By way of example, the LED chip comprises, on its lower face, electrical connection terminals electrically connected to electrical connection terminals arranged on the upper face of the control chip.

[0012] In this example, we consider more particularly the production of a so-called multi-view display device, that is to say in which the image to be displayed is divided into pixels each comprising a plurality of sub-pixels corresponding to different views of the scene that we wish to reproduce. By way of example, the different sub-pixels of the same pixel correspond respectively to the same pixel of different images of the same scene, taken from different viewing angles. A multi-view display device can for example be used in applications in which we wish to give the user an impression of three-dimensional viewing.

[0013] In the example of the figure 1 , the display device is a monochromatic device. Each module 100 comprises a set of N elementary LEDs 101 of the same color, that is to say having the same central emission wavelength, with N being an integer, preferably greater than or equal to 4, forming the LED chip of the module. The N LEDs 101 are for example identical apart from manufacturing dispersions. The N LEDs of the module are individually controllable and correspond respectively to N sub-pixels of a multi-view pixel. Each module further comprises, attached and electrically connected to the LED chip, an integrated circuit for controlling the N LEDs, for example a CMOS circuit (from the English "Complementary Metal Oxide Semiconductor"), forming the control chip of the module.

[0014] A display device may comprise a plurality of elementary modules 100, identical or similar, arranged on the same transfer substrate, for example in a matrix arrangement. The transfer substrate is for example a passive transfer substrate, comprising electrical connection elements for powering and controlling the modules.

[0015] In the example of the figure 1 , the N LEDs 101 of the module 100 are divided into M groups G(1),..., G(M) of L LEDs each, with M and L integers greater than or equal to 2. Hereinafter, the reference 101(i,j) designates the LED 101 of rank j of the group G(i), with i integer ranging from 1 to M and j integer ranging from 1 to L.

[0016] In the example of the figure 1 , the control circuit of the module 100 comprises M bias circuits 103(1),..., 103(M) associated respectively with the M groups of LEDs G(1),..., G(M). The control circuit of the module 100 further comprises a circuit 105 for controlling the M bias circuits 103(i).

[0017] The M bias circuits 103(1),..., 103(M) are for example identical, apart from manufacturing variations. Each bias circuit 103(i) comprises L output nodes S(1),..., S(L) connected, preferably connected, respectively to the anodes of the L LEDs 101(i,1),..., 101(i,L) of the corresponding group G(i). In this example, in each group G(i) of LEDs, the cathodes of the LEDs are connected, preferably connected, to the same node for applying a fixed reference potential GNDLED of the module, for example ground. As a variant (not shown), the orientations of the LEDs can be reversed. In other words, each LED 101(i,j) can have its cathode connected, for example connected, to the corresponding output node S(j) of the bias circuit 103(i), and its anode connected, for example connected, to a terminal for applying a reference potential. The bias circuit 103 can then be a CMOS circuit complementary to that described previously.

[0018] In the example of the figure 1 , each bias circuit 103(i) comprises a bias current source 107 common to the L LEDs 101(j) of the corresponding group G(i). The bias current source 107 comprises an input node d_in intended to receive a reference signal for adjusting the bias current delivered by the source 107. The bias source 107 further comprises an output node out intended to provide a bias current ib depending on the value of the reference signal applied to the node d_in.

[0019] In this example, each bias circuit 103(i) further comprises L individually controllable switches k(1),..., k(L), respectively connecting the L output nodes S(1),..., S(L) of the circuit 103(i) to the output node out of the bias current source 107 of the circuit 103(i). Each switch K(j) has a first conduction node connected, for example connected, to the out node of the bias current source 107 of the circuit 103(i), and a second conduction node connected, for example connected, to the output node S(j) of the same rank j of the circuit 103(i).

[0020] In the example of the figure 1 , each bias circuit 103(i) further comprises a switch SW. The switch SW connects the control node d_in of the current source 107 to a DATA terminal for applying a control signal of the module 100. More particularly, the switch SW has a first conduction node connected, for example connected, to the DATA terminal, and a second conduction node connected, for example connected, to the d_in node. The DATA input terminal is common to all the LEDs of the module 100. The individual brightness adjustment signals of the M*L LEDs 101 are time-multiplexed on the DATA terminal. The M switches SW and the M*L switches K(j) of the module make it possible to demultiplex the brightness adjustment signals so as to individually control the M*L LEDs 101.

[0021] The control circuit 105 makes it possible to control the M switches SW and the M*L switches K(j). More particularly, in this example, the control circuit 105 generates a control signal W_EN on M bits to respectively control the M switches SW. In this example, the signal W_EN is supplied on a parallel port of M output nodes of the circuit 105, connected respectively to the control nodes of the M switches SW. The control circuit 105 further generates a control signal LED_EN on L bits to respectively control the L switches K(j) of each bias circuit 103(i). In this example, the same control signal LED_EN is applied in parallel to the M bias circuits 103(i). The signal LED_EN is supplied on a parallel port of L output nodes of the circuit 105, connected respectively to the control nodes of the L switches K(j) of each of the M bias circuits 103(i). Thus, each bit LED_EN <j>of the LED_EN signal is applied simultaneously to the control nodes of the M switches K(j) of the same rank j of the control circuit. In other words, for each rank j ranging from 1 to L, the M switches K(j) of the same rank j are all simultaneously controlled in the same state. Thus, for each rank j ranging from 1 to L, the M LEDs 101(i,j) of the same rank j are all simultaneously activated in transmission or are all simultaneously deactivated.

[0022] There figure 2 is a timing diagram illustrating an example of operation of module 100 of the figure 1 .

[0023] We have represented schematically on the figure 2 the evolution, as a function of time, of the control signals W_EN (M bits) and LED_EN (L bits) supplied by the control circuit 105.

[0024] Below we define a period T_TRAME corresponding to the time available to individually control the M*L LEDs 101 of the module 100 according to M*L specific brightness levels respectively. At each new period T_TRAME, the brightness levels of the M*L LEDs 101 can be modified.

[0025] The period T_TRAME is divided into L successive periods T1, T2, ... TL, for example of approximately the same duration, for example approximately equal to T_TRAME / L.

[0026] During each period Tj, the M LEDs 101(1,j), ... 101(M,j) of the same rank j of the module are simultaneously controlled in emission. The other LEDs 101 are deactivated.

[0027] More specifically, in this example, each period Tj is divided into two successive periods T_INIT and T_E. The period T_INIT is an initialization period and the period T_E is an emission period.

[0028] During the period T_INIT, the adjustment signals of the M LEDs 101(1,j),..., 101(M,j), received sequentially on the input terminal DATA of the module, are successively applied to the input terminals d in of the respective bias current sources 107 of the M bias circuits 103(i). More particularly, in this example, the period T_INIT is divided into M successive periods t1,..., tM, for example of substantially the same duration, for example substantially equal to T_INIT / M. At each period ti, with i ranging from 1 to M, the switch SW of the bias circuit 103(i) is controlled to the closed (conducting) state, the other switches SW being kept open (blocked). The adjustment signal applied to the DATA terminal is thus transmitted to the input terminal d_in of the bias source 107 of the bias circuit 103(i).Thus, the bias current sources 107 of the M bias circuits 103(i) are successively set to current values ​​corresponding to the respective desired brightness levels of the LEDs 101(1,j), ..., 101(M,j).

[0029] During the emission period T_E, the switches K(j) of the M bias circuits 103(i) are simultaneously closed, while the other switches K are all kept open. Thus, the LEDs 101(1,j), ..., 101(M,j) emit simultaneously at brightness levels set individually during the period T_INIT. The other LEDs 101 remain inactive. During the emission period T_E, the M switches SW can all be simultaneously controlled to the open state.

[0030] At the end of the transmission period T_E, a new period Tj+1 begins, during which the LEDs 101(1,j+1), ..., 101(M,j+1) are set individually and then simultaneously controlled in transmission.

[0031] We thus carry out, in parallel in the M groups of LEDs G(i), a sequential scanning of the L LEDs 101 of each group G(i).

[0032] An advantage of the architecture of the figure 1 and the operation described in relation to the figure 2 is linked to the provision of bias circuits 103(i) shared by groups of L LEDs 101. This makes it possible to limit the overall size of the LED control circuit. In particular, the size of the control circuit 105 is relatively small. For example, the control circuit 105 may comprise two shift registers, not detailed in the figure, of respectively L bits and M bits, to generate the signals LED_EN and W_EN respectively.

[0033] The number of connection terminals outside the module 100 is furthermore relatively small due to the time multiplexing of the data signals on a single DATA terminal. For example, in addition to the DATA terminal, the module 100 may comprise a VDD terminal for connection to a high supply potential and a GND terminal for connection to a low supply potential. Each bias current source 107 may have a supply node connected, for example connected, to the VDD terminal (connections not detailed on the figure 1 ). The GND terminal can be connected, for example, to the GNDLED node (connection not detailed on the figure 1 ). The module 100 may further comprise one or more control signal application terminals. For example, the module 100 may comprise a CT_W port consisting of three terminals (not detailed on the figure 1 ) for applying control signals to the shift register generating the W_EN signal, and a CT_LED port consisting of three terminals (not detailed on the figure 1 ) for applying control signals of the shift register generating the LED_EN signal. The CT_W port comprises, for example, a first terminal for applying a clock signal of the shift register generating the W_EN signal, a second terminal for applying a reset signal of the shift register generating the W_EN signal, and a third terminal for applying an initialization signal of the shift register generating the W_EN signal. The CT_LED port comprises, for example, a first terminal for applying a clock signal of the shift register generating the LED_EN signal, a second terminal for applying a reset signal of the shift register generating the LED_EN signal, and a third terminal for applying an initialization signal of the shift register generating the LED_EN signal.Thus, in this example, the module 100 has, in addition to the internal electrical connections between the LED chip and the control chip, 9 electrical connection terminals, intended to be connected respectively to corresponding connection terminals of the transfer substrate.

[0034] There figure 3 is a simplified schematic representation of another example of a module 300 of a display device according to one embodiment.

[0035] Module 300 of the figure 3 differs from module 100 of the figure 1 mainly in that, in the module 300, the LED chip comprises LEDs of several colors, i.e. having distinct central emission wavelengths. In the example of the figure 3 , the LED chip of the module 300 comprises LEDs of three distinct colors, for example first ones adapted to emit mainly red light, second ones adapted to emit mainly green light, and third LEDs adapted to emit mainly blue light. As in the example of the figure 1 , the module 300 comprises, attached and electrically connected to the LED chip, a control chip adapted to individually control the LEDs of the LED chip.

[0036] In the example of the figure 3 , the assembly comprising the M*L elementary LEDs 101, the M bias circuits 103(i) and the data input terminal DATA of the module of the figure 1 is replicated three times (once per color), with three types of elementary LEDs of different colors respectively. The M bias circuits 103(i) can optionally be adapted to provide different average currents depending on whether they are connected to the red, blue or green LEDs, but their structure remains unchanged.

[0037] On the figure 3 , the data input terminals corresponding to the three emission colors are designated respectively by the references DATA_R, DATA_G and DATA_B. In addition, the reference 301R designates the set of red M*L LEDs 101 and the corresponding bias circuits 103(i), the reference 301G designates the set of green M*L LEDs 101 and the corresponding bias circuits 103(i), and the reference 301B designates the set of blue M*L LEDs 101 and the corresponding bias circuits 103(i).

[0038] In the example of the figure 3 , the control circuit 105 is shared by the three colors. This circuit and its operation are for example identical or similar to what has been described in relation to the figures 1 et 2 .

[0039] So, if we refer to the figure 2 , during each period Tj of the period T_TRAME, the M LEDs 101 of the same rank j of the set 301R, the M LEDs 101 of the same rank j of the set 301G and the M LEDs 101 of the same rank j of the set 301B are simultaneously controlled in transmission, the other LEDs 101 being deactivated.

[0040] More particularly, during the initialization period T_INIT of the phase Tj, the adjustment signals of the M LEDs 101(1,j),..., 101(M,j) of the set 301R, received sequentially on the input terminal DATA_R of the module, are successively applied to the input terminals d_in of the respective bias current sources 107 of the M bias circuits 103(i) of the set 301R, in a manner identical or similar to that described above. In parallel, and in a similar manner, the adjustment signals of the M LEDs 101(1,j),..., 101(M,j) of the set 301G, received sequentially on the input terminal DATA_G of the module, are successively applied to the input terminals d_in of the respective bias current sources 107 of the M bias circuits 103(i) of the set 301G, and the adjustment signals of the M LEDs 101(1,j),..., 101(M,j) of the set 301B, received sequentially on the input terminal DATA_B of the module, are successively applied to the input terminals d_in of the respective bias current sources 107 of the M bias circuits 103(i) of the set 301B.

[0041] More particularly, at each period ti of the period T_INIT of the phase Tj, with i ranging from 1 to M, in each of the sets 301R, 301G and 301B, the switch SW of the bias circuit 103(i) is controlled to the closed (conducting) state, the other switches SW being kept open (blocked). The adjustment signal applied to the terminal DATA_R, respectively DATA_G, respectively DATA_B, is thus transmitted to the input terminal d in of the bias source 107 of the bias circuit 103(i) of the set 301R, respectively 301G, respectively 301B. Thus, in each of the assemblies 301R, 301G and 301B, the bias current sources 107 of the M bias circuits 103(i) are successively set to current values ​​corresponding to the respective desired brightness levels of the LEDs 101(1,j), ..., 101(M,j) of the assembly.

[0042] During the emission period T_E, in each of the sets 301R, 301G and 301B, the switches K(j) of the M bias circuits 103(i) are simultaneously closed, while the other switches K are all kept open. Thus, the LEDs 101(1,j), ..., 101(M,j) of the set emit simultaneously at brightness levels set individually during the period T_INIT. The other LEDs 101 remain inactive. During the emission period T_E, the M switches SW can all be simultaneously controlled to the open state.

[0043] In the example of the figure 3 , the module 300 has, in addition to the internal electrical connections between the LED chip and the control chip, 11 electrical connection terminals, intended to be connected respectively to corresponding connection terminals of the transfer substrate.

[0044] There figure 4 illustrates in more detail an example of a control circuit of a module according to one embodiment. The figure 4 illustrates more particularly an example of embodiment of a polarization circuit 103(i) of the module 100 of the figure 1 .

[0045] In this example, the bias circuit 103(i) comprises two transistors M1 and M2 forming a cascoded current source. In the example shown, the transistors M1 and M2 are P-channel MOS transistors. The transistor M1 has its source connected, for example connected, to the node VDD and its drain connected, for example connected, to an intermediate node n1. The transistor M2 has its source connected, for example connected, to the node n1 and its drain connected, for example connected, to the node out. The gate of the transistor M1 is connected, for example connected, to the node d_in. The gate of the transistor M2 is connected, for example connected, to a node for applying a fixed voltage Vcasc. In this example, each bias circuit 103(i) further comprises a switch SW' connecting the output node out of the current source 107 to the terminal DATA.The switch SW' has a first conduction node connected, for example connected, to the DATA terminal, and a second conduction node connected, for example connected, to the out node. The switch SW' has a control node connected, for example connected, to the W_EN node. . In each bias circuit 103(i), the switches SW and SW' of the bias circuit are for example simultaneously controlled in the same state. When the switches SW and SW' are in the closed state, the drain of the transistor M2 is connected, for example connected, to the gate of the transistor M1. The potential difference applied between the nodes d_in and VDD defines the intensity of the bias current ib delivered by the current source 107 on its output node out, and therefore the luminous intensity of emission of the LED 101(i,j) to which the current ib is applied. The gate-source capacitance of the transistor M1 (not detailed in the figure) makes it possible to maintain the voltage between the nodes d_in and VDD substantially constant throughout the emission duration of the LED.

[0046] Alternatively, the cascode circuit can be replaced by a simple transistor. In this case, transistor M2 is omitted, the drain of transistor M1 then being directly connected, for example connected, to the out node. More generally, the person skilled in the art will be able to provide other implementations of the current source 107. In another alternative, voltage control can be provided. In this case, transistor M2 can be omitted and transistor M1 can be replaced by an N-channel MOS transistor acting as a voltage follower.

[0047] In the example of the figure 4 , the control signal W_EN directly controls the switch SW connecting the input node d in of the current source 107 to the DATA terminal and the switch SW' connecting the output node out of the current source 107 to the DATA terminal. Furthermore, in this example, the switches K(1), ..., K(L) are controlled not directly by the signal LED_EN<1:L> but by a combination of the signal LED _EN<1:L> and the complemented signal W_EN(i). In other words, each switch K(j) is controlled to the closed (conducting) state only when the signal LED_EN <j>is high and the W_EN signal is in the low state (switch SW of circuit 103(i) open).

[0048] In the examples described above, if the initialization time of the LED bias circuits is neglected, the emission time T_E of each LED is substantially equal to T_TRAME / L. Thus, compared to a non-multiplexed display device, i.e. in which all the LEDs emit simultaneously during the entire period T_TRAME, the intensity of the bias current ib must be multiplied by L to obtain an equivalent brightness level. This is an advantage since LEDs generally have better external quantum efficiency (EQE) for high bias currents. The number M of bias circuits 103(i) and consequently the number L of elementary LEDs addressed by each bias circuit 103(i) can be chosen so as to maximize the external quantum efficiency.

[0049] There figure 5 is a diagram schematically representing the evolution of the external quantum efficiency EQE (on the ordinate) of an LED as a function of the density I (on the abscissa) of bias current applied to the LED.

[0050] As shown in the figure, the external quantum efficiency has a bell shape with a maximum for a current value IMAX. I0 denotes the average intensity of the range P1 in which we would like to polarize the LEDs in the case of continuous emission during the entire duration T_TRAME (i.e. in a non-multiplexed device). In this example, the value I0 is lower than the value IMAX.

[0051] Considering the example of the figure 1 , if the ratio IMAX / I0 is less than N-1, N being the number of sub-pixels, corresponding to the number of different views, of the multi-view pixel, we will preferably choose L equal to E[IMAX / I0]+1, where E[IMAX / I0] designates the integer part of IMAX / I0, and M equal to E[(N-1) / L]+1. We will then have an emission time per LED substantially equal to T_TRAME / L and consequently an average bias current ILED of each LED substantially equal to I0*L, that is to say substantially equal to I0*(E[IMAX / I0]+1). Thus, the current ILED approaches the current IMAX by higher value. This makes it possible to maximize the external quantum efficiency of the LEDs.

[0052] This configuration is illustrated schematically by the figure 6 (considering the durations of the T_INIT initialization phases as negligible).

[0053] If the ratio IMAX / I0 is greater than N-1, it is preferable that the emission time of each LED is less than T_TRAME / L to have an average bias current I0 approaching the current IMAX. Each period Tj of the period T_TRAME can then include a period of extinction of the LED. In other words, each LED emits during only a part of the period T_E allocated for emission.

[0054] This configuration is illustrated schematically by the figure 7 (again considering the durations of the T_INIT initialization phases as negligible).

[0055] On the figure 5 , we have schematically represented a range P2 centered on the current IMAX, corresponding to the transposition of the range P1 around the value IMAX due to the reduction in the effective emission time of each LED.

[0056] There figure 8 illustrates in more detail another example of a control circuit of a module according to one embodiment. The figure 8 illustrates more particularly an alternative embodiment of a polarization circuit 103(i) of the module 100 of the figure 1 . In the following description, only the differences from the bias circuit 103(i) of the figure 1 will be highlighted.

[0057] In this example, circuit 103(i) is a time-bias circuit. In other words, the bias voltage applied to the LEDs has a fixed value. The individual brightness levels of the LEDs are controlled by modulating the emission time of each LED. With a sufficiently high refresh rate, for example greater than or equal to 50 frames per second, retinal persistence makes it possible to average the luminance perceived from each LED during each period T_TRAME. For example, the modulation of the emission times of each LED is a binary-coded modulation, for example a BCM (Binary Code Modulation) type modulation.By designating by L_PERCUE the perceived luminance, by L0 the fixed luminance defined by the fixed bias voltage VREF applied to the LEDs, by n the number of bits on which the brightness information is coded, and by bk the bit of weight k of the coding, with k an integer ranging from 1 to n, we have: . L PERCUE = ∑ k = 1 μ bk L 0 M ∗ 2 n + 1 − k

[0058] In the example of the figure 8 , the current source 107 is omitted, and the switches K(1), ... K(L) directly connect the respective anodes of the LEDs 101(i,1), ... 101(i,L) to the same node of application of a fixed polarization potential VREF.

[0059] In this example, the brightness information is stored in binary form in a memory circuit or a register 801 (MEM) of the circuit 103(i), during the period ti of the phase T_INIT of each period Tj of the period T_TRAME.

[0060] The switch SW connects the DATA terminal to an input node d_in of the memory circuit 801. During the emission phase T_E of each LED 101(i,j) of the group G(i), the corresponding switch K(j) (i.e. of the same rank j) is controlled alternately to the closed state and to the open state according to a modulation pattern fixed by the n-bit digital code stored in the memory circuit 801. The other switches K(j) are kept open.

[0061] In the example of the figure 8 , the bias circuit 103(i) comprises L switches K' <1> , ... K' <l>. Each switch K' <j>has a first conduction node connected, for example connected, to an output node out of the memory circuit 801, and a second conduction node connected, for example connected, to a control node of the switch K(j) of the same rank j. During the emission phase T_E of each LED 101(i,j), the corresponding switch K'(j) is kept closed, the other switches K' of the circuit 103(i) being kept open. Thus the n bits of the brightness code are applied successively to the control node of the switch K(j), which makes it possible to control the average light power emitted by the LED 101(i,j).

[0062] In the example of the figure 8 , the control signal W_EN directly controls the switch SW connecting the DATA terminal to the input node d in of the memory circuit 801. Furthermore, in this example, the switches K'(1), ..., K' (L) are controlled not directly by the signal LED_EN<1:L> but by a combination of the signal LED_EN<1:L> and the complemented signal W_EN(i). In other words, each switch K' (j) is controlled to the closed (passing) state only when the signal LED_EN <j>is high and the W_EN signal is in the low state (switch SW of circuit 103(i) open).

[0063] More generally, the person skilled in the art will be able to adapt the embodiments described to other types of polarization circuits with time modulation of the emission time of the LEDs, for example circuits of the type described in patent application FR3076396A1.

[0064] There figure 9 illustrates in more detail another example of a control circuit of a module according to one embodiment. The figure 9 illustrates more particularly an alternative embodiment of a polarization circuit 103(i) of the module 100 of the figure 1 . In the following description, only the differences from the bias circuit 103(i) of the figure 1 will be highlighted.

[0065] In this example, circuit 103(i) combines brightness control by adjusting the strength of the bias current of the LEDs, as described in connection with figures 1 And 4 , and by temporal modulation, as described in relation to the figure 8 .

[0066] More specifically, in the example of the figure 9 , circuit 103(i) comprises the same elements as in the example of the figure 8 , arranged in substantially the same manner, and further comprises an adjustable current source 107 identical or similar to what has been described in connection with the figures 1 And 4 . The output node out of the current source is connected, for example connected, to the ends of the switches K(1), ... K(L) opposite the LEDs 101. The circuit 103(i) further comprises a switch SW' connecting the input node d in of the current source 107 to an additional data input terminal BIAS_DATA of the module, and a switch SW'' connecting the output node out of the current source 107 to the BIAS DATA terminal.

[0067] The switches SW' and SW" of the M circuits 103(i) are controlled by a signal WBIAS_EN on M bits, for example identical to the signal W_EN. In each circuit 103(i), the switches SW' and SW" are for example controlled simultaneously in the same state by the signal WBIAS_EN .

[0068] On the figure 9 , we have also shown a logic circuit 901, integrating in particular the switches K' <j>of the figure 8 . The logic circuit 901 receives the control signal LED_EN (on L bits) and the binary modulation codes supplied on the output node out of the memory circuit 801, and generates the control signals for the switches K(j). The logic circuit 901 makes it possible in particular to select the emitting LED, in a similar manner to what has been described in relation to the figure 8 .

[0069] Current bias allows an average luminance point L0 to be set individually for each LED, for example identical for all LEDs. This allows, for example, to compensate for possible manufacturing dispersions between the LEDs. For example, the adjustment value applied to the BIAS_DATA terminal is coded on 5 bits, which gives 32 possible values ​​of the bias current intensity ib. The time modulation controlled via the DATA terminal allows the desired gray levels to be set for each elementary LED of the module.

[0070] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the described embodiments are not limited to the aforementioned application to multi-view display devices, but can be applied to any display device comprising elementary modules each comprising several LEDs.

[0071] Furthermore, the embodiments described are not limited to the particular case described above in which each set of N LEDs distributed in M ​​groups G(i) comprises only LEDs of the same color. As a variant, each set of N LEDs and / or each group G(i) may comprise LEDs of different colors.

[0072] Furthermore, the embodiments described are not limited to the preferred examples described above in which a set of N LEDs is divided into M groups each comprising the same number L of LEDs. As a variant, different groups may contain different numbers of LEDs, at least one group comprising at least two LEDs. A bias circuit 103(i) is then provided per group of LEDs (i.e. M bias circuits), in a manner similar to that described above. The bias circuits 103(i) and their operation are identical or similar to that described previously, except that, in the groups comprising fewer LEDs, the missing LEDs are not addressed. In particular, the number of switches K(j) or K'(j) may be different in the different bias circuits 103(i).

[0073] Furthermore, it has been described above in relation to the figure 3 an example of a color module in which the number of LEDs of each color is identical. Alternatively, the number of LEDs may vary from one color to another. The person skilled in the art will know how to adapt the control circuit 105 accordingly. In the example of the figure 3 , we can also plan to duplicate one of the sets of LEDs, for example in order to have a more homogeneous polarization in the case where one of the colors has a different output from the others.

[0074] It should be noted that in this description, a pixel is understood to mean a pixel of the image that one wishes to display. In the case where an elementary module integrates several sub-pixels, for example N sub-pixels, each sub-pixel corresponds to a pixel of one of the N images that one wishes to render (with N different viewing angles). If an image is made up of a matrix of X*Y pixels, then the i-th sub-pixel associated with a given pixel corresponds to a pixel of the same coordinate (x,y) in the i-th image.

[0075] As a variant, an elementary module within the meaning of the present application may integrate several pixels of the same image to be displayed. In the case of elementary modules each comprising a single pixel, the modules may be spaced apart from each other on the transfer substrate. The surface area of ​​the control chip of each module may then be greater than the surface area of ​​the LED chip of the module. This makes it possible to save the surface area of ​​LED material compared to the silicon surface area of ​​the control chip. In the case of elementary modules each comprising several pixels, provision may be made to laterally attach several elementary modules to form a display screen of larger dimensions. The control chip of each module will then preferably have substantially the same lateral dimensions as the LED chip of the module.Alternatively, the control chip of each module may have a smaller area than the area of ​​the LED chip, although this is unlikely since the area of ​​the control chip is generally constrained, especially when the control chip has a single semiconductor layer and not a "3D" circuit.

[0076] Furthermore, in the present description, the term "chip" has been used to designate the presence in each module of a control chip and an LED chip. In practice, each chip comprises semiconductor components formed in and / or on a layer of a semiconductor material. Thus, the control chip comprises, among other things, transistors, for example of the MOS type, comprising, as is well known, portions formed in a semiconductor layer (for example silicon) and portions (for example metallic, insulating) formed above the semiconductor layer, and covered with dielectric materials in which metallic connection lines between components are formed. Similarly, the LED chip comprises light-emitting diodes formed at least in part in one or more superimposed semiconductor layers.The LED chip can also include a set of other layers to form colored filters for example, or light conversion elements.

[0077] The control and LED chips can be manufactured separately and then bonded together. Alternatively, one chip can be built directly onto the other chip using a sequential manufacturing process.

[0078] It should also be noted that a chip, in particular the control chip, can in practice be made up of several "stages" or in other words several chips superimposed to form a "3D" circuit. The English word "tier" is often used to designate the different stages each comprising a semiconductor layer with components (transistors, resistors, etc.), also called "front-end" in English, and an alternation of dielectric and conductive layers to form an electrical interconnection network, also called "back-end" in English.

[0079] Finally, the practical implementation of the described embodiments is within the reach of the person skilled in the art from the functional indications given above. In particular, the production of the elementary LEDs and the control circuits of the modules is within the reach of the person skilled in the art from the functional indications of the present description.< / j> < / j> < / j> < / l> < / j> < / j>

Claims

1. Display device comprising a transfer substrate and a plurality of elementary modules (100; 300) arranged in an array on the transfer substrate, each module forming a compact assembly of one or a plurality of electronic chips, each module comprising a connection surface comprising connection pads bonded and electrically connected to corresponding connection pads of the transfer substrate, intended to convey signals for powering and controlling the module, each module enabling to display at least one pixel of an image, each module comprising: - a first assembly of N electroluminescent diodes (101(i,j)), LED, distributed into M groups (G(i)), at least one of the M groups comprising at least two LEDs, where N and M are integers, with M greater than or equal to 2; and - a control circuit comprising M bias circuits 103(i)) respectively associated with the M groups of LEDs, each bias circuit (103(i)) being shared by the LEDs of the corresponding group (G(i)) and being adapted to successively controlling the emission of the LEDs of the group, wherein each module comprises one connection pad (DATA; DATA_R, DATA_G, DATA_B), called data pad, intended to receive individual signals for adjusting the emission powers of the N LEDs (101(i,j)) of the module, multiplexed in the time domain, and wherein in each module, each bias circuit (103(i)) of the module comprises a unique light power adjustment node (d_in) and a unique first selection switch (SW) coupling said data pad of the module to said light power adjustment node (d_in) of the bias circuit, each bias circuit (103(i)) of the module further comprising an assembly of second selection switches (K(1), ... K(L)) respectively coupling the LEDs (101(i,j)) of the group (G(i)) corresponding to a same node for supplying a bias current (ib) of the bias circuit (103(i)), said bias current received by a selected LED being a function of the adjustment signal transmitted on said light power adjustment node (d_in), wherein, in each module (100; 300), the control circuit is configured to, during a period T_TRAME, individually adjust the respective emission powers of the N LEDs (101(i,j)), period T_TRAME being divided into L successive periods Tj, with L an integer and j an integer ranging from 1 to L, each period Tj comprising an initialization period T_INIT followed by an emission period T_E, the control circuit being configured to, at each period Tj, during initialization period T_INIT, successively apply to the M bias circuits (103(i)) a signal for individually adjusting the desired emission power of the LED of rank j of the corresponding group of LEDs G(i), and then, during the emission period (T_E), simultaneously control the emission of the M LEDs of rank j according to said individual adjustment signals, and wherein, during each initialization period T_INIT, the first switches (SW) of the bias circuits are successively turned on to transmit a signal received on said data pad to a light power adjustment node (d_in) of the group selected by said first turned on switch (SW), the second switches (K(1), ... K(L)) then being off, and wherein, in each bias circuit, during each emission period T_E, a single switch from among the second switches (K(1), ... K(L)) is turned on to select a single LED per group and apply thereto a bias current which is a function of the adjustment signal transmitted on said light power adjustment node of the associated bias circuit.

2. Display device according to claim 1, wherein, in each module (100; 300), each of the M groups (G(i)) comprises a same number of LEDs.

3. Display device according to claim 1 or 2, wherein, in each module (100; 300), the bias circuits (103(i)) are configured so that, in each group (G(i)), for each LED (101(i,j)) in the group, an emission period (T_E) of the LED is simultaneous with a period of emission (T_E) of a corresponding LED (101(i,j)) of each other group.

4. Display device according to any of claims 1 to 5, wherein, in each module (100; 300), each bias circuit (103(i)) comprises a bias current source (107) having an adjustable intensity, the emission power of each of the LEDs (101(i,j)) in the corresponding group being adjusted by varying the current supplied by said current source (107).

5. Display device according to any of claims 1 to 3, wherein, in each module (100; 300), each bias circuit (103(i)) comprises a fixed bias voltage source, the emission power of each of the LEDs (101(i,j)) in the corresponding group being adjusted by modulation of the emission time of the LED, for example, according to a binary code modulation.

6. Display device according to any of claims 1 to 3, wherein, in each module (100; 300), each bias circuit (103(i)) comprises a bias current source having an adjustable intensity, the emission power of each of the LEDs (101(I,j)) in the corresponding group being adjusted by varying the current supplied by said current source (107) and by modulation of the emission time of the LED, for example, according to a binary code modulation.

7. Display device according to any of claims 1 to 6, wherein, in each module (100; 300), the N LEDs of the first assembly are of a same first color, the module further comprising a second assembly of N LEDs (101(i,j)) of a same second color distributed into M groups (G(i)), at least one of the M groups comprising at least two LEDs, and a third assembly of N LEDs (101(i,j)) of a same third color distributed into M groups (G(i)), at least one of the M groups comprising at least two LEDs.

8. Display device according to any of claims 1 to 7, wherein, in each module (100; 300), the first LED assembly forms a LED chip and the control circuit is a CMOS-type integrated circuit forming a control chip placed against a surface of the LED chip.

9. Display device according to any of claims 1 to 8, wherein each module (100; 300) is configured to display a single pixel of same spatial coordinate for a set of N images of same dimensions, the N LEDs of the module corresponding to N sub-pixels of a same pixel, each subpixel enabling to display a pixel of one of the N images respectively corresponding to N viewing angles of a multi-view display device.

10. Display device according to any of claims 1 to 9, wherein each module (100; 300) further comprises at least another connection pad, called control pad, allowing the reception of control signals used to generate internal signals for controlling the first and second selection switches.

11. Device according to claims 7 and 10, wherein the same internal controls signals are used to control the switches of the first, second, and third LED assemblies, and wherein first, second, and third data pads are respectively coupled to the first, second, and third LED assemblies to transfer in parallel light intensity adjustment signals to each of the three LED assemblies.

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