Detection and correction of errors using limited error correction data
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- RAMBUS INC
- Filing Date
- 2023-06-13
- Publication Date
- 2026-06-03
AI Technical Summary
Existing error correction techniques require substantial processing time and memory access bandwidth when using sub-threshold numbers of error correction symbols, leading to irreversible data loss in cases of chip failure, especially when additional data is stored alongside the message.
The implementation of reduced error locator polynomials allows for fast identification of failed memory devices using fewer than 2L error correction symbols, enabling efficient detection and correction of errors confined to a single chip, even with sub-threshold error correction symbols, by simplifying the error locator polynomial to have fewer degrees of freedom.
This approach enables fast and efficient identification of errors using limited error correction symbols beyond the Singleton bound, ensuring reliable recovery of data even when errors are confined to a particular memory chip or result in a total chip failure, with reduced processing time and memory access requirements.
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