Analog circuit having reconfiguration means for a stress test and / or for an iddq test, and associated methods

Abstract

The invention relates to an analog circuit (1) based on MOS, BCMOS or CMOS. The analog circuit (1) is designed to fulfil a predetermined circuit purpose in a normal state of the analog circuit (1). The analog circuit (1) has an analog input or output signal or an analog signal within the analog circuit (1). The analog circuit (1) is coupled to a test logic (38). The test logic (38) is designed to put the analog circuit (1) into the normal state and at least a first test state. The analog circuit (1) comprises first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) which are designed to carry out a function of the analog circuit (1) in accordance with the predetermined circuit purpose during normal operation. According to the invention, the analog circuit (1) further comprises second components (S1 to S9; Gl to G9) which are designed to enable the test logic (38) to set switching states of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in the case of the at least first test state of the analog circuit (1).

Description

Analog circuit with means for reconfiguration for a stress test and / or for an IDDQ test and associated methods Field of invention The invention relates to an IDDQ-testable and / or stress-testable analog circuit. General introduction A key prerequisite for the use of microelectronic circuits in motor vehicles is high quality and a low failure rate. When manufacturing mixed-signal CMOS circuits for the automotive industry, it is therefore essential that the microelectronic circuits are tested after production with sufficient test coverage. For example, the IDDQ test is well-known for the digital circuit components of such automotive microelectronic circuits. IDDQ testing is a method for testing CMOS integrated circuits for the presence of manufacturing defects. It relies on measuring the supply current (IDD) in the quiescent state (when the circuit is not switching and the inputs are held at static values). The supply current consumed in this state is commonly referred to as the IDDQ quiescent current, or IDD quiescent current. The supply line is often referred to as the VDD line, and the associated supply current is referred to as the IDD current, hence the name. The IDDQ test is based on the principle that in a correctly functioning digital CMOS circuit, there is no static current path between the positive and negative supply voltage lines in the idle state. At the end of the microelectronic circuit production, a fully automated test device tests the finished microelectronic circuit. Typically, the digital circuit components of themicroelectronic circuit is clocked with a clock pulse. With each clock edge, circuit nodes within the digital circuit part of the microelectronic circuit change their logical states. These logical states of these circuit nodes are linked to voltage levels of the potential of these circuit nodes relative to a reference node at a reference potential. Since the circuit nodes always have a parasitic node capacitance, this capacitance must be electrically recharged to the new electrical potential when the logical state and thus the electrical potential changes. Therefore, an electrical recharge current flows as a result of the clocking of the digital circuit part of the microelectronic circuit.When the clock is stopped, the circuit nodes in standard CMOS circuits typically maintain their electrical potentials and thus their logic levels, since within the digital part of the microelectronic circuit, each potential current path typically comprises at least one P-channel transistor and one N-channel transistor, one of which is always off and the other complementarily conducting. Thus, apart from leakage currents, after the clock of the digital part of the microelectronic circuit is stopped, no electrical current can flow from the positive supply voltage line of the microelectronic circuit to the negative supply voltage line of the microelectronic circuit via this digital part. The state of the digital part of the microelectronic circuit with the clock switched off is the aforementioned idle state of the digital part of the microelectronic circuit. In reality, however, a small leakage current flows from the positive supply voltage line of the microelectronic circuit to the negative supply voltage line of the microelectronic circuit through this digital part when the digital part's clock cycles are stopped. Normally, this leakage current is very small, essentially negligible. If one of the digital transistors in the digital part is faulty, this very often leads to an increase in its leakage current. This is particularly measurable when it should actually be off due to its control. In order to test this transistor, the test device controls the microelectronic circuit with special signal sequences, so-called patterns. The transistor to be tested is located in one or more current paths between the positive supply voltage line and the negative supply voltage line. The test vectors that the test system applies to the microelectronic circuit during the test are designed in such a way that when the test system stops clock pulses, firstly at least one time position in the test vectors the transistor to be tested is blocked and secondly at this time position simultaneously in at least one of the current paths in which the transistor to be tested is located, all other transistors of this current path are switched on. If the transistor under test exhibits an increased leakage current, an increased leakage current flows through this current path between the positive supply voltage line and the negative supply voltage line. The test system detects the electrical current in one of the two supply voltage lines. The test performed by the test system can use this current value and conclude that one or more transistors are defective if this current value is too high, particularly if it exceeds a threshold value. In the event of a fault, the increase in the current value of the leakage current through the tested transistor compared to the current value for the fault-free case is typically in the range of several orders of magnitude. This is why it is even possible to detect this fault based on the supply current.Another advantage of the IDDQ test is that the test system can check the microelectronic circuit for a relatively large number of potential transistor faults with just a few measurements. Another advantage is that the test system can detect transistor faults that cannot be detected using conventional test vectors (patterns) for static faults. The IDDQ test The IDDQ test is somewhat more complex than simply measuring the supply current. For example, if a line is shorted to the positive supply voltage, it will not draw any additional current even if a logic circuit generating the signal attempts to pull it high. However, if the logic circuit attempts to pull the signal low, a sharp increase in leakage current results. This increase in the magnitude of the leakage current above a current threshold signals a failing component. The test system discards such failing components. It is important to note that IDDQ test inputs only require controllability of the logical states of the nodes of the digital part; they do not require observability of these nodes in the sense of logical observability.The fault effects can be observed via the leakage current by observing and evaluating the current consumption of the circuit's supply voltage terminals. This controllability of the states of the control signals of the transistors of analog circuits is precisely the problem why IDDQ tests are carried out in analog parts of mixed-signal circuits according to the State-of-the-art technology is not applicable. Therefore, mixed-signal circuits often have separate positive analog supply voltage lines that supply the analog part with electrical power, and digital positive supply voltage lines that supply the digital part with electrical power. Additional circuits allow the analog circuit parts to be separated from the digital circuit parts. This document explains the problem using a simple differential amplifier stage, presented here as an example of an analog circuit. Figure 1 shows such an example analog circuit. However, the principles described here and proposed below can be applied to other analog circuits. The voltage source 2 supplies the exemplary analog circuit 1 with electrical energy. A current source 4 draws electrical energy from the supply voltage line 3 and feeds a reference current 5 into a first node 6. The first transistor 7, connected as a MOS diode, acts as a reference node, draws this reference current 5 from the first node 6 and diverts it to the reference potential line 8. The first transistor 7, connected as a MOS diode, converts the reference current 5 into a reference voltage 27. The reference voltage 27 is applied between the first node 6 and the reference potential line 8. A second transistor 9 forms a current mirror with the first transistor 7, connected as a MOS diode. The second transistor 9 therefore operates as a current source for the differential stage comprising the third transistor 10, the fourth transistor 11, and the fifth transistor 12, and the sixth transistor 13.The control electrode 28 of the third transistor 10 and the control electrode 29 of the fourth transistor 11 form the differential input of the exemplary differential amplifier. The fifth transistor 12 is connected as a MOS diode and serves as the load resistor of the left amplifier branch consisting of the third transistor 10 and the fifth transistor 12. The sixth transistor 13 is connected as the current source of a current mirror consisting of the sixth transistor 13 and the MOS diode 12 and serves as the load resistor of the right amplifier branch consisting of the fourth transistor 11 and the sixth transistor 13. The seventh transistor 15 takes the signal at the second node 14 between the fourth transistor 11 and the sixth transistor 13 and amplifies the power as part of a source-follower circuit comprising the seventh transistor 15 and the eighth transistor 16. The eighth transistor 16 operates as a current source transistor and thus as the load resistor of the source-follower circuit. The eighth Transistor 16 is part of a current mirror consisting of the eighth transistor 16 and the first transistor 7 connected as a MOS diode. An inverter 17 generates an inverted digital transport clock 19 from a digital transport clock 18 for subsequent transfer gates. In the example of Figure 1, a first transfer gate comprising a ninth transistor 20 and a tenth transistor 21 can charge an intermediate node 25 to the potential of the output of the source follower 26 when the digital transport clock 18 is at a high level. The inverted digital transport clock 19 is then at a low level. If the digital transport clock 18 is at a low level and thus the inverted digital transport clock is at a high level, the first transfer gate comprising the ninth transistor 20 and the tenth transistor 21 is blocked. In this case, the intermediate node 25 essentially maintains its voltage level due to parasitic capacitances. In the example of Figure 1, a second transfer gate comprising an eleventh transistor 22 and a twelfth transistor 23 can charge an input node 24 of a subsequent analog circuit to the potential of the intermediate node 25 when the digital transport clock 18 is at a high level. The inverted digital transport clock 19 is then at a low level. If the digital transport clock 18 is at a low level and thus the inverted digital transport clock 19 is at a high level, the second transfer gate comprising the eleventh transistor 22 and the twelfth transistor 23 is blocked. In this case, the input node 24 essentially maintains its voltage level due to parasitic capacitances. A thirteenth transistor 30 can connect the intermediate node 25 to the reference potential 8. A first problem is that the reference voltage source consisting of current source 4 and first transistor 7 has a permanent quiescent current due to the MOS diode connection of the first transistor 7. This current value is far above the leakage current of a blocked first transistor 7. Therefore, the first transistor 7 is not accessible to the IDDQ test in the circuit of Figure 1. A second problem is that the second transistor 9 always has such a reference voltage at its control input, its gate, that it operates as a current source and therefore also has a continuous quiescent current. This current value is far above the leakage current. a blocked second transistor 9. The second transistor 9 is therefore not accessible to the IDDQ test in the circuit of Figure 1. A third problem is that the eighth transistor 16 always has such a reference voltage at its control input, its gate, that it operates as a current source and therefore also has a continuous quiescent current. This current value is far above the leakage current of a blocked eighth transistor 16. Therefore, the eighth transistor 16 is not accessible to the IDDQ test in the circuit of Figure 1. A fourth problem is that the reference voltage source consisting of the second transistor 9 and the fifth transistor 12 has a permanent quiescent current due to the MOS diode connection of the fifth transistor 12 when the third transistor 10 is on. The current value of the fifth transistor 12 is typically far above the leakage current of a blocked fifth transistor 12. Therefore, the fifth transistor 12 is not accessible to the IDDQ test in the circuit of Figure 1. A fifth problem is that the sixth transistor 13 always has such a reference voltage at its control input, its gate, that it operates as a current source and therefore also has a continuous quiescent current. This current value is far above the leakage current of a blocked sixth transistor 13. Therefore, the sixth transistor 13 is not accessible to the IDDQ test in the circuit of Figure 1. A sixth problem is that the seventh transistor 15 always has such a voltage at its control input, its gate, that it is not free of quiescent current. Therefore, it also has a continuous quiescent current. This current value is far above the leakage current of a blocked seventh transistor 15. Therefore, the seventh transistor 15 is not accessible to the IDDQ test in the circuit of Figure 1. Due to the current source function of the second transistor 9, a quiescent current flows through both the third transistor 10 and the fourth transistor 11. Although one of the two transistors can be switched off via the input, the other amplifier branch in the supply lines 3, 8 still generates a quiescent current that is far higher than the leakage current of blocked transistors. Therefore, the third transistor 10 and the fourth transistor 11 are not accessible to the IDDQ test in the circuit of Figure 1. For the same reason, the The fifth transistor 12 and the sixth transistor 11 in the circuit of Figure 1 are therefore also not accessible to the IDDQ test. Due to the current source function of the eighth transistor 16, a quiescent current flows through both the eighth transistor 16 and the seventh transistor 15. The seventh transistor 15 and the eighth transistor 16 are therefore not accessible to the IDDQ test in the circuit of Figure 1. In contrast, the transfer gates are not necessarily subject to leakage current. If the output 26 of the source follower and the intermediate node 25 are at the same or substantially the same potential, no electrical leakage current flows through the ninth transistor 20 and the tenth transistor 21. Thus, for an IDDQ test of the ninth transistor 20 and the tenth transistor 21s, the ability to stimulate a leakage current through these transistors is already lacking. The same applies to the eleventh transistor 22 and the twelfth transistor 23. Thus, for an IDDQ test of the eleventh transistor 22 and the twelfth transistor 23, the ability to stimulate a leakage current through these transistors is also lacking. However, in the interest of improved functional safety, stress testing of all transistors of a mixed-signal circuit in the IDDQ test with an increased operating voltage is desirable in order to be able to detect imperfectly manufactured transistors and circuit components and, if necessary, to activate errors that have not yet been activated by the stress voltage. Thus, there is a current problem in generating test vectors for analog components and a need for the applicability of IDDQ testing to transistors in the analog portion of mixed-signal circuits. For the reasons mentioned above, functional test patterns for large digital control buses of analog components within mixed-signal circuits generally have far too limited test coverage. Furthermore, designers cannot generate test patterns for the analog circuit components fully automatically, as is the case with digital circuits. Fully automatic test vector generation (ATPG) for the analog circuit components would be very helpful for optimal test coverage. The control signals of the digital component that control the analog component (hereinafter referred to as D2A control signals) must generally not be freely modified to avoid short circuits, damage, and the like. The static current consumption of the analog component and its scatter are significantly higher than the expected leakage currents of the transistors in the event of a fault. Therefore, specifying a test threshold for the quiescent current is at least difficult, if not impossible. Experience has shown that a voltage stress with an imposed elevated voltage between the positive supply voltage line 3 of the analog section of the mixed-signal circuit and the reference potential line 8 VDDA places almost no stress on any of the transistors in the analog section. The experiments and investigations conducted during the development of the technical teaching presented here resulted in a stress level of only 2% of the transistors in the analog section. This value can be classified as "untestable." Implementing a bus system from the digital part of a mixed-signal circuit to the analog part of the mixed-signal circuit typically requires a large number of memory cells (latches), which can comprise a large number of transistors in the 5V range and have significant gate electrode areas. In the interest of a zero-defect strategy, such a large gate electrode area should be subjected to a voltage stress test. US 2005 / 0 024 075 A1 discloses a device in which faulty states are generated in analog circuits by using "fault injection transistors," which allow the detection of faulty states. However, the technical teaching of US 2005 / 0 024 075 A1 does not disclose a method or associated devices that allow the performance of an IDDQ test similar to that of digital circuits. The technical teaching of US 2005 / 0 024 075 A1 discloses the injection of faulty node potentials by means of "fault injection transistors." In this way, US 2005 / 0 024 075 A1 improves the stimulability of the analog circuits under test. However, the technical teaching of US 2005 / 0 024 075 A1 does not solve the problem of the lack of IDDQ testability of an analog circuit. The circuit examples cited in US 2005 / 0 024 075 A1 are not all fully IDDQ testable. "Fully" refers to an IDDQ test of ALL analog transistors. The technical teaching of US 2005 / 0 024 075 A1 therefore solves a completely different problem. The technical teaching of US 2005 / 0 024 075 Al provides for the ground lead of an analog CMOS circuit block - referred to as CUT in US 2005 / 0 024 075 A1 - a test block - in the US 2005 / 0 024 075 A1 referred to as BICS - and use it to monitor the operating current of the analog circuit block CUT. However, this is not an IDDQ test as understood in test technology. We quote Wikipedia here (available at https: / / en.wikipedia.org / wiki / lddq_testing): "Iddq testing is a method for testing CMOS integrated circuits for the presence of manufacturing faults. It relies on measuring the supply current (Idd) in the quiescent state (when the circuit is not switching and inputs are held at static values). The current consumed in the state is commonly called Iddq for Idd (quiescent) and hence the name. Iddq testing uses the principle that in a correctly operating quiescent CMOS digital circuit, there is no static current path between the power supply and ground, except for a small amount of leakage. Many common semiconductor manufacturing faults will cause the current to increase by orders of magnitude, which can be easily detected. This has the advantage of checking the chip for many possible faults with one measurement. Another advantage is that it may catch faults that are not found by conventional stuck-at fault test vectors. Iddq testing is somewhat more complex than just measuring the supply current. If a line is shorted to Vdd, for example, it will still draw no extra current if the gate driving the signal is attempting to set it to '1'. However, a different input that attempts to set the signal to 0 will show a large increase in quiescent current, signalling a bad part. Typical Iddq tests may use 20 or so inputs. Note that Iddq test inputs require only controllability, and not observability. This is because the observability is through the shared power supply connection." The German translation reads: "The Iddq test is a method for testing CMOS integrated circuits for the presence of manufacturing defects. It is based on measuring the supply current (Idd) in the quiescent state (when the circuit is not switching and the inputs are held at static values). The current consumed in this state is commonly referred to as Iddq for Idd (quiescent current), hence the name. The Iddq test is based on the principle that in a correctly operating digital CMOS circuit, there is no static current path between the power supply and ground in the idle state, except for a small amount of leakage current. Many common defects in semiconductor manufacturing result in an increase in current by orders of magnitude, which can easily be This has the advantage that the chip can be tested for many possible defects with a single measurement. Another advantage is that it can detect defects that cannot be found with conventional test vectors for dead-end defects. Iddq testing is somewhat more complex than simply measuring the supply current. For example, if a line is shorted to Vdd, it won't draw any additional current even if the gate controlling the signal tries to force it to '1'. However, another input trying to force the signal to 0 will indicate a sharp increase in quiescent current, signaling a bad component. For typical Iddq tests, approximately 20 inputs can be used. Note that Iddq test inputs require only controllability, not observability. This is because observability is achieved through the common power supply connection. However, the technical teaching of US 2005 / 0 024 075 A1 still shows static current paths between the positive and negative supply voltage. If in section

[0042] When US 2005 / 0 024 075 Al refers to "IDDQ. current", this is not a leakage current of a digital circuit in the static switching state, but the quiescent current of an analog circuit that originates from a static current path. The technical doctrine of US 2005 / 0 024 075 A1 does not allow for the fully automated generation of IDDQ test patterns. This makes it difficult to demonstrate appropriate test coverage in circuit designs with functional safety requirements according to ISO 26262. The technical teaching of US 2005 / 0 024 075 Al also does not teach any suggestions on how to deal with feedback branches within the analog circuit In the circuit shown in Figure 4 of US 2005 / 0 024 075 A1, an operating current always flows, even in a test state, and not just the leakage current of the blocked transistors. Therefore, US 2005 / 0 024 075 A1 does NOT disclose a circuit that is IDDQ testable in any state, as defined by the document presented here or by the Wikipedia definition. From JP 2003-156545 A, a semiconductor chip is known in which an analog circuit and a digital circuit are integrated. According to the technical teaching of JP 2003-156545 A, THIS semiconductor chip is mounted. A common power supply terminal of the semiconductor chip is used according to the technical teaching of JP 2003-156545 A to form a semiconductor device which supplies a power supply voltage to the analog circuit and the digital circuit, for current leakage in the digital circuit. According to JP 2003-156545 A, the method of JP 2003-156545 A consists of interrupting the power supply line from the power supply terminal to the digital circuit at the time of testing and placing the digital circuit in the test mode according to JP 2003-156545 A. Task The proposal is therefore based on the task of creating a solution that does not have the above-mentioned disadvantages of the prior art and has further advantages. This problem is solved by the technical teaching of the independent claims. Further embodiments may be the subject of subclaims. Solution to the task The basic idea of ​​the technical teaching presented here is to switch the transistors of the analog part of the mixed-signal circuit by means of additional switching transistors in a test state of the analog circuit 1 in such a way that essentially a CMOS logic circuit is produced which can be stimulated with test vectors like a normal CMOS logic circuit and for which the IDDQ test vectors can be generated fully automatically by means of an ATPG program. For this purpose, the technical teaching presented here proposes providing at least one IDDQ test state for the exemplary analog circuit 1. Furthermore, the technical teaching presented here proposes inserting additional switches into the circuit of the analog circuit elements, which switches have at least one switching state during normal operation of the exemplary analog circuit 1 and have at least one IDDQ switching state. The invention thus relates to an analog circuit 1 based on MOS, BiCMOS, or CMOS, wherein the analog circuit 1 is configured to fulfill a predetermined circuit purpose in a normal state of the analog circuit 1. The analog circuit 1 has one or more input signals and / or one or more output signals. The analog circuit 1 typically comprises one or more analog signals within the analog circuit 1. The analog circuit (1) is proposed to be coupled to a test logic 38, which puts the analog circuit 1 into the normal state and, depending on the control of the test logic 38 by an external measuring system, into at least a first test state and / or possibly further test states. The analog circuit 1 comprises first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) which carry out the function of the analog circuit 1 in accordance with the predetermined circuit purpose of the analog circuit 1 in the normal state of the analog circuit 1.These first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) thus represent the actual analog circuit 1 or at least essential parts of the analog circuit 1. These first components are preferably MOS transistors or bipolar transistors. Such first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) then typically each have a control electrode, by means of which the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) can also be operated as switches. The first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) can then be assembled in one. During operation as a switch, each switch assumes an on-state and an off-state as its respective switching states. For the purposes of this document, the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are fully switched on, i.e. conductive. Fully switched on means that the conduction resistance (RoN resistance) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), i.e. the transistors, is equal to the minimum conduction resistance of these first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30). The first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are typically completely switched off in the off state, i.e., blocking. Completely switched off means that the conduction resistance (R 0FF -resistance) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), i.e. the transistors, up to a deviation of less than 25% the maximum conduction resistance of these first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30). The analog circuit (1) preferably comprises second components (S1 to S9; G1 to G9). The test logic 38 uses the second components (S1 to S9; G1 to G9) to set these switching states of one or more of the first components (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in the first test state of the analog circuit 1. The control electrode (33, 34, 36, 37) of at least one first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is not directly connected to an input signal or not directly to an output signal. The IDDQ test of such an analog circuit 1 is not described in the prior art. In the first test state, the test logic 38 now disconnects this control electrode (33, 34, 36, 37) of this first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is separated from the rest of the analog circuit (1) by means of at least one switch (S1, S2, S3, S4). As a result, this control electrode (33, 34, 36, 37, 39) of this first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) floats. It is thus susceptible to influence. However, its potential is not fixed. Thus, the switching state of this first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is also not fixed. To specify this switching state, the test logic 38 switches this control electrode (33, 34, 36, 37, 39) of this first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) into an on state or off in an off state by means of first means (G1, G2, G5, G6).In the normal state, the test logic 38 controls these first means (Gl, G2, G5, G6) in such a way that these first means (Gl, G2, G5, G6) do not influence the control electrode (33, 34, 36, 37, 39) of this first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in the normal state of the analog circuit 1. Preferably, the first means (G1, G2, G5, G6) are tri-state drivers whose output switches the first test logic 38 to the tri-state state with a high-impedance output resistance in the normal state and to a low-impedance low-level or high-level state in the first test state. The output of the respective tri-state driver is connected to the respective control electrode (33, 34, 36, 37, 39) of a respective first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30). In the normal state, the test logic 38 connects the control electrode (33, 34, 36, 37, 39) of said first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) by means of the switch (S1, S2, S3, S4) to a node of the rest of the analog circuit (1) and thus ensures the normal function of the analog circuit 1 in the normal state. The exemplary analog circuit 1 preferably has at least one normal state and a first IDDQ test state and a second IDDQ test state. In the normal state, the exemplary analog circuit 1 performs its intended normal operation. In the first IDDQ test state, all P-channel transistors of the exemplary analog circuit 1 are preferably completely turned on and all N-channel transistors of the exemplary analog circuit 1 are completely turned off. In the second IDDQ test state, all P-channel transistors of the exemplary analog circuit 1 are preferably completely turned off and all N-channel transistors of the exemplary analog circuit 1 are completely turned on. In order to make this possible, the technical teaching presented here proposes to separate all feedback branches by feedback switches in said first IDDQ test state and in said second IDDQ test state. The invention comprises a modified analog circuit that can be manufactured, for example, using MOS, BiCMOS, or CMOS semiconductor technology. Semiconductor technologies that are functionally equivalent to such MOS, BiCMOS, or CMOS semiconductor technologies are encompassed by the term "MOS, BiCMOS, or CMOS" within the meaning of the present document. A semiconductor technology is functionally equivalent if it provides semiconductor switches that have a first terminal, a second terminal, and a control terminal, and wherein the semiconductor switch opens or closes the electrical connection between the first terminal and the second terminal depending on the potential or the input current at the control terminal. Any leakage current is not taken into account in this definition. The technical teaching presented here is intended to relate to analog circuits in general. The analog circuit is preferably part of a microintegrated circuit. Such an analog circuit typically fulfills a predetermined circuit purpose during the intended operation of the circuit in which the analog circuit is used. This predetermined circuit purpose can be, for example, an amplifier, a differential amplifier, a current source, a voltage source, an analog multiplier, an analog multiplexer, an analog filter, an oscillator, a delay line, a phase shifter, an analog PLL, a reset circuit, an electronic fuse, an analog adder, an analog subtractor, an analog differentiator, an analog integrator, etc., and their interconnections, without limiting the technical teaching presented here to this.The text presented here refers to the following books as examples:. Dietmar Ehrhardt, "Integrated Analog Circuit Technology: Technology, Design, Simulation, and Layout," June 28, 2000, Vieweg Verlagsgesellschaft; 2000th edition (June 28, 2000), ISBN-10: 3528038608, ISBN-13: 978-352803860 Phillip E. Allen (author), Douglas R. Holberg, "CMOS Analog Circuit Design", Oxford University Press; 3rd edition. International (July 13, 2012), ISBN-10: 0199937427, ISBN-13: 978-0199937424 Saggio, Giovanni, Tor Vergata, "Principles of Analog Electronics", ASIN: 1466582014, Taylor & Francis Inc, January 29, 2014, ISBN-10: 9781466582019, ISBN-13: 978-1466582019 Ulrich Tietze, Christoph Schenk, "Semiconductor Circuit Technology" Hardcover - July 5, 2019, Springer Vieweg; 16th, expanded, and updated edition, 2019 Edition, ISBN-10: 3662485532, ISBN-13: 978-3662485538 For an analog circuit to be considered an analog circuit within the meaning of this document, the analog circuit should have at least one analog input signal or one analog output signal, or one analog signal within the analog circuit. Supply voltage lines should expressly be taken into account when assessing whether a circuit is an analog circuit or not. For the definition of an analog signal, the document presented here uses the text available on the Internet at https: / / www.elektronik-kompendium.de / sites / kom / 2405151.htm as an example from the state of the art: "An analog signal is a physical quantity that can assume continuous values ​​both in terms of size (amplitude) and time. A digital signal (digitus: finger, Latin) is a physical quantity that can only assume certain discrete values. The values ​​correspond to the number of agreed states. If two states are agreed, then these are binary (digital) signals. For an analog circuit to be considered an analog circuit within the meaning of this document, the analog circuit should have at least one input signal or one output signal, or one signal within the analog circuit, that can assume continuous values ​​both in terms of magnitude (amplitude) and over time. This magnitude is typically the value of the potential of the line of this signal relative to the potential of a reference node of the analog circuit or the value of the electrical current in the line of the respective signal. In particular, the proposed analog circuit is coupled to test logic (see Figure 2). As mentioned above, this is preferably test logic based on IEEE Standard 1149 and its sub-variants. However, it can also be just a scan path activated by a test pin external to the microintegrated circuit. In particular, the test logic is a digital circuit. In particular, the test logic is configured to place the analog circuit into a normal state and at least a first test state. Preferably, the test logic can place the analog circuit into a normal state and several test states. The different test states serve different test purposes and / or enable the activation of failures of specific parts of the analog circuit in load tests, for example, during a voltage stress test. The paper presented here refers, as an example, to the paper by Ian A. Grout, "Integrated Circuit Test Engineering: Modern Techniques," Springer London; 2006. Edition, June 2, 2010, ISBN-10: 1846280230, ISBN-13: 978-1846280238. In particular, the analog circuit according to the invention comprises first components that perform the function of the analog circuit in accordance with the circuit purpose during normal operation. The interconnection of these first components in the normal state of the analog circuit typically corresponds, at least in part, to a circuit from the prior art. It is conceivable that the principles presented here also to be applied to analog circuits after the disclosure of the technical teaching presented here, which are not yet known in the current state of the art. In particular, to increase testability and / or stress tolerance, the analog circuit according to the invention comprises, in addition to the first components, second components that, in the case of the at least one first test state of the analog circuit, enable the test logic to adjust the switching states of the first components. The test logic preferably controls the additional second components. In one embodiment, the analog circuit according to the invention comprises N-channel transistors and P-channel transistors. In particular, the second components of the test logic in the at least one first test state of the analog circuit enable the switching states of the first components to be set such that in the first test state either all N-channel transistors are off and all P-channel transistors are conducting or, alternatively, all N-channel transistors are conducting and all P-channel transistors are off. Analogously, the analog circuit may have a second test state that the test logic can set, in which either all N-channel transistors are conducting and all P-channel transistors are blocking, or alternatively all N-channel transistors are blocking and all P-channel transistors are conducting. The second test state would therefore preferably be complementary to the first test state in terms of the switching states of the N-channel transistors and the P-channel transistors. In a further embodiment, the analog circuit 1 according to the invention comprises a positive supply voltage line and a negative supply voltage line. As before, the test logic can preferably place the analog circuit into a normal state and at least a first test state. In this further scenario, the analog circuit preferably also has more than one test state. The above description should also apply here. In particular, the analog circuit 1 again comprises first components that carry out the intended function of the analog circuit in normal operation. In particular, the analog circuit 1 comprises, in addition to the first components, second components which, in the case of the at least one first test state of the analog circuit, enable the test logic to adjust the switching states of the first components. This makes it possible for a measuring device to to control the test logic of the exemplary analog circuit of the exemplary microintegrated circuit, to place the first analog circuit into a test state, and thus to control the switching states of the first components. The measuring device can then preferably also control the switching states of the second components. As a result, the analog circuit in such a test state preferably behaves like a digital circuit. Therefore, the analog circuit is then accessible for the application of methods for testing digital circuits in such a test state. Therefore, methods for planning the testing of digital circuits, such as fully automatic test pattern generation and / or IDDQ test methods, can then also be applied to the analog circuit in this test state. In particular, the analog circuit according to the invention has a plurality of possible current paths from the positive supply voltage line to the negative supply voltage line. These current paths from the positive supply voltage line to the negative supply voltage line of the analog circuit typically comprise components of the first components and / or the second components. The analog circuit is preferably designed such that essentially all of the first components and / or second components S1 to S9; G1 to G9 are part of at least one such current path. The current paths therefore typically and preferably run through these first components and / or through these second components. The second components enable the test logic to set the switching states of the first components in the case of the at least one first test state of the analog circuit. The test logic preferably sets the switching states of the first components in such a way that at least one first component and / or one second component is blocked in each of the possible current paths from the positive supply voltage line to the negative supply voltage line. If a measuring device now applies an increased supply voltage between the positive supply voltage line and the negative supply voltage line to the analog circuit, this increased voltage is applied via the blocked first components and / or the blocked second components. As a result, these blocked components are exposed to a greater voltage load, which potentially stresses pre-damaged components and typically leads to an increase in the leakage current between the positive supply voltage line and the negative supply voltage line. The measuring device can later record this leakage current and compare it with a permissible leakage current threshold. If the value of the leakage current recorded by the measuring device then exceeds the leakage current threshold, the measuring device can to rule out a fault, deviation, quality defect, or similar in the analog circuit and to discard the relevant microelectronic circuit, of which the analog circuit is a part. For the sake of clarity, this document refers to faults, deviations, quality defects, and similar in the analog circuit collectively as "faults." In a further development of the above embodiment, the second components of the test logic enable the switching states of the first components to be set in the case of the at least one first test state of the analog circuit, wherein the test logic sets the switching states of the first components in such a way that, in at least one current path of the analog circuit between the positive supply voltage line and the negative supply voltage line, either exactly one first component and / or exactly one second component is blocked. The document presented here refers to this current path as the current path under consideration. In the other current paths of the analog circuit between the positive supply voltage line and the negative supply voltage line, which are not the current path under consideration, more than exactly one component can be blocked.However, in the other current paths of the analog circuit between the positive supply voltage line and the negative supply voltage line, which are not the current path under consideration, at least one component of the analog circuit is also blocking. Therefore, only a leakage current flows between the positive supply voltage line and the negative supply voltage line of the analog circuit. The other components in this current path under consideration are then not blocking. In the following, this document refers to this one blocking component in the current path in question as an IDDQ component. By limiting the component blocking to the IDDQ component in the current path under consideration and by switching the other components in the relevant current path on, a measuring device can apply a voltage between the positive supply voltage line and the negative supply voltage line of the analog circuit, which then drops completely across the IDDQ component. If the measuring device increases the voltage between the positive supply voltage line and the negative supply voltage line to the maximum permissible value, it is ensured that the measuring device places the maximum load on the IDDQ component using the applied voltage. This accelerates the aging of the IDDQ component to a maximum. Experience has shown that such loads do not occur cumulatively during the intended service life of the IDDQ component. Experience has shown that with properly manufactured IDDQ components will not be damaged if the parameters of this stress test, for example the value of the applied supply voltage, are selected correctly. Using this methodology, the measuring device can specifically load individual components of the analog circuit. Preferably, the test patterns generated by the test logic are selected so that, with each test pattern, several components of the analog circuit become IDDQ components. A test pattern is a vector that typically includes the switching states of the first and second components. By setting a test state, the test logic generates a specific test pattern, whereupon the components of the analog circuit assume the switching states corresponding to this test pattern. At this point, the document presented here clarifies that this applies to the entire proposed solution in the document presented here. By simultaneously setting several components of the analog circuit as IDDQ components of a respective current path, the number of test states required for a complete test of all or most of the components of the analog circuit is reduced. FURTHER EXPLANATIONS USING THE FIGURES The document presented here further explains the invention using exemplary figures 2 to 7. The technical teaching presented here proposes, for the example of the exemplary analog circuit 1, to disconnect a MOS diode circuit of a first transistor 7 by means of a first switch S1 in the said first IDDQ test state and in the said second IDDQ test state by opening the first switch S1. In the normal state, the first switch S1 is closed, resulting in a MOS diode circuit of the first transistor 7. The first switch S1 is thus a feedback switch that is closed during normal operation and open in two test states, namely the first IDDQ test state and the second IDDQ test state. The first switch S1 is preferably a MOS transistor, which is preferably opened or closed via a test logic of the microintegrated circuit, of which the exemplary analog circuit 1 typically forms a part.Using said test logic, a test device can, for example, set normal operation, the first IDDQ test state, or the second IDDQ test state. For example, the test logic can be a JTAG test interface or the like. EXPLANATION OF THE EXAMPLE The document presented here explains the proposal using the example of Figure 2. The example analog circuit 1 of Figure 2 can expressly have more than two test states. For greater clarity of disclosure, the document presented here initially describes only a first IDDQ test state and a second IDDQ test state, without this constituting a limitation of the technical teaching presented here. Test logic The analog circuit 1 presented as an example in Figure 2 preferably has a test logic 38. The test logic 38 can, for example, be a test interface according to the JTAG boundary scan standard. The document presented here cites the JTAG standard IEEE 1149, for example. Further information can be found online at https: / / de.wikipedia.org / wiki / Boundary_Scan_Test (NPL1). A good overview is provided by LY Ungar, H. Bleeker, JE McDermid, and H. Hulvershorn, "IEEE-1149.X Standards: achievements vs. expectations," 2001 IEEE Autotestcon Proceedings. IEEE Systems Readiness Technology Conference. (Cat. No. 01CH37237), 2001, pp. 188-205, doi: 10.1109 / AUTEST.2001.948964 (NPL2). The IEEE Standard 1149 includes several substandards: "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks," in IEEE Std 1149.6-2015 (Revision of IEEE Std 1149.6-2003) , vol., no., pp.1-230, 18 March 2016, doi: 10.1109 / IEEESTD.2016.7436703. (NPL3) "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture," in IEEE Std 1149.7-2009 , vol., no., pp.1-985, 10 Feb. 2010, doi: 10.1109 / IEEESTD.2010.5412866. (NPL4) "IEEE Standard for Test Access Port and Boundary-Scan Architecture - Redline," in IEEE Std 1149.1- 2013 (Revision of IEEE Std 1149.1-2001) - Redline , vol., no., pp.1-899, 13 May 2013. (NPL5) "IEEE Standard for Test Access Port and Boundary-Scan Architecture," in IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001) , vol., no., pp.1-444, 13 May 2013, doi: 10.1109 / IEEESTD.2013.6515989. (NPL6) "IEEE Standard for a Mixed-Signal Test Bus," in IEEE Std 1149.4-2010 (Revision of IEEE Std 1149.4- 1999) , vol., no., pp.1-116, 18 March 2011, doi: 10.1109 / IEEESTD.2011.5738198. (NPL7) "IEEE Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and / or Active Components," in IEEE Std 1149.8.1-2012 , vol., no., pp.1-95, 9 Aug. 2012, doi: 10.1109 / IEEESTD.2012.6259815. (NPL8) "IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture," in IEEE Std 1149.10-2017 , vol., no., pp.1-96, 28 July 2017, doi: 10.1109 / IEEESTD.2017.7995164. (NPL9) "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks - Redline," in IEEE Std 1149.6-2015 (Revision of IEEE Std 1149.6-2003) - Redline , vol., no., pp.1-441, 18 March 2016. (NPL10) "IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device," in IEEE Std 1687-2014 , vol., no., pp.1-283, 5 Dec. 2014, doi: 10.1109 / IEEESTD.2014.6974961. (NPL11) "IEEE Draft Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary- Scan Architecture," in IEEE P1149.7 / D6, July 2020 , vol., no., pp.1-1043, 3 Nov. 2020. (NPL12) "IEEE Draft Standard for a Mixed-Signal Test Bus," in IEEE P1149.4 / D2, September 2010 , vol., no., pp.1-113, 7 Oct. 2010. (NPL14) "IEEE Approved Draft Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits," in IEEE P1838_D3.00, September 2019 , vol., no., pp.1-63, 7 Nov. 2019. (NPL15) Die hier vorgelegte Schrift zitiert der Vollständigkeit halber auch die Schrift G. O. D. Acevedo and J. Ramirez-Angulo, "VDDQ: a built-in self-test scheme for analog on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard," Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611), 2002, pp. 1026-1026, doi: 10.1109 / ICCDCS.2002.1004083. (NPL13) For a better overview, Figure 2 does not show any control lines between the test logic 38 and the tri-state gates (Gl to G9) explained below and the switches (S1 to S9) also explained below and the other test control lines also explained below. However, these control lines between the test logic 38 and the tri-state gates (G1 to G9) explained below, the switches (S1 to S9) also explained below, and the other test control lines also explained below are necessary for the functionality of the technical teaching disclosed here. The figures are therefore schematic and simplified. Changing the wiring of the first transistor 7 The technical teaching presented here further proposes, for the example of the exemplary analog circuit 1, to disconnect the MOS diode circuit of the fifth transistor 12 by means of a second switch S2 in said first IDDQ test state and in said second IDDQ test state by opening the second switch S2. As a result, the second switch S2 disconnects the control electrode 33 of the first transistor 7 from the first node 6. As a result, the potential of the control electrode 33 of the first transistor 7 is not defined after the opening of the second switch S2. However, for an orderly test, such a clear imprinting of an unambiguous electrical potential of the control electrode 33 of the first transistor 7 relative to the reference potential of the reference potential line 8 is necessary.In the normal state, the second switch S2 is closed, resulting in a MOS diode connection of the fifth transistor 12 and a correspondingly clear potential of the control electrode 33 of the first transistor 7. The second switch S2 is thus a feedback switch that is closed during normal operation and open in the two exemplary test states, namely the first IDDQ test state and the second IDDQ test state. The second switch S2 is preferably a MOS transistor, which is preferably opened or closed via the test logic of the microintegrated circuit. GENERAL TREATMENT OF FEEDBACK AND PROPERTIES OF TRI-STATE GATES During normal operation, feedback determines the potential of the control electrodes of some transistors in analog circuit 1. However, by opening the feedback switches, the potentials of the control electrodes of these transistors are no longer defined. The document presented here therefore proposes to preferably connect these control electrodes to a device which sets the potential of the control electrodes in question to a defined potential in the case of a first IDDQ test state or a second IDDQ test state and does not influence it in the case of a normal state. The document presented here recommends setting each of the control electrodes, which are now floating (i.e. whose potential is not defined) as a result of the opening of the feedback switch, to a defined potential using a generally additional tri-state gate. To simplify the explanation, we will assume, as an example, that the tri-state gate comprises a first tri-state gate transistor which pulls the output of the tri-state gate to the positive supply potential when it is closed and leaves the output of the tri-state gate unaffected when it is open. To simplify the explanation, we will further assume, as an example, that the tri-state gate comprises a second tri-state gate transistor which pulls the output of the tri-state gate to the negative supply potential when it is closed and leaves the output of the tri-state gate unaffected when it is open.Control logic ensures that the first tri-state gate transistor and the second tri-state gate transistor are never closed simultaneously. The tri-state gate has three states at its output. In a first state, the output of the tri-state gate is high-impedance. In this high-impedance state of the tri-state gate, the first tri-state gate transistor and the second tri-state gate transistor are open in the example. Thus, the tri-state gate does not affect the node at its output in the first state. In a second state, the output of the tri-state gate is connected to the negative supply voltage line. In this high-impedance state of the tri-state gate, the first tri-state gate transistor is open and the second tri-state gate transistor is closed. In a third state, the output of the tri-state gate is connected to the positive supply voltage line. In this high-impedance state of the tri-state gate, the first tri-state gate transistor is closed and the second tri-state gate transistor is open. IMPLEMENTATION TO THE EXAMPLE ANALOGUE CIRCUIT 1 The document presented here therefore proposes inserting a first switch S1 into the reference voltage line of the first node 6. The test logic 38 controls the first switch S1. For clarity, the exemplary Figure 2 does not show these control lines from the test logic 38 to the first switch S1. If the exemplary analog circuit 1 is in the normal state, the test logic 38 closes the first switch S1. If the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state, the test logic 38 opens the first switch S1, thus breaking the feedback of the first transistor 7 to itself. The document presented here further proposes connecting the control electrode 33 of the first transistor 7 to the output of a first tri-state gate Gl. The test logic 38 controls the first tri-state gate Gl. For clarity, the exemplary Figure 2 does not show these control lines from the test logic 38 to the first tri-state gate Gl. Thus, the test logic 38 is able to impress a defined logic level into the control electrode 33 of the first transistor 7 by means of the first tri-state gate Gl when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state and the first switch S1 is therefore open. If the exemplary analog circuit 1 is in the normal state, the test logic 1 switches the first tri-state gate Gl to high impedance.If the exemplary analog circuit 1 is in the normal state, the first tri-state gate Gl ideally behaves as if it were non-existent and does not disturb the analog circuit function of the exemplary analog circuit 1. If the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state, the first tri-state gate Gl ideally sets the potential at the control electrode 33 of the first transistor 7. If the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state, the first tri-state gate Gl ideally sets the switching state of the first transistor 7. The document presented here thus also proposes connecting the control electrode 36 of the fifth transistor 12 to the output of a second tri-state gate G2. The test logic 38 controls the second tri-state gate G2. For clarity, the exemplary figure does not show these control lines from the test logic 38 to the second tri-state gate G2. Thus, the test logic 38 is capable of impressing a defined logic level onto the control electrode of the fifth transistor 12 when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state and the second switch S2 is therefore open. In the example of Figure 1, the control electrode 28 of the third transistor 10 is intended to be an external input of the exemplary analog circuit 1. In the example of Figure 1, the control electrode 29 of the fourth transistor 11 is intended to be an external input of the exemplary analog circuit 1. The document presented here thus proposes connecting the control electrode 28 of the third transistor 10 to the output of a third tri-state gate G3. The test logic 38 preferably controls the third tri-state gate G3. For clarity, the exemplary Figure 2 does not show these control lines from the test logic 38 to the third tri-state gate G3. Thus, the test logic 38 is capable of impressing a defined logic level onto the control electrode 28 of the third transistor 10 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state.Preferably, a seventh switch S7 is inserted into the line of the control electrode 28 of the third transistor 10, which separates the control electrode 28 of the third transistor 10 and the feed point of the third tri-state gate G3 on one side of the seventh switch S7 from the third node 31 on the other side of the seventh switch S7 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state. The seventh switch S7 is then preferably open. In the normal state, the seventh switch S7 is then preferably closed and preferably connects the third node 31 to the control electrode 28 of the third transistor 10.It is thus conceivable to insert this seventh switch S7 into the line of the control electrode 28 of the third transistor 10, which switch separates this input of the third node 31 from the feed point of the third tri-state gate G3 and the control electrode 28 of the third transistor 10 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state, and which connects this input of the third node 31 to the feed point of the third tri-state gate G3 and the control electrode 28 of the third transistor 10 when the exemplary analog circuit 1 is in the normal state. In this case, the test logic 38 preferably controls this additional seventh switch S7. The document presented here further proposes connecting the control electrode 29 of the fourth transistor 11 to the output of a fourth tri-state gate G4. The test logic 38 controls the fourth tri-state gate G4. The exemplary Figure 2 does not show these control lines from the test logic 38 to the fourth tri-state gate G4 for clarity. Thus, the test logic 38 is able to impress a defined logic level into the control electrode 29 of the fourth transistor 11 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ Test state. Preferably, an eighth switch S8 is inserted into the line of the control electrode 29 of the fourth transistor 11, which switch separates the control electrode 29 of the fourth transistor 11 and the feed point of the fourth tri-state gate G4 on one side of the eighth switch S8 from the fourth node 32 on the other side of the eighth switch S8 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state. The eighth switch S8 is then preferably open. In the normal state, the eighth switch S8 is then preferably closed and preferably connects the fourth node 32 to the control electrode 29 of the fourth transistor 11.It is thus conceivable to insert an eighth switch S8 into the line of the control electrode 29 of the fourth transistor 11, which switch S8, on the one hand, separates this input of the fourth node 32 from the feed point of the fourth tri-state gate G4 and the control electrode 29 of the fourth transistor 11, on the other hand, when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state, and which connects this input of the fourth node 32 to the feed point of the fourth tri-state gate G4 and the control electrode 29 of the fourth transistor 11 when the exemplary analog circuit 1 is in the normal state. The test logic preferably controls this additional switch. SEPARATION OF ELECTRICALLY CONNECTED CIRCUIT NODES The document presented here further proposes that control electrodes of the exemplary analog circuit 1, which are electrically connected to one another, be separated from one another by additional switches when the exemplary analog circuit is in an IDDQ test state, in particular in the first IDDQ test state or in the second IDDQ test state. In the example of Figure 1, the control electrode of the first transistor 7 and the control electrode of the second transistor 9 and the control electrode 37 of the eighth transistor 16 are connected to each other via the first node 6, which is a reference voltage line. Figure 2 shows the modifications that the document presented here proposes in this regard. By way of example, the document presented here proposes that the test logic 38 preferably disconnects the control electrode 34 of the second transistor 9 from the first node 6 by means of a third switch S3 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state, and that the test logic 38 preferably disconnects the control electrode 34 of the second Transistor 9 connects to the first node 6 by means of the third switch S3 when the exemplary analog circuit 1 is in the normal state. The test logic 38 therefore preferably closes the third switch S3 when the exemplary analog circuit 1 is in the normal state, and preferably opens the third switch S3 when the exemplary analog circuit is in the first IDDQ test state or in the second IDDQ test state. The test logic 38 preferably controls the third switch S3. The exemplary Figure 2 does not show these control lines from the test logic 38 to the third switch S3 for clarity. By way of example, the document presented here proposes that the test logic 38 preferably disconnects the control electrode 37 of the eighth transistor 16 from the first node 6 by means of a fourth switch S4 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state, and that the test logic 38 preferably connects the control electrode 37 of the eighth transistor 16 to the first node 6 by means of a fourth switch S4 when the exemplary analog circuit 1 is in the normal state. The test logic 38 therefore preferably closes the fourth switch S4 when the exemplary analog circuit 1 is in the normal state and preferably opens the fourth switch S4 when the exemplary analog circuit is in the first IDDQ test state or in the second IDDQ test state. The test logic 38 preferably controls the fourth switch S4.The exemplary Figure 2 does not show these control lines from the test logic 38 to the fourth switch S4 for better clarity. To ensure that the control electrode 37 of the second transistor 9 does not have an undefined potential in the first IDDQ test state or in the second IDDQ test state, the document presented here proposes preferably connecting the control electrode 37 of the second transistor 9 to the output of a fifth tri-state gate G5. The test logic 38 preferably controls the fifth tri-state gate G5. As a result, the test logic 38 is typically capable of impressing a defined logic level into the control electrode 37 of the second transistor 9 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state and the third switch S3, the first switch S1, and the fourth switch S4 are therefore open. INDIRECT CONTROL OF SWITCHING STATES Since the test logic 38 can now typically control the switching states of the second transistor 9, the third transistor 10, the fourth transistor 11 and the fifth transistor 12 in the first IDDQ test state or in the second IDDQ test state of the exemplary analog circuit 1, The test logic 38 can thus also monitor the switching state of the sixth transistor 13 in the first IDDQ test state or in the second IDDQ test state. The reason for this is that the test logic 38 can typically adjust the potential of the control electrode 28 of the sixth transistor 13 by adjusting the switching states of the second transistor 9, the third transistor 10, the fourth transistor 11, and the fifth transistor 12. Thus, the test logic 38 can typically adjust the switching state of the sixth transistor 13 by adjusting the switching states of the second transistor 9, the third transistor 10, the fourth transistor 11, and the fifth transistor 12. Since the test logic 38 can control the switching state of the sixth transistor 13 and the fourth transistor 11 in the first IDDQ test state or in the second IDDQ test state, the test logic 38 can typically also control the switching state of the seventh transistor 15 in the first IDDQ test state or in the second IDDQ test state. The reason for this is that the test logic 38 can typically control the switching state of the sixth transistor 13 and the fourth transistor 11 in the first IDDQ test state or in the second IDDQ test state, the test logic 38 can typically also control the potential of the second node 14 and thus typically also the potential of the control electrode 39 of the seventh transistor 15 in the first IDDQ test state or in the second IDDQ test state. Since the test logic 38 can control the switching state of the seventh transistor 15 and the eighth transistor 16 in the first IDDQ test state or in the second IDDQ test state, the test logic 38 can also control the potential of the output of the source follower 26 from the seventh transistor 15 and the eighth transistor 16 in the first IDDQ test state or in the second IDDQ test state. TREATMENT OF INTERMEDIATE NODES Analog circuits typically also include switches designed to pull a node such as intermediate node 25 to a supply voltage potential or the like under certain conditions during normal operation. In the case of the exemplary analog circuit 1 of Figure 1, the thirteenth transistor 30 is such a transistor. Such a transistor is connected on one side to a supply voltage line of a first polarity and on the other side to a node of the exemplary electrical side. The document presented here proposes additionally providing a switch that can connect the respective node to the other supply voltage line. The document presented here proposes designing the control of such a transistor and the additional switch such that, in the normal state of the exemplary analog circuit, the additional switch is open and the transistor operates normally depending on the other control signals 40 of the overall circuit, as if the modification did not exist. However, in the first IDDQ test state or the second IDDQ test state of the exemplary analog circuit 1, the additional switch and the transistor operate as a tri-state gate, allowing the test logic to control the voltage level of the node. The exemplary thirteenth transistor 30 is such a transistor. The thirteenth transistor 30 of the exemplary analog circuit 1 is connected on one side to a supply voltage line 8 of a first polarity and on the other side to the intermediate node 25 of the exemplary analog circuit 1. The document presented here proposes additionally providing a fifth switch S5, which can connect the respective intermediate node 25 to the other supply voltage line. The document presented here proposes that the control of the thirteenth transistor 30 and the additional fifth switch S5 by the test logic 38 be designed such that in the normal state of the exemplary analog circuit 1, the additional fifth switch S5 is open and the thirteenth transistor 30 operates normally depending on the other control signals of the overall circuit, as if the modification did not exist. Specifically, this may mean, for example, that in the example of Figure 2, the digital transport clock 18 is an input signal of the test logic 38 and that in the normal state of the exemplary analog circuit 1, the digital transport clock 18 is equal to the modified digital transport clock 41 and that in the first IDDQ test state or in the second IDDQ test state, the test logic 38 typically generates the modified digital transport clock 41 independently of the digital transport clock 18.Furthermore, this can mean, for example, that in the example of Figure 2, the inverted digital transport clock 19 is an input signal of the test logic 38 and that in the normal state of the exemplary analog circuit 1, the inverted digital transport clock 19 is equal to the modified inverted digital transport clock 42 and that in the first IDDQ text state or in the second IDDQ test state, the test logic 38 typically generates the modified inverted digital transport clock 42 independently of the inverted digital transport clock 19. However, in the first IDDQ test state or in the second IDDQ test state of the exemplary analog circuit 1, the additional fifth switch S5 and the thirteenth transistor 30 operate together as an eighth tri-state gate G8, so that the test logic 38 can preferably control the voltage level of the intermediate node 25. To this end, the test logic 38 preferably controls the potential of the control electrode 43 of the thirteenth transistor 30. This means that the test logic preferably controls the switching state of the thirteenth transistor 30. Preferably, in the example of Figure 2, in the normal state of the exemplary analog circuit 1, the signal of the control electrode 43 of the thirteenth transistor 30 is equal to the inverted digital transport clock 19. In the first IDDQ test state and in the second IDDQ test state, the test logic 38 typically generates the signal of the control electrode 43 of the thirteenth transistor 30 independently of the inverted digital transport clock 19. In the exemplary analog circuit 1 of Figure 2, the ninth transistor 20 and the tenth transistor 21 form a so-called transfer gate, which can connect the intermediate node 25 to the output 26 of the source follower comprising the seventh transistor 15 and the eighth transistor 16 with appropriate control of the control electrodes of the ninth transistor 20 and the tenth transistor 21. In the example of Figure 2, the test logic 38 generates the modified digital transport clock 41 such that the modified digital transport clock 41 is equal to the digital transport clock 18 when the exemplary analog circuit 1 is in the normal state, and the test logic 38 generates the modified digital transport clock 41 independently of the digital transport clock 18 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state. Preferably, the test logic 38 then controls the control electrodes of the ninth transistor 21 and the tenth transistor 21, the twelfth transistor 23, the eleventh transistor 22, and the thirteenth transistor 30 independently of one another, with the test logic 38 preventing and locking uncontrolled cross-currents. In the first IDDQ test state or the second IDDQ test state of the exemplary analog circuit 1, the test logic 38 can typically control the switching states of the seventh transistor 15 and the eighth transistor 16, the thirteenth transistor 30, the ninth transistor 20, the tenth transistor 21, and the fifth switch S5 such that no cross-current occurs there either. Figure 3 essentially corresponds to Figure 2 with the difference that a ninth switch S9 can separate the second node 14 from the control electrode 39 of the seventh transistor 15. By way of example, the document presented here proposes that the test logic 38 preferably disconnects the control electrode 39 of the seventh transistor 15 from the second node 14 by means of an additional ninth switch S9 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state, and that the test logic 38 preferably connects the control electrode 39 of the seventh transistor 15 to the fourth node 6 by means of the ninth switch S9 when the exemplary analog circuit 1 is in the normal state. The test logic 38 therefore preferably closes the ninth switch S9 when the exemplary analog circuit 1 is in the normal state and preferably opens the ninth switch S9 when the exemplary analog circuit is in the first IDDQ test state or in the second IDDQ test state. The test logic 38 preferably controls the ninth switch S9.The exemplary Figure 3 does not show these control lines from the test logic 38 to the ninth switch S9 for better clarity. To ensure that the control electrode 39 of the seventh transistor 15 does not have an undefined potential in the first IDDQ test state or in the second IDDQ test state, the document presented here proposes preferably connecting the control electrode 39 of the seventh transistor 15 to the output of a ninth tri-state gate G9. The test logic 38 preferably controls the ninth tri-state gate G9. As a result, the test logic 38 is typically capable of impressing a defined logic level into the control electrode 39 of the seventh transistor 15 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state and the ninth switch S9 is open. Thus, the test logic 38 is typically also able to control the switching state of the seventh transistor 15 when the exemplary analog circuit 1 is in the first IDDQ test state or in the second IDDQ test state and the ninth switch S9 is open. This simplifies the generation of test patterns because the test logic 38 no longer has to generate and set pattern sequences from a predetermined time sequence of multiple patterns. This simplifies the test pattern generation for generating the sequence of patterns to be set by the test logic 38. This shortens the test time for the measurement device, which represents an economic advantage. In a transfer gate with a first transfer gate terminal and a second Transfer gate connection, the test logic 38 can therefore preferentially use the potentials at the first transfer gate terminal and a second transfer gate terminal in the first IDDQ test state or in the second IDDQ test state, by means of at least one additional switch—here, the fifth switch S5. Here, "control" preferably means that the test logic 38 can apply a voltage equal to the operating voltage to the transfer gate by controlling the transfer gate and the transistors and switches that determine the potential at the first transfer gate terminal and the second transfer gate terminal. The direction of the voltage across the transfer gate can preferably be specified by the test logic. The example of analog circuit 1 in Figure 2 now provides that the test logic 38 can also connect the analog output 24 of the exemplary analog circuit 1 to the positive supply voltage or the negative supply voltage via a seventh tri-state gate G7 in the first IDDQ test state or in the second IDDQ test state. In the normal state of the exemplary analog circuit 1 in Figure 2, the output of the seventh tri-state gate G7 is preferably high-impedance, since the switches of this seventh tri-state gate G7 are typically open. STRESS LOAD TO ACTIVATE PRE-DAMAGED COMPONENTS In the first exemplary embodiment of the proposal, the transistors of the exemplary analog circuit 1 are to be subjected to maximum voltage stress before the actual IDDQ test in order to reveal latent defects in the transistors. Typically, such latent defects do not cause failures in preceding functional tests because the transistors are functioning. The voltage stress, which perfectly manufactured transistors survive unscathed, further damages such pre-damaged transistors, so that the stress test magnifies the effects of the thus amplified damage in the manufacturing test to such an extent that a measuring device for measuring the exemplary analog circuit 1 can detect it. In this first exemplary embodiment, the document presented here proposes, for example, that in a first test step, the measuring device, using the test logic 38 in the first IDDQ test state of the exemplary analog circuit 1, switches all P-channel transistors of the exemplary analog circuit 1 to conducting and all N-channel transistors to blocking. The measuring device raises the supply voltage to the maximum permissible level for a just-allowable time. This leads to damage to previously damaged transistors of the exemplary analog circuit 1. However, this does not lead to damage to non-previously damaged transistors of the exemplary analog circuit 1. The just-allowable time for such a stress load depends on the semiconductor or CMOS technology used. The just-allowable The permissible time should preferably be determined in the context of the development of semiconductor or CMOS technology or in the context of the qualification of the component for the technical teaching disclosed in this document by load tests on a sufficient number of components with a preferably typical control of the production parameters in production tests and load tests. In this first exemplary embodiment, the document presented here proposes, for example, that in a second test step, the measuring device, using test logic 38 in the second IDDQ test state of the exemplary analog circuit 1, switches all N-channel transistors of the exemplary analog circuit 1 to conducting and all P-channel transistors to blocking. The measuring device raises the supply voltage to the maximum permissible level for a just-allowable time. This leads to damage to previously damaged transistors of the exemplary analog circuit 1. However, this does not lead to damage to non-previously damaged transistors of the exemplary analog circuit 1. If not all P-channel transistors and / or not all N-channel transistors can be brought into the intended switching state, additional switches or tri-state gates are inserted in the design in order to isolate the control nodes of these transistors from other nodes in the first IDDQ test state and in the second IDDQ test state and to be able to control them according to the above examples. For example, in the sense of the document presented here, the measuring device and / or the testing process of the analog circuit 1 can carry out said first step and said second step individually or sequentially in any order. Leakage current measurement of individual transistors In a second exemplary embodiment of the proposal, the measuring device applies a typically increased supply voltage to the exemplary analog circuit 1. The measuring device then successively brings the exemplary analog circuit 1 into various test states using the test logic 38. In each test state of the exemplary analog circuit 1, the test logic 38 typically sets the switching states of the transistors and the switches and the tri-state gates of the exemplary analog circuit 1 differently. In the following, we refer to the vector of the switching states of these elements of the exemplary analog circuit 1, i.e., the transistors and the switches and the tri-state gates of the exemplary analog circuit 1, as Pattern. The difference between two different patterns can therefore only affect the switching state of a single transistor, a single switch, or a single tri-state gate of the exemplary analog circuit 1 between these two patterns. Typically, however, in two different patterns, at least two switching states of at least two of these elements are different between these patterns. A developer of a manufacturing test will typically select the patterns so that only the leakage current can flow in each of these test states.To this end, this developer designs the control signals of the measuring device such that the test logic generates the patterns for controlling the transistors, switches, and tri-state gates and controls them in such a way that, in every conceivable current path between the positive supply voltage and the negative supply voltage, at least one transistor or switch is blocked, and no cross-current flows in the exemplary analog circuit 1 from the positive supply voltage line to the negative supply voltage line. A cross-current, in the sense of the document presented here, is therefore typically a short-circuit current from the positive supply voltage line 3 of the exemplary analog circuit 1 to the negative supply voltage line 8 or a fault current with the same effect.Preferably, in each of these test states, the test logic 38 should control the transistors, switches, and tri-state gates such that in at least one current path between the positive supply voltage line and the negative supply voltage line, or their functional equivalents, exactly one transistor or exactly one switch is off, and the other transistors and switches of this current path are open. In all other possible current paths between the positive supply voltage line and the negative supply voltage line, and their functional equivalents, at least one switch is open, or at least one transistor is off, so that no current can flow there either. The switches can also expressly be switches within the tri-state gates. This document hereinafter refers to this off-state transistor or off-state switch as the "IDDQ-tested transistor" for this test state.The measuring device then sets one test state after another using test logic 38. Test logic 38 preferably sets a test-state-specific pattern for each test state. The measuring device preferably determines the leakage current for each test state. The leakage current is typically the current consumption of the exemplary analog circuit 1, preferably via the Supply voltage lines. The measuring device compares these recorded leakage current values ​​of the different test conditions with a specified value. The specified value can be globally or specific to groups of test states, or specific to the respective test states. Mixtures of test states are conceivable. The current consumption of the exemplary analog circuit 1 is typically the leakage current of the IDDQ-tested transistors of the respective test states. Preferably, the measuring device changes the test states in the form of the patterns generated by the test logic 38 until all transistors and switches of the exemplary analog circuit 1 have been an IDDQ-tested transistor at least once. In a preferred implementation, the measuring device can, for example, control the test logic 38 via a JTAG test bus interface.The advantage of this method, in conjunction with the switches and tri-state gates of the exemplary analog circuit 1, is that, first, the leakage current of each transistor can be measured, and second, a maximum voltage stress can be applied to each transistor when the measuring device measures the transistor's leakage current. Furthermore, the test patterns for generating the control signals of the test logic 38 for adjusting the patterns can be generated using ATPG methods. The test logic 38 should reliably prevent cross-currents. The test procedure preferably consists of a first stress test, which, by means of the first embodiment of the proposal, causes a maximum acceleration of the activation of latent errors by applying a maximum supply voltage and optionally a subsequent systematic measurement of the leakage currents of all transistors by means of one or more IDDQ measurements, possibly using different patterns. It has also been shown that in many cases it is sufficient to simply perform the stress test using the method of the first version of the proposal and then measure the current consumption of the example analog circuit 1 during normal operation. However, this measurement method is less precise. The document presented here proposes combining the test of the exemplary analog circuit 1 with the digital test by the measuring device. To make this possible, the document presented here proposes integrating digital flip-flops (memory cells) into the scan path of the test logic 38 in one, several, or all test states. These digital flip-flops thereby block the signals to and from the analog circuit 1 in these test states. In other words, the "doors" to the exemplary analog circuit are thus closed and under the control of the test logic 38, which may control these digital flip-flops or of which these digital flip-flops may be a part. The measuring device preferably sets the test states and patterns via the scan path of the test logic 38 and controls the test logic 38 accordingly. During measurements in the test states with stopped clocks, the supply current of the example analog circuit should typically be close to zero in the various test states with different patterns. Practical tests during the development of the proposed approach have shown that the use of automatically generated IDDQ test patterns with approximately 20 IDDD measurement points produces very good results. The development of the proposal presented here has shown that a voltage stress with an elevated gate voltage typically lasting 20 ms destroys even weak transistors. Subsequently, a noticeably increased leakage current can be measured. These voltage overshoot levels and the duration of the overshoot depend heavily on the specific semiconductor technology or CMOS technology used to implement analog circuit 1. To solve the above problem, the document presented here further proposes a method for performing an IDDQ test of an analog circuit 1. Figure 4 illustrates the method in a simplified, schematic form. The analog circuit 1 is assumed to be, for example, an analog circuit 1 corresponding to the embodiment shown in Figure 3. The procedure proposed here comprises several steps. If no measuring device is available, the method begins with step 400 of providing a measuring device. In the following step, the analog circuit 1 is supplied 401 with electrical energy, wherein the supply is preferably provided by the measuring device. In the subsequent step, the analog circuit 1 is transferred 402 into the first test state, wherein the measuring device preferably carries out this transfer by means of the test logic 38, for example via a JTAG test bus interface. In the following step, the current consumption of the analog circuit 1 in this first test state is recorded 403 and a current consumption value is determined, in particular by means of the Measuring device which preferably detects a value of the electric current which it supplies to one of the Supply voltage lines 3, 8 of the analog circuit 1. In the following step, the comparison 404 of the detected current consumption value with a default value takes place, wherein said measuring device preferably carries out this comparison. In the subsequent step, the conclusion 405 is drawn that an error is present if the magnitude of the current consumption value is greater than the magnitude of the preset value, wherein the measuring device preferably carries out this conclusion and then preferably rejects the possibly faulty analog circuit 1 in the event of such an error 406. If the measuring device does not conclude that the analog circuit 1 is faulty in the preceding step 405, the analog circuit 1 can be used as intended with a higher probability 407 if the analog circuit 1 is not rejected for other reasons in further, subsequent or preceding tests. To solve the above problem, the document presented here further proposes a further method for performing an IDDQ test of an analog circuit 1. Figure 5 illustrates the method in a simplified, schematic form. The analog circuit 1 is assumed to be, for example, an analog circuit 1 corresponding to the embodiment shown in Figure 3. The analog circuit 1 should now, by way of example, deviate from the embodiment shown in Fig. 3, have one or more further test states in addition to the said first test state. The document presented here refers to these further test states and the said first test state jointly as "test states" in the following. These test states should preferably be distinguished in that at least one IDDQ component of a test state of the test states differs from all other IDDQ components of all other test states. Thus, this IDDQ component of the test state differs from any other IDDQ components of the other test states. The procedure proposed here comprises several steps. If no measuring device is available, the method begins with step 500 of providing a measuring device. In the following step, the analog circuit 1 is supplied 501 with electrical energy, wherein the supply is preferably provided by the measuring device. In the subsequent step, the analog circuit 1 is transferred 502 into a test state of the test states by setting and assuming this test state, wherein the measuring device preferably carries out this transfer and the setting by means of the test logic 38, for example via a JTAG test bus interface, whereupon the analog circuit 1 assumes this test state. In the following step a), the current consumption of the analog circuit 1 in this test state is detected 503 and a current consumption value is determined, in particular by means of the measuring device, which preferably detects a value of the electrical current that it feeds into one of the supply voltage lines 3, 8 of the analog circuit 1. In the subsequent step b), the comparison 504 of the detected current consumption value with a default value which may be specific to the set test condition takes place, wherein preferably the said measuring device carries out this comparison. In the subsequent step c), the transfer 508 of the analog circuit 1 into a further test state of the test states takes place by setting and assuming this further test state, wherein this further test state differs from the previously assumed test states of the test states and wherein in particular the transfer 508, the setting takes place by means of the measuring device, and the continuation of the method with step a) until all test states or a predetermined subset of the test states have been assumed; Therefore, a check 509 is performed to determine whether all test states or all test states specified as being to be assumed have been assumed. If all test states to be assumed have been assumed, the method 507 is terminated and, if applicable, the intended use of analog circuit 1 is permitted. If not all test states to be assumed have been assumed, the method continues at step a) with the detection 503 of the current consumption of analog circuit 1. The intended use 507 of the analog circuit 1 naturally presupposes that no errors within the meaning of the document presented here are or have been discovered during any further preceding and / or subsequent tests and / or during operation of the analog circuit. In step d), which follows the comparison 504 of the current consumption value with a preset value, the conclusion 505 that an error is present is drawn if the amount of the current consumption value is greater than the amount of the preset value, wherein preferably the said measuring device carries out this conclusion and then preferably rejects the possibly faulty analog circuit 1 in the event of such an error 506. The conclusion 505 on an error can swap the order with the transfer 508 of the analog circuit 1 into another test state of the test states. The check 509 as to whether all test states or all test states specified as being to be assumed have been assumed can swap the order with the transfer 508 of the analog circuit 1 into a further test state of the test states. In this respect, the numbering of the steps from a) to d) in the description and in the claims does not imply any chronological sequence. To solve the above problem, the document presented here further proposes a further method for performing an IDDQ test of an analog circuit 1. Figure 6 illustrates the method in a simplified, schematic form. The analog circuit 1 is assumed to be, for example, an analog circuit 1 corresponding to the embodiment shown in Figure 2. The procedure proposed here comprises several steps. If no measuring device is available, the method begins with step 600 of providing a measuring device. In the following step, the analog circuit 1 is supplied 601 with electrical energy, wherein the supply is preferably provided by the measuring device. In the subsequent step, the analog circuit 1 is transferred 602 into the first test state, wherein the measuring device preferably carries out and preferably controls this transfer by means of the test logic 38, for example via a JTAG test bus interface. In the subsequent step, the current consumption of the analog circuit 1 in this first test state is detected 503 and a current consumption value is determined, in particular by means of the measuring device, which preferably detects a value of the electrical current that it feeds into one of the supply voltage lines 3, 8 of the analog circuit 1. In the following step, the comparison 604 of the determined current consumption value with a default value takes place, wherein the said measuring device preferably carries out this comparison. In the subsequent step, the conclusion 605 is drawn that an error is present if the magnitude of the current consumption value is greater than the magnitude of the preset value, wherein the said measuring device preferably carries out this conclusion and then preferably rejects the possibly faulty analog circuit 1 in the event of such an error 606. If the measuring device does not conclude that the analog circuit 1 is faulty in the preceding step 605, the analog circuit 1 can be used as intended with a higher probability 607 if the analog circuit 1 is not rejected for other reasons in further, subsequent or preceding tests. To solve the above problem, the document presented here further proposes a method for performing a stress test on an analog circuit 1. Figure 7 illustrates the method in a simplified, schematic form. Analog circuit 1 is assumed to be, for example, an analog circuit according to the embodiment shown in Figure 2. The procedure proposed here comprises several steps. If no measuring device is available, the method begins with step 700 of providing a measuring device. In the following step, the analog circuit 1 is supplied with electrical energy 701, wherein the supply is preferably provided by the measuring device. In the subsequent step, the analog circuit 1 is transferred 702 into the first test state, wherein the measuring device preferably carries out this transfer by means of the test logic 38, for example via a JTAG test bus interface. In the subsequent step, the supply voltage is increased 708 for a predetermined period of time by a predetermined stress voltage value, wherein the measuring device preferably carries out this increase 708; reversing 709 the increase 708 of the supply voltage, wherein preferably the measuring device carries out this reversal of the increase 708; In the subsequent step, the current consumption of the analog circuit 1 in this first test state is detected 703 and a current consumption value is determined, in particular by means of the measuring device, which preferably detects a value of the electrical current that it feeds into one of the supply voltage lines 3, 8 of the analog circuit 1. In the following step, the comparison 704 of the detected current consumption value with a default value takes place, wherein the said measuring device preferably carries out this comparison. In the subsequent step, the conclusion 705 is drawn that an error is present if the magnitude of the current consumption value is greater than the magnitude of the preset value, wherein the said measuring device preferably carries out this conclusion and then preferably rejects the possibly faulty analog circuit 1 in the event of such an error 706. If the measuring device does not conclude that the analog circuit 1 is faulty in the preceding step 705, the analog circuit 1 can be used as intended with a higher probability 707 if the analog circuit 1 is not rejected for other reasons in further, subsequent or preceding tests. Advantage The use of the proposed switches and tri-state gates for setting specific test states can enable a meaningful IDDQ test of the exemplary analog circuit 1. This increases the testability of the exemplary analog circuit 1 and thus the delivery quality. In contrast to the technical teaching of US 2005 / 0 024 075 A1, the technical teaching presented here solves the problem of IDDQ testability of an analog circuit. In contrast to the examples of US 2005 / 0 024 075 A1, the technical teaching presented here discloses a fully IDDQ testable solution. "Fully" refers to an IDDQ test of ALL analog transistors in the example presented here. In contrast to the technical teaching of US 2005 / 0 024 075 Al, the technical teaching of the proposal presented here does not have any static current paths between the positive and the negative supply voltage in the test state. In contrast to the technical teaching of US 2005 / 0 024 075 A1, the document presented here proposes the reconfiguration of the analog circuit to be tested into a digital circuit. Regarding the technical teaching of US 2005 / 0 024 075 A1, the technical teaching of the document presented here enables the fully automated generation of IDDQ test patterns. Thus, the use of the technical teaching of the document presented here can enable the generation of verifications in accordance with the requirements of ISO 26262. In contrast to the technical teaching of US 2005 / 0 024 075 Al, the document presented here proposes a separation of the feedback branches. In contrast to the technical teaching of US 2005 / 0 024 075 A1, the document presented here proposes complete isolation of the control nodes. In the example shown in Figure 2 of the document presented here, this is achieved in particular by the exemplary switches S6, S7, S8, S1, S2, S3, and S4. In contrast, the technical teaching of US 2005 / 0 024 075 A1 does not provide for such additional transfer gates for test purposes. In contrast to US 2005 / 0 024 075 A1, the document presented here discloses a circuit that is testable in the IDDQ test state, and furthermore, its principles for transfer to other analog circuits. List of characters Figure 1 shows an example analog circuit 1. Figure 2 Shows, by way of example, a proposed analog circuit 1 which can be reconfigured in a test state by means of a test logic 38, for example by means of control via a JTAG test bus interface, by suitably setting the switching state of additional components (S1 to S9, Gl to G9) in such a way that it is suitable for an IDDQ test and / or a voltage stress test in this reconfigured test state. Figure 3 corresponds to Figure 2, whereby the test logic 38 can now also directly control the switching state of the seventh transistor 15. Figure 4 shows a method for performing an IDDQ test of an analog circuit according to Fig. 3. Figure 5 shows a further method for performing an IDDQ test of an analog circuit according to Fig. 3 Figure 6 shows a method for performing an IDDQ test of an analog circuit according to Fig. 2 Figure 7 shows a method for performing a stress test of an analog circuit according to Fig. 2. List of reference symbols 1 example analog circuit; 2 voltage source; 3 supply voltage line; 4 power source; 5 Reference current; 6 first node; 7 first transistor; 8 reference potential line; 9 second transistor; 10 third transistor; 11 fourth transistor; 12 fifth transistor; 13 sixth transistor; 14 second node; 15 seventh transistor; 16 eighth transistor; 17 inverters; 18 digital transport clock; 19 inverted digital transport clock; 20 ninth transistor; 21 tenth transistor; 22 eleventh transistor; 23 twelfth transistor; 24 analog output and input node of a subsequent circuit; 25 intermediate nodes; 26 Output of the source follower from seventh transistor 15 and eighth transistor 16; TI reference voltage between first node 6 and reference potential line 8; 28 Control electrode of the third transistor 10; 29 Control electrode of the fourth transistor 11; 30 thirteenth transistor; 31 third node; 32 fourth node; 33 Control electrode 33 of the first transistor 7; 34 Control electrode of the second transistor 9; 36 Control electrode of the fifth transistor 12; 37 Control electrode of the eighth transistor 16; 38 test logic; 39 Control electrode of the sixth transistor 13; 40 other control signals of the overall circuit of which the exemplary analog circuit 1 is a part; 41 modified digital transport clock; 42 modified inverted digital transport clock; 43 Control electrode of the thirteenth transistor 30; 400 Providing a measuring device; 401 Supplying the analog circuit 1 with electrical energy; 402 Transferring 402 the analog circuit 1 into the first test state; 403 Detecting the current consumption of the analog circuit 1 in a test state and determining a current consumption value, in particular by means of a measuring device; 404 Comparing the current consumption value with a default value, 405 Inferring an error; 406 Discarding a faulty analog circuit 1; 407 Termination of the procedure and, if applicable, intended use of analog circuit 1; 500 Providing a measuring device; 501 Supplying the analog circuit 1 with electrical energy; 502 Transferring 502 the analog circuit 1 into a test state of the test states by setting and assuming this test state; 503 Detecting the current consumption of the analog circuit 1 in a test state and determining a current consumption value, in particular by means of a measuring device; 504 Comparing the current consumption value with a default value, 505 Inferring an error; 506 Discard a faulty analog circuit 1; 507 Termination of the procedure and, if applicable, intended use of analog circuit 1; 508 Transferring the analog circuit 1 into a further test state of the test states by setting and assuming this further test state; 509 Checking 509 whether all test states or all test states specified as being to be taken have been taken; 600 Providing a measuring device; 601 Supplying the analog circuit 1 with electrical energy; 602 Transferring 602 the analog circuit 1 into the first test state; 603 Detecting the current consumption of the analog circuit 1 in a test state and determining a current consumption value, in particular by means of a measuring device; 604 Comparing the current consumption value with a default value, 605 Inferring an error; 606 Discard a faulty analog circuit 1; 607 Termination of the procedure and, if applicable, intended use of analog circuit 1; 700 Providing a measuring device; 701 Supplying the analog circuit 1 with electrical energy; 702 Transferring 402 the analog circuit 1 into the first test state; 703 Detecting the current consumption of the analog circuit 1 in a test state and determining a current consumption value, in particular by means of a measuring device; 704 Comparing the current consumption value with a specified value, 705 Inferring an error; 706 Discarding a faulty analog circuit 1; 707 Termination of the procedure and, if applicable, intended use of the Analog circuit 1; 708 Increase the supply voltage; 709 Reversal of the increase in the supply voltage, which may be done in whole or in part; Gl first tri-state gate; G2 second tri-state gate; G3 third tri-state gate; G4 fourth tri-state gate; G5 fifth tri-state gate; G6 sixth tri-state gate; G7 seventh tri-state gate; G8 eighth tri-state gate; G9 ninth tri-state gate; 51 first switch; 52 second switch; 53 third switch; 54 fourth switch; 55 fifth switch; 56 sixth switch; 57 seventh switch; 58 eighth switch; 59 ninth switch; Idd supply current into analog circuit 1; List of cited writings If the application for a property right claiming priority of the document presented here is filed in a state that allows the claiming of the technical teaching of cited documents in combination with the technical teaching of this document as part of the disclosure of this document, the following documents are expressly part of this disclosure in combination with the document presented here. PATENT LITERATURE US 2005 / 0 024 075 Al NON-PATENT LITERATURE NPL1: https: / / de.wikipedia.org / wiki / Boundary_Scan_Test (download 11.02.2022) NPL2: L. Y. Ungar, H. Bleeker, J. E. McDermid and H. Hulvershorn, "IEEE-1149.X standards: achievements vs. expectations," 2001 IEEE Autotestcon Proceedings. IEEE Systems Readiness Technology Conference. (Cat. NO.01CH37237), 2001, pp. 188-205, doi: 10.1109 / AUTEST.2001.948964 NPL3: "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks," in IEEE Std 1149.6- 2015 (Revision of IEEE Std 1149.6-2003) , vol., no., pp.1-230, 18 March 2016, doi: 10.1109 / IEEESTD.2016.7436703. NPL4: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary- Scan Architecture," in IEEE Std 1149.7-2009 , vol., no., pp.1-985, 10 Feb. 2010, doi: 10.1109 / IEEESTD.2010.5412866. NPL5: "IEEE Standard for Test Access Port and Boundary-Scan Architecture - Redline," in IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001) - Redline, vol., no., pp.1-899, 13 May 2013. NPL6: "IEEE Standard for Test Access Port and Boundary-Scan Architecture," in IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001), vol., no., pp.1-444, 13 May 2013, doi: 10.1109 / IEEESTD.2013.6515989. NPL7: "IEEE Standard for a Mixed-Signal Test Bus," in IEEE Std 1149.4-2010 (Revision of IEEE Std 1149.4-1999) , vol., no., pp.1-116, 18 March 2011, doi: 10.1109 / IEEESTD.2011.5738198. NPL8: "IEEE Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and / or Active Components," in IEEE Std 1149.8.1-2012, vol., no., pp.1-95, 9 Aug. 2012, doi: 10.1109 / IEEESTD.2012.6259815. NPL9: "IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture," in IEEE Std 1149.10-2017 , vol., no., pp.1-96, 28 July 2017, doi: 10.1109 / IEEESTD.2017.7995164. NPL10: "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks - Redline," in IEEE Std 1149.6-2015 (Revision of IEEE Std 1149.6-2003) - Redline, vol., no., pp.1-441, 18 March 2016. NPL11: "IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device," in IEEE Std 1687-2014 , vol., no., pp.1-283, 5 Dec. 2014, doi: 10.1109 / IEEESTD.2014.6974961. NPL12: "IEEE Draft Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture," in IEEE P1149.7 / D6, July 2020 , vol., no., pp.1-1043, 3 Nov. 2020. NPL13: G. O. D. Acevedo and J. Ramirez-Angulo, "VDDQ: a built-in self-test scheme for analog on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard," Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611), 2002, pp. 1026-1026, doi: 10.1109 / ICCDCS.2002.1004083. NPL14: "IEEE Draft Standard for a Mixed-Signal Test Bus," in IEEE P1149.4 / D2, September 2010, vol., no., pp.1-113, 7 Oct. 2010. NPL15: "IEEE Approved Draft Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits," in IEEE P1838_D3.00, September 2019, vol., no., pp.1-63, 7 Nov. 2019. NPL16: Dietmar Ehrhardt, "Integrierte analoge Schaltungstechnik: Technologie, Design, Simulation Und Layout", 28. Juni 2000, Vieweg Verlagsgesellschaft; 2000. Edition (28. Juni 2000), ISBN-10: 3528038608, ISBN-13: 978-352803860 NPL17: Phillip E. Allen (author), Douglas R. Holberg, "CMOS Analog Circuit Design", Oxford University Press; 3rd edition. International (July 13, 2012), ISBN-10: 0199937427, ISBN-13: 978-0199937424 NPL18: Saggio, Giovanni, Tor Vergata, "Principles of Analog Electronics", ASIN: 1466582014, Taylor & Francis Inc, January 29, 2014, ISBN-10: 9781466582019, ISBN-13: 978-1466582019 NPL19: Ulrich Tietze, Christoph Schenk, "Semiconductor Circuit Technology" Hardcover - July 5, 2019, Springer Vieweg; 16th, expanded and updated edition, 2019 Edition, ISBN-10: 3662485532, ISBN-13: 978-3662485538 NPL20: Ian A. Grout, "Integrated Circuit Test Engineering: Modern Techniques" Springer London; 2006. Edition, June 2, 2010, ISBN-10: 1846280230, ISBN-13: 978-1846280238 NPL21: Wikipedia https: / / en.wikipedia.org / wiki / lddq_testing. NPL22: ISO26262

Claims

Patent claims 1. Analog circuit (1) based on MOS, BiCMOS or CMOS, wherein the analog circuit (1) is configured to fulfill a predetermined circuit purpose in a normal state of the analog circuit (1), and wherein the analog circuit (1) has one or more input signals and / or one or more output signals, and wherein the analog circuit (1) has at least one analog signal within the analog circuit (1), and wherein the analog circuit (1) is coupled to a test logic (38), and wherein the test logic (38) is configured to put the analog circuit (1) into the normal state and at least a first test state, and wherein the analog circuit (1) comprises first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), and wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are designed toperform a function of the analog circuit (1) according to the predetermined circuit purpose of the analog circuit (1) in the normal state of the analog circuit (1), and wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) each have a control electrode, and wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are designed to also be able to be operated as switches by means of their respective control electrodes, and wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in a respective operation as switches each have an on-state and an off-state as respective switching states and wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are fully switched on in the on state and wherein the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23,30) are completely switched off in the off state and wherein the analog circuit (1) comprises second components (S1 to S9; Gl to G9) and wherein the test logic (38) is designed to, by means of the second components (S1 to S9; Gl to G9) in the first test state of the analog circuit (1), at least a first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), and wherein the control electrode (33, 34, 36, 37) of this first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is not directly connected to an input signal or not directly connected to an output signal, and wherein the test logic (38) is designed to control this control electrode (33, 34, 36, 37) of this first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in the first test state by means of at least one Switch (SI, S2, S3, S4) from the rest of the analog circuit (1), and wherein the test logic (38) is designed to connect this control electrode (33, 34, 36, 37) of this first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) by means of at least the switch (SI, S2, S3, S4) in the normal state to a node of the rest of the analog circuit (1), and wherein the test logic (38) is designed toin the first test state, this control electrode (33, 34, 36, 37, 39) of this first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is switched on into an on state or switched off into an off state by means of first means (Gl, G2, G5, G6), and wherein the test logic (38) is designed to control these first means (Gl, G2, G5, G6) in the normal state such that these first means (Gl, G2, G5, G6) switch the control electrode (33, 34, 36, 37, 39) of this first component (7, 9, 12, 16) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in the normal state of the analog circuit (1).

2. Analog circuit (1) according to claim 1, characterized in that the analog circuit (1) comprises N-channel transistors (7, 9, 16, 30, 10, 11, 20, 22) and P-channel transistors (12, 13, 15, 21, 23) and the second components (S1 to S9; G1 to G9) are designed to enable, in the case of the at least one first test state of the analog circuit (1), the test logic (38) to set the switching states of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) such that in the first test state of the analog circuit (1) either all N-channel transistors (7, 9, 16, 30, 10, 11, 20, 22) of the analog circuit (1) and conduct all P-channel transistors (12, 13, 15, 21, 23) of the analog circuit (1) or that in the first test state of the analog circuit (1) either all N-channel transistors (7, 9, 16, 30, 10, 11, 20, 22) of the analog circuit (1) and all P-channel transistors (12, 13, 15, 21, 23) of the analog circuit (1).

3. Analog circuit (1) according to claim 1, characterized in that the analog circuit (1) has a positive supply voltage line (3) and that the analog circuit (1) has a negative supply voltage line (8), and that the analog circuit (1) has several possible current paths from the positive Supply voltage line (3) to the negative supply voltage line (8) through at least one component of these first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) and / or these second components (S1 to S9; G1 to G9), wherein the second components (S1 to S9; G1 to G9) are designed to enable, in the case of the at least one first test state of the analog circuit (1), the test logic (38) to set the switching states of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in such a way that in each current path of these possible current paths at least one first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) and / or at least one second component (S1 to S9; Gl to G9).

4. Analog circuit (1) according to claim 3, characterized in that in at least one current path of the possible current paths, which is referred to below as the considered current path, exactly one first component or exactly one second component blocks in the first test state and that this exactly one blocking first component or exactly one blocking second component in the considered current path corresponds to an IDDQ component and that the other components which are different from the IDDQ component do not block in this considered current path in the first test state.

5. A method for performing an IDDQ test of an analog circuit (1) according to claim 4, comprising the steps Providing a measuring device; Supplying the analog circuit (1) with electrical energy; Transferring the analog circuit (1) to the first test state; Detecting a current consumption of the analog circuit (1) in this first test state and determining a current exception value by means of the measuring device; Comparing the current exception value with a default value; Infer an error if the current consumption value is above the specified value.

6. A method for performing an IDDQ test of an analog circuit (1) according to claim 4, wherein the analog circuit (1) has one or more further test states in addition to a first test state, and wherein these further test states and the first test state are hereinafter referred to collectively as test states, and wherein the test states differ from one another in that an IDDQ component of one test state of the test states differs from another IDDQ component of another of the test states, and wherein the method comprises the following steps: Providing a measuring device; Supplying the analog circuit (1) with electrical energy; Transferring the analog circuit (1) into a test state of the test states by setting and adopting this test state by means of the measuring device; Step a): Detecting a current consumption of the analog circuit (1) in the set test state and determining a current consumption value by means of the measuring device; Step b): Comparing the determined current consumption value with a default value, which may be specific to the set test condition; Step c): Transferring the analog circuit (1) into a further test state of the test states by setting and assuming this further test state, wherein this further set test state differs from the previously assumed test states of the test states and wherein the transfer is carried out by means of the measuring device, and continuing with step a) until all test states or a predetermined subset of the test states have been assumed; Step d): Inferring a fault if the measured current consumption value is above the specified value, whereby step d) can also be carried out between steps b) and c) and whereby the measuring device can also carry out this inference of a fault.

7. A method for performing an IDDQ test of an analog circuit (1) according to claim 2 or 4, comprising the steps: Providing a measuring device; Supplying the analog circuit (1) with electrical energy, whereby the measuring device can carry out this supply; Transferring the analog circuit (1) into the first test state, whereby the measuring device can also control this transfer; Detecting a current consumption of the analog circuit (1) in the first test state and determining a current consumption value, wherein the measuring device can also carry out this detection; Comparing the recorded current consumption value with a specified value, whereby the measuring device can also carry out this comparison; Inferring a fault when the detected current consumption value is above the specified value and the measuring device can also perform this inference of a fault.

8. Method for carrying out a stress test of an analog circuit (1) according to claim 2 or 4, comprising the steps Providing a measuring device; Supplying the analog circuit (1) with electrical energy; Transferring the analog circuit (1) into a first test state; Increasing a supply voltage by a predetermined stress voltage value for a predetermined period of time; Reverse the increase in supply voltage; Detecting a current consumption of the analog circuit (1) in this first test state and determining a current consumption value by means of the measuring device; Comparing the current consumption value with a specified value; Infer an error if the current consumption value is above the specified value.

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