Analog circuits with reconfiguration mechanism for stress testing and / or IDDQ testing and related methods

Abstract

The invention relates to a MOS, BiCMOS or CMOS-based analog circuit (1). The analog circuit (1) is designed to implement a predetermined circuit function in a normal state of the analog circuit (1). The analog circuit (1) has an analog input or output signal, or has an analog signal inside the analog circuit (1). The analog circuit (1) is connected to test logic (38). The test logic (38) is designed to bring the analog circuit (1) into the normal state and into at least a first test state. The analog circuit (1) comprises a first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) which is designed to perform a function of the analog circuit (1) in accordance with the predetermined circuit function during normal operation. According to the invention, the analog circuit (1) further comprises a second component (S1 to S9; G1 to G9) which is designed to enable the test logic (38) to set a switching state of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in at least the first test state of the analog circuit (1).

Description

Technical Field

[0001] This invention relates to an analog circuit capable of performing IDDQ testing and / or stress testing. Background Technology

[0002] High quality and low defect rates are critical prerequisites for using microelectronic circuits in motor vehicles. Therefore, when manufacturing mixed-signal CMOS circuits for the automotive industry, it is essential to ensure adequate test coverage of the microelectronic circuits after manufacturing. For example, IDDQ testing can be used for digital circuit elements in such automotive microelectronic circuits.

[0003] IDDQ testing is a method used to test for manufacturing defects in CMOS integrated circuits. This method is based on measuring the power supply current (Idd) in a static state (when the circuit is not switched and the inputs hold static values). The power supply current consumed in this state is commonly referred to as the IDDQ quiescent current, or IDD quiescent current. The power supply line is usually called the VDD line, and the associated power supply current is called the IDD current, hence the name.

[0004] IDDQ testing is based on the principle that in a normally operating digital CMOS circuit under static conditions, there is no static current path between the positive and negative voltage supply lines. At the end of the fabrication process, fully automated test equipment tests the manufactured microelectronic circuit. Typically, the digital circuitry of a microelectronic circuit is clock-driven. With each clock edge, the circuit nodes within the digital circuitry of the microelectronic circuit change their logic states. These logic states are associated with the voltage levels of these circuit nodes relative to a reference node at a reference potential. Since circuit nodes always have parasitic node capacitance, this capacitance must charge to the new potential when the logic state changes and consequently, the potential changes. Therefore, charging current flows due to the clock driving of the digital circuitry components of the microelectronic circuit. When the clock stops, the circuit nodes in a standard CMOS circuit typically maintain their potential, thus maintaining their logic level, because each potential current path in the digital section of a microelectronic circuit typically contains at least one P-channel transistor and one N-channel transistor, one of which is always off, while the other is complementary and on. Therefore, apart from the leakage current after the clock of the digital section of the microelectronic circuit stops, no current can flow from the positive power supply voltage line of the microelectronic circuit through the digital section to the negative power supply voltage line of the microelectronic circuit. After the clock is turned off, the state of the digital section of the microelectronic circuit is the aforementioned static state of the digital section of the microelectronic circuit.

[0005] However, in reality, when the clock in the digital section stops, a tiny leakage current flows from the positive power supply line of the microelectronic circuit through the digital section to the negative power supply line. Normally, this leakage current is very small and can be essentially ignored.

[0006] If a digital transistor in the digital section is defective, this typically results in increased leakage current. Leakage current is particularly easy to measure when the transistor should actually be in the off state due to its control. To test the transistor, the test setup uses a specific signal sequence (i.e., a mode) to control the microelectronic circuit. The transistor under test is located in one or more current paths between the positive and negative power supply lines. The test vector applied to the microelectronic circuit by the test system during testing is designed such that when the test system stops clocking, firstly, the transistor under test is in the off state at at least one time position in the test vector; secondly, at that time position, all other transistors in at least one current path containing the transistor under test switch to the on state.

[0007] If the leakage current of the transistor under test increases, the increased leakage current flows through the current path between the positive and negative power supply voltage lines. The test system detects the current in one of the two power supply voltage lines. The test performed by the test system can use this current value, and if the current value is too high (especially exceeding a threshold), it indicates that one or more transistors are defective. In the presence of a defect, the leakage current flowing through the transistor under test is typically several orders of magnitude higher than the current value in the absence of a defect. Therefore, this defect can be detected in the power supply current. Another advantage of IDDQ testing is that the test system can check for a relatively large number of transistor defects in a microelectronic circuit with only a few measurements. Furthermore, the test system can detect transistor defects that cannot be found using conventional static defect test vectors (patterns).

[0008] IDDQ test

[0009] IDDQ testing is slightly more complex than simply measuring supply current. For example, if a line is shorted to a positive supply voltage, it will not draw any additional current even if the logic circuit generating the signal attempts to pull it high. However, if the logic circuit attempts to pull the signal low, it causes a sharp increase in leakage current. If the leakage current exceeds a current threshold in magnitude, this indicates a defect in the component. The test system discards such defective components. Importantly, IDDQ test inputs only require the controllability of the logic state of the digital section nodes, not their observability in a logically observable sense. The observability of the defect's impact is achieved by observing and evaluating the current consumption at the circuit's supply voltage terminals using leakage current.

[0010] However, this controllability of the control signal states of transistors in analog circuits is precisely why the IDDQ test, according to existing technology, is not applicable to the analog portion of mixed-signal circuits. Therefore, mixed-signal circuits typically have separate positive analog power supply lines (powering the analog portion) and positive digital power supply lines (powering the digital portion). Additional circuitry can disconnect the analog circuitry from the digital circuitry.

[0011] This specification uses a simple differential amplifier stage, shown here as an example of an analog circuit application, to explain this problem. Figure 1 An example of this analog circuit 1 is shown. However, the principles described herein and presented below can be applied to other analog circuits.

[0012] Voltage source 2 provides electrical energy to exemplary analog circuit 1. Current source 4 draws electrical energy from power supply voltage line 3 and feeds reference current 5 to first node 6. First transistor 7, connected as a MOS diode, draws the reference current 5 from first node 6, which serves as a reference node, and transfers it to reference potential line 8. First transistor 7, connected as a MOS diode, converts reference current 5 into reference voltage 27. Reference voltage 27 is applied between first node 6 and reference potential line 8. Second transistor 9, together with first transistor 7 connected as a MOS diode, forms a current mirror. Therefore, second transistor 9 acts as a differential current source composed of third transistor 10, fourth transistor 11, fifth transistor 12, and sixth transistor 13. Control electrode 28 of third transistor 10 and control electrode 29 of fourth transistor 11 constitute the differential input of exemplary differential amplifier. Fifth transistor 12, connected as a MOS diode, acts as the operating resistor of the left amplifier branch composed of third transistor 10 and fifth transistor 12. The sixth transistor 13 is connected as a current source for the current mirror formed by the sixth transistor 13 and the MOS diode 12, and also acts as the operating resistor for the right amplifier branch formed by the fourth transistor 11 and the sixth transistor 13.

[0013] The seventh transistor 15 receives the signal at the second node 14 between the fourth transistor 11 and the sixth transistor 13, and amplifies it as part of a source follower circuit consisting of the seventh transistor 15 and the eighth transistor 16. The eighth transistor 16 acts as a current source transistor and therefore also acts as the operating resistor of the source follower circuit. The eighth transistor 16 is part of a current mirror consisting of the eighth transistor 16 and the first transistor 7 connected as a MOS diode.

[0014] Inverter 17 generates an inverted digital transmission clock 19 based on digital transmission clock 18 for use by subsequent transmission gates.

[0015] exist Figure 1In the example, when the digital transmission clock 18 is high, the first transmission gate, composed of the ninth transistor 20 and the tenth transistor 21, can charge the intermediate node 25 to the potential of the source follower's output 26. At this time, the inverting digital transmission clock 19 is low. If the digital transmission clock 18 is low, and therefore the inverting digital transmission clock is high, the first transmission gate, composed of the ninth transistor 20 and the tenth transistor 21, is turned off. In this case, the intermediate node 25 essentially maintains its voltage level due to parasitic capacitance.

[0016] exist Figure 1 In the example, when the digital transmission clock 18 is high, the second transmission gate, consisting of the eleventh transistor 22 and the twelfth transistor 23, can charge the input node 24 of the subsequent analog circuit to the potential of the intermediate node 25. At this time, the inverting digital transmission clock 19 is low. If the digital transmission clock 18 is low, and therefore the inverting digital transmission clock 19 is high, the second transmission gate, consisting of the eleventh transistor 22 and the twelfth transistor 23, is turned off. In this case, the input node 24 essentially maintains its voltage level due to parasitic capacitance.

[0017] The thirteenth transistor 30 can connect the intermediate node 25 to the reference potential 8.

[0018] The first problem that arises is that the reference voltage source, composed of current source 4 and the first transistor 7, has a permanent quiescent current due to the MOS diode connection of the first transistor 7. This current is significantly higher than the leakage current of the first transistor 7 when it is turned off. Therefore, in Figure 1 In the circuit, the first transistor 7 cannot perform the IDDQ test.

[0019] The second problem is that the control input terminal (its gate) of the second transistor 9 always has a reference voltage, causing it to operate as a current source and thus have a continuous quiescent current. This current is much higher than the leakage current of the second transistor 9 when it is off. Therefore, in Figure 1 In the circuit shown, the second transistor 9 cannot perform the IDDQ test.

[0020] The third problem is that the control input (gate) of the eighth transistor 16 always has a reference voltage, causing it to operate as a current source and therefore also have a continuous quiescent current. This current is much higher than the leakage current of the eighth transistor 16 when it is off. Therefore, in Figure 1 In the circuit shown, the eighth transistor 16 cannot perform the IDDQ test.

[0021] The fourth problem is that when the third transistor 10 is turned on, the reference voltage source composed of the second transistor 9 and the fifth transistor 12 has a constant quiescent current due to the MOS diode connection of the fifth transistor 12. This current is typically much higher than the leakage current of the fifth transistor 12 when it is turned off. Therefore, in Figure 1 In the circuit shown, the fifth transistor 12 cannot perform the IDDQ test.

[0022] The fifth problem is that the control input (gate) of the sixth transistor 13 always has a reference voltage, causing it to operate as a current source and thus have a continuous quiescent current. This current is much higher than the leakage current of the sixth transistor 13 when it is off. Therefore, in Figure 1 In the circuit shown, the sixth transistor 13 cannot perform the IDDQ test.

[0023] The sixth problem is that the control input terminal (its gate) of the seventh transistor 15 always has a certain voltage, meaning it is not without quiescent current. Therefore, it also has a continuous quiescent current. This current is much higher than the leakage current of the seventh transistor 15 when it is off. Therefore, in Figure 1 In the circuit shown, the seventh transistor 15 cannot perform the IDDQ test.

[0024] Due to the current source function of the second transistor 9, quiescent current flows through the third transistor 10 and the fourth transistor 11. Although one of the transistors can be turned off at the input, the other amplifier branch still generates quiescent current in power lines 3 and 8, which is much higher than the leakage current of the turn-off transistor. Therefore, in Figure 1 In the circuit, the third transistor 10 and the fourth transistor 11 cannot perform the IDDQ test. For the same reason, in... Figure 1 In the circuit, the fifth transistor 12 and the sixth transistor 13 also cannot perform IDDQ testing.

[0025] Because of the current source function of the eighth transistor 16, quiescent current flows through the eighth transistor 16 and the seventh transistor 15. Therefore, in Figure 1 In the circuit, the seventh transistor 15 and the eighth transistor 16 cannot perform the IDDQ test.

[0026] In contrast, transmission gates do not necessarily have leakage current. If the output terminal 26 of the source follower and the intermediate node 25 are at the same or substantially the same potential, no leakage current will flow through the ninth transistor 20 and the tenth transistor 21. Therefore, the IDDQ test of the ninth transistor 20 and the tenth transistor 21 lacks simulation of the leakage current in these transistors. The same applies to the eleventh transistor 22 and the twelfth transistor 23. Therefore, the IDDQ test of the eleventh transistor 22 and the twelfth transistor 23 lacks simulation of the leakage current in these transistors.

[0027] However, in order to improve functional safety, it is desirable to stress test all transistors in mixed-signal circuits with an increased operating voltage during IDDQ testing, so as to detect imperfectly manufactured transistors and circuit elements, and activate defects that have not yet manifested by stress voltage if necessary.

[0028] Therefore, there are currently problems in generating test vectors for the analog section and in making IDDQ testing applicable to transistors in the analog section of mixed-signal circuits. For the reasons mentioned above, the test coverage of functional test vectors for large digital control buses used in the analog section of mixed-signal circuits is typically very limited.

[0029] Furthermore, unlike digital circuits, designers cannot automatically generate test vectors for analog circuitry. Fully automatic test vector generation (ATPG) for analog circuitry is extremely helpful in achieving optimal test coverage. The control signals used by the digital section to control the analog section (hereinafter referred to as D2A control signals) generally cannot be arbitrarily changed to avoid short circuits, damage, etc.

[0030] The quiescent current consumption and its deviation in the analog section are significantly higher than the expected leakage current of the transistor in the presence of defects. Therefore, specifying a test threshold for the quiescent current is at least difficult, if not impossible.

[0031] Experience shows that applying an increased voltage between the positive power supply line 3 and the reference potential line 8 (VDDA) in the analog section of a mixed-signal circuit causes almost no load on any transistors in the analog section. Experiments and research conducted during the development of the technical concept described in this invention have shown that the load level on the transistors in the analog section is only 2%. This value can be classified as "untestable".

[0032] Implementing a bus system from the digital to the analog section of a mixed-signal circuit typically requires a large number of memory cells (latches), which can contain numerous transistors in the 5V range and have a significant control electrode area. To achieve a zero-defect strategy, such a large control electrode area should be subjected to voltage stress testing.

[0033] US 2005 / 0024075 A1 discloses an apparatus that uses a "defect injection transistor" to generate a defect state in an analog circuit, thereby enabling the detection of the defect state. However, the technical concept of US 2005 / 0024075 A1 does not disclose a method or related apparatus for performing IDDQ testing in a manner similar to that permitted by digital circuits.

[0034] The technical concept disclosed in US 2005 / 0024075 A1 is a method of injecting defect node potential through a "defect injection transistor". In this way, US 2005 / 0024075 A1 improves the excitability of the analog circuit under test.

[0035] However, the technical concept of US 2005 / 0024075 A1 does not solve the problem of the lack of IDDQ testability in analog circuits. None of the circuit examples cited in US 2005 / 0024075 A1 achieve complete IDDQ testability. "Complete" means performing IDDQ testing on all analog transistors. Therefore, the technical concept of US 2005 / 0024075 A1 addresses a completely different problem.

[0036] The technical concept of US 2005 / 0024075 A1 proposes inserting a test block (referred to as BICS in US 2005 / 0024075 A1) into the ground terminal of an analog CMOS circuit block (referred to as CUT in US 2005 / 0024075 A1) and using this test block to monitor the operating current of the analog circuit block CUT. However, this is not the IDDQ test as understood in testing techniques.

[0037] In this regard, this article cites the following content from Wikipedia (source: https: / / en.wikipedia.org / wiki / Iddq_testing):

[0038] “Iddq testing is a method for testing CMOS integrated circuits for the presence of manufacturing faults. It relies on measuring the supplycurrent (Idd) in the quiescent state (when the circuit is not switching and inputs are held at static values). The current consumed in the state iscommonly called Iddq for Idd (quiescent) and hence the name.

[0039] Iddq testing uses the principle that in a correctly operatingquiescent CMOS digital circuit, there is no static current path between thepower supply and ground, except for a small amount of leakage. Many commonsemiconductor manufacturing faults will cause the current to increase byorders of magnitude, which can be easily detected. This has the advantage ofchecking the chip for many possible faults with one measurement. Anotheradvantage is that it may catch faults that are not found by conventionalstuck-at fault test vectors.

[0040] Iddq testing is somewhat more complex than just measuring the supplycurrent. If a line is shorted to Vdd, for example, it will still draw noextra current if the gate driving the signal is attempting to set it to '1'.However, a different input that attempts to set the signal to 0 will show alarge increase in quiescent current, signaling a bad part. Typical Iddq testsmay use 20 or so inputs. Note that Iddq- -test inputs require onlycontrollability, not observability. This is because observability is achieved through the shared power supply connection".

[0041] The translation is as follows: "The Iddq test is a method used to test for manufacturing defects in CMOS integrated circuits. It relies on measuring the supply current (Idd) in a static state (when the circuit is not switching and the inputs hold static values). Therefore, the current consumed in this state is usually referred to as Iddq, i.e., Idd (static)."

[0042] Iddq testing utilizes the following principle: In a normally operating CMOS digital circuit under static conditions, there is no static current path between power supply and ground, and only a small amount of leakage current. Many common semiconductor manufacturing defects can cause current increases of several orders of magnitude, and these defects are easily detected. The advantage of this is that many possible defects in the chip can be checked with a single measurement. Another advantage is that it can capture defects that traditional fixed defect test vectors cannot detect.

[0043] Iddq testing is far more complex than simply measuring supply current. For example, if a line is shorted to Vdd, it will still not draw additional current when the gate used to drive the signal attempts to set it to "1". However, if different inputs attempt to set the signal to 0, it will cause a significant increase in quiescent current, indicating a defect in the device. A typical Iddq test may require around 20 inputs. Note that Iddq test inputs only require controllability, not observability. This is because observability is achieved through a shared power terminal.

[0044] However, the technical concept of US 2005 / 0024075 A1 still indicates that there is a quiescent current path between the positive and negative power supply voltages. The “IDDQ current” mentioned in paragraph

[0042] of US 2005 / 0024075 A1 is not the leakage current of the digital circuit in the static switching state, but the quiescent current of the analog circuit originating from the quiescent current path.

[0045] The technical concept of US 2005 / 0024075 A1 does not allow for the fully automated generation of IDDQ test vectors. This makes it difficult to demonstrate adequate test coverage in circuit designs that comply with ISO 26262 functional safety requirements.

[0046] The technical concept of US 2005 / 0024075 A1 also does not provide any advice on how to handle feedback branches in analog circuits.

[0047] In US 2005 / 0024075 A1 Figure 4 In the circuit shown, operating current is always present, even in the test state, and not just the leakage current of the cutoff transistor. Therefore, US 2005 / 0024075 A1 does not disclose any circuit that can perform IDDQ testing in any state (as described in this invention or as defined in Wikipedia).

[0048] JP 2003-156545 A discloses a semiconductor chip integrating analog and digital circuits. This semiconductor chip is assembled according to the technical concept of JP 2003-156545 A. According to the technical concept of JP 2003-156545 A, the common power supply terminal of the semiconductor chip is used to test semiconductor devices that supply power voltage to the analog and digital circuits to detect leakage current in the digital circuits. According to JP 2003-156545 A, the method includes interrupting the power line from the power supply terminal to the digital circuit during testing and placing the digital circuit in test mode. Summary of the Invention

[0049] Purpose

[0050] Therefore, the objective of this invention is to create a solution that does not have the aforementioned disadvantages of the prior art and has further advantages.

[0051] Solution

[0052] The basic idea of ​​the technical concept proposed here is to use additional switching transistors to switch the transistors of the analog part of the mixed-signal circuit in the test state of analog circuit 1, thereby essentially obtaining a CMOS logic circuit. This circuit can be stimulated by test vectors like a normal CMOS logic circuit, and IDDQ test vectors can be generated for this circuit completely automatically through the ATPG program.

[0053] Therefore, the present invention proposes to provide at least one IDDQ test state for the exemplary analog circuit 1. Furthermore, the present invention proposes to insert additional switches into the circuitry of the analog circuit elements, these switches having at least one switching state during normal operation of the exemplary analog circuit 1, and having at least one IDDQ switching state.

[0054] Therefore, the present invention relates to an analog circuit 1 based on MOS, BiCMOS, or CMOS, wherein the analog circuit 1 is designed to perform a predetermined circuit purpose in its normal state. The analog circuit 1 has one or more input signals and / or one or more output signals. The analog circuit 1 typically includes one or more analog signals internal to the analog circuit 1. According to the proposal, the analog circuit (1) is connected to test logic 38, which is designed to set the analog circuit 1 to a normal state and to set the analog circuit 1 to at least a first test state and / or, if necessary, to other test states, based on control of the test logic 38 by an external measurement system. The analog circuit 1 includes first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) that perform the functions of the analog circuit 1 according to its predetermined circuit purpose in its normal state. Therefore, these first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) represent an actual analog circuit 1 or at least a basic part of an analog circuit 1. These first components are preferably MOS transistors or bipolar transistors. Each of these first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) typically has a control electrode, and each first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) can also be operated as a switch via the control electrode. Each first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) can be in an on state and an off state during its respective switch operation, representing its respective switching state. For the purposes of this paper, the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is fully connected in the ON state, i.e., conductive. Fully connected means that the on-resistance (R) of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) (i.e., the transistor) is within the on-resistance range. ON The resistance (R) corresponds to the minimum on-resistance of these first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), with a deviation of less than 25%. The first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are typically completely off in the off state, i.e., cut off. Complete off refers to the on-resistance (R) of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) (i.e., transistors). OFFThe resistance corresponds to the maximum on-resistance of these first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), and the deviation is less than 25%. Preferably, the analog circuit (1) includes second components (S1 to S9; G1 to G9). Test logic 38 sets the switching state of one or more of the first components (7, 9, 12, 16) through the second components (S1 to S9; G1 to G9) in the first test state of the analog circuit 1. At least one of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) has its control electrodes (33, 34, 36, 37) not directly connected to the input signal or directly connected to the output signal. IDDQ testing of this analog circuit 1 is not described in the prior art. In a first test state, test logic 38 disconnects the control electrodes (33, 34, 36, 37) of the first component (7, 9, 12, 16) from the rest of the analog circuit (1) via at least one switch (S1, S2, S3, S4). Therefore, the control electrodes (33, 34, 36, 37, 39) of the first component (7, 9, 12, 16) in the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are left floating. Thus, these control electrodes are easily affected. However, their potentials are not fixed. Therefore, the switching state of the first component (7, 9, 12, 16) in the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is also not fixed. To set the switch state, test logic 38 uses the first devices (G1, G2, G5, G6) to connect the control electrodes (33, 34, 36, 37, 39) of the first components (7, 9, 12, 16) in the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) to enter the on state or to turn them off to enter the off state. Under normal conditions, test logic 38 controls these first devices (G1, G2, G5, G6) so that they do not affect the control electrodes (33, 34, 36, 37, 39) of the first components (7, 9, 12, 16) in the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) under normal conditions of analog circuit 1.Preferably, the first device (G1, G2, G5, G6) is a tri-state driver. The first test logic 38 switches its output to a tri-state with a high-ohm output resistance in the normal state, and switches to a low-ohm low-level or high-level state in the first test state. The output of the corresponding tri-state driver is connected to the corresponding control electrode (33, 34, 36, 37, 39) of the corresponding first component (7, 9, 12, 16) in the first component (7, 9, 12, 16).

[0055] Under normal conditions, test logic 38 connects the control electrodes (33, 34, 36, 37, 39) of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) to the nodes of the rest of the analog circuit (1) via switches (S1, S2, S3, S4), thereby ensuring the normal function of the analog circuit 1 under normal conditions.

[0056] Preferably, the exemplary analog circuit 1 has at least a normal state, a first IDDQ test state, and a second IDDQ test state. In the normal state, the exemplary analog circuit 1 performs its intended normal operation. In the first IDDQ test state, all P-channel transistors of the exemplary analog circuit 1 are preferably fully turned on, and all N-channel transistors of the exemplary analog circuit 1 are preferably fully turned off. In the second IDDQ test state, all P-channel transistors of the exemplary analog circuit 1 are preferably fully turned off, and all N-channel transistors of the exemplary analog circuit 1 are preferably fully turned on.

[0057] To achieve this, the technical concept proposed here suggests disconnecting all feedback branches via a feedback switch in both the first IDDQ test state and the second IDDQ test state.

[0058] This invention includes an improved analog circuit that can be manufactured using, for example, MOS, BiCMOS, or CMOS semiconductor technologies. For the purposes of this document, semiconductor technologies functionally equivalent to such MOS, BiCMOS, or CMOS semiconductor technologies are all included in the term "MOS, BiCMOS, or CMOS". A semiconductor technology is functionally equivalent if it provides a semiconductor switch having a first terminal, a second terminal, and a control terminal, and the semiconductor switch opens or closes the electrical connection between the first and second terminals according to the potential of the control terminal or an input current. This definition does not take into account any leakage current.

[0059] The technical concept proposed in this invention relates generally to analog circuits. The analog circuit is preferably part of a microintegrated circuit. Such analog circuits typically achieve a predetermined circuit purpose during the intended operation of a circuit using the analog circuit. This predetermined circuit purpose can be, for example, an amplifier, differential amplifier, current source, voltage source, analog multiplier, analog multiplexer, analog filter, oscillator, delay line, phase shifter, analog phase-locked loop (PLL), reset circuit, electronic fuse, analog adder, analog subtractor, analog differentiator, analog integrator, etc., and their interconnections, but the technical concept proposed in this invention is not limited thereto. This invention references, for example, the following books:

[0060] Dietmar Ehrhardt, “Integrated Analog Circuit Technology: Technology, Design, Simulation, and Layout”, Vieweg Publishing, June 28, 2000, 2000 edition, ISBN-10: 3528038608, ISBN-13: 978-352803860;

[0061] Phillip E. Allen and Douglas R. Holberg, "CMOS Analog Circuit Design", Oxford University Press, 3rd edition, international edition, July 13, 2012, ISBN-10: 0199937427, ISBN-13: 978-0199937424;

[0062] Saggio, Giovanni, and Tor Vergata, "Principles of Analog Electronics", Taylor & Francis Inc., January 29, 2014, ASIN: 1466582014, ISBN-10: 9781466582019, ISBN-13: 978-1466582019;

[0063] Ulrich Tietze and Christoph Schenk, "Halbleiter-Schaltungstechnik (Semiconductor Circuit Technology)," Springer Vieweg, 16th edition, expanded and updated, July 5, 2019, ISBN-10: 3662485532, ISBN-13: 978-3662485538.

[0064] An analog circuit must have at least one analog input signal, one analog output signal, or one analog signal within the analog circuit to be considered an analog circuit in the sense of this invention. Power supply voltage lines should be explicitly considered when evaluating whether a circuit is an analog circuit.

[0065] For the definition of analog signals, this invention uses the prior art from the following website as an example: https: / / www.elektronik-kompendium.de / sites / kom / 2405151.htm.

[0066] "An analog signal is a physical quantity whose magnitude (amplitude) and its value over time can change continuously."

[0067] A digital signal (Latin for "digitus," meaning finger) is a physical quantity whose value can only take on specific discrete values. These values ​​correspond to a predetermined number of states. If there are two predetermined states, then these signals are binary (digital) signals.

[0068] To be considered an analog circuit in the sense of this invention, it must have at least one input signal, one output signal, or one signal within the analog circuit. These signals must be continuous in both amplitude and time. The amplitude is typically the potential value of the line carrying the signal relative to the reference node of the analog circuit, or the value of the current in the line carrying the signal.

[0069] In particular, the proposed analog circuit is connected to the test logic (see...). Figure 2 As mentioned above, this test logic is preferably based on IEEE Standard 1149 and its sub-versions. However, it can also simply be a scan path activated by test terminals outside the microintegrated circuit.

[0070] Specifically, the test logic is a digital circuit. Specifically, the test logic is designed to place the analog circuit in a normal state and at least a first test state.

[0071] Preferably, the test logic can place the analog circuit in a normal state and multiple test states. Different test states are used for different test purposes and / or to activate defects in specific parts of the analog circuit during load testing (e.g., voltage stress testing).

[0072] In this regard, the present invention cites Ian A. Grout's "Integrated Circuit Test Engineering: Modern Techniques", Springer London, June 2, 2010 (2006 edition), ISBN-10: 1846280230, ISBN-13: 978-1846280238.

[0073] Specifically, the analog circuit according to the invention includes first components that perform the functions of the analog circuit during normal operation, depending on the purpose of the circuit. In the normal state of the analog circuit, the interconnection of these first components generally corresponds at least partially to circuits in the prior art. It is conceivable that the principles proposed in this invention can also be applied to analog circuits that were not known in the prior art after the disclosure of the technical concept of this invention.

[0074] In particular, to improve testability and / or stress resistance, in addition to the first component, the analog circuit according to the invention further includes a second component that enables the test logic to set the switching state of the first component when the analog circuit is in at least a first test state. Preferably, the test logic controls the additional second component.

[0075] In one embodiment, the analog circuit according to the present invention includes an N-channel transistor and a P-channel transistor.

[0076] Specifically, the second component of the test logic is capable of setting the switching state of the first component in at least a first test state of the analog circuit, such that in the first test state, all N-channel transistors are turned off and all P-channel transistors are turned on, or alternatively, all N-channel transistors are turned on and all P-channel transistors are turned off.

[0077] Similarly, the analog circuit may have a second test state that can be set by test logic, in which all N-channel transistors are turned on and all P-channel transistors are turned off, or alternatively, all N-channel transistors are turned off and all P-channel transistors are turned on.

[0078] Therefore, regarding the switching states of N-channel and P-channel transistors, the second test state is preferably complementary to the first test state.

[0079] In another embodiment, the analog circuit 1 according to the invention includes a positive power supply voltage line and a negative power supply voltage line. As before, the test logic preferably places the analog circuit in a normal state and at least a first test state. Preferably, in this other scenario, the analog circuit also has multiple test states. The above description also applies here.

[0080] In particular, again, the analog circuit 1 includes a first component that performs the intended function of the analog circuit during normal operation.

[0081] Specifically, in addition to the first component, the analog circuit 1 also includes a second component that, in at least a first test state of the analog circuit, enables the test logic to set the switching state of the first component. Thus, the measuring device can control the test logic of the exemplary analog circuit of the exemplary microintegrated circuit, placing the first analog circuit in a test state and thereby controlling the switching state of the first component. In this case, the measuring device can preferably also control the switching state of the second component. Therefore, the analog circuit behaves similarly to a digital circuit in this test state. Therefore, in this test state, the analog circuit can be applied to testing methods for digital circuits. Therefore, methods for planning digital circuit tests (e.g., fully automated test pattern generation and / or IDDQ testing methods) can also be applied to the analog circuit in this test state.

[0082] In particular, the analog circuit according to the invention has multiple potential current paths from the positive power supply voltage line to the negative power supply voltage line. These current paths from the positive power supply voltage line to the negative power supply voltage line of the analog circuit typically include components in the first and / or second components. The analog circuit is preferably designed such that substantially all of the first and / or second components (S1 to S9; G1 to G9) are part of at least one such current path. Therefore, these current paths typically and preferably pass through these first and / or second components.

[0083] The second component enables the test logic to set the switching state of the first component under at least a first test state of the analog circuit. Preferably, the test logic sets the switching state of the first component such that at least one first component and / or at least one second component is turned off in each possible current path from the positive power supply voltage line to the negative power supply voltage line.

[0084] If the measuring device now applies an increased power supply voltage to the analog circuit between the positive and negative power supply lines, this increased voltage is applied to the first and / or second components that are cut off. Therefore, these cut-off components will bear a greater voltage load, which may stress potentially damaged components and typically leads to an increase in leakage current between the positive and negative power supply lines. The measuring device can then detect this leakage current as needed and compare it to an allowable leakage current threshold. If the leakage current value detected by the measuring device is higher than the leakage current threshold, the measuring device can infer the presence of a defect, deviation, quality problem, or similar condition in the analog circuit and can discard the associated microelectronic circuit containing that analog circuit. For clarity, this invention refers to defects, deviations, quality problems, etc., in analog circuits collectively as defects.

[0085] In a further improvement to the above embodiments, a second component of the test logic is capable of setting the switching state of the first component in at least a first test state of the analog circuit. The test logic executes the setting of the switching state of the first component such that exactly one first component and / or exactly one second component is turned off in at least one current path of the analog circuit between the positive and negative power supply voltage lines. This current path is referred to as the target current path. Therefore, in other current paths of the analog circuit between the positive and negative power supply voltage lines (which are not the target current path), multiple components can be turned off. In other current paths of the analog circuit between the positive and negative power supply voltage lines (which are not the target current path), at least one component of the analog circuit is also turned off. Therefore, only leakage current flows between the positive and negative power supply voltage lines of the analog circuit. Then, other components in the target current path are not turned off. Hereinafter, this turned-off component in the target current path is referred to as the IDDQ component.

[0086] By limiting the IDDQ component to the cutoff state in the target current path and switching other components in the relevant current path to the on state, the measuring device can apply a voltage between the positive and negative power supply lines of the analog circuit, and this voltage falls entirely on the IDDQ component. If the measuring device increases the voltage between the positive and negative power supply lines to the maximum permissible value, it ensures that the measuring device applies the maximum load to the IDDQ component through the applied voltage. This will accelerate the aging of the IDDQ component to the maximum extent. Experience shows that such a load will not accumulate over the expected lifespan of the IDDQ component. Experience shows that if the parameters for this load test (e.g., the applied power supply voltage value) are correctly selected, a properly manufactured IDDQ component will not suffer any prior damage.

[0087] In this way, the measuring device can apply specific loads to individual components of an analog circuit. Preferably, test modes generated by the test logic are selected, thereby converting multiple components of the analog circuit into IDDQ components using each test mode. A test mode is a vector that typically contains the switching states of first and second components. By setting the test states, the test logic generates specific test modes, whereby components of the analog circuit will be in the switching states corresponding to those test modes. This is clarified herein, and it applies to the entire solution proposed in this invention.

[0088] By simultaneously setting multiple components of an analog circuit as IDDQ components for corresponding current paths, the number of test states required to perform a complete test of all or most components of the analog circuit is reduced. Attached Figure Description

[0089] Figure 1 An exemplary analog circuit 1 is shown.

[0090] Figure 2 The proposed exemplary analog circuit 1 is shown, which can be reconfigured in the test state by test logic 38, for example, by controlling the switching states of additional components (S1 to S9, G1 to G9) through the JTAG test bus interface, so that it is suitable for IDDQ testing and / or voltage stress testing in such a reconfigured test state.

[0091] Figure 3 Corresponding to Figure 2 The test logic 38 can now also directly control the switching state of the seventh transistor 15.

[0092] Figure 4 It shows that according to Figure 3 Methods for performing IDDQ tests on analog circuits.

[0093] Figure 5 It shows that according to Figure 3 Another method for performing IDDQ testing on analog circuits.

[0094] Figure 6 It shows that according to Figure 2 Methods for performing IDDQ tests on analog circuits.

[0095] Figure 7 It shows that according to Figure 2 A method for stress testing of analog circuits. Detailed Implementation

[0096] Further explanation based on the attached figures

[0097] This invention refers to exemplary cases Figures 2 to 7The present invention is further explained.

[0098] For example, taking the exemplary analog circuit 1 as an example, the technical concept proposed in this invention disconnects the MOS diode circuit of the first transistor 7 by opening the first switch S1 in the first IDDQ test state and the second IDDQ test state. In the normal state, the first switch S1 is closed, thereby forming the MOS diode circuit of the first transistor 7. Therefore, the first switch S1 is a feedback switch, which is closed in the normal operating state and open in both test states (i.e., the first IDDQ test state and the second IDDQ test state). The first switch S1 is preferably a MOS transistor, which is preferably opened or closed by the test logic of a microintegrated circuit, and the exemplary analog circuit 1 is usually part of this microintegrated circuit. For example, the test device can be set to normal operation, the first IDDQ test state, or the second IDDQ test state by the test logic. For example, the test logic can be a JTAG test interface or a similar device.

[0099] Example description

[0100] ===============================================

[0101] This invention utilizes Figure 2 The example shown illustrates the scheme. Figure 2 The exemplary analog circuit 1 shown may explicitly have more than two test states. For clarity, the present invention initially only describes the first IDDQ test state and the second IDDQ test state, but this does not constitute a limitation on the technical concept presented in the present invention.

[0102] Test logic

[0103] ===============================================

[0104] As an example, Figure 2 The analog circuit 1 preferably includes test logic 38. Test logic 38 may, for example, be a test interface conforming to the JTAG boundary scan standard. This invention references, for example, the JTAG standard IEEE 1149. More information about this standard is available at: https: / / de.wikipedia.org / wiki / Boundary_Scan_Test (Non-Patent Document 1).

[0105] The paper “IEEE-1149.x standards: achievements vs. expectations” by LY Ungar, H. Bleeker, JE McDermid, and H. Hulvershorn provides a good overview. This paper is included in the proceedings of IEEE Autotestcon 2001 (IEEE Systems Readiness Technology Conference) (No.: 01CH37237), 2001, pp. 188-205, DOI: 10.1109 / AUTEST.2001.948964 (Non-Patent Document 2).

[0106] IEEE Standard 1149 includes several sub-standards:

[0107] "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks", IEEE Std 1149.6-2015 (revised from IEEE Std 1149.6-2003), pp. 1-230, March 18, 2016, DOI: 10.1109 / IEEESTD.2016.7436703 (Non-Patent Document 3).

[0108] "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test AccessPort and Boundary-Scan Architecture", IEEE Std 1149.7-2009, pp. 1-985, February 10, 2010, DOI: 10.1109 / IEEESTD.2010.5412866 (Non-Patent Document 4).

[0109] "IEEE Standard for Test Access Port and Boundary-Scan Architecture – Redline", IEEE Std 1149.1-2013 (revised from IEEE Std 1149.1-2001), Redline version, pp. 1-899, May 13, 2013 (Non-Patent Document 5).

[0110] "IEEE Standard for Test Access Port and Boundary-Scan Architecture", IEEE Std 1149.1-2013 (revised from IEEE Std1149.1-2001), pp. 1-444, May 13, 2013, DOI: 10.1109 / IEEESTD.2013.6515989 (Non-Patent Document 6).

[0111] "IEEE Standard for a Mixed-Signal Test Bus", IEEE Std 1149.4-2010 (revised from IEEE Std 1149.4-1999), pp. 1-116, March 18, 2011, DOI: 10.1109 / IEEESTD.2011.5738198 (Non-Patent Document 7).

[0112] "IEEE Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and / or Active Components", IEEE Std 1149.8.1-2012, pp. 1-95, August 9, 2012, DOI: 10.1109 / IEEESTD.2012.6259815 (Non-Patent Document 8).

[0113] "IEEE Standard for High-Speed ​​Test Access Port and On-Chip Distribution Architecture", IEEE Std1149.10-2017, pp. 1-96, July 28, 2017, DOI: 10.1109 / IEEESTD.2017.7995164 (Non-Patent Document 9).

[0114] "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks - Redlin", IEEE Std 1149.6-2015 (revised from IEEE Std 1149.6-2003), Redlin version, pp. 1-441, March 18, 2016 (Non-Patent Document 10).

[0115] "IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device", IEEE Std 1687-2014, pp. 1-283, December 5, 2014, DOI: 10.1109 / IEEESTD.2014.6974961 (Non-Patent Document 11).

[0116] "IEEE Draft Standard for Reduced-Pin and Enhanced-Functionality TestAccess Port and Boundary-Scan Architecture", IEEE P1149.7 / D6, July 2020, pp. 1-1043, November 3, 2020 (Non-Patent Document 12).

[0117] "IEEE Draft Standard for a Mixed-Signal Test Bus", IEEE P1149.4 / D2, September 2010, pp. 1-113, October 7, 2010 (Non-Patent Document 14).

[0118] "IEEE Approved Draft Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits", IEEE P1838_D3.00, September 2019, pp. 1-63, November 7, 2019 (Non-Patent Document 15).

[0119] For completeness, the present invention also cites the following references.

[0120] GOD Acevedo and J. Ramírez-Angulo's "VDDQ: a built-in self-test scheme for analog on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard" is included in the "Proceedings of the 4th IEEE International Conference on Devices, Circuits and Systems in Caracas" (No. 02TH8611), 2002, pp. I026-I026, DOI: 10.1109 / ICCDCS.2002.1004083 (Non-Patent Document 13).

[0121] For clarity, Figure 2 The control lines between test logic 38 and the tri-state gates (G1 to G9) explained below, the switches (S1 to S9) also explained below, and other test control lines also explained below are not shown.

[0122] However, the control lines between test logic 38 and the tri-state gates (G1 to G9) explained below, the switches (S1 to S9) also explained below, and other test control lines also explained below are necessary for the functionality of the technical principles disclosed in this invention. Therefore, the accompanying drawings are merely schematic and simplified.

[0123] Changes in the interconnection of the first transistor 7

[0124] ===============================================

[0125] The technical concept proposed in this invention further proposes, taking an exemplary analog circuit 1 as an example, that the MOS diode circuit of the first transistor 7 is disconnected by opening the first switch S1 in the first IDDQ test state and by opening the first switch S1 in the second IDDQ test state. Thus, the first switch S1 disconnects the control electrode 33 of the first transistor 7 from the first node 6. Therefore, after the first switch S1 is opened, the potential of the control electrode 33 of the first transistor 7 is undefined. However, for ordered testing, it is necessary to establish a defined potential of the control electrode 33 of the first transistor 7 relative to the reference potential line 8. In the normal state, the first switch S1 is closed, thereby causing the MOS diode circuit of the first transistor 7 to close, and generating this unique potential on the control electrode 33 of the first transistor 7. Therefore, the first switch S1 is a feedback switch that is closed during normal operation and open in both test states (i.e., the first IDDQ test state and the second IDDQ test state). The first switch S1 is preferably a MOS transistor, and its opening or closing is preferably implemented by the test logic of a microintegrated circuit.

[0126] General feedback handling and characteristics of tri-state gates

[0127] ===============================================

[0128] During normal operation, feedback determines the potential of the control electrodes of certain transistors in analog circuit 1. However, by turning on the feedback switch, the potentials of the control electrodes of these transistors are no longer defined.

[0129] Therefore, the present invention proposes to preferably connect these control electrodes to a device that sets the potential of the target control electrode to a defined potential in a first IDDQ test state or a second IDDQ test state, but does not affect it in a normal state.

[0130] This invention proposes setting each control electrode (which is in a floating state due to the opening of the feedback switch, i.e., its potential is undefined) to a defined potential using a tri-state gate (usually additional). For simplicity, let's assume, for example, that the tri-state gate includes a first tri-state transistor that pulls the output of the tri-state gate to a positive supply potential when closed and does not affect the output when open. Further, for simplicity, let's assume that the tri-state gate includes a second tri-state transistor that pulls the output of the tri-state gate to a negative supply potential when closed and does not affect the output when open. The control logic ensures that the first and second tri-state transistors are never closed simultaneously. The output of the tri-state gate has three states.

[0131] In the first state, the output of the tri-state gate is in a high-impedance state. In this high-impedance state, in this example, both the first and second tri-state transistors are turned on. Therefore, in the first state, the tri-state gate does not affect the node at its output.

[0132] In the second state, the output of the tri-state gate is connected to the negative power supply line. In this high-impedance state of the tri-state gate, the first tri-state transistor is turned on, and the second tri-state transistor is turned off.

[0133] In the third state, the output of the tri-state gate is connected to the positive power supply line. In this high-impedance state of the tri-state gate, the first tri-state transistor is closed, and the second tri-state transistor is open.

[0134] Implementation of Exemplary Analog Circuit 1

[0135] ===============================================

[0136] Therefore, the present invention proposes inserting a first switch S1 into the reference voltage line of the first node 6. Test logic 38 controls the first switch S1. For clarity, an example is provided. Figure 2 The control lines from test logic 38 to the first switch S1 are not shown. If the exemplary analog circuit 1 is in a normal state, test logic 38 closes the first switch S1. If the exemplary analog circuit 1 is in a first IDDQ test state or a second IDDQ test state, test logic 38 opens the first switch S1, thereby disconnecting the feedback from the first transistor 7 to itself.

[0137] The present invention further proposes connecting the control electrode 33 of the first transistor 7 to the output terminal of the first tri-state gate G1. Test logic 38 controls the first tri-state gate G1. For clarity, an example is provided. Figure 2 The control lines from test logic 38 to the first tri-state gate G1 are not shown. Therefore, when the exemplary analog circuit 1 is in a first IDDQ test state or a second IDDQ test state and the first switch S1 is open, test logic 38 can apply a defined logic level to the control electrode 33 of the first transistor 7 via the first tri-state gate G1. If the exemplary analog circuit 1 is in a normal state, the test logic circuit 1 switches the first tri-state gate G1 to high impedance. If the exemplary analog circuit 1 is in a normal state, the first tri-state gate G1 ideally behaves as if it does not exist and does not interfere with the analog circuit function of the exemplary analog circuit 1.

[0138] If the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the first tri-state gate G1 ideally sets the potential at the control electrode 33 of the first transistor 7. If the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the first tri-state gate G1 ideally sets the switching state of the first transistor 7.

[0139] Therefore, the present invention also proposes connecting the control electrode 36 of the fifth transistor 12 to the output of the second tri-state gate G2. Test logic 38 controls the second tri-state gate G2. For clarity, the control lines from test logic 38 to the second tri-state gate G2 are not shown in the exemplary drawings. Therefore, when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, and the second switch S2 is open, test logic 38 can apply a defined logic level to the control electrode of the fifth transistor 12.

[0140] exist Figure 1 In the example, the control electrode 28 of the third transistor 10 should be used as an external input to the exemplary analog circuit 1.

[0141] exist Figure 1 In the example, the control electrode 29 of the fourth transistor 11 should be used as an external input to the exemplary analog circuit 1.

[0142] Therefore, this invention proposes connecting the control electrode 28 of the third transistor 10 to the output terminal of the third tri-state gate G3. Test logic 38 preferably controls the third tri-state gate G3. For clarity, an example is provided. Figure 2The control lines from test logic 38 to the third tri-state gate G3 are not shown. Therefore, when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, test logic 38 can apply a defined logic level to the control electrode 28 of the third transistor 10. Preferably, a seventh switch S7 is inserted in the line of the control electrode 28 of the third transistor 10. When the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, this switch disconnects the feed point of the control electrode 28 of the third transistor 10 and the third tri-state gate G3 located on one side of the seventh switch S7 from the third node 31 located on the other side of the seventh switch S7. At this time, the seventh switch S7 is preferably open. In the normal state, the seventh switch S7 is preferably closed, and preferably connects the third node 31 to the control electrode 28 of the third transistor 10. Therefore, the seventh switch S7 can be inserted into the circuit of the control electrode 28 of the third transistor 10. When the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, the switch S7 disconnects the input of the third node 31 from the feed point of the third tri-state gate G3 and the control electrode 28 of the third transistor 10; when the exemplary analog circuit 1 is in the normal state, the switch S7 connects the input of the third node 31 to the feed point of the third tri-state gate G3 and the control electrode 28 of the third transistor 10. The test logic 38 preferably controls the additional seventh switch S7.

[0143] The present invention further proposes connecting the control electrode 29 of the fourth transistor 11 to the output terminal of the fourth tri-state gate G4. Test logic 38 controls the fourth tri-state gate G4. For clarity, an example is provided. Figure 2The control lines from test logic 38 to the fourth tri-state gate G4 are not shown. Therefore, when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, test logic 38 can apply a defined logic level to the control electrode 29 of the fourth transistor 11. Preferably, an eighth switch S8 is inserted in the line of the control electrode 29 of the fourth transistor 11. When the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, this eighth switch S8 disconnects the feed point of the control electrode 29 of the fourth transistor 11 and the fourth tri-state gate G4 located on one side of the eighth switch S8 from the fourth node 32 located on the other side of the eighth switch S8. At this time, the eighth switch S8 is preferably open. In the normal state, the eighth switch S8 is preferably closed, and preferably connects the fourth node 32 to the control electrode 29 of the fourth transistor 11. Therefore, it is advisable to insert an eighth switch S8 into the circuit of the control electrode 29 of the fourth transistor 11. When the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, this switch S8 disconnects the input of the fourth node 32 from the feed point of the fourth tri-state gate G4 and the control electrode 29 of the fourth transistor 11; when the exemplary analog circuit 1 is in the normal state, this switch S8 connects the input of the fourth node 32 to the feed point of the fourth tri-state gate G4 and the control electrode 29 of the fourth transistor 11. The test logic preferably controls this additional switch.

[0144] Disconnection of electrically connected circuit nodes

[0145] ================================================

[0146] The present invention further proposes that when the exemplary analog circuit is in an IDDQ test state, particularly in a first IDDQ test state or a second IDDQ test state, the control electrodes of the exemplary analog circuit 1 that are electrically connected to each other are disconnected from each other by an additional switch.

[0147] exist Figure 1 In the example, the control electrode of the first transistor 7, the control electrode of the second transistor 9, and the control electrode 37 of the eighth transistor 16 are connected to each other through the first node 6, which serves as a reference voltage line.

[0148] Figure 2 Examples of variations of the invention in this respect are shown.

[0149] For example, this invention proposes that when the exemplary analog circuit 1 is in a first IDDQ test state or a second IDDQ test state, the test logic 38 preferably disconnects the control electrode 34 of the second transistor 9 from the first node 6 via the third switch S3; when the exemplary analog circuit 1 is in a normal state, the test logic 38 preferably connects the control electrode 34 of the second transistor 9 to the first node 6 via the third switch S3. Therefore, when the exemplary analog circuit 1 is in a normal state, the test logic 38 preferably closes the third switch S3; when the exemplary analog circuit is in a first IDDQ test state or a second IDDQ test state, the test logic 38 preferably opens the third switch S3. The test logic 38 preferably controls the third switch S3. For clarity, the exemplary... Figure 2 These control lines from test logic 38 to the third switch S3 are not shown.

[0150] For example, this invention proposes that when the exemplary analog circuit 1 is in a first IDDQ test state or a second IDDQ test state, the test logic 38 preferably disconnects the control electrode 37 of the eighth transistor 16 from the first node 6 via the fourth switch S4; when the exemplary analog circuit 1 is in a normal state, the test logic 38 preferably connects the control electrode 37 of the eighth transistor 16 to the first node 6 via the fourth switch S4. Therefore, when the exemplary analog circuit 1 is in a normal state, the test logic 38 preferably closes the fourth switch S4; when the exemplary analog circuit is in a first IDDQ test state or a second IDDQ test state, the test logic 38 preferably opens the fourth switch S4. The test logic 38 preferably controls the fourth switch S4. For clarity, the exemplary... Figure 2 These control lines from test logic 38 to the fourth switch S4 are not shown.

[0151] To ensure that the control electrode 34 of the second transistor 9 does not have an undefined potential in either the first IDDQ test state or the second IDDQ test state, this invention proposes connecting the control electrode 34 of the second transistor 9 to the output of the fifth tri-state gate G5. The test logic 38 preferably controls the fifth tri-state gate G5. Therefore, when the exemplary analog circuit 1 is in either the first or second IDDQ test state, and the third switch S3, the first switch S1, and the fourth switch S4 are thus open, the test logic 38 is typically able to apply a defined logic level to the control electrode 34 of the second transistor 9.

[0152] Indirect control of switch state

[0153] Since test logic 38 can typically control the switching states of the second transistor 9, the third transistor 10, the fourth transistor 11, and the fifth transistor 12 in either the first or second IDDQ test state of the exemplary analog circuit 1, test logic 38 can also control the switching state of the sixth transistor 13 in either the first or second IDDQ test state. This is because test logic 38 can typically set the potential of the control electrode 44 of the sixth transistor 13 by setting the switching states of the second transistor 9, the third transistor 10, the fourth transistor 11, and the fifth transistor 12. Therefore, test logic 38 can typically set the switching state of the sixth transistor 13 by setting the switching states of the second transistor 9, the third transistor 10, the fourth transistor 11, and the fifth transistor 12.

[0154] Since test logic 38 can control the switching states of the sixth transistor 13 and the fourth transistor 11 in either the first IDDQ test state or the second IDDQ test state, test logic 38 can also typically control the switching state of the seventh transistor 15 in either the first IDDQ test state or the second IDDQ test state. This is because test logic 38 can typically control the switching states of the sixth transistor 13 and the fourth transistor 11 in either the first IDDQ test state or the second IDDQ test state, therefore test logic 38 can also typically control the potential of the second node 14 in either the first IDDQ test state or the second IDDQ test state, and thus can also typically control the potential of the control electrode 39 of the seventh transistor 15 in either the first IDDQ test state or the second IDDQ test state.

[0155] Since test logic 38 can control the switching state of the seventh transistor 15 and the eighth transistor 16 in the first IDDQ test state or the second IDDQ test state, test logic 38 can also control the potential of the output terminal 26 of the source follower composed of the seventh transistor 15 and the eighth transistor 16 in the first IDDQ test state or the second IDDQ test state.

[0156] Processing of intermediate nodes

[0157] Analog circuits typically also include switches designed to pull nodes such as intermediate node 25 to the supply voltage potential or a similar potential under certain conditions during normal operation. Figure 1 In the case of the exemplary analog circuit 1, the thirteenth transistor 30 is such a transistor.

[0158] One side of this transistor is connected to a power supply voltage line of a first polarity, and the other side is connected to a node on an exemplary electrical side. The invention also proposes providing an additional switch for connecting this corresponding node to another power supply voltage line.

[0159] This invention proposes a design for controlling such a transistor and an additional switch such that, under normal conditions of the exemplary analog circuit, the additional switch is in the open state, and the transistor operates normally according to other control signals 40 of the entire circuit, as if no change has occurred. However, under either the first or second IDDQ test state of the exemplary analog circuit 1, the additional switch and transistor operate as tri-state gates, allowing the test logic to control the voltage level of the nodes.

[0160] The exemplary thirteenth transistor 30 is such a transistor. One side of the exemplary analog circuit 1's thirteenth transistor 30 is connected to a power supply voltage line 8 of the first polarity, and the other side is connected to an intermediate node 25 of the exemplary analog circuit 1. The invention also proposes to provide an additional fifth switch S5, which can connect the corresponding intermediate node 25 to another power supply voltage line.

[0161] The present invention proposes to design the control of the test logic 38 on the thirteenth transistor 30 and the additional fifth switch S5 such that, under the normal state of the exemplary analog circuit 1, the additional fifth switch S5 is in the open state, and the thirteenth transistor 30 operates normally according to other control signals of the entire circuit, as if no change has occurred.

[0162] Specifically, this can mean, for example, that in Figure 2 In the example, digital transmission clock 18 is the input signal to test logic 38, and in the normal state of exemplary analog circuit 1, digital transmission clock 18 is equal to variant digital transmission clock 41, and in either the first IDDQ test state or the second IDDQ test state, test logic 38 typically generates variant digital transmission clock 41 in a manner independent of digital transmission clock 18. Furthermore, this could mean, for example, that in Figure 2 In the example, the inverted digital transmission clock 19 is the input signal of the test logic 38, and in the normal state of the exemplary analog circuit 1, the inverted digital transmission clock 19 is equal to the distorted inverted digital transmission clock 42, and in the first IDDQ test state or the second IDDQ test state, the test logic 38 typically generates the distorted inverted digital transmission clock 42 in a manner independent of the inverted digital transmission clock 19.

[0163] However, in the first or second IDDQ test state of the exemplary analog circuit 1, the additional fifth switch S5 and the thirteenth transistor 30 operate together as an eighth tri-state gate G8, allowing the test logic 38 to preferably control the voltage level of the intermediate node 25. For this purpose, the test logic 38 preferably controls the potential of the control electrode 43 of the thirteenth transistor 30. This means that the test logic preferably controls the switching state of the thirteenth transistor 30. Preferably, in Figure 2In the example, under normal conditions of the exemplary analog circuit 1, the signal at the control electrode 43 of the thirteenth transistor 30 is equal to the inverted digital transmission clock 19. Under the first IDDQ test state and the second IDDQ test state, the test logic 38 typically generates the signal 19 at the control electrode 43 of the thirteenth transistor 30 in a manner independent of the inverted digital transmission clock.

[0164] exist Figure 2 In the exemplary analog circuit 1, the ninth transistor 20 and the tenth transistor 21 form a so-called transmission gate, which, with proper control of the control electrodes of the ninth transistor 20 and the tenth transistor 21, connects the intermediate node 25 to the output 26 of the source follower composed of the seventh transistor 15 and the eighth transistor 16. Figure 2 In the example, test logic 38 generates a variant digital transmission clock 41 such that when the exemplary analog circuit 1 is in a normal state, the variant digital transmission clock 41 is equal to the digital transmission clock 18, and when the exemplary analog circuit 1 is in a first IDDQ test state or a second IDDQ test state, test logic 38 generates the variant digital transmission clock 41 in a manner independent of the digital transmission clock 18.

[0165] Preferably, test logic 38 then controls the control electrodes of the ninth transistor 20, tenth transistor 21, twelfth transistor 23, eleventh transistor 22, and thirteenth transistor 30 in a manner independent of each other, wherein test logic 38 prevents and locks out uncontrolled lateral currents. In the first or second IDDQ test state of the exemplary analog circuit 1, test logic 38 can typically control the switching states of the seventh transistor 15, eighth transistor 16, thirteenth transistor 30, ninth transistor 20, tenth transistor 21, and fifth switch S5 such that no lateral current occurs at these locations.

[0166] Figure 3 Basically with Figure 2 Correspondingly, but with a difference, the ninth switch S9 can disconnect the second node 14 from the control electrode 39 of the seventh transistor 15.

[0167] For example, this invention proposes that when the exemplary analog circuit 1 is in a first IDDQ test state or a second IDDQ test state, the test logic 38 preferably disconnects the control electrode 39 of the seventh transistor 15 from the second node 14 via an additional ninth switch S9, and when the exemplary analog circuit 1 is in a normal state, the test logic 38 preferably connects the control electrode 39 of the seventh transistor 15 to the second node 14 via the ninth switch S9. Therefore, when the exemplary analog circuit 1 is in a normal state, the test logic 38 preferably closes the ninth switch S9, and when the exemplary analog circuit is in a first IDDQ test state or a second IDDQ test state, the test logic 38 preferably opens the ninth switch S9. The test logic 38 preferably controls the ninth switch S9. For clarity, the exemplary... Figure 3 These control lines from test logic 38 to the ninth switch S9 are not shown.

[0168] To ensure that the control electrode 39 of the seventh transistor 15 does not have an undefined potential in the first IDDQ test state or the second IDDQ test state, the present invention proposes to preferably connect the control electrode 39 of the seventh transistor 15 to the output terminal of the ninth tri-state gate G9. The test logic 38 preferably controls the ninth tri-state gate G9. Thus, when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, and the ninth switch S9 is open, the test logic 38 is generally able to apply a defined logic level to the control electrode 39 of the seventh transistor 15. Therefore, when the exemplary analog circuit 1 is in the first IDDQ test state or the second IDDQ test state, and the ninth switch S9 is open, the test logic 38 is also generally able to control the switching state of the seventh transistor 15.

[0169] This simplifies test pattern generation because test logic 38 no longer needs to generate and set a pattern sequence based on multiple predetermined pattern time series. This simplifies the test pattern generation process for generating the pattern sequence required for test logic 38. This reduces the testing time of the measuring device, demonstrating economic advantages.

[0170] In a transmission gate having a first transmission gate terminal and a second transmission gate terminal, test logic 38 may also preferably control the potentials at the first and second transmission gate terminals in a first IDDQ test state or a second IDDQ test state via at least one additional switch (here, the fifth switch S5). In this context, "control" preferably means that test logic 38 can apply a voltage equal to the operating voltage to the transmission gate by controlling the transmission gate and the transistors and switches used to determine the potentials at the first and second transmission gate terminals, wherein the direction of the voltage across the transmission gate can preferably be specified by the test logic.

[0171] Figure 2The example analog circuit 1 in the example is now configured as follows: Test logic 38 can also connect the analog output 24 of the exemplary analog circuit 1 to a positive or negative power supply voltage via the seventh tri-state gate G7 in either the first IDDQ test state or the second IDDQ test state. Figure 2 In the normal state of the exemplary analog circuit 1, the output of the seventh tri-state gate G7 is preferably in a high impedance state because the switch of the seventh tri-state gate G7 is usually in the open state.

[0172] Voltage stress load used to activate previously damaged components

[0173] In a first exemplary embodiment of the invention, maximum voltage stress is applied to the transistors of the exemplary analog circuit 1 prior to actual IDDQ testing to detect potential defects in the transistors. Normally, such potential defects would not cause previous functional tests to fail because the transistors function normally. The voltage stress that perfectly manufactured transistors could withstand without damage would further damage these previously damaged transistors, causing the stress test to amplify the effects of damage already increased during manufacturing testing, to the point that the measuring device used to measure the exemplary analog circuit 1 could detect it.

[0174] In this first exemplary embodiment, the present invention proposes, for example, in a first test step, that a measuring device uses test logic 38 to switch all P-channel transistors of the exemplary analog circuit 1 to the on state and all N-channel transistors to the off state in a first IDDQ test state of the exemplary analog circuit 1. The measuring device increases the power supply voltage to the maximum permissible level and maintains it for the maximum permissible time. This causes previously damaged transistors in the exemplary analog circuit 1 to be damaged. However, this does not damage previously undamaged transistors in the exemplary analog circuit 1. The maximum permissible time for this stress load depends on the semiconductor or CMOS technology used. The maximum permissible time is preferably determined during the development of the semiconductor or CMOS technology, or during component certification of the technical concept disclosed in this invention, by load testing a sufficient number of components, and manufacturing parameters are preferably typically controlled during production testing and load testing.

[0175] In this first exemplary embodiment, the present invention proposes, for example, in a second test step, that the measuring device uses test logic 38 to switch all N-channel transistors of the exemplary analog circuit 1 to the on state and all P-channel transistors to the off state in a second IDDQ test state of the exemplary analog circuit 1. The measuring device increases the power supply voltage to the maximum permissible level and maintains it for the maximum permissible time. This causes previously damaged transistors in the exemplary analog circuit 1 to be damaged. However, this does not damage previously undamaged transistors in the exemplary analog circuit 1.

[0176] If it is not possible to bring all P-channel transistors and / or all N-channel transistors into the expected switching state, then insert additional switches or tri-state gates into the design to isolate the control nodes of these transistors from other nodes in the first IDDQ test state and the second IDDQ test state, and to be able to control them according to the example above.

[0177] In the context of this invention, for example, the measuring device and / or testing process of analog circuit 1 may perform the first step and the second step individually or in any order.

[0178] Leakage current measurement of individual transistors

[0179] In a second exemplary embodiment of the invention, a measuring device applies a typically increased power supply voltage to an exemplary analog circuit 1. The measuring device then sequentially places the exemplary analog circuit 1 into different test states using test logic 38. In each test state of the exemplary analog circuit 1, the test logic 38 typically sets the switching states of the transistors, switches, and tri-state gates of the exemplary analog circuit 1 in a different manner. Hereinafter, the switching state vectors of these elements of the exemplary analog circuit 1 (i.e., the transistors, switches, and tri-state gates of the exemplary analog circuit 1) are referred to as modes. Therefore, the difference between two different modes involves only the switching state of a single transistor, a single switch, or a single tri-state gate in the exemplary analog circuit 1 between the two modes. However, typically, for two different modes, at least two switching states of at least two of these elements are different between the two modes. Developers of manufacturing tests typically select modes such that only leakage current flows in each of these test states. To this end, the developers designed control signals for the measuring device such that the test logic generates and controls the transistors, switches, and tri-state gates in such a way that at least one transistor or switch is turned off in all potential current paths between the positive and negative power supply voltages, and no lateral current flows from the positive power supply voltage line to the negative power supply voltage line in the exemplary analog circuit 1. Therefore, in the sense of this invention, the lateral current is typically a short-circuit current flowing from the positive power supply voltage line 3 to the negative power supply voltage line 8 of the exemplary analog circuit 1, or a fault current with the same effect. Preferably, in each of these test states, the test logic 38 should control the transistors, switches, and tri-state gates such that in at least one current path between the positive and negative power supply voltage lines (or their functional equivalents), exactly one transistor or exactly one switch is turned off, and the other transistors and switches in that current path are turned on. In all other potential current paths between the positive and negative power supply voltage lines (or their functional equivalents), at least one switch is turned on, or at least one transistor is turned off, so that current cannot flow through that path. These switches may also explicitly refer to switches within the tri-state gates. This invention refers to the transistor or switch in the off state as the "IDDQ test transistor" in this test state. The measuring device then uses test logic 38 to sequentially set each test state in chronological order. During this process, test logic 38 preferably sets a mode specific to each test state. The measuring device preferably determines the leakage current in each test state. The leakage current is typically the current consumption of the exemplary analog circuit 1, preferably the current consumption through the power supply voltage line. The measuring device compares the detected leakage current values ​​in each test state with a set value. The set value can be global, specific to a group of test states, or specific to each test state.Mixing of test states is also conceivable. The current consumption of the exemplary analog circuit 1 is typically the leakage current of the transistors being tested by IDDQ in each test state. Preferably, the measuring device changes the test states in the form of a pattern generated by test logic 38 until all transistors and switches of the exemplary analog circuit 1 have undergone at least one IDDQ test. In a preferred embodiment, the measuring device can control the test logic 38, for example, via a JTAG test bus interface. The advantage of using this method in conjunction with the switches and tri-state gates in the exemplary analog circuit 1 is that: firstly, the leakage current of each transistor can be measured; secondly, when the measuring device measures the leakage current of the transistors, maximum voltage stress can be applied to each transistor. Furthermore, the test patterns used to generate the control signals for setting the test patterns in the test logic 38 can be generated using the ATPG method. The test logic 38 should reliably prevent lateral current.

[0180] The testing procedure preferably includes an initial stress test, which utilizes the first embodiment of the invention to maximize the activation of potential defects by applying the maximum supply voltage, and optionally followed by a systematic measurement of the leakage current of all transistors by one or more IDDQ measurements (possibly using different modes).

[0181] Furthermore, practice has shown that in many cases, it is sufficient to perform stress testing using the method described in the first embodiment of the present invention, and then measure the current consumption of the exemplary analog circuit 1 during normal operation. However, the accuracy of this measurement method is relatively low.

[0182] This invention proposes combining the testing of the exemplary analog circuit 1 with digital testing of the measuring device. To achieve this, the invention proposes integrating digital flip-flops (memory cells) into the scan path of test logic 38 in one, several, or all test states. These digital flip-flops thus block signals traveling to and from the analog circuit 1 in these test states. Simply put, the "gates" of the exemplary analog circuit are therefore turned off and controlled by test logic 38, which can control these digital flip-flops, or these digital flip-flops can be part of test logic 38.

[0183] The measuring device sets the test state and mode through the scan path of test logic 38, and controls test logic 38 accordingly.

[0184] When measurements are performed in a clock-stopped test state, the power supply current of the exemplary analog circuit should generally be close to zero in different states with different modes. Actual testing conducted during the development of the method of this invention showed that very good results could be obtained by using an automatically generated IDDQ test pattern (containing approximately 20 IDDD measurement points).

[0185] The development of this invention demonstrates that voltage stress (typically an increased gate voltage lasting 20 ms) can damage weaker transistors. Subsequently, a significant increase in leakage current can be measured. These voltage overshoot levels and overshoot durations depend heavily on the specific semiconductor technology or CMOS technology used to implement analog circuit 1.

[0186] To address the aforementioned problems, this invention further proposes a method for performing IDDQ testing on analog circuit 1. Figure 4 The method is illustrated in a simplified schematic diagram. Assume analog circuit 1 is, for example, connected to... Figure 3 The analog circuit 1 corresponding to the embodiment shown.

[0187] The method presented here involves multiple steps.

[0188] If no measuring device is available, the method begins at step 400, which provides the measuring device.

[0189] In subsequent steps, power is preferably supplied to analog circuit 1 (401) via a measuring device.

[0190] In a subsequent step, analog circuit 1 is switched to a first test state (402), wherein the measuring device preferably performs this switch via test logic 38 (e.g., via a JTAG test bus interface).

[0191] In subsequent steps, the current consumption (403) of the analog circuit 1 under the first test state is detected by a measuring device, and the current consumption value is determined. The measuring device preferably detects the current value of one of the power supply voltage lines 3 and 8 fed to the analog circuit 1.

[0192] In a subsequent step, the detected current consumption value is compared with a set value (404), wherein the comparison is preferably performed by the measuring device.

[0193] In subsequent steps, if the current consumption value is greater than the set value, a defect is deduced (405), wherein the measuring device preferably performs the deduction, and preferably, in the event of such a defect, the analog circuit 1 that may be defective is discarded (406).

[0194] If the measuring device does not infer a defect in analog circuit 1 in the previous step 405, then analog circuit 1 can be used as intended with a higher probability if it is not discarded for other reasons in further, subsequent or previous tests (407).

[0195] To address the aforementioned problems, this invention also proposes a method for performing IDDQ testing on analog circuit 1. Figure 5The method is illustrated in a simplified schematic diagram. Assume analog circuit 1 is, for example, connected to... Figure 3 The analog circuit 1 corresponding to the embodiment shown.

[0196] For example, with Figure 3 Unlike the embodiment shown, analog circuit 1 should now have one or more other test states in addition to the first test state.

[0197] This invention refers to these other test states and the first test state collectively as "test states".

[0198] These test states should preferably be distinguished such that at least one IDDQ component in one test state differs from all other IDDQ components in all other test states. Therefore, this IDDQ component in that test state is different from any other IDDQ component in other test states.

[0199] The method presented here involves multiple steps.

[0200] If no measuring device is available, the method begins at step 500, which provides the measuring device.

[0201] In subsequent steps, power is preferably supplied to analog circuit 1 via a measuring device (501).

[0202] In a subsequent step, the analog circuit 1 is switched to a test state (502) by setting and adopting one of the test states, wherein the measuring device preferably performs this switch and setting via test logic 38 (e.g., via a JTAG test bus interface), and then the analog circuit 1 adopts the test state.

[0203] In subsequent step a), the current consumption (503) of the analog circuit 1 under the test state is detected by a measuring device and the current consumption value is determined. The measuring device preferably detects the current value of one of the power supply voltage lines 3 and 8 fed to the analog circuit 1.

[0204] In subsequent step b), the detected current consumption value is compared with a set value (504), which may be specific to the set test conditions, wherein the comparison is preferably performed by the measuring device.

[0205] In subsequent step c), the analog circuit 1 is switched to another test state (508) by setting and adopting another test state in the test states, wherein the other test state is different from the previously adopted test state, and wherein, in particular, the switch 508 and setting are performed by a measuring device, and the method continues to perform step a) until all test states or a predetermined subset of test states have been adopted.

[0206] Therefore, a check (509) is performed to determine whether all test states or all specified test states to be used have been used. If all test states to be used have been used, the method terminates, and analog circuit 1 is used as intended (507) (if necessary). If not all test states to be used have been used, the method continues to step a) and detects the current consumption of analog circuit 1 (503).

[0207] Naturally, the use of analog circuit 1 (507) is contingent upon the premise that no defects in the sense of the present invention are found or have not yet been found during any prior and / or subsequent testing and / or during operation of the analog circuit.

[0208] In step d) after comparing the current consumption value with a preset value (504), if the amount of the current consumption value is greater than the set value, a defect is inferred (505), wherein preferably, the measuring device performs the inference, and then preferably, in the case of inferring such a defect (506), the analog circuit 1 that may have a defect is discarded.

[0209] The inference 506 regarding the existence of a defect can be interchanged with the transition 508 from analog circuit 1 to another test state in the test state.

[0210] The check 509, which checks whether all test states or all test states designated for use have been used, can be interchanged with the transfer 508 from analog circuit 1 to another test state among the test states.

[0211] In this respect, the step numbers from a) to d) in the specification and claims do not imply any temporal order.

[0212] The present invention also proposes a method for performing IDDQ testing on analog circuit 1. Figure 6 The method is illustrated in a simplified schematic diagram. Assume analog circuit 1 is, for example, connected to... Figure 2 The analog circuit 1 corresponding to the embodiment shown.

[0213] The method presented here involves multiple steps.

[0214] If no measuring device is available, the method begins at step 600, which provides the measuring device.

[0215] In subsequent steps, the analog circuit 1 is preferably powered by a measuring device (601).

[0216] In a subsequent step, analog circuit 1 is switched to a first test state (602), wherein the measuring device preferably performs and controls the switch via test logic 38 (e.g., via a JTAG test bus interface).

[0217] In subsequent steps, the current consumption (603) of the analog circuit 1 under the first test state is detected by a measuring device, and the current consumption value is determined. The measuring device preferably detects the current value of one of the power supply voltage lines 3 and 8 fed to the analog circuit 1.

[0218] In a subsequent step, the determined current consumption value is compared with a set value (604), wherein the comparison is preferably performed by the measuring device.

[0219] In subsequent steps, if the current consumption value is greater than the set value, a defect is deduced (605), wherein the measuring device preferably performs the deduction, and then preferably, in the event of such a defect, the analog circuit 1 that may be defective is discarded (606).

[0220] If the measuring device does not infer a defect in analog circuit 1 in the previous step 605, analog circuit 1 can be used as intended with a higher probability if it is not discarded for other reasons in further, subsequent or previous tests (607).

[0221] To address the aforementioned problems, this invention further proposes a method for stress testing of analog circuit 1. Figure 7 The method is illustrated schematically in a simplified manner. Assume analog circuit 1 is, for example, connected to... Figure 2 The analog circuit corresponding to the embodiment shown.

[0222] The method presented here involves multiple steps.

[0223] If no measuring device is available, the method begins at step 700, which provides the measuring device.

[0224] In subsequent steps, power is preferably supplied to analog circuit 1 via a measuring device (701).

[0225] In a subsequent step, analog circuit 1 is switched to a first test state (702), wherein the measuring device preferably performs this switch via test logic 38 (e.g., via a JTAG test bus interface).

[0226] In a subsequent step, the power supply voltage is increased by a predetermined stress voltage value (708) over a predetermined time period, wherein the measuring device preferably performs this increase 708;

[0227] The increase in power supply voltage is canceled 708 (709), wherein such cancellation (709) is preferably performed by a measuring device;

[0228] In subsequent steps, the current consumption (703) of the analog circuit 1 under the first test state is detected by a measuring device, and the current consumption value is determined. The measuring device preferably detects the current value of one of the power supply voltage lines 3 and 8 fed to the analog circuit 1.

[0229] In a subsequent step, the detected current consumption value is compared with a predetermined value (704), wherein the comparison is preferably performed by the measuring device.

[0230] In subsequent steps, if the current consumption value is greater than the set value, a defect is deduced (705), wherein the measuring device preferably performs the deduction, and then preferably, in the presence of such a defect, the analog circuit 1 that may be defective is discarded (706).

[0231] If no defect was deduced in the previous step 705, the analog circuit 1 can be used as intended with a higher probability if it is not discarded for other reasons in further, subsequent or previous tests (707).

[0232] advantage

[0233] Meaningful IDDQ testing of the exemplary analog circuit 1 can be achieved by setting specific test states using the proposed switches and tri-state gates. This increases the testability of the exemplary analog circuit 1, thereby improving delivery quality.

[0234] Compared to the technical concept of US 2005 / 0024075 A1, the technical concept proposed in this invention solves the IDDQ testability problem of analog circuits. Compared to the example in US 2005 / 0024075 A1, the technical concept proposed in this invention discloses a fully testable IDDQ solution. "Fully" means that IDDQ testing is possible for all analog transistors in the example of this invention.

[0235] Compared to the technical concept of US 2005 / 0024075 A1, the technical concept of this invention has no static current path between the positive and negative power supply voltages under test conditions.

[0236] Compared to the concept of US 2005 / 0024075 A1, this invention proposes reconfiguring the analog circuit under test into a digital circuit. Compared to the concept of US 2005 / 0024075 A1, the concept of this invention enables fully automated generation of IDDQ test vectors. Therefore, by using the concept of this invention, certification texts conforming to ISO 26262 requirements can be generated.

[0237] Compared to the technical concept of US 2005 / 0024075 A1, this invention proposes the disconnection of the feedback branch.

[0238] Compared to the technical concept of US 2005 / 0024075 A1, this invention proposes a complete disconnection of the control node. In this invention... Figure 2 In the example shown, this is specifically achieved via exemplary switches S6, S7, S8, S1, S2, S3, and S4. In contrast, the technical concept of US 2005 / 0024075 A1 does not provide such an additional transmission gate for testing purposes.

[0239] Compared to US 2005 / 0024075 A1, this invention discloses a circuit that can be tested in IDDQ test state, and further discloses the principle that it can be transferred to other analog circuits.

[0240] List of reference numerals

[0241] 1. Exemplary analog circuit;

[0242] 2. Voltage source;

[0243] 3. Power supply voltage line;

[0244] 4. Current source;

[0245] 5. Reference current;

[0246] 6. First node;

[0247] 7. First transistor;

[0248] 8. Reference potential line;

[0249] 9. Second transistor;

[0250] 10. The third transistor;

[0251] 11. Fourth transistor;

[0252] 12. The fifth transistor;

[0253] 13. The sixth transistor;

[0254] 14. Second node;

[0255] 15. The seventh transistor;

[0256] 16. The eighth transistor;

[0257] 17. Inverter;

[0258] 18. Digital transmission clock;

[0259] 19. Inverting digital transmission clock;

[0260] 20. Ninth transistor;

[0261] 21. The tenth transistor;

[0262] 22. The eleventh transistor;

[0263] 23 The twelfth transistor;

[0264] 24. Analog outputs and input nodes for subsequent circuits;

[0265] 25. Intermediate nodes;

[0266] 26 The output terminal of the source follower composed of the seventh transistor 15 and the eighth transistor 16;

[0267] 27. Reference voltage between the first node 6 and the reference potential line 8;

[0268] 28. Control electrode of the third transistor 10;

[0269] 29. Control electrode of the fourth transistor 11;

[0270] 30. The thirteenth transistor;

[0271] 31. The third node;

[0272] 32. Fourth node;

[0273] 33. Control electrode 33 of the first transistor 7;

[0274] 34. Control electrode of the second transistor 9;

[0275] 36. Control electrode of the fifth transistor 12;

[0276] 37. Control electrode of the eighth transistor 16;

[0277] 38. Test logic;

[0278] 39. Control electrode of the seventh transistor 15;

[0279] 40 Other control signals of the overall circuit to which exemplary analog circuit 1 belongs;

[0280] 41. Variant digital transmission clock;

[0281] 42. Modified inverting digital transmission clock;

[0282] 43 The control electrode of the thirteenth transistor 30;

[0283] 400 provides measuring devices;

[0284] 401 supplies power to analog circuit 1;

[0285] 402 Switches analog circuit 1 to the first test state;

[0286] 403 Specifically, the current consumption of analog circuit 1 under test conditions is detected by a measuring device, and the current consumption value is determined;

[0287] 404 compares the current consumption value with the set value.

[0288] 405. A defect was deduced.

[0289] 406 Defective Analog Circuit 1 (Discarded);

[0290] Method 407 terminates and analog circuit 1 is expected to be used if necessary;

[0291] 500 provides measuring devices;

[0292] 501 provides electrical power to analog circuit 1;

[0293] 502 By setting and adopting one of the test states, analog circuit 1 is switched to that test state;

[0294] 503 Specifically, the current consumption of analog circuit 1 under test conditions is detected by a measuring device, and the current consumption value is determined;

[0295] 504 compares the current consumption value with the set value.

[0296] 505 indicates that a defect exists;

[0297] 506 Defective Analog Circuit 1 (Discarded);

[0298] Method 507 terminates, and analog circuit 1 is expected to be used if necessary;

[0299] 508 By setting and adopting another test state in the test state, analog circuit 1 is switched to that other test state;

[0300] 509 Check that all test states or all specified test states have been used;

[0301] 600 provides measuring devices;

[0302] 601 provides electrical power to analog circuit 1;

[0303] 602 switches analog circuit 1 to the first test state;

[0304] 603 Specifically, the current consumption of analog circuit 1 under test conditions is detected by a measuring device, and the current consumption value is determined;

[0305] 604 compares the current consumption value with the set value.

[0306] 605. A defect was deduced.

[0307] 606 Defective Analog Circuit 1 (Discarded);

[0308] Method 607 terminates, and analog circuit 1 is expected to be used if necessary;

[0309] 700 provides measuring devices;

[0310] 701 supplies power to analog circuit 1;

[0311] 702 switches analog circuit 1 to the first test state;

[0312] 703 Specifically, the current consumption of analog circuit 1 under test conditions is detected by a measuring device, and the current consumption value is determined;

[0313] 704 Compare the sixth consumption value with the set value.

[0314] 705. The existence of the condition is deduced;

[0315] 706 Defective Analog Circuit 1 (Discarded);

[0316] Method 707 terminates, and analog circuit 1 is expected to be used if necessary;

[0317] 708 Increase the power supply voltage;

[0318] 709 Cancel the increase in power supply voltage, which can be done in whole or in part;

[0319] G1 First Tri-State Gate;

[0320] G2 Second Three-State Gate;

[0321] G3 Third Tri-State Gate;

[0322] G4 is the fourth three-state gate;

[0323] G5 is the fifth three-state gate;

[0324] G6 is the sixth three-state gate;

[0325] G7 Seventh Three-State Gate;

[0326] G8 is the eighth three-state gate;

[0327] G9 is the ninth third-state gate;

[0328] S1 First switch;

[0329] S2 Second Switch;

[0330] S3 Third Switch;

[0331] S4 Fourth Switch;

[0332] S5 Fifth Switch;

[0333] S6, the sixth switch;

[0334] S7 Seventh Switch;

[0335] S8, the eighth switch;

[0336] S9 Ninth Switch;

[0337] Idd is the power supply current entering analog circuit 1;

[0338] List of cited references

[0339] If a priority claim for this invention has been filed in a country that allows the combination of the technical concept of the claimed references with the technical concept of this invention as part of this disclosure, then the following documents, in combination with this invention, explicitly constitute part of this invention.

[0340] Patent documents

[0341] US 2005 / 0024075 A1

[0342] Non-patent literature

[0343] Non-patent document 1: https: / / de.wikipedia.org / wiki / Boundary_Scan_Test (Download date: February 11, 2022)

[0344] Non-Patent Literature 2: LY Ungar, H. Bleeker, JE McDermid, and H. Hulvershorn, “IEEE-1149.x standards: achievements vs. expectations,” Proceedings of IEEE Autotestcon 2001 (IEEE Systems Readiness Technology Conference) (No. 01CH37237), 2001, pp. 188-205, doi: 10.1109 / AUTEST.2001.948964

[0345] Non-Patent Document 3: "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks", IEEE Std 1149.6-2015 (revised from IEEE Std 1149.6-2003), pp. 1-230, March 18, 2016, DOI: 10.1109 / IEEESTD.2016.7436703

[0346] Non-Patent Document 4: "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture", IEEE Std 1149.7-2009, pp. 1-985, February 10, 2010, DOI: 10.1109 / IEEESTD.2010.5412866

[0347] Non-Patent Document 5: “IEEE Standard for Test Access Port and Boundary-Scan Architecture – Redline”, IEEE Std 1149.1-2013 (revised from IEEE Std 1149.1-2001), Redline version, pp. 1-899, May 13, 2013.

[0348] Non-Patent Document 6: "IEEE Standard for Test Access Port and Boundary-Scan Architecture", IEEE Std 1149.1-2013 (revised from IEEE Std 1149.1-2001), pp. 1-444, May 13, 2013, DOI: 10.1109 / IEEESTD.2013.6515989

[0349] Non-Patent Document 7: "IEEE Standard for a Mixed-Signal Test Bus", IEEE Std 1149.4-2010 (revised from IEEE Std 1149.4-1999), pp. 1-116, March 18, 2011, DOI: 10.1109 / IEEESTD.2011.5738198

[0350] Non-Patent Document 8: "IEEE Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and / or Active Components", IEEE Std 1149.8.1-2012, pp. 1-95, August 9, 2012, DOI: 10.1109 / IEEESTD.2012.6259815

[0351] Non-Patent Document 9: "IEEE Standard for High-Speed ​​Test Access Port and On-Chip Distribution Architecture", IEEEStd 1149.10-2017, pp. 1-96, July 28, 2017, DOI: 10.1109 / IEEESTD.2017.7995164

[0352] Non-Patent Document 10: "IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks - Redlin", IEEE Std 1149.6-2015 (revised from IEEE Std 1149.6-2003), Redlin version, pp. 1-441, March 18, 2016

[0353] Non-Patent Document 11: "IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device", IEEE Std 1687-2014, pp. 1-283, December 5, 2014, DOI: 10.1109 / IEEESTD.2014.6974961

[0354] Non-Patent Document 12: “IEEE Draft Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture”, IEEE P1149.7 / D6, July 2020, pp. 1-1043, November 3, 2020

[0355] Non-Patent Document 13: GOD Acevedo and J. Ramírez-Angulo, “VDDQ: a built-in self-test scheme for analog on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard,” included in the Proceedings of the 4th IEEE International Conference on Devices, Circuits and Systems in Caracas (No. 02TH8611), 2002, pp. I026-I026, DOI: 10.1109 / ICCDCS.2002.1004083

[0356] Non-Patent Document 14: "IEEE Draft Standard for a Mixed-Signal Test Bus", IEEE P1149.4 / D2, September 2010, pp. 1-113, October 7, 2010

[0357] Non-Patent Document 15: "IEEE Approved Draft Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits", IEEE P1838_D3.00, September 2019, pp. 1-63, November 7, 2019

[0358] Non-Patent Document 16: Dietmar Ehrhardt, “Integrated Analog Circuit Technology: Technology, Design, Simulation, and Layout,” Vieweg Verlagsgesellschaft, June 28, 2000; 2000 edition (June 28, 2000), ISBN-10: 3528038608, ISBN-13: 978-352803860

[0359] Non-Patent Document 17: Phillip E. Allen (author), Douglas R. Holberg, "CMOS Analog Circuit Design", Oxford University Press; 3rd edition, International Edition (July 13, 2012), ISBN-10: 0199937427, ISBN-13: 978-0199937424

[0360] Non-Patent Document 18: Saggio, Giovanni, and Tor Vergata, “Principles of Analog Electronics”, ASIN: 1466582014, Taylor & Francis Inc., January 29, 2014, ISBN-10: 9781466582019, ISBN-13: 978-1466582019

[0361] Non-Patent Document 19: Ulrich Tietze and Christoph Schenk, "Halbleiter-Schaltungstechnik (Semiconductor Circuit Technology)" Hardcover Edition – July 5, 2019, Springer Vieweg, 16th Edition (Revised and Updated 2019), ISBN-10: 3662485532, ISBN-13: 978-3662485538

[0362] Non-Patent Document 20: Ian A. Grout, “Integrated Circuit Test Engineering: Modern Techniques”, Springer London, 2006 edition, June 2, 2010, ISBN-10: 1846280230, ISBN-13: 978-1846280238

[0363] Non-patent literature 21: Wikipedia https: / / en.wikipedia.org / wiki / Iddq_testing

[0364] Non-patent document 22: ISO 26262.

Claims

1. An analog circuit based on MOS, BiCMOS or CMOS (1), in, The analog circuit (1) is designed to perform a predetermined circuit function under normal operating conditions, and The analog circuit (1) has one or more input signals and / or one or more output signals, and The analog circuit (1) has at least one analog signal within the analog circuit (1), and The analog circuit (1) is connected to the test logic (38), and The test logic (38) is designed to set the analog circuit (1) to the normal state and at least the first test state, and The analog circuit (1) includes a first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), and The first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is designed to perform the function of the analog circuit (1) according to its predetermined circuit purpose under the normal state of the analog circuit (1), and Each of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) has a control electrode, and The first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) are designed to also function as switches via their respective control electrodes, and Among them, the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) have an on state and a closed state respectively in their respective operation as switches, and as their respective switch states, and Wherein, the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is fully connected in the open state, and Wherein, the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) is completely turned off in the off state, and The analog circuit (1) includes a second component (S1 to S9; G1 to G9), and Wherein, the test logic (38) is designed to use the second component (S1 to S9; G1 to G9) to set the switching state of at least one of the first components (7, 9, 12, 16) among the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in the first test state of the analog circuit (1), and Wherein, at least one of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) has its control electrodes (33, 34, 36, 37) not directly connected to the input signal or not directly connected to the output signal, and Wherein, the test logic (38) is designed to, in the first test state, disconnect the control electrodes (33, 34, 36, 37) of at least one of the first components (7, 9, 12, 16) from the rest of the analog circuit (1) by at least one switch (S1, S2, S3, S4), and Wherein, the test logic (38) is designed to, under the normal state, at least via the switches (S1, S2, S3, S4), connect the control electrodes (33, 34, 36, 37) of at least one of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) to the nodes of the rest of the analog circuit (1), and The test logic (38) is designed to, under the first test state, connect the control electrodes (33, 34, 36, 37, 39) of at least one of the first components (7, 9, 12, 16) via the first device (G1, G2, G5, G6) to switch to the on state or disconnect to switch to the off state. The test logic (38) is designed to control the first device (G1, G2, G5, G6) in the normal state such that the first device (G1, G2, G5, G6) does not affect the control electrode (33, 34, 36, 37, 39) of at least one of the first components (7, 9, 12, 16) in the normal state of the analog circuit (1).

2. The analog circuit (1) according to claim 1, characterized in that, The analog circuit (1) includes N-channel transistors (7, 9, 16, 30, 10, 11, 20, 22) and P-channel transistors (12, 13, 15, 21, 23), and The second component (S1 to S9; G1 to G9) is designed to enable the test logic (38) to set the switching state of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), so that In the first test state of the analog circuit (1), all N-channel transistors (7, 9, 16, 30, 10, 11, 20, 22) of the analog circuit (1) are turned off, and all P-channel transistors (12, 13, 15, 21, 23) of the analog circuit (1) are turned on, or In the first test state of the analog circuit (1), all N-channel transistors (7, 9, 16, 30, 10, 11, 20, 22) of the analog circuit (1) are turned on, and all P-channel transistors (12, 13, 15, 21, 23) of the analog circuit (1) are turned off.

3. The analog circuit (1) according to claim 1, characterized in that... , The analog circuit (1) has a positive power supply voltage line (3), and The analog circuit (1) has a negative power supply voltage line (8), and The analog circuit (1) has multiple potential current paths from the positive power supply voltage line (3) through at least one of the first components (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) and / or the second components (S1 to S9; G1 to G9) to the negative power supply voltage line (8). The second component (S1 to S9; G1 to G9) is designed to enable the test logic (38) to set the switching state of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30), thereby enabling the test logic (38) to set the switching state of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30). In each of the potential current paths, at least one first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) and / or at least one second component (S1 to S9; G1 to G9) is cut off.

4. The analog circuit (1) according to claim 3, characterized in that, In at least one of the potential current paths, referred to as the target current path, under the first test state, exactly one first component or exactly one second component is turned off, and The exact first cutoff component or the exact second cutoff component in the target current path corresponds to the IDDQ component, and In the first test state, no components in the target current path other than the IDDQ component are cut off.

5. A method for performing IDDQ testing on the analog circuit (1) according to claim 4, comprising the following steps: Provide measuring devices; Power is supplied to the analog circuit (1); The analog circuit (1) is switched to the first test state; The current consumption of the analog circuit (1) under the first test state is detected by the measuring device, and the current consumption value is determined. Compare the current consumption value with the set value; If the current consumption value is higher than the set value, it is inferred that there is a defect.

6. A method for performing IDDQ testing on the analog circuit (1) according to claim 4, in, In addition to the first test state, the analog circuit (1) also has one or more other test states. The other test states and the first test state are collectively referred to as test states. The test states are different from each other because the IDDQ component of one test state is different from the IDDQ component of another test state in the same test state. The method includes the following steps: Provide measuring devices; Power is supplied to the analog circuit (1); Using the measuring device, the analog circuit (1) is switched to the test state by setting and adopting one of the test states; Step a): Using the measuring device, detect the current consumption of the analog circuit (1) under the set test state and determine the current consumption value; Step b): Compare the determined current consumption value with a set value that is specific to the set test state; Step c): The analog circuit (1) is switched to another test state by setting and adopting another test state in the test state, wherein the other test state set is different from the previously adopted test state in the test state, and wherein the switch is performed by the measuring device, and step a) continues until all test states or a predetermined subset of test states in the test state are adopted; Step d): If the determined current consumption value is higher than the set value, a defect is inferred. Step d) can also be performed between steps b) and c), and the measuring device can also perform the inference of a defect.

7. A method for performing an IDDQ test on an analog circuit (1) according to claim 2 or 4, comprising the following steps: Provide measuring devices; Power is supplied to the analog circuit (1), wherein the measuring device can also be powered. The analog circuit (1) is switched to the first test state, wherein the measuring device is also capable of controlling the switch; The current consumption of the analog circuit (1) in the first test state is detected and the current consumption value is determined, wherein the measuring device is also capable of performing the detection; The detected current consumption value is compared with a set value, wherein the measuring device is also capable of performing the comparison; If the detected current consumption value is higher than the set value, a defect is inferred, wherein the measuring device is also capable of performing the inference of a defect.

8. A method for performing stress testing on an analog circuit (1) according to claim 2 or 4, comprising the following steps: Provide measuring devices; Power is supplied to the analog circuit (1); The analog circuit (1) is switched to the first test state; Increase the power supply voltage to a predetermined stress voltage value and maintain it for a predetermined period of time; Cancel the increase in the power supply voltage; The current consumption of the analog circuit (1) under the first test state is detected by the measuring device, and the current consumption value is determined. Compare the current consumption value with the set value; If the current consumption value is higher than the set value, an error is deduced.

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