Pixel drive circuit and driving method therefor, and array substrate and display panel

Abstract

Disclosed is a pixel drive circuit. The pixel drive circuit comprises a drive sub-circuit, a light-emission control sub-circuit, a writing sub-circuit, a compensation sub-circuit and a storage sub-circuit, wherein the drive sub-circuit is coupled to a first node, a second node and a third node; the light-emission control sub-circuit comprises a first branch, and the first branch is coupled to a first power supply signal line, a first enable signal line and the second node; the compensation sub-circuit is coupled to a first scanning signal line, a second scanning signal line, the first node, the third node, a fourth node and a second power supply signal line; the writing sub-circuit is coupled to a third scanning signal line, a data writing signal line and the fourth node; and the storage sub-circuit is coupled to the first node and the fourth node.

Description

[0001] This application claims priority to Chinese Patent Application No. 202310945825.X, filed on July 28, 2023, which is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit and a driving method therefor, an array substrate and a display panel.BACKGROUND

[0003] At present, organic light-emitting diode (OLED) display apparatuses have been widely used due to their characteristics such as self-luminescence, quick response, wide viewing angle, being capable of being manufactured on flexible substrates. The OLED display apparatus includes a plurality of sub-pixels, each sub-pixel includes a pixel driving circuit and a light-emitting device, and the pixel driving circuit is used to drive the light-emitting device to emit light, so that display is achieved.SUMMARY

[0004] In an aspect, a pixel driving circuit is provided. The pixel driving circuit includes: a driving sub-circuit, a light-emitting control sub-circuit, a writing sub-circuit, a compensation sub-circuit and a storage sub-circuit. The driving sub-circuit includes a control terminal, a first terminal and a second terminal; the driving sub-circuit is coupled to a first node, a second node and a third node; the driving sub-circuit is configured to transmit a voltage of the second node to the third node under control of a voltage of the first node. The light-emitting control sub-circuit includes a first branch, the first branch is coupled to a first power signal line, a first enable signal line, and the second node; the first branch is configured to, in a compensation phase, cooperate with the driving sub-circuit to transmit a first power signal received from the first power signal line to the third node under control of a first enable signal from the first enable signal line. The compensation sub-circuit is coupled to a first scanning signal line, a second scanning signal line, the first node, the third node, a fourth node and a second power signal line; the compensation sub-circuit is configured to: in the compensation phase, transmit a voltage of the third node to the first node under control of a first scanning signal received from the first scanning signal line, and transmit a second power signal received from the second power signal line to the fourth node under control of a second scanning signal received from the second scanning signal line. The writing sub-circuit is coupled to a third scanning signal line, a data writing signal line and the fourth node; the writing sub-circuit is configured to, in a writing phase, transmit a data writing signal received from the data writing signal line to the fourth node under control of a third scanning signal received from the third scanning signal line. The storage sub-circuit is coupled to the first node and the fourth node; the storage sub-circuit is configured to, in the writing phase, couple a voltage of the fourth node to the first node.

[0005] In some embodiments, the driving sub-circuit includes a driving transistor; a control electrode of the driving transistor is coupled to the first node, a first electrode of the driving transistor is coupled to the second node, and a second electrode of the driving transistor is coupled to the third node.

[0006] In some embodiments, the compensation sub-circuit includes a second transistor and a ninth transistor. A control electrode of the second transistor is coupled to the first scanning signal line, a first electrode of the second transistor is coupled to the third node, and a second electrode of the second transistor is coupled to the first node. A control electrode of the ninth transistor is coupled to the third scanning signal line, a first electrode of the ninth transistor is coupled to the second power signal line, and a second electrode of the ninth transistor is coupled to the fourth node.

[0007] In some embodiments, the writing sub-circuit includes a fourth transistor, a control electrode of the fourth transistor is coupled to the third scanning signal line, a first electrode of the fourth transistor is coupled to the data writing signal line, and a second electrode of the fourth transistor is coupled to the fourth node.

[0008] In some embodiments, the storage sub-circuit includes a storage capacitor, a first plate of the storage capacitor is coupled to the fourth node, and a second plate of the storage capacitor is coupled to the first node.

[0009] In some embodiments, the light-emitting control sub-circuit further includes a second branch. The second branch is coupled to the third node, a second enable signal line and a light-emitting device; the light-emitting control sub-circuit is configured to: in a light-emitting phase, cooperate with the driving sub-circuit to transmit the first power signal received from the first power signal line to the light-emitting device under the control of the first enable signal from the first enable signal line and control of a second enable signal from the second enable signal line.

[0010] In some embodiments, the first branch includes a fifth transistor; a control electrode of the fifth transistor is coupled to the first enable signal line, a first electrode of the fifth transistor is coupled to the first power signal line, and a second electrode of the fifth transistor is coupled to the second node. The second branch includes a sixth transistor; a control electrode of the sixth transistor is coupled to the second enable signal line, a first electrode of the sixth transistor is coupled to the third node, and a second electrode of the sixth transistor is coupled to the light-emitting device.

[0011] In some embodiments, the pixel driving circuit further includes a first reset sub-circuit. The first reset sub-circuit is coupled to the first node, a first reset signal line and a first initialization signal line; the first reset sub-circuit is configured to transmit, under control of a first reset signal received from the first reset signal line, a first initialization signal received from the first initialization signal line to the first node to reset the first node.

[0012] In some embodiments, the first reset sub-circuit includes a first transistor; a control electrode of the first transistor is coupled to the first reset signal line, a first electrode of the first transistor is coupled to the first initialization signal line, and a second electrode of the first transistor is coupled to the first node.

[0013] In some embodiments, the pixel driving circuit further includes a second reset sub-circuit. The second reset sub-circuit is coupled to a light-emitting device, a second reset signal line, and a second initialization signal line; the second reset sub-circuit is configured to transmit, under control of a second reset signal received from the second reset signal line, a second initialization signal received from the second initialization signal line to the light-emitting device to reset the light-emitting device.

[0014] In some embodiments, the second reset sub-circuit includes a seventh transistor; a control electrode of the seventh transistor is coupled to the second reset signal line, a first electrode of the seventh transistor is coupled to the second initialization signal line, and a second electrode of an eighth transistor is coupled to the light-emitting device.

[0015] In some embodiments, the pixel driving circuit further includes a third reset sub-circuit. The third reset sub-circuit is coupled to the second node, a third reset signal line and a first reference voltage signal line; the third reset sub-circuit is configured to transmit, under control of a third reset signal received from the third reset signal line, a first reference voltage signal received from the first reference voltage signal line to the second node to reset the second node.

[0016] In some embodiments, the third reset sub-circuit includes an eighth transistor; a control electrode of the eighth transistor is coupled to the third reset signal line, a first electrode of the eighth transistor is coupled to the first reference voltage signal line, and a second electrode of the eighth transistor is coupled to the second node.

[0017] In some embodiments, a voltage of the first power signal is equal to a voltage of the second power signal.

[0018] In some embodiments, the first power signal line is also used as the second power signal line.

[0019] In some embodiments, in a case where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor, at least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is a dual-gate transistor.

[0020] In some embodiments, in a case where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor, at least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is an N-type transistor.

[0021] In another aspect, a driving method for a pixel driving circuit is provided. The pixel driving circuit includes a driving sub-circuit, a light-emitting control sub-circuit, a writing sub-circuit, a compensation sub-circuit and a storage sub-circuit. The driving sub-circuit is coupled to a first node, a second node and a third node. The light-emitting control sub-circuit includes a first branch, the first branch is coupled to a first power signal line, a first enable signal line, and the second node. The compensation sub-circuit is coupled to a first scanning signal line, a second scanning signal line, the first node, the third node, a fourth node, the first power signal line and a second power signal line; a voltage of the first power signal is equal to a voltage of the second power signal. The writing sub-circuit is coupled to a third scanning signal line, a data writing signal line and the fourth node. The storage sub-circuit is coupled to the first node and the fourth node.

[0022] The driving method includes: a compensation phase and a writing phase. In the compensation phase, the first branch cooperates with the driving sub-circuit to transmit a first power signal received from the first power signal line to the third node under control of a first enable signal from the first enable signal line; the compensation sub-circuit transmits a voltage of the third node to the first node under control of a first scanning signal received from the first scanning signal line, and transmits a second power signal received from the second power signal line to the fourth node under control of a second scanning signal received from the second scanning signal line; the storage sub-circuit receives a voltage of the first node and a voltage of the fourth node. In the writing phase, the writing sub-circuit transmits a data writing signal received from the data writing signal line to the fourth node under control of a third scanning signal received from the third scanning signal line; and the storage sub-circuit couples the voltage of the fourth node to the first node.

[0023] In some embodiments, the pixel driving circuit further includes a third reset sub-circuit, and the third reset sub-circuit is coupled to the second node, a third reset signal line, and a first reference voltage signal line. The driving method further includes a first reset phase. In the first reset phase, the third reset sub-circuit transmits, under control of a third reset signal received from the third reset signal line, a first reference voltage signal received from the first reference voltage signal line to the second node to reset the second node.

[0024] In some embodiments, the pixel driving circuit further includes a first reset sub-circuit, and the first reset sub-circuit is coupled to the first node, a first reset signal line and a first initialization signal line. The driving method further includes a first initialization phase. In the first initialization phase, the first reset sub-circuit transmits, under control of a first reset signal received from the first reset signal line, a first initialization signal received from the first initialization signal line to the first node to initialize the first node.

[0025] In some embodiments, the driving method further includes a second initialization phase. In the second initialization phase, the first reset sub-circuit transmits the first initialization signal received from the first initialization signal line to the first node under the control of the first reset signal received from the first reset signal line; the compensation sub-circuit transmits the voltage of the first node to the third node under control of the first scanning signal received from the first scanning signal line; the driving sub-circuit transmits a voltage of the second node to the third node under control of the voltage of the first node, so as to initialize the first node, the second node, and the third node.

[0026] In yet another aspect, an array substrate is provided. The display substrate includes a substrate and a plurality of pixel driving circuits each as described in any of the above embodiments. The plurality of pixel driving circuits are located on the substrate.

[0027] In some embodiments, the plurality of pixel driving circuits are arranged in multiple rows and columns. The array substrate further includes: a plurality of first scanning signal lines, a plurality of second scanning signal lines and a plurality of first reset signal lines. The plurality of first scanning signal lines are located on a side of the substrate, the plurality of first scanning signal lines all extending in a first direction and are arranged in a second direction. The second direction intersects the first direction. The plurality of second scanning signal lines are located on the side of the substrate, the plurality of second scanning signal lines all extending in the first direction and are arranged in the second direction. The plurality of first reset lines are located on the side of the substrate, the plurality of first reset lines all extending in the first direction and are arranged in the second direction. A second scanning signal line coupled to an n-th row of pixel driving circuits, a first scanning signal line coupled to an (n+3)-th row of pixel driving circuits, and a first reset signal line coupled to an (n+6)-th row of pixel driving circuits respond to control of a same control signal, where n is a positive integer.

[0028] In still another aspect, a display panel is provided. The display panel includes a light-emitting device layer and the array substrate as described in any of the above embodiments. The light-emitting device layer includes a plurality of light-emitting devices. A pixel driving circuit is coupled to a light-emitting device.BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to describe technical solutions in the present disclosure more clearly, the accompanying drawings to be used in some embodiments of the present disclosure will be introduced briefly. Obviously, the accompanying drawings to be described below are merely drawings of some embodiments of the present disclosure, and a person of ordinary skill in the art can obtain other drawings according to those drawings. In addition, the accompanying drawings in the following description may be regarded as schematic diagrams, but are not limitations on actual sizes of products, actual processes of methods and actual timings of signals involved in the embodiments of the present disclosure. FIG. 1 is a structural diagram of a display apparatus, in accordance with some embodiments; FIG. 2 is a structural diagram of a display panel, in accordance with some embodiments; FIG. 3 is a sectional view of a display panel, in accordance with some embodiments; FIG. 4 is a structural diagram of an array substrate, in accordance with some embodiments; FIG. 5 is an equivalent circuit diagram of a pixel driving circuit, in accordance with some implementations; FIG. 6 is an equivalent circuit diagram of a pixel driving circuit, in accordance with some embodiments; FIG. 7 is an equivalent circuit diagram of another pixel driving circuit, in accordance with some embodiments; FIG. 8 is an equivalent circuit diagram of yet another pixel driving circuit, in accordance with some embodiments; FIG. 9 is an equivalent circuit diagram of yet another pixel driving circuit, in accordance with some embodiments; FIG. 10 is an equivalent circuit diagram of yet another pixel driving circuit, in accordance with some embodiments; FIG. 11 is a timing diagram of a pixel driving circuit, in accordance with some embodiments; FIG. 12 is a timing diagram of another pixel driving circuit, in accordance with some embodiments; FIG. 13 is a structural diagram of another array substrate, in accordance with some embodiments; FIG. 14 is a timing diagram of yet another pixel driving unit, in accordance with some embodiments; and FIG. 15 is a timing diagram of yet another pixel driving unit, in accordance with some embodiments. DETAILED DESCRIPTION

[0030] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings, and obviously, the described embodiments are merely some but not all embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on embodiments provided in the present disclosure shall be included in the protection scope of the present disclosure.

[0031] Unless the context requires otherwise, throughout the specification and the claims, the term "comprise" and other forms thereof such as the third-person singular form "comprises" and the present participle form "comprising" are construed as an open and inclusive meaning, i.e., "including, but not limited to". In the description of the specification, the terms such as "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples" are intended to indicate that specific features, structures, materials, or characteristics related to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s). In addition, the specific features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0032] Hereinafter, terms such as "first" and "second" are used for descriptive purposes only, and are not to be construed as indicating or implying the relative importance or implicitly indicating the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the terms "a plurality of", "the plurality of" and "multiple" each mean two or more unless otherwise specified.

[0033] Some embodiments may be described using the terms "coupled", "connected" and their derivatives. The term "connected" should be understood in a broad sense; for example, "connected" may be a fixed connection, a detachable connection, or an integrated connection; "connected" may be directly connected or indirectly connected through an intermediate medium. The term "coupled", for example, indicates that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also indicate that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the context herein.

[0034] The phrase "at least one of A, B and C" has the same meaning as the phrase "at least one of A, B or C", both including following combinations of A, B and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B and C.

[0035] The phrase "A and / or B" includes following three combinations: only A, only B, and a combination of A and B.

[0036] As used herein, depending on the context, the term "if" is, optionally, construed as "when" or "in a case where" or "in response to determining that" or "in response to detecting". Similarly, depending on the context, the phrase "if it is determined that" or "if [a stated condition or event] is detected" is optionally construed as "in a case where it is determined that" or "in response to determining that" or "in a case where [the stated condition or event] is detected" or "in response to detecting [the stated condition or event].

[0037] The use of the phrase "applicable to" or "configured to" herein means an open and inclusive expression, which does not exclude devices that are applicable to or configured to perform additional tasks or steps.

[0038] In addition, the use of the phrase "based on" is meant to be open and inclusive, since a process, step, calculation or other action that is "based on" one or more of the stated conditions or values may, in practice, be based on or according to additional conditions or values exceeding those stated.

[0039] The term such as "about", "substantially" or "approximately" as used herein includes a stated value and an average value within an acceptable range of deviation of a particular value, and the acceptable range of deviation is determined, for example, by a person of ordinary skill in the art, considering measurement in question and errors (i.e., limitations of a measurement system) associated with measurement of a particular quantity.

[0040] The term "perpendicular" as used herein includes a stated condition and a condition similar to the stated condition, the range of the similar condition is within an acceptable range of deviation, and the acceptable range of deviation is determined by, for example, a person of ordinary skill in the art, considering measurement in question and errors (i.e., limitations of a measurement system) associated with measurement of a particular quantity. For example, the term "perpendicular" includes absolute perpendicularity and approximate perpendicularity, and an acceptable range of deviation of the approximate perpendicularity may be, for example, a deviation within 5°.

[0041] It will be understood that, in a case where a layer or element is referred to be on another layer or substrate, it may be that the layer or element is directly on the another layer or substrate, or it may be that intervening layer(s) exist between the layer or element and the another layer or substrate.

[0042] Exemplary embodiments are described herein with reference to sectional views and / or plan views as idealized exemplary drawings. In the drawings, thicknesses of layers and sizes of regions are enlarged for clarity. Variations in shapes relative to the accompanying drawings due to, for example, manufacturing technologies and / or tolerances may be envisaged. Therefore, the exemplary embodiments should not be construed to be limited to the shapes of regions shown herein, but to include deviations in the shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle generally has a feature of being curved. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to show actual shapes of regions in the apparatuses, and are not intended to limit the scope of the exemplary embodiments.

[0043] In the circuit structures provided in the embodiments of the present disclosure, nodes, such as a first node and a second node, do not represent actual existing components, but represent junctions of related electrical connections in the circuit diagram. That is, these nodes are nodes equivalent to the junctions of the related electrical connections in the circuit diagram.

[0044] In the circuit structures provided in the embodiments of the present disclosure, a first electrode of each transistor used is one of a source and a drain, and a second electrode of each transistor is the other one of the source and the drain. Since the source and the drain of the transistor may be symmetrical in structure, there may be no difference in structure between the source and the drain of the transistor. That is, there may be no difference in structure between the first electrode and the second electrode of the transistor in the embodiments of the present disclosure.

[0045] FIG. 1 is a structural diagram of a display apparatus, in accordance with some embodiments. As shown in FIG. 1, some embodiments of the present disclosure provide a display apparatus 300, and the display apparatus 300 includes a display panel 200.

[0046] For example, the display apparatus 300 further includes a frame, and other electronic components.

[0047] For example, the display apparatus 300 may be an electroluminescent display apparatus or a photoluminescent display apparatus. In a case where the display apparatus is the electroluminescent display apparatus, the electroluminescent display apparatus may be an organic light-emitting diode (OLED) display apparatus or a quantum dot light-emitting diode (QLED) display apparatus. In a case where the display apparatus is the photoluminescent display apparatus, the photoluminescent display apparatus may be a quantum dot photoluminescent display apparatus.

[0048] For example, the display apparatus 300 may be any display apparatus that can display images whether in motion (e.g., videos) or stationary (e.g., static images), and whether textual or graphical. More specifically, it is expected that the display apparatus provided in the embodiments may be implemented in or associated with various electronic devices, which include (but is not limit to), for example, a mobile phone, a wireless device, a personal digital assistant (PDA), a hand-held or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a TV monitor, a flat panel display, a computer monitor, a car display (e.g., an odometer display), a navigator, a cockpit controller and / or display, a display in camera view (e.g., a display for a rear camera in a vehicle), an electronic photo, an electronic billboard or indicator, a projector, a building structure, a packaging and aesthetic structure (e.g., a display for an image of a piece of jewelry).

[0049] FIG. 2 is a structural diagram of a display panel, in accordance with some embodiments; FIG. 3 is a sectional view of a display panel, in accordance with some embodiments.

[0050] Some embodiments of the present disclosure provide a display panel 200. Referring to FIGS. 2 and 3, the display panel 200 includes a display area (also referred as an active area) AA. The display area AA includes a plurality of sub-pixel regions P, and the plurality of sub-pixel regions P are arranged in an array. The sub-pixel P is the smallest unit of the display panel 200 for displaying an image.

[0051] In some examples, a pixel driving circuit Q and a light-emitting device O electrically connected to the pixel driving circuit Q are provided in a sub-pixel region P therein. The pixel driving circuit Q may be adjusted based on the various signal lines to generate a driving signal, and each light-emitting device O may emit light under driven of the driving signal generated by the respective pixel driving circuit Q. Based on this, the pixel driving circuits Q in the plurality of sub-pixel regions may be used to drive the respective light-emitting devices O to emit light, so that the display panel 200 may display a predetermined image in the display area AA. Specifically, the plurality of sub-pixel regions P may include multiple sub-pixel regions P that emit light of different colors.

[0052] For example, the plurality of sub-pixel regions P may include first sub-pixel regions, second sub-pixel regions and third sub-pixel regions. The first sub-pixel regions, second sub-pixel regions and third sub-pixel regions may emit light of three primary colors. For example, the first sub-pixel regions may emit red light, the second sub-pixel regions may emit green light, and the third sub-pixel regions may emit blue light. Based on this, by adjusting the luminance (gray scale) of sub-pixels P of different colors, color combination and superposition may realize display of multiple colors, thereby realizing full-color display of the display panel 200.

[0053] Referring to FIGS. 2 and 3, the display panel 200 further includes an array substrate 100, and a light-emitting device layer 210. The array substrate 100 may include a plurality of pixel driving circuits Q. The light-emitting device layer 210 is located on a side of the array substrate 100. The light-emitting device layer 210 includes a plurality of light-emitting devices O, a light-emitting device O is electrically connected to a pixel driving circuit Q in the array substrate 100.

[0054] In some examples, the light-emitting device O includes an anode layer, a light-emitting layer, and a cathode layer that are sequentially stacked. In some examples, an electron transport layer is provided between the cathode layer and the light-emitting layer, and a hole transport layer is provided between the anode layer and the light-emitting layer. For example, the light-emitting device O may be an OLED light-emitting device, and it is not limited thereto. In the embodiments of the present disclosure, there is no limitation on the type of the light-emitting device. That is, the light-emitting device O may be any other type of the light-emitting device (e.g., a light-emitting device that emits light by discharging), as long as it is capable of emitting light to enable the display panel 200 to display images.

[0055] In some examples, the plurality of pixel driving circuits Q and the plurality of light-emitting devices O may be coupled in one-to-one correspondence. In some other examples, a pixel driving circuit Q may be coupled to multiple light-emitting devices O, or multiple pixel driving circuits Q may be coupled to a light-emitting device O.

[0056] Hereinafter, the structure of the display pane 200 will be described in the present disclosure by taking an example in which a pixel driving circuit Q is coupled to a light-emitting device O.

[0057] FIG. 4 is a structural diagram of an array substrate, in accordance with some embodiments.

[0058] As shown in FIG. 4, some embodiments of the present disclosure provide an array substrate 100. The array substrate 100 includes a substrate 01 and a pixel circuit layer 02 that is located on a side of the substrate 01. The pixel circuit layer 02 includes a plurality of pixel driving circuits Q.

[0059] In some examples, the substrate 01 may be a flexible substrate. For example, the substrate 01 is made of an organic material. For example, the substrate 01 is made of any one of polyimide (PI), polycarbonate (PC) or polyvinyl chloride (PVC).

[0060] In some other examples, the substrate 01 is a rigid substrate. For example, the rigid substrate is a glass substrate, a polymethyl methacrylate (PMMA) substrate, or the like.

[0061] In some examples, the pixel circuit layer 02 includes a plurality of metal layers that are stacked on the substrate 01. The plurality of metal layers are provided with pixel driving circuits Q and multiple various types of signal lines therein. The various types of signal lines include a plurality of first scanning signal lines G1, but are not limited thereto. The various types of signal lines may further include other types of signal lines, which will be described in detail below.

[0062] The plurality of pixel driving circuits Q are located on a side of the substrate 01, and the plurality of pixel driving circuits Q are arranged in a plurality of rows and columns. For convenience of description, the plurality of pixel driving circuits Q are described in the present disclosure by taking an example in which the plurality of pixel driving circuits Q are arranged in an array.

[0063] In this case, referring to FIG. 2, pixel driving circuits Q arranged in a row in a first direction X may be referred to as a row of pixel driving circuits Q, and pixel driving circuits Q arranged in a column in a second direction Y may be referred to as a column of pixel driving circuits Q.

[0064] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit, in accordance with some implementations.

[0065] Referring to FIG. 5, the pixel driving circuit Q may be a first type of pixel driving circuit. The first type of pixel driving circuit Q may include: a first reset transistor M1, a compensation transistor M2, a driving transistor M3, a data writing transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a second reset transistor M7, and a capacitor Cst.

[0066] Since the first type of pixel driving circuit needs to be electrically connected to multiple various types of signal lines, a plurality of signal lines with different types are illustrated in FIG. 5. The various types of signal lines may include: a first scanning signal line G1, a second scanning signal line G2, a data writing signal line Data, an enable signal line EM, a first power signal line Vdd, a first reset signal line R1, a second reset signal line R2, a first initialization signal line Vinit1, and a second initialization signal line Vinit2.

[0067] A control electrode of the first reset transistor M1 is coupled to the first reset signal line R1, a first electrode of the first reset transistor M1 is coupled to the first initial signal line Vinit1, and a second electrode of the first reset transistor M1 is coupled to a first node N1.

[0068] A control electrode of the compensation transistor M2 is coupled to the first scanning signal line Gate1, a first electrode of the compensation transistor M2 is coupled to the first node N1, and a second electrode of the compensation transistor M2 is coupled to a third node N3.

[0069] For example, a control electrode of the driving transistor M3 is coupled to the first node N1, a first electrode of the driving transistor M3 is coupled to the second node N2, and a second electrode of the driving transistor M3 is coupled to the third node N3.

[0070] A control electrode of the data writing transistor M4 is coupled to the second scanning signal line Gate2, a first electrode of the data writing transistor M4 is coupled to the data writing signal line Data, and a second electrode of the data writing transistor M4 is coupled to the second node N2.

[0071] A control electrode of the first light-emitting control transistor M5 is coupled to the enable signal line EM, a first electrode of the first light-emitting control transistor M5 is coupled to the first power signal line VDD, and a second electrode of the first light-emitting control transistor M5 is coupled to the second node N2.

[0072] A control electrode of the second light-emitting control transistor M6 is coupled to the enable signal line EM, a first electrode of the second light-emitting control transistor M6 is coupled to the third node N3, and a second electrode of the second light-emitting control transistor M6 is coupled to an end of the light-emitting device O, and the other end of the light-emitting device O is coupled to a third power signal line VSS. A voltage of a third power signal provided by the third power signal line VSS is less than a voltage of a first power signal provided by the first power signal line VDD.

[0073] For example, the end of the light-emitting device O coupled to the first type of pixel driving circuit is an anode of the light-emitting device O, and the end of the light-emitting device O coupled to the third power signal line VSS is a cathode of the light-emitting device O.

[0074] A control electrode of the second reset transistor M7 is coupled to the second reset signal line R2, a first electrode of the second reset transistor M7 is coupled to the second initial signal line Vinit2, and a second electrode of the second reset transistor M7 is coupled to the light-emitting device O.

[0075] It will be noted that each sub-pixel in the display panel 200 is driven by a plurality of thin film transistors (TFTs) to emit light, and the TFT driving technology is employed to improve display speed, contrast, brightness, and resolution. However, TFT exhibits hysteresis effect, and the hysteresis effect of TFT refers to an uncertainty in the electrical characteristics of TFT under a certain bias voltage. That is, the current flowing through the TFT is related to not only the current bias voltage, but also the state of the TFT at the previous moment. The hysteresis effect of TFT is related to the gate dielectric, semiconductor material and interface state traps between the two of the TFT. In the light-emitting phase, the hysteresis effect of TFT will cause a trend of current decrease within a frame, which is perceived by the human eyes as a flickering phenomenon and affects the display quality of the display panel 200.

[0076] In order to improve the hysteresis effect of the driving transistor M3, a threshold voltage of a pixel circuit is usually compensated to improve the brightness uniformity of the entire display screen. Specifically, the threshold voltage of the pixel circuit may be compensated when data is written.

[0077] In some embodiments, a driving process of the first type of pixel driving circuit shown in FIG. 5 is as follows. A frame period includes an initialization phase, a writing phase and a light-emitting phase.

[0078] In the initialization phase: the first reset signal transmitted by the first reset signal line R1 is an effective signal, and in this case, the first reset transistor M1 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 is transmitted to the third node N3 to reset the third node N3, so as to improve the stability of the driving transistor M3 included in the first type of pixel driving circuit.

[0079] In the writing phase: the first scanning signal transmitted by the first scanning signal line G1 is an effective signal, and the compensation transistor M2 is turned on; the second scanning signal transmitted by the second scanning signal line G2 is an effective signal, and in this case, the data writing transistor M4 is turned on, and the data writing signal transmitted by the data writing signal line Data may be transmitted to the first node N1 via the data writing transistor M4, the driving transistor M3, and the compensation transistor M2 in sequence to compensate the first node N1, so that the potential of the first node N1 gradually rises to (Vdata+Vth).

[0080] Here, Vdata is a voltage value of the data writing signal provided by the data writing signal line Data, and Vth is a threshold voltage of the driving transistor M3 in the first type of pixel driving circuit. When the potential of the first node N1 is (Vdata+Vth), the charging process is completed. Subsequently, the storage capacitor Cst is discharged to keep the driving transistor M3 included in the first type of pixel driving circuit continuously turned on, so as to ensure that the light-emitting device O emits light.

[0081] In the light-emitting phase: the enable signal transmitted by the enable signal line EM is an effective signal, and in this case, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both turned on. In this case, the driving transistor M3 included in the first type of pixel driving circuit may be kept turned on continuously by discharging the storage capacitor Cst.

[0082] Based on this, the constant-voltage power signal provided by the first power signal line Vdd may flow to the anode of the light-emitting device O via the first light-emitting control transistor M5, the driving transistor M3, and the second light-emitting control transistor M6 in sequence, and the cathode of the light-emitting device O may be electrically connected to the second power signal line Vss, thereby driving the light-emitting device O to emit light. The first power signal line Vdd may be a high-voltage power signal line, and the third power signal line Vss may be a low-voltage power signal line.

[0083] It will be noted that, the "effective signal" refers to a signal that can enable a transistor to be turned on. For example, the first scanning signal line G1 is electrically connected to a P-type transistor, and the effective signal is a low voltage signal; alternatively, the first scanning signal line G1 is electrically connected to an N-type transistor, and the effective signal is a high voltage signal, and the same is true for other signal lines.

[0084] The inventors have found through researches that in the above operation process of the first type of pixel driving circuit, since the threshold compensation and the data voltage writing are in the same phase (writing phase), the threshold compensation duration and the row period cannot be separated.

[0085] In a case where the display panel 200 has a high resolution or is driven at a high refresh rate, the row period of the display panel 200 becomes shorter, that is, the row period of each first type of pixel driving circuit becomes shorter, resulting in a shorter writing phase of the first type of pixel driving circuit, which leads to a shorter threshold compensation time of the first type of pixel driving circuit. Therefore, threshold compensation effect of the pixel driving circuit is poor, and in turn the display uniformity of the display panel 200 is poor.

[0086] Furthermore, when the display panel 200 displays a low grayscale image or is in a black state, the voltage value Vdata of the data writing signal provided by the data writing signal line Data required by the driving transistor M3 is large, which will result in a long time required for data writing and thus a short threshold compensation time for the first type of pixel driving circuit. Therefore, the threshold compensation effect of the pixel driving circuit is poor, which will result in poor display uniformity of the display panel 200.

[0087] FIG. 6 is an equivalent circuit diagram of a pixel driving circuit, in accordance with some embodiments.

[0088] Base on the above problems, referring to FIG. 6, some embodiments of the present disclosure provide a pixel driving circuit Q, which may be referred to as a second type of pixel driving circuit. The pixel driving circuit Q mentioned below are all the second type of pixel driving circuit.

[0089] The pixel driving circuit (the second type of pixel driving circuit) Q includes a driving sub-circuit 10, a light-emitting control sub-circuit 20, a writing sub-circuit 30, a compensation sub-circuit 40 and a storage sub-circuit 50.

[0090] The driving sub-circuit 10 is coupled to a first node N1, a second node N2 and a third node N3. The driving transistor T3 is configured to transmit a voltage of the second node N2 to the third node N3 under control of a voltage of the first node N1. The driving sub-circuit 10 includes a driving transistor.

[0091] The light-emitting control sub-circuit 20 includes a first branch 21, and the first branch 21 is coupled to a first power signal line VDD, a first enable signal line EM1 and a second node N2. The first branch 21 is configured to cooperate with the driving sub-circuit 10 to transmit the first power signal received from the first power signal line VDD to the third node N3 under control of the first enable signal from the first enable signal line EM1 in the compensation phase.

[0092] The compensation sub-circuit 40 is coupled to a first scanning signal line Gate1, a second scanning signal line Gate2, the first node N1, the third node N3, a fourth node N4, and a second power signal line VGH. The compensation sub-circuit 40 is configured to: in the compensation phase, transmit the voltage of the third node N3 to the first node N1 under control of the first scanning signal received from the first scanning signal line Gate1, and transmit a second power signal received from the second power signal line VGH to the fourth node N4 under control of the second scanning signal received from the second scanning signal line Gate2.

[0093] The writing sub-circuit 30 is coupled to a third scanning signal line Gate3, a data writing signal line Data and a fourth node N4. The writing sub-circuit 30 is configured to transmit a data writing signal received from the data writing signal line to the fourth node N4 under control of a third scanning signal received from the third scanning signal line Gate3 in the writing phase.

[0094] The storage sub-circuit 50 is coupled to the first node N1 and the fourth node N4. The storage sub-circuit 50 is configured to couple the voltage of the fourth node N4 to the first node N1 in the writing phase.

[0095] With the above configuration, in the compensation phase, the first enable signal from the first enable signal line EM1 is an effective signal to control the first branch 21 in the light-emitting control sub-circuit 20 to be turned on, the first scanning signal received from the first scanning signal line Gate1 is an effective signal, and the second scanning signal received from the second scanning signal line Gate2 is also an effective signal to control the compensation sub-circuit 40 to be turned on.

[0096] Based on this, the compensation sub-circuit 40 is controlled to be turned on, and the second power signal received from the second power signal line VGH may be transmitted to the fourth node N4. In this case, the voltage of the fourth node N4 is the voltage V2 of the second power signal.

[0097] Furthermore, based on the compensation sub-circuit 40 being controlled to be turned on, the first branch 21 is turned on and then is cooperated with the driving sub-circuit 10 (in this case, the driving sub-circuit 10 is in the on state), the first power signal received from the first power signal line VDD may be transmitted to the first node N1 via the second node N2 and the third node N3 to compensate the first node N1, and the potential of the first node N1 gradually rises to (V1+Vth).

[0098] Here, V1 is a voltage value of the first power signal provided by the first power signal line VDD, and Vth is a threshold voltage of the driving sub-circuit 10 (a driving transistor T3) in the second type of pixel driving circuit. When the potential of the first node N1 is (V1 +Vth), the driving sub-circuit 10 (the driving transistor T3) is turned off, and the threshold compensation is completed.

[0099] Moreover, since the storage sub-circuit 50 is connected in series between the first node N1 and the fourth node N4, an end of the storage sub-circuit 50 receives the voltage V2 from the fourth node N4, and the other end of the storage sub-circuit 50 receives the voltage (V1+Vth) from the first node N1, and the storage sub-circuit 50 determines the voltage difference between the two ends.

[0100] Subsequently, a storage capacitor Cst is used to discharge to keep the driving sub-circuit 10 (the driving transistor T3) included in the second type of pixel driving circuit continuously turned on, so as to ensure that the light-emitting device O emits light.

[0101] When entering the writing phase after the compensation phase, the third scanning signal received from the third scanning signal line is an effective signal, which controls the writing sub-circuit to be turned on to transmit the data writing signal received from the data writing signal line to the fourth node N4. In this case, the voltage of the fourth node N4 changes from V2 to Vdata. That is, the amount of voltage change of the fourth node N4 is expressed as: Δ = Vdata - V2, where Vdata is a voltage value of the data writing signal provided by the data writing signal line Data.

[0102] Due to the coupling effect of the storage sub-circuit 50, the voltage of the first node N1 follows the change of the voltage of the fourth node N4, and the amount of voltage change of the first node N1 is also approximately expressed as: Δ = Vdata - V2. Based on this, the voltage of the first node N1 may change from (V1+Vth) to (V1+Vth+Δ), which is expressed as: V1 + Vth + Δ = V1 + Vth + Vdata - V2.

[0103] In the light-emitting phase, the first enable signal on the first enable signal line EM1 is an effective signal, which controls the first branch 21 in the light-emitting control sub-circuit 20 to be turned on, so that the first power signal received from the first power signal line VDD is transmitted to the second node N2. In the case, a voltage of the second node N2 is V1. Then, the first branch 21 cooperates with the driving sub-circuit 10, so that the voltage of the second node N2 may be transmitted to the third node N3 and then transmitted to the light-emitting device O. In this case, the voltage of the first node N1 is maintained at (Vdata+Vth).

[0104] The light-emitting current of the light-emitting device O electrically connected to the pixel driving circuit Q is equal to the current flowing through the driving sub-circuit 10, and its expression is as follows: I D = 1 2 μCox W L Vgs − Vth 2

[0105] Here, µ is the electron mobility of the driving sub-circuit 10 (the driving transistor), Cox is the insulation capacitance per unit area, W L is the aspect ratio of the driving sub-circuit 10 (the driving transistor), Vth is the threshold voltage of the driving sub-circuit 10 (the driving transistor), and Vgs is the gate-source voltage of the driving sub-circuit 10 (the driving transistor). That is, Vgs is a difference between the voltage of the first node N1 and the voltage of the second node N2, and its expression is as follows: Vgs = V 1 + Vth + Vdata − V 2 − V 1 = Vth + Vdata − V 2

[0106] Based on this, the expression (2) is substituted into the expression (1), and the following expression is obtained: I D = 1 2 μCox W L Vth + Vdata − V 2 − Vth 2 = 1 2 μCox W L Vdata − V 2 2

[0107] It can be seen from the above that, the current I D flowing through the driving sub-circuit 10 (the driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V2 of the second power signal provided by the second power signal line VGH, and the current I D flowing through the driving sub-circuit 10 (the driving transistor) is independent of the threshold voltage Vth. Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O may be ameliorated, so that the uniformity of the luminance of the light-emitting device O is improved.

[0108] In summary, in the pixel driving circuit Q provided in the embodiments of the present disclosure, the driving sub-circuit 10, the light-emitting control sub-circuit 20, the writing sub-circuit 30, the compensation sub-circuit 40 and the storage sub-circuit 50 cooperate with each other, and the writing data voltage Vdata and the compensation threshold voltage are respectively realized through two separate paths, so as to separate the threshold compensation phase from the writing phase to prevent the duration of the writing phase from limiting the duration of the threshold compensation phase. That is, the duration of the threshold compensation phase may be made unaffected by the data writing duration (row time), which may ensure that the threshold compensation phase has sufficient duration to fully write the required voltage to compensate for the threshold voltage that fluctuations in a large range, so that the threshold voltage is fully compensated.

[0109] Based on this, the problem of poor display uniformity of a display panel 200 with high resolution or display panel 200 driven with high refresh rate due to insufficient duration of the threshold compensation phase when driving the pixel driving circuit Q may be effectively ameliorated. Furthermore, the problem of poor display uniformity of the display panel 200 when displaying a low grayscale image or being in a black state due to insufficient duration of the threshold compensation phase when driving the pixel driving circuit may be effectively ameliorated.

[0110] That is, in the embodiments of the present disclosure, even when the pixel driving circuit Q operates at a high refresh rate, or displays a low grayscale image or is in a black state, the threshold voltage of the driving sub-circuit 10 (the driving transistor T3) in the pixel driving circuit Q may be fully compensated, which may help ameliorate the difference in luminance to enhance the uniformity of display image quality.

[0111] In some embodiments, referring to FIG. 6, the voltage value V1 of the first power signal is equal to the voltage value V2 of the second power signal, and the expression thereof is as follows: V 2 = V 1

[0112] Based on this, after the compensation phase and in the light-emitting phase, the voltage of the first node N1 may be expressed as: V1 + Vth + Vdata - V2 = Vth+ Vdata.

[0113] Furthermore, the gate-source voltage of the driving sub-circuit 10 (the driving transistor) may be expressed as follows: Vgs = Vth + Vdata − V 1

[0114] The expression (5) is substituted into the above expression (1), the following expression may be obtained: I D = 1 2 μCox W L Vdata − V 1 2

[0115] It can be seen from the above that, the current I D flowing through the driving sub-circuit 10 (the driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V1 of the first power signal provided by the first power signal line VDD, and the current I D flowing through the driving sub-circuit 10 (the driving transistor) is independent of the threshold voltage Vth. Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O may be ameliorated, so that the uniformity of the luminance of the light-emitting device O is improved.

[0116] In some embodiments, referring to FIG. 6, the first power signal line VDD is also used as the second power signal line VGH.

[0117] With such a configuration, the first power signal line VDD is also used as the second power signal line VGH, i.e., there is no need to separately provide the second power signal line VGH, which may help simplify the structure of the pixel driving circuit Q and reduce the difficulty of layout in the display panel 200.

[0118] Furthermore, the first power signal line VDD is also used as the second power signal line VGH, and thus, the voltage value V1 of the first power signal may be made equal to the voltage value V2 of the second power signal, so that the current I D flowing through the driving sub-circuit 10 (the driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V1 of the first power signal provided by the first power signal line VDD, and the current I D flowing through the driving sub-circuit 10 (the driving transistor) is independent of the threshold voltage Vth. Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O may be ameliorated, so that the uniformity of the luminance of the light-emitting device O is improved.

[0119] FIG. 7 is an equivalent circuit diagram of a pixel driving circuit, in accordance with some other embodiments.

[0120] In some embodiments, as shown in FIG. 7, the driving sub-circuit 10 includes a driving transistor T3. A control electrode of the driving transistor T3 is coupled to the first node N1, a first electrode of the driving transistor T3 is coupled to the second node N2, and a second electrode of the driving transistor T3 is coupled to the third node N3.

[0121] In a case where the voltage of the first node N1 is an effective signal, the driving transistor T3 is turned on under control of the voltage of the first node N1, and transmit an electrical signal (e.g., the data signal) from the second node N2 to the third node N3.

[0122] It will be noted that, the "effective signal" in the present disclosure refers to a signal that can enable a transistor to be turned on. In a case where the transistor is an N-type transistor, the "effective signal" is a high voltage signal; in a case where the transistor is a P-type transistor, the "effective signal" is a low voltage signal. The following embodiments have the same meaning as the above, and details will not be repeated.

[0123] For example, in the case where the driving transistor T3 is a P-type transistor, and the voltage of the first node N1 is a low voltage signal, the driving transistor T3 is controlled to be turned on, and transmit an electrical signal (e.g., the data signal) from the second node N2 to the third node N3.

[0124] For example, the driving transistor T3 is an N-type transistor, and the voltage of the first node N1 is a high voltage signal, the driving transistor T3 is controlled to be turned on, and transmit an electrical signal (e.g., the data signal) from the second node N2 to the third node N3.

[0125] It will be noted that, the "high voltage signal" and "low voltage signal" mentioned above are common terms. Generally, the turn-on condition of the N-type transistor is that a gate-source voltage difference is greater than the threshold voltage of the N-type transistor, i.e., a gate voltage of the N-type transistor is greater than a sum of a source voltage thereof and the threshold voltage thereof; the threshold voltage of the N-type transistor is positive, then a gate voltage signal that turns on the N-type transistor is a high-voltage signal. The conduction condition of the P-type transistor is that an absolute value of the gate-source voltage difference is greater than the threshold voltage thereof, and the threshold voltage of the P-type transistor is negative; that is, a gate voltage that turns on the P-type transistor is a low-voltage signal.

[0126] In some examples, as shown in FIG. 7, the compensation sub-circuit 40 includes a second transistor T2 and a nine transistor T9. A control electrode of the second transistor T2 is coupled to the first scanning signal line Gate1, a first electrode of the second transistor T2 is coupled to a third node N3, and a second electrode of the second transistor T2 is coupled to the first node N1. A control electrode of the ninth transistor T9 is coupled to the third scanning signal line Gate3, a first electrode of the ninth transistor T9 is coupled to the second power signal VGH, and a second electrode of the ninth transistor T9 is coupled to the fourth node N4.

[0127] Based on this, in the compensation phase, the second scanning signal received from the second scanning signal line Gate2 is also an effective signal, so that the ninth transistor T9 is controlled to be turned on, and transmits the second power signal received from the second power signal line VGH to the fourth node N4.

[0128] Furthermore, in the compensation phase, the first scanning signal received from the first scanning signal line Gate1 is an effective signal, so that the second transistor T2 is controlled to be turned on and transmits the voltage of the third node N3 to the first node N1 to compensate the first node N1. The potential of the first node N1 gradually rises to (V1 +Vth), and the driving sub-circuit 10 (the driving transistor T3) is turned off, so that the threshold compensation is completed, and the charging process of the storage sub-circuit 50 is completed.

[0129] In some examples, referring to FIG. 7, the writing sub-circuit 30 includes a fourth transistor T4; a control electrode of the fourth transistor T4 is coupled to the third scanning signal line Gate3, a first electrode of the fourth transistor T4 is coupled to the data writing signal line Data, and a second electrode of the fourth transistor T4 is coupled to a fourth node N4.

[0130] Based on this, in the writing phase, the third scanning signal received from the third scanning signal line Gate3 is an effective signal, which controls the fourth transistor T4 to be turned on to transmit the data writing signal received from the data writing signal line Data to the fourth node N4. In this case, the voltage of the fourth node N4 changes from V2 to Vdata. That is, the amount of voltage change of the fourth node N4 is expressed as: Δ = Vdata - V2, where Vdata is the voltage value of the data writing signal provided by the data writing signal line Data.

[0131] Due to the coupling effect of the storage sub-circuit 50, the voltage of the first node N1 follows the change of the voltage of the fourth node N4, and the amount of voltage change of the first node N1 is also approximately expressed as: Δ = Vdata - V2. Based on this, the voltage of the first node N1 may change from (V1+Vth) to (V1+Vth+Δ), which is expressed as: V1 + Vth + Δ = V1 + Vth + Vdata - V2.

[0132] When the current I D flowing through the driving sub-circuit 10 (the driving transistor) is calculated subsequently, the threshold voltage Vth will be eliminated. Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O may be ameliorated, so that the uniformity of the luminance of the light-emitting device O is improved.

[0133] In some embodiments, referring to FIG. 7, the storage sub-circuit 50 includes a storage capacitor Cst; a first plate of the storage capacitor Cst is coupled to the fourth node N4, and a second plate of the storage capacitor Cst is coupled to the first node N1.

[0134] In the compensation phase, since the first plate of the storage capacitor Cst is coupled to the fourth node N4, the voltage of the first plate of the storage capacitor Cst is the voltage V2 of the second power signal received from the second power signal line VGH; moreover, since the second plate of the storage capacitor Cst is coupled to the first node N1, the voltage of the second plate of the storage capacitor Cst is the voltage (V1 +Vth) of the first node N.

[0135] In the writing phase, the third scanning signal received from the third scanning signal line Gate3 is an effective signal, which controls the data writing transistor T4 to be turned on to transmit the data writing signal received from the data writing signal line Data to the fourth node N4. In this case, the voltage of the fourth node N4 changes from V2 to Vdata, and the amount of voltage change of the fourth node N4 is expressed as: Δ = Vdata - V2.

[0136] Due to the coupling effect of the storage capacitor Cst, the voltage of the first node N1 may follow the change of the voltage of the fourth node N4.

[0137] Based on this, the amount of voltage change of the first node N1 is also approximately expressed as: Δ = Vdata - V2. Furthermore, the voltage of the first node N1 may change from (V1 +Vth) to (V1 +Vth+Δ), which is expressed as: V1 + Vth + Δ = V1 + Vth + Vdata - V2.

[0138] When the current I D flowing through the driving sub-circuit 10 (the driving transistor) is calculated subsequently, the threshold voltage Vth will be eliminated. Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O may be ameliorated, so that the uniformity of the luminance of the light-emitting device O is improved.

[0139] FIG. 8 is an equivalent circuit diagram of another pixel driving circuit, in accordance with some embodiments.

[0140] In some embodiments, referring to FIG. 8, the light-emitting control sub-circuit 20 included in the pixel driving circuit Q further includes a second branch 22. The second branch 22 is coupled to the third node N3, the second enable signal line EM2, and the light-emitting device O.

[0141] In the light-emitting phase, under the control of the second enable signal from the second enable signal line EM2, the second branch 22 is turned on, and transmits the voltage of the third node N3 to the light-emitting device O to drive the light-emitting device O to emit light.

[0142] As for the light-emitting control sub-circuit 20, in the light-emitting phase, the light-emitting control sub-circuit 20 is configured that the first branch 21 is turned on under the control of the first enable signal from the first enable signal line EM1 and the second branch 22 is turned on under the control of the second enable signal from the second enable signal line EM2, so that the light-emitting control sub-circuit 20 may cooperate with the driving sub-circuit 10 to transmit the first power signal received from the first power signal line VDD to the light-emitting device O. That is, in the light-emitting phase, the light-emitting control sub-circuit 20 is configured to transmit the first power signal received from the first power signal line VDD to the anode of the light-emitting device O, and the cathode of the light-emitting device O may be electrically connected to the second power signal line Vss, thereby driving the light-emitting device O to emit light.

[0143] In some embodiments, as shown in FIG. 8, the first branch 21 includes a fifth transistor T5; a control electrode of the fifth transistor T5 is coupled to the first enable signal line EM1, a first electrode of the fifth transistor T5 is coupled to the first power signal line VDD, and a second electrode of the fifth transistor T5 is coupled to the second node N2.

[0144] In the compensation phase, the first enable signal provided by the first enable signal line EM1 is an effective signal, and the fifth transistor T5 is controlled to be turned on to transmit the first power signal provided by the first power signal line VDD to the second node N2; then, the fifth transistor T5 cooperates with the driving sub-circuit 10 to enable the voltage of the second node N2 (the voltage V1 of the first power signal) to be transmitted to the third node N3; finally, the fifth transistor T5 cooperates with the compensation sub-circuit 40 to enable the voltage of the third node N3 (the voltage V1 of the first power signal) to be transmitted to the first node N1, until the voltage of the first node N1 is (V1+Vth), the driving sub-circuit 10 (the driving transistor T3) is controlled to be turned off, and the threshold compensation is completed.

[0145] In some embodiments, with continued reference to FIG. 8, the second branch 22 includes a sixth transistor T6; a control electrode of the sixth transistor T6 is coupled to the second enable signal line EM2, a first electrode of the sixth transistor T6 is coupled to the third node N3, and a second electrode of the sixth transistor T6 is coupled to the light-emitting device O.

[0146] In the light-emitting phase, the first enable signal provided by the first enable signal line EM1 is an effective signal, so that the fifth transistor T5 is controlled to be turned on; the second enable signal provided by the second enable signal line EM2 is also an effective signal, so that the sixth transistor T6 is controlled to be turned on; and then, the light-emitting control sub-circuit 20 cooperates with the driving sub-circuit 10 to enable the first power signal provided by the first power signal line VDD to be transmitted to the light-emitting device O to drive the light-emitting device O to emit light.

[0147] In some embodiments, with continued reference to FIG. 8, the pixel driving circuit Q further includes a first reset sub-circuit 60. The first reset sub-circuit 60 is coupled to the first node N1, the first reset signal line R1, and the first initialization signal line Vinit1. The first reset sub-circuit 60 is configured to transmit the first initial signal received from the first initial signal line Vinit1 to the first node N1 under control of the first reset signal transmitted by the first reset signal line R1, so as to initialize the first node N1.

[0148] Before the compensation phase, the first node N1 of the pixel driving circuit Q may be initialized. In this case, the first reset signal provided by the first reset signal line R1 is an effective signal, so that the first reset sub-circuit 60 is controlled to be turned on to transmit the first initialization signal provided by the first initialization signal line Vinit1 to the first node N1 to initialize the first node N1. That is, the control electrode of the driving transistor T3 is initialized by using the first initialization signal provided by the first initialization signal line Vinit1, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0149] In some examples, the first initialization signal provided by the first initialization signal line Vinit1 is a low voltage signal. Based on this, before the compensation phase, a low voltage signal is transmitted to the first node N1 to initialize the control electrode of the driving transistor T3 so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0150] For example, the low voltage signal may be a signal with a voltage that is lower than the voltage Vdata of the data writing signal when the display panel 200 displays any gray scale, so as to eliminate the residual signal when displaying the previous frame of image.

[0151] In some embodiments, with continued reference to FIG. 8, the first reset sub-circuit 60 includes a first transistor T1; a control electrode of the first transistor T1 is coupled to a first reset signal line R1, a first electrode of the first transistor T1 is coupled to the first initial signal line Vinit1, and a second electrode of the first transistor T1 is coupled to a first node N1.

[0152] Before the compensation phase, the first reset signal provided by the first reset signal line R1 may be controlled to be an effective signal, so that the first transistor T1 may be controlled to be turned on to transmit the first initialization signal received from the first initialization signal line Vinit1 to the first node N1. Thus, the first node N1 may be reset, and the control electrode of the driving transistor T3 may be reset, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0153] In addition, when the first node N1 is initialized by using the first initialization signal provided by the first initialization signal line Vinit1, the first initialization signal provided by the first initialization signal line Vinit1 is synchronously transmitted to the storage capacitor Cst in the storage sub-circuit 50. In the subsequent compensation phase, the storage capacitor Cst in the storage sub-circuit 50 may be discharged to keep the driving sub-circuit 10 (the driving transistor T3) continuously turned on, thereby ensuring that the first power signal provided by the first power signal terminal VDD is transmitted to the first node N1.

[0154] In some embodiments, with continued reference to FIG. 8, the pixel driving circuit Q further includes a second reset sub-circuit 70. The second reset sub-circuit 70 is coupled to the light-emitting device O, the second reset signal line R2 and the second initialization signal line Vinit2. The second reset sub-circuit 70 is configured to transmit a second initialization signal received from the second initialization signal line Vinit2 to the light-emitting device O under control of the second reset signal received from the second reset signal line R2, so as to reset the light-emitting device O.

[0155] Before the light-emitting phase, the light-emitting device O electrically connected to the pixel driving circuit Q may be reset first. In this case, the second reset signal provided by the second reset signal line R2 is an effective signal, so that the second reset sub-circuit 70 is controlled to be turned on to transmit the second initialization signal received from the second initialization signal line Vinit2 to the light-emitting device O, so as to reset the anode of the light-emitting device O, which is beneficial to improving the stability of the light-emitting device O.

[0156] In some examples, the second initialization signal provided by the second initialization signal line Vinit2 is a low voltage signal. Based on this, before the light-emitting phase, a low voltage signal is transmitted to the anode of the light-emitting device O to control the light-emitting device O not to emit light, thereby ameliorating the influence of the charge remaining on the anode of the light-emitting device O on the light-emitting luminance and improving the uniformity of the luminance of the light-emitting device O.

[0157] For example, the low voltage signal may be a signal less than 0 V, so as to control the light-emitting device O not to emit light, thereby ameliorating the influence of the charge remaining on the anode of the light emitting device O on the light-emitting luminance.

[0158] In some embodiments, with continued reference to FIG. 8, the second reset sub-circuit 70 includes a seventh transistor T7, a control electrode of the seventh transistor T7 is coupled to the second reset signal line R2, a first electrode of the seventh transistor T7 is coupled to the second initialization signal line Vinit2, and a second electrode of the eighth transistor T8 is coupled to the light-emitting device O.

[0159] Before the light-emitting phase, the second reset signal provided by the second reset signal line R2 may be controlled to be an effective signal to control the seventh transistor T7 to be turned on, so that the second initialization signal received from the second initialization signal line Vinit2 is transmitted to the light-emitting device O to reset the anode of the light-emitting device O, which is beneficial to improving the stability of the light-emitting device O.

[0160] In some embodiments, with continued reference to FIG. 8, the pixel driving circuit Q further includes a third reset sub-circuit 80. The third reset sub-circuit 80 is coupled to the second node N2, a third reset signal line R3 and a first reference voltage signal line Vref; the third reset sub-circuit 80 is configured to transmit a first reference voltage signal received from the first reference voltage signal line Vref to the second node N2 under control of a third reset signal received from the third reset signal line R3, thereby resetting the second node N2.

[0161] Before the compensation phase, the third reset signal provided by the third reset signal line R3 may be controlled to be an effective signal to control the third reset sub-circuit 80 to be turned on, so that the first reference voltage signal received from the first reference voltage signal line Vref is transmitted to the second node N2 to reset the second node N2. Thus, the initial state of the driving transistor T3 is fixed before the writing phase, which helps the driving transistor T3 to be in a stable state in the writing phase, thereby greatly ameliorating the hysteresis effect of the driving transistor T3.

[0162] In some examples, the first reference voltage signal provided by the first reference voltage signal line Vref may be a high voltage signal. The gate-source voltage Vgs of the driving transistor T3 in the pixel driving circuit Q is less than Vth, and the driving transistor T3 is in a turn-on bias state. That is, before data is written, the driving transistor is in a turn-on bias state, which may ensure that the driving transistor in each pixel driving circuit is charged and compensated from the turn-on bias state without being affected by the data voltage in the previous frame, thereby eliminating the influence of the hysteresis effect of the driving transistor T3 to ameliorate the problems of image sticking and response time.

[0163] In some embodiments, with continued reference to FIG. 8, the third reset sub-circuit 80 includes an eighth transistor T8, a control electrode of the eighth transistor T8 is coupled to the third reset signal line R3, a first electrode of the eighth transistor T8 is coupled to the first reference voltage signal line Vref, and a second electrode of the eighth transistor T8 is coupled to the second node N2.

[0164] Before the compensation phase, the third reset signal provided by the third reset signal line R3 may be controlled to be an effective signal to control the eighth transistor T8 to be turned on, so that the first reference voltage signal received from the first reference voltage signal line Vref is transmitted to the second node N2 to reset the second node N2. Thus, the initial state of the driving transistor T3 is fixed before the writing phase, which helps the driving transistor TD to be in a stable state in the writing phase, thereby greatly ameliorating the hysteresis effect of the driving transistor T3.

[0165] In some embodiments, with continued reference to FIG. 8, the third reset signal line R3 is multiplexed as the second reset signal line R2.

[0166] With such configuration, the third reset signal line R3 is also used as the second reset signal line R2, and there is no need to separately provide the second reset signal line R2, which may help simplify the structure of the pixel driving circuit Q and reduce the difficulty of layout in the display panel 200.

[0167] Furthermore, the third reset signal line R3 is also used as the second reset signal line R2, and the third reset signal may be used to control the second reset sub-circuit 70 (the seventh transistor T7) to be turned on multiple times (turned on once in the reset phase, and turned on once again after the writing phase and before the light-emitting phase), so that the second initialization signal received from the second initialization signal line Vinit2 is transmitted to the light-emitting device O to reset the anode of the light-emitting device O multiple times, which may help improve the stability of the light-emitting device O.

[0168] In some embodiments, with continued reference to FIG. 8, the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.

[0169] The above 9 transistors are all P-type transistors. That is, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8, and the ninth transistor T9 are all P-type transistors.

[0170] In the case where the above 9 transistors are all P-type transistors, the above "effective signal" may be understood as a low voltage signal. That is, the above 9 transistors may all be turned on under the control of a low voltage signal.

[0171] In some examples, the above 9 transistors may all be low temperature polysilicon (LTPS) transistors. That is, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8, and the ninth transistor T9 are all be LTPS transistors. Since the LTPS transistor has a high carrier mobility, the transistor may have a fast response speed.

[0172] FIG. 9 is an equivalent circuit diagram of yet another pixel driving circuit, in accordance with some embodiments.

[0173] In some embodiments, referring to FIG. 9, the first transistor T1 in the first reset sub-circuit 60 of the pixel driving circuit Q is an N-type transistor. In a case where the first transistor T1 is an N-type transistor, the above "effective signal" is a high voltage signal. That is, the first transistor T1 may be turned on under the control of the high voltage signal.

[0174] The first transistor T1 is set as an N-type transistor, which may help reduce the risk of leakage of the first transistor T1 and help ensure the stability of the voltage of the first node N1, i.e., ensure the stability of the driving transistor T3, so as to improve the luminance retention rate of the light-emitting device O within a frame.

[0175] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO). The oxide transistor has a small off-leakage current, thereby reducing the leakage current of the first node N1 through the first transistor T1 during the light emitting phase.

[0176] In some embodiments, referring to FIG. 9, the second transistor T2 in the compensation sub-circuit 40 of the pixel driving circuit Q may be an N-type transistor. In a case where the second transistor T2 is an N-type transistor, the "effective signal" may be understood as a high voltage signal. That is, the second transistor T2 may be turned on under the control of the high voltage signal.

[0177] The second transistor T2 is set as an N-type transistor, which may help reduce the risk of leakage of the second transistor T2 and help ensure the stability of the voltage of the first node N1, i.e., ensure the stability of the driving transistor T3, so as to improve the luminance retention rate of the light-emitting device O within a frame.

[0178] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO). The oxide transistor has a small off-leakage current, thereby reducing the leakage current of the first node N1 through the second transistor T2 during the light-emitting phase.

[0179] In some embodiments, referring to FIG. 9, since the two plates of the storage capacitor Cst are respectively coupled to the first node N1 and the fourth node N4, in the light-emitting phase, the first node N1 and the fourth node N4 are both in a floating state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0180] Based on this, the fourth transistor T4 in the data writing sub-circuit 30 in the pixel driving circuit Q may be an N-type transistor. In a case where the fourth transistor T4 is an N-type transistor, the "effective signal" may be understood as a high voltage signal. That is, the fourth transistor T4 may be turned on under the control of the high voltage signal.

[0181] The fourth transistor T4 is set as an N-type transistor, which may help reduce the risk of leakage of the fourth transistor T4 and help ensure the stability of the voltage of the fourth node N4, thereby preventing the fourth node N4 from affecting the voltage of the first node N1 to improve the stability of the voltage of the first node N1, i.e., ensure the stability of the driving transistor T3, so as to improve the luminance retention rate of the light-emitting device O within a frame.

[0182] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO). The oxide transistor has a small off-leakage current, thereby reducing the leakage current of the fourth node N4 through the fourth transistor T4 during the light-emitting phase.

[0183] In some embodiments, referring to FIG. 9, since the two plates of the storage capacitor Cst are respectively coupled to the first node N1 and the fourth node N4, in the light-emitting phase, the first node N1 and the fourth node N4 are both in a floating state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0184] Based on this, the ninth transistor T9 in the compensation sub-circuit 40 in the pixel driving circuit Q may be an N-type transistor. In a case where the ninth transistor T9 is an N-type transistor, the "effective signal" is a high voltage signal. That is, the ninth transistor T9 may be turned on under the control of the high voltage signal.

[0185] The ninth transistor T9 is set as an N-type transistor, which may help reduce the risk of leakage of the ninth transistor T9 and help ensure the stability of the voltage of the fourth node N4, thereby preventing the fourth node N4 from affecting the voltage of the first node N1 to improve the stability of the voltage of the first node N1, i.e., ensure the stability of the driving transistor T3, so as to improve the luminance retention rate of the light-emitting device O within a frame.

[0186] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO). The oxide transistor has a small off-leakage current, thereby reducing the leakage current of the fourth node N4 through the ninth transistor T9 during the light-emitting phase.

[0187] In some embodiments, referring to FIG. 9, in the case where the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a fourth transistor T4, and a ninth transistor T9, at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 is an N-type transistor.

[0188] With such configuration, it is possible to improve the stability of the voltage of the first node N1, i.e., ensure the stability of the driving transistor T3, so as to improve the luminance retention rate of the light-emitting device O within a frame.

[0189] Here, "at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 is an N-type transistor" may include the following cases.

[0190] First case: any one of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 is an N-type transistor.

[0191] Second case: any two of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are N-type transistors.

[0192] Third case: any three of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are N-type transistors.

[0193] Fourth case: the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all the N-type transistors. FIG. 9 is illustrated by taking an example in which the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all the N-type transistors, and the present disclosure is not limited thereto.

[0194] No matter which of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is set as an N-type transistor, the stability of the driving transistor T3 is improved, and the luminance retention rate of the light-emitting device O in a frame may be improved.

[0195] FIG. 10 is an equivalent circuit diagram of yet another pixel driving circuit, in accordance with some embodiments.

[0196] In some embodiments, referring to FIG. 10, the first transistor T1 in the first reset sub-circuit 60 of the pixel driving circuit Q may be a dual-gate transistor.

[0197] In the case where the first transistor T1 is a dual-gate transistor, the first transistor T1 may be a P-type transistor, or first transistor T1 may be an N-type transistor.

[0198] In the case where the first transistor T1 is a P-type dual-gate transistor, the above-mentioned "effective signal" may be understood as a low voltage signal. That is, the first transistor T1 may be turned on under the control of the low voltage signal.

[0199] In the case where the first transistor T1 is an N-type dual-gate transistor, the above-mentioned "effective signal" may be understood as a high voltage signal. That is, the first transistor T1 may be turned on under the control of the high voltage signal.

[0200] The first transistor T1 is set as a dual-gate transistor, which may help improve the stability of the first transistor, thereby helping to reduce the risk of leakage of the first transistor T1. As a result, it is helpful to ensure the stability of the voltage of the first node N1, i.e., ensure the stability of the driving transistor T3, so as to improve the luminance retention rate of the light-emitting device O within a frame.

[0201] In some embodiments, referring to FIG. 10, the second transistor T2 in the compensation sub-circuit 40 in the pixel driving circuit Q may be a dual-gate transistor.

[0202] In a case where the second transistor T2 is a dual-gate transistor, the second transistor T2 may be a P-type transistor, or the second transistor T2 may be an N-type transistor.

[0203] In a case where the second transistor T2 is a P-type dual-gate transistor, the above-mentioned "effective signal" may be understood as a low voltage signal. That is, the second transistor T2 may be turned on under the control of the low voltage signal.

[0204] In the case where the second transistor T2 is an N-type dual-gate transistor, the above-mentioned "effective signal" may be understood as a high voltage signal. That is, the second transistor T2 may be turned on under the control of the high voltage signal.

[0205] The second transistor T2 is set as a dual-gate transistor, which may help improve the stability of the second transistor T2, thereby helping to reduce the risk of leakage of the second transistor T2. Based on this, it is helpful to ensure the stability of the voltage of the first node N1, i.e., ensure the stability of the driving transistor T3, so as to improve the luminance retention rate of the light-emitting device O within a frame.

[0206] In some embodiments, referring to FIG. 10, since the two plates of the storage capacitor Cst are respectively coupled to the first node N1 and the fourth node N4, in the light-emitting phase, the first node N1 and the fourth node N4 are both in a floating state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0207] Based on this, the fourth transistor T4 in the data writing sub-circuit 30 in the pixel driving circuit Q may be a dual-gate transistor.

[0208] In the case where the fourth transistor T4 is a dual-gate transistor, the fourth transistor T4 may be a P-type transistor, or the fourth transistor T4 may be an N-type transistor.

[0209] In the case where the fourth transistor T4 is a P-type dual-gate transistor, the above-mentioned "effective signal" may be understood as a low voltage signal. That is, the fourth transistor T4 may be turned on under the control of the low voltage signal.

[0210] In the case where the fourth transistor T4 is an N-type dual-gate transistor, the above-mentioned "effective signal" may be understood as a high voltage signal. That is, the fourth transistor T4 may be turned on under the control of the high voltage signal.

[0211] The fourth transistor T4 is set as a dual-gate transistor, which may help improve the stability of the fourth transistor T4, thereby helping to reduce the risk of leakage of the fourth transistor T4, so as to ensure the stability of the voltage of the fourth node N4. Therefore, it is possible to prevent the fourth node N4 from affecting the voltage of the first node N1 to improve the stability of the voltage of the first node N1, i.e., ensure the stability of the driving transistor T3, so as to improve the luminance retention rate of the light-emitting device O within a frame.

[0212] In some embodiments, referring to FIG. 10, since the two plates of the storage capacitor Cst are respectively coupled to the first node N1 and the fourth node N4, in the light-emitting phase, the first node N1 and the fourth node N4 are both in a floating state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0213] Based on this, the ninth transistor T9 in the compensation sub-circuit 40 in the pixel driving circuit Q may be set as a dual-gate transistor.

[0214] In a case where the ninth transistor T9 is a dual-gate transistor, the ninth transistor T9 may be a P-type transistor, or the ninth transistor T9 may be an N-type transistor.

[0215] In the case where the ninth transistor T9 is a P-type dual-gate transistor, the above-mentioned "effective signal" may be understood as a low voltage signal. That is, the ninth transistor T9 may be turned on under the control of the low voltage signal.

[0216] In the case where the ninth transistor T9 is an N-type dual-gate transistor, the above-mentioned "effective signal" may be understood as a high voltage signal. That is, the ninth transistor T9 may be turned on under the control of the high voltage signal.

[0217] The ninth transistor T9 is set as a dual-gate transistor, which may help improve the stability of the ninth transistor T9, thereby helping to reduce the risk of leakage of the ninth transistor T9, so as to ensure the stability of the voltage of the fourth node N4. Therefore, it is possible to prevent the fourth node N4 from affecting the voltage of the first node N1 to improve the stability of the voltage of the first node N1, i.e., ensure the stability of the driving transistor T3, so as to improve the luminance retention rate of the light-emitting device O within a frame.

[0218] In some embodiments, referring to FIG. 10, in the case where the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a fourth transistor T4, and a ninth transistor T9, at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 is a dual-gate transistor.

[0219] With such configuration, it may be possible to improve the stability of the voltage of the first node N1, i.e., ensure the stability of the driving transistor T3, so as to improve the luminance retention rate of the light-emitting device O within a frame.

[0220] Here, "at least one of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is a dual-gate transistor" may include the following cases.

[0221] First case: any one of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is a dual-gate transistor.

[0222] Second case: any two of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 are dual-gate transistors.

[0223] Third case: any three of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 are dual-gate transistors.

[0224] Fourth case: the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 are all dual-gate transistors. FIG. 10 is illustrated by taking an example in which the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 are all dual-gate transistors, and the present disclosure is not limited thereto.

[0225] No matter which of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is set as a dual-gate transistor, the stability of the driving transistor T3 may be improved, and the luminance retention rate of the light-emitting device O within a frame may be improved.

[0226] FIG. 11 is a timing diagram of a pixel driving circuit, in accordance with some embodiments.

[0227] Some embodiments of the present disclosure provide a driving method for a pixel driving circuit, and the driving method is applied to the pixel driving circuit Q provided in any of the embodiments of the present disclosure.

[0228] Referring to FIGS. 8 to 10, the pixel driving circuit Q includes: a driving sub-circuit 10, a light-emitting control sub-circuit 20, a writing sub-circuit 30, a compensation sub-circuit 40 and a storage sub-circuit 50. The driving sub-circuit 10 is coupled to a first node N1, a second node N2 and a third node N3. The light-emitting control sub-circuit 20 includes a first branch 21, and the first branch 21 is coupled to a first power signal line VDD, a first enable signal line EM1 and a second node N2. The compensation sub-circuit 40 is coupled to a first scanning signal line Gate1, a second scanning signal line Gate2, the first node N1, the third node N3, a fourth node N4, the first power signal line VDD, and a second power signal line VGH. A voltage of a first power signal is equal to a voltage of a second power signal. The writing sub-circuit 30 is coupled to a third scanning signal line Gate3, a data writing signal line Data, and the fourth node N4. The storage sub-circuit 50 is coupled to a first node N1 and the fourth node N4.

[0229] The description will be made by taking the pixel driving circuit Q shown in FIG. 8, i.e., the 9 transistors in the pixel driving circuit Q are all P-type transistors, as an example. The following method is also applicable to the pixel driving circuit Q including P-type dual-gate transistors; that is, the following method is also applicable to the pixel driving circuit shown in FIG. 10.

[0230] The driving method includes multiple light-emitting periods, one light-emitting period F (one frame) of which includes a refresh frame and at least one holding frame, and another one light-emitting period (one frame) of which is a display frame, i.e., a display picture.

[0231] The refresh frame includes a compensation phase t2 and a writing phase t3.

[0232] In the compensation phase t2, a second scanning signal provided by the second scanning signal line Gate2 is a low voltage signal, so that the compensation sub-circuit 40 (the ninth transistor T9) is controlled to be turned on to transmit the second power signal received from the second power signal line VGH to the fourth node N4. In this case, a voltage of the fourth node N4 is a voltage V2 of the second power signal.

[0233] A first enable signal provided by the first enable signal line EM1 is a low voltage signal, so that the first branch 21 is controlled to be turned on to transmit the first power signal received from the first power signal line VDD to the second node N2; and then the first branch 21 cooperates with the driving sub-circuit to transmit a voltage of the second node N2 to the third node N3.

[0234] The first scanning signal provided by the first scanning signal line Gate1 is a low voltage signal, so that the compensation sub-circuit 40 (the second transistor T2) is controlled to be turned on to transmit the voltage of the third node N3 to the first node N1, so as to compensate the first node N1. Thus, the potential of the first node N1 gradually rises to (V1+Vth).

[0235] Here, V1 is the voltage value of the first power signal provided by the first power signal line VDD, and Vth is the threshold voltage of the driving sub-circuit 10 (the driving transistor T3) in the second type of pixel driving circuit. When the potential of the first node N1 is (V1+Vth), the driving sub-circuit 10 (the driving transistor T3) is turned off, and the threshold compensation is completed.

[0236] Since the storage sub-circuit 50 is connected in series between the first node N1 and the fourth node N4, when an end of the storage sub-circuit 50 receives the voltage V2 from the fourth node N4 and the other end of the storage sub-circuit 50 receives the voltage (V1+Vth) from the first node N1, the charging process for the storage sub-circuit 50 is completed.

[0237] Based on this, the first power signal provided by the first power signal line VDD may be used to perform threshold compensation on the driving transistor T3 included in the driving sub-circuit 10.

[0238] In the writing phase, the third scanning signal provided by the third scanning signal line Gate3 is a low voltage signal, so that the data writing sub-circuit 30 (the fourth transistor T4) is controlled to be turned on to transmit the data writing signal received from the data writing signal line Data to the fourth node N4. At this time, the voltage of the fourth node N4 changes from V2 to Vdata. That is, the amount of voltage change of the fourth node N4 is expressed as: Δ = Vdata - V2, where Vdata is the voltage value of the data writing signal provided by the data writing signal line Data.

[0239] The storage sub-circuit 50 couples the voltage of the fourth node N4 to the first node N1. That is, the voltage of the first node N1 follows the change of the voltage of the fourth node N4, and the amount of voltage change of the first node N1 is also approximately expressed as: Δ = Vdata - V2. Based on this, the voltage of the first node N1 may change from (V1+Vth) to (V1+Vth+Δ), which is expressed as: V1 + Vth + Δ = V1 + Vth + Vdata - V2.

[0240] In some examples, the refresh frame may further include a light-emitting phase t5 after the writing phase t3.

[0241] In the light-emitting phase t5, the first enable signal on the first enable signal line EM1 is a low voltage signal, so that the first branch 21 (the fifth transistor T5) is controlled to be turned on to transmit the first power signal received from the first power signal line VDD to the second node N2. In this case, the voltage of the second node N2 is V1. Then, the first branch 21 cooperates with the driving sub-circuit 10, so that the voltage of the second node N2 may be transmitted to the third node N3, and then transmitted to the light-emitting device O.

[0242] The light-emitting current of the light-emitting device O electrically connected to the pixel driving circuit Q is equal to the current flowing through the driving sub-circuit 10, and its expression is as follows: I D = 1 2 μCox W L Vgs − Vth 2

[0243] Here, µ is the electron mobility of the driving sub-circuit 10 (the driving transistor), Cox is the insulation capacitance per unit area, W L is the aspect ratio of the driving sub-circuit 10 (the driving transistor), Vth is the threshold voltage of the driving sub-circuit 10 (the driving transistor), and Vgs is the gate-source voltage of the driving sub-circuit 10 (the driving transistor). That is, Vgs is a difference between the voltage of the first node N1 and the voltage of the second node N2, and its expression is as follows: Vgs = V 1 + Vth + Vdata − V 2 − V 1 = Vth + Vdata − V 2

[0244] Based on this, the expression (2) is substituted into the expression (1), and the following expression is obtained: I D = 1 2 μCox W L Vth + Vdata − V 2 − Vth 2 = 1 2 μCox W L Vdata − V 2 2

[0245] It can be seen from the above that, the current I D flowing through the driving sub-circuit 10 (the driving transistor T3) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V2 of the second power signal provided by the second power signal line VGH, and the current I D flowing through the driving sub-circuit 10 (the driving transistor) is independent of the threshold voltage Vth. Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O may be ameliorated, so that the uniformity of the luminance of the light-emitting device O is improved.

[0246] In summary, in the driving method for the pixel driving circuit Q provided by the embodiments of the present disclosure, a separate compensation phase t2 and a writing phase t3 is provided. That is, the writing data voltage Vdata and the compensation threshold voltage are respectively realized through two separate paths, so as to separate the threshold compensation phase from the writing phase to prevent the duration of the writing phase from limiting the duration of the threshold compensation phase. Thus, the duration of the threshold compensation phase may be not affected by the data writing duration (row time), which may ensure that the threshold compensation phase has sufficient duration to fully write the required voltage to compensate for the threshold voltage that fluctuations in a large range, so that the threshold voltage is fully compensated.

[0247] Based on this, the problem of poor display uniformity of a display panel 200 with high resolution or display panel 200 driven with high refresh rate due to insufficient duration of the threshold compensation phase when driving the pixel driving circuit Q may be effectively ameliorated. Furthermore, the problem of poor display uniformity of the display panel 200 when displaying a low grayscale image or being in a black state due to insufficient duration of the threshold compensation phase when driving the pixel driving circuit may be effectively ameliorated.

[0248] That is, in the embodiments of the present disclosure, even when the pixel driving circuit Q operates at a high refresh rate, or displays a low grayscale image or is in a black state, the threshold voltage of the driving sub-circuit 10 (the driving transistor T3) in the pixel driving circuit Q may be fully compensated, which may help ameliorate the difference in luminance to enhance the uniformity of display image quality.

[0249] In some embodiments, referring to FIGS. 8 and 11, the pixel driving circuit 31 may further include a third reset sub-circuit 80. The third reset sub-circuit 80 is coupled to the second node N2, the third reset signal line R3 and a first reference voltage signal line Vref.

[0250] The refresh frame further includes a reset phase t1, and the reset phase t1 may include a first reset phase t11.

[0251] In the first reset phase t11, a third reset signal provided by the third reset signal line R3 is a low voltage signal, so that the third reset sub-circuit 80 (the eighth transistor T8) is controlled to be turned on to transmit a first reference voltage signal received from the first reference voltage signal line Vref to the second node N2, so as to reset the second node N2.

[0252] Based on this, it is equivalent to resetting the second node N2 of the pixel driving circuit Q before the compensation phase t2. Thus, the initial state of the driving transistor T3 is fixed before the writing phase, which helps the driving transistor T3 to be in a stable state in the writing phase, thereby greatly ameliorating the hysteresis effect of the driving transistor T3.

[0253] In some examples, the first reference voltage signal provided by the first reference voltage signal line Vref may be a high voltage signal. The gate-source voltage Vgs of the driving transistor T3 in the pixel driving circuit Q is less than Vth, and the driving transistor T3 is in a turn-on bias state. That is, before data is written, the driving transistor is in a turn-on bias state, which may ensure that the driving transistor in each pixel driving circuit is charged and compensated from the turn-on bias state without being affected by the data voltage in the previous frame, thereby eliminating the influence of the hysteresis effect of the driving transistor T3 to ameliorate the problems of image sticking and response time.

[0254] In some embodiments, referring to FIGS. 8 and 11, the pixel driving circuit Q further includes a second reset sub-circuit 70. The second reset sub-circuit 70 is coupled to the light-emitting device O, the second reset signal line R2 and the second initialization signal line Vinit2.

[0255] In the first reset phase t11, the second reset signal provided by the second reset signal line R2 may be a low voltage signal, so that the second reset sub-circuit 70 (the seventh transistor T7) is controlled to be turned on to transmit the second initialization signal received from the second initialization signal line Vinit2 to the light-emitting device O, so as to reset the light-emitting device O.

[0256] It is equivalent to that, before the light-emitting phase t5, the light-emitting device O electrically connected to the pixel driving circuit Q is reset first, which helps improve the stability of the light-emitting device O.

[0257] In some examples, the second initialization signal provided by the second initialization signal line Vinit2 is a low voltage signal. Based on this, before the light-emitting phase, a low voltage signal is transmitted to the anode of the light-emitting device O to control the light-emitting device O not to emit light, thereby ameliorating the influence of the charge remaining on the anode of the light-emitting device O on the light-emitting luminance and improving the uniformity of the luminance of the light-emitting device O.

[0258] For example, the low voltage signal may be a signal less than 0 V, so as to control the light-emitting device O not to emit light, thereby ameliorating the influence of the charge remaining on the anode of the light emitting device O on the light-emitting luminance.

[0259] In some embodiments, with continued reference to FIGS. 8 and 11, the third reset signal line R3 is also used as the second reset signal line R2.

[0260] With the above structure configuration, in the first reset phase t11, the second reset sub-circuit 70 and the third reset sub-circuit 80 are turned on simultaneously in response to the low voltage signal provided by the third reset signal line R3, and the first reference voltage signal received from the first reference voltage signal line Vref is transmitted to the second node N2 to reset the second node N2, which may help to ameliorate the influence of hysteresis effect of the driving transistor T3. Furthermore, the second initialization signal received from the second initialization signal line Vinit2 is transmitted to the light-emitting device O to reset the light-emitting device O, which is beneficial to improving the stability of the light-emitting device O.

[0261] In some embodiments, referring to FIGS. 8 and 11, the pixel driving circuit Q further includes a first reset sub-circuit 60. The first reset sub-circuit 60 is coupled to the first node N1, the first reset signal line R1, and the first initialization signal line Vinit1.

[0262] The refresh frame further includes a reset phase t1, and the reset phase t1 may further include a first initialization phase t12.

[0263] In the first initialization phase t12, the first reset signal provided by the first reset signal line R1 is a low voltage signal, so that the first reset sub-circuit 60 (the first transistor T1) is controlled to be turned on to transmit a first initialization signal provided by the first initialization signal line Vinit1 to the first node N1, so as to initialize the first node N1.

[0264] Based on this, it is equivalent to initializing the first node N1 in the pixel driving circuit Q before the compensation phase t2, which helps to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0265] In some examples, the first initialization signal provided by the first initialization signal line Vinit1 is a low voltage signal. Based on this, before the compensation phase, the low voltage signal is transmitted to the first node N1 to initialize the control electrode of the driving transistor T3, which helps to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0266] For example, the low voltage signal may be a signal with a voltage that is lower than the voltage Vdata of the data writing signal when the display panel 200 displays any gray scale, so as to eliminate the residual signal when displaying the previous frame of image.

[0267] In some embodiments, with continued reference to FIGS. 8 and 11, the reset phase t1 further includes a second initialization phase t13.

[0268] In the second initialization phase t13, the first reset signal provided by the first reset signal line R1 is kept as a low voltage signal, so that the first reset sub-circuit 60 (the first transistor T1) is controlled to be turned on to transmit the first initialization signal received from the first initialization signal line Vinit1 to the first node N1. In this case, a voltage of the first node N1 is the voltage of the first initialization signal. Furthermore, the first scanning signal provided by the first scanning signal line Gate1 is a low voltage signal, so that the second transistor T2 in the compensation sub-circuit 40 is controlled to be turned on to transmit the voltage of the first node N1 to the third node N3.

[0269] In addition, the driving sub-circuit 10 (the driving transistor T3) may be turned on under control of the voltage of the first node N1 to transmit the voltage of the third node N3 to the second node N2.

[0270] Based on this, the first reset signal line R1, the first scanning signal line Gate1 and the first initialization signal line Vinit1 may be used to synchronously initialize the first node N1, the second node N2 and the third node N3, which helps to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0271] In some embodiments, with continued reference to FIGS. 8 and 11, the refresh frame further includes a second reset phase t4. The second reset phase t4 is after the writing phase t3 and before the light-emitting phase t5.

[0272] In the second reset phase t4, the low voltage signal provided by the second reset signal line R2 is used to control the second reset sub-circuit 70 (the seventh transistor T7) to be turned on, so that the second initialization signal received from the second initialization signal line Vinit2 is transmitted to the light-emitting device O, so as to reset the light-emitting device O again, which is beneficial to improving the stability of the light-emitting device O.

[0273] Furthermore, the third reset signal line R3 is also used as the second reset signal line R2. In the second reset phase t4, the low voltage signal provided by the third reset signal line R3 may be used to control the third reset sub-circuit 80 (the eighth transistor T8) to be turned on, so that the first reference voltage signal received from the first reference voltage signal line Vref is transmitted to the second node N2, so as to reset the second node N2, which is beneficial to improving the stability of the driving transistor T3.

[0274] In addition, after the refresh frame in each light-emitting period F is completed, the holding frame phase is performed. In this case, the third reset signal line R3 may be used to provide a low voltage signal to control the second reset sub-circuit 70 and the third reset sub-circuit 80 to be turned on to transmit the first reference voltage signal received from the first reference voltage signal line Vref to the second node N2, so as to reset the second node N2, which may help to improve the stability of the driving transistor T3. Furthermore, the second initialization signal received from the second initialization signal line Vinit2 is transmitted to the light-emitting device O to reset the light-emitting device O to ensure that the anode voltage of each light-emitting device O is consistent at the start time of refreshing the next frame of the picture, thereby improving the uniformity of the luminance of the light-emitting device O.

[0275] In addition, in the holding frame, the first enable signal line EM1 and the second enable signal line EM2 may also be used to provide a low voltage signal to control the light-emitting control sub-circuit 20 to be turned on and cooperate with the driving sub-circuit 10 to drive the light-emitting device O to emit light.

[0276] FIG. 12 is a timing diagram of another pixel driving circuit, in accordance with some embodiments.

[0277] The description will be made by taking the pixel driving circuit Q shown in FIG. 9 as an example. That is, the description will be made by taking an example in which the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 in the pixel driving circuit Q are all N-type transistors. The following method is also applicable to the pixel driving circuit Q including N-type dual-gate transistors.

[0278] The difference from the driving method shown in FIG. 11 is that the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 in the pixel driving circuit Q that is driven referring to FIG. 11 are all P-type transistors.

[0279] However, the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 in the pixel driving circuit Q that is driven in FIG. 12 are all N-type transistors.

[0280] Based on this, effective signals of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 in the pixel driving circuit Q that is driven by the timing diagram shown in FIG. 12 are all high voltage signals. That is, the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are all be turned on under control of the high voltage signal. However, the driving method shown in FIG. 12 is consistent with the driving method shown in FIG. 11, the difference is only that the "effective signal" for controlling the turn-on of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is different. As for how to drive the pixel driving circuit in other phases, it may be combined with FIG. 11 and the above-mentioned driving method, which will not be repeated here.

[0281] FIG. 13 is a structural diagram of another array substrate, in accordance with some embodiments. In order to clearly illustrate how to set various signal lines to respond to the same signal terminal, FIG. 13 only illustrates a second scanning signal line Gate2 coupled to the first row of pixel driving circuits, a first scanning signal line Gate1 coupled to the fourth row of pixel driving circuits, and a first reset signal line R1 coupled to the seventh row of pixel driving circuits Q.

[0282] Referring to FIG. 13, some embodiments of the present disclosure provide an array substrate 100. The array substrate 100 includes a display area AA and a peripheral area SA. The peripheral region SA is located on at least one side (e.g., one side, or four sides including upper and lower sides and left and right sides) of the display area AA.

[0283] The array substrate 100 includes a substrate 01 and a pixel circuit layer 02 that is located on a side of the substrate 01. The pixel circuit layer 02 includes a plurality of pixel driving circuits Q, and the plurality of pixel driving circuits Q are arranged in multiple rows and columns.

[0284] For convenience of description, the plurality of sub-pixels Q are described in the present disclosure by taking an example in which the plurality of sub-pixels Q are arranged in a matrix.

[0285] In this case, pixel driving circuits Q arranged in a row in a first direction X may be referred to as a row of pixel driving circuits Q, and pixel driving circuits Q arranged in a column in a second direction Y may be referred to as a column of pixel driving circuits Q.

[0286] The array substrate 100 further includes a plurality of various types of signal lines to drive the pixel driving circuits Q. The plurality of various types of signal lines include a plurality of first scanning signal lines Gate1, a plurality of second scanning signal lines Gate2, and a plurality of first reset signal lines R1.

[0287] The plurality of first scanning signal lines Gate1 are located on a side of the substrate, and the plurality of first scanning signal lines Gate1 extend in the first direction X and are arranged in the second direction Y, and the second direction Y intersects with the first direction X. A first scanning signal line Gate1 is coupled to a row of pixel driving circuits Q.

[0288] The plurality of second scanning signal lines Gate2 are located on a side of the substrate, and the plurality of second scanning signal lines Gate2 extend in the first direction X and are arranged in the second direction Y. A second scanning signal line Gate2 is coupled to a row of pixel driving circuits Q.

[0289] The plurality of first reset signal lines R1 are located on a side of the substrate, and the plurality of first reset signal lines R1 extend in the first direction X and are arranged in the second direction Y. A first reset signal line R1 is coupled to a row of pixel driving circuits Q.

[0290] The plurality of first scanning signal lines Gate1, the plurality of second scanning signal lines Gate2, and the plurality of first reset signal lines R1 may be controlled by using different signal terminals, respectively. However, it has found through researches that, since the signal terminals are located in the peripheral area SA, if the plurality of first scanning signal lines Gate1, the plurality of second scanning signal lines Gate2, and the plurality of first reset signal lines R1 are controlled respectively by using different signal terminals, too many signal terminals will be required to be provided in the array substrate 100, causing too much space to be occupied in the array substrate 100, i.e., causing the area of the peripheral area SA to increase, which will affect the display panel 200 to achieve a narrow bezel.

[0291] In some examples, the first direction X and the second direction Y may be substantially perpendicular to each other. In this case, an included angle between the first direction X and the second direction Y is equal to approximately 90°. For example, the included angle between the first direction X and the second direction Y is 85°, 90°, 95°, or the like.

[0292] Based on the above problems, in the array substrate 100 provided in some embodiments of the present disclosure, referring to FIG. 13, a second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits and a first scanning signal line Gate1 coupled to the (n+3)-th row of pixel driving circuits are provided to response to the control of a same control signal.

[0293] That is, a second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits and a first scanning signal line Gate1 coupled to the (n+3)-th row of pixel driving circuits are provided to be coupled to a same signal terminal, where n is a positive integer.

[0294] The first scanning signal provided by the first scanning signal line Gate1 may be used to control the second transistor T2 in the compensation sub-circuit 40 to be turned on to cooperate with the first reset sub-circuit 60 and the driving sub-circuit 10, so as to initialize the first node N1, the second node N2 and the third node N2 synchronously; then, the second scanning signal provided by the second scanning signal line Gate2 may be used to control the ninth transistor T9 in the compensation sub-circuit 40 to be turned on to cooperate with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light-emitting control sub-circuit 20 and the storage sub-circuit 50, so as to perform threshold compensation.

[0295] Based on this, the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits and the first scanning signal line Gate1 coupled to the (n+3)-th row of pixel driving circuits may be coupled to a same signal terminal. That is, when the signal terminal is used to transmit a gate signal to the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits to control the ninth transistor T9 in the compensation sub-circuit 40 in the n-th row pixel driving circuit to be turned on, the signal terminal may be used to synchronously transmit the gate signal to the first scanning signal line Gata1 coupled to the (n+3)-th row of pixel driving circuits to control the second transistor T2 in the compensation sub-circuit 40 in the (n+3)-th row of pixel driving circuits to be turned on, so that the first node N1, the second node N2 and the third node N2 in the (n+3)-th row of pixel driving circuits may be initialized before performing threshold compensation.

[0296] With such configuration, it may not only ensure the turn-on of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first scanning signal line Gate1 and the second scanning signal line Gate2, but also effectively reduce the number of signal terminals in the array substrate 100, which may be beneficial to reducing the area of the peripheral area SA, so as to facilitate the realization of a narrow bezel of the display panel 200.

[0297] In some embodiments, as shown in FIG. 13, the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits and the first reset signal line R1 coupled to the (n+6)-th row of pixel driving circuits may be set to respond to the control of a same control signal.

[0298] That is, the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits and the first reset signal line R1 coupled to the (n+6)-th row of pixel driving circuits may be set to be coupled to a same signal terminal, where n is a positive integer.

[0299] When driving the pixel driving circuit Q, it is necessary to first use the first reset signal provided by the first reset signal line R1 to control the first transistor T1 in the first reset sub-circuit to be turned on to initialize the first node N1, and then use the second scanning signal provided by the second scan signal line Gate2 to control the ninth transistor T9 in the compensation sub-circuit 40 to be turned on to cooperate with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light-emitting control sub-circuit 20 and the storage sub-circuit 50 to perform threshold compensation.

[0300] Based on this, the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits and the first reset signal line R1 coupled to the (n+6)-th row of pixel driving circuits may be set to be coupled to the same signal terminal.

[0301] That is, when the signal terminal is used to transmit a gate signal to the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits to control the ninth transistor T9 in the compensation sub-circuit 40 in the n-th row of pixel driving circuits to be turned on, the signal terminal may be used to synchronously transmit the gate signal to the first reset signal line R1 coupled to the (n+6)-th row of pixel driving circuits to control the first transistor T1 in the first reset sub-circuit in the (n+6)-th row of pixel driving circuits to be turned on, so that the first node N1 in the (n+6)-th row of pixel driving circuits may be initialized before performing threshold compensation.

[0302] With such configuration, it may not only ensure the turn-on of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first reset signal line R1 and the second scanning signal line Gate2, but also effectively reduce the number of signal terminals in the array substrate 100, which may be beneficial to reducing the area of the peripheral area SA, so as to facilitate the realization of a narrow bezel of the display panel 200.

[0303] In some embodiments, referring to FIG. 13, a first scanning signal line Gate1 coupled to the n-th row of pixel driving circuits and a first reset signal line R1 coupled to the (n+3)-th row of pixel driving circuits may be set to respond to the control of a same control signal, where n is a positive integer.

[0304] That is, the first scanning signal line Gate1 coupled to the n-th row of pixel driving circuits and the first reset signal line R1 coupled to the (n+3)-th row of pixel driving circuits may be coupled to a same signal terminal.

[0305] When driving the pixel driving circuit Q, it is necessary to first use the first reset signal provided by the first reset signal line R1 to control the first reset sub-circuit to be turned on to initialize the first node N1, and then use the first scanning signal provided by the first scanning signal line Gate1 to control the second transistor T2 in the compensation sub-circuit 40 to be turned on to cooperate with the first reset sub-circuit 60 and the driving sub-circuit 10 to initialize the first node N1, the second node N2 and the third node N3 synchronously.

[0306] Based on this, the first scanning signal line Gate1 coupled to the n-th row of pixel driving circuits and the first reset signal line R1 coupled to the (n+3)-th row of pixel driving circuits may be coupled to a same signal terminal.

[0307] That is, when the signal terminal is used to transmit a gate signal to a scanning signal line Gate1 coupled to the n-th row of pixel driving circuits to control the second transistor T2 in the compensation sub-circuit 40 in the n-th row of pixel driving circuits to be turned on, the signal terminal may be used to synchronously transmit the gate signal to the first reset signal line R1 coupled to the (n+3)-th row of pixel driving circuits to control the first transistor T1 in the first reset sub-circuit in the (n+3)-th row of pixel driving circuits to be turned on, so that the first node N1, the second node N2 and the third node N2 in the (n+3)-th row of pixel driving circuits may be initialized before performing threshold compensation.

[0308] With such configuration, it may not only ensure the turn-on of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first reset signal line R1 and the first scanning signal line Gate1, but also effectively reduce the number of signal terminals in the array substrate 100, which may be beneficial to reducing the area of the peripheral area SA, so as to facilitate the realization of a narrow bezel of the display panel 200.

[0309] In some embodiments, referring to FIG. 13, the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits, the first scanning signal line Gate1 coupled to the (n+3)-th row of pixel driving circuits, and the first reset signal line R1 coupled to the (n+6)-th row of pixel driving circuits may be set to respond to the control of a same control signal, where n is a positive integer.

[0310] When driving the pixel driving circuit Q, the first reset signal provided by the first reset signal line R1 is first required to be used to control the first reset sub-circuit to be turned on to initialize the first node N1, and then the first scanning signal provided by the first scanning signal line Gate1 is used to control the second transistor T2 in the compensation sub-circuit 40 to be turned on to cooperate with the first reset sub-circuit 60 and the driving sub-circuit 10, so as to initialize the first node N1, the second node N2 and the third node N2 synchronously; then, the second scanning signal provided by the second scanning signal line Gate2 is used to control the ninth transistor T9 in the compensation sub-circuit 40 to be turned on to cooperate with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light-emitting control sub-circuit 20 and the storage sub-circuit 50 to perform threshold compensation.

[0311] Based on this, the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits, the first scanning signal line Gate1 coupled to the (n+3)-th row of pixel driving circuits, and the first reset signal line R1 coupled to the (n+6)-th row of pixel driving circuits may be set to respond to a same control signal.

[0312] That is, when the signal terminal is used to transmit a gate signal to the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits to control the ninth transistor T9 in the compensation sub-circuit 40 in the n-th row of pixel driving circuits to be turned on, the signal terminal may be used to transmit a gate signal to a scanning signal line Gate1 coupled to the (n+3)-th row of pixel driving circuits to control the second transistor T2 in the compensation sub-circuit 40 in the (n+3)-th row of pixel driving circuits to be turned on, so that the first node N1 in the (n+3)-th row of pixel driving circuits may be initialized before performing threshold compensation; moreover, the signal terminal may be used to synchronously transmit the gate signal to the first reset signal line R1 coupled to the (n+6)-th row of pixel driving circuits to control the first transistor T1 in the first reset sub-circuit in the (n+6)-th row of pixel driving circuits to be turned on, so that each node in the (n+6)-th row of pixel driving circuits may be initialized before performing threshold compensation.

[0313] With such configuration, it may not only ensure the turn-on of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first scanning signal line Gate1, the second scanning signal line Gate2, and the first reset signal line R1 to be turned on, but also effectively reduce the number of signal terminals in the array substrate 100, which may be beneficial to reducing the area of the peripheral area SA, so as to facilitate the realization of a narrow bezel of the display panel 200.

[0314] In some examples, referring to FIG. 13, the plurality of first scanning signal lines Gate1, the plurality of second scanning signal lines Gate2, and the plurality of first reset signal lines R1 may be coupled to the same signal terminal, and the signal terminal may be a gate driver circuit 101 (e.g., a gate driver on array, GOA).

[0315] The gate driver circuit 101 is used to provide gate signals for the first scanning signal line Gate1, the second scanning signal line Gate2 and the first reset signal line R1. The first scanning signal lines Gate1, the second scanning signal lines Gate2 and the first reset signal line R1 transmit the gate signals to the corresponding coupled sub-circuit to control the turn-on and turn-off of the transistor included in the sub-circuit.

[0316] In some examples, the gate driving circuit 101 may include a plurality of shift register units 21 that are cascaded. A shift register unit may be coupled to the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits, the first scanning signal line Gate1 coupled to the (n+3)-th row of pixel driving circuits, and the first reset signal line R1 coupled to the (n+6)-th row of pixel driving circuits, so that the same shift register unit is used to drive the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits, the first scanning signal line Gate1 coupled to the (n+3)-th row of pixel driving circuits, and the first reset signal line R1 coupled to the (n+6)-th row of pixel driving circuits.

[0317] For example, a shift register 102 may be coupled to the second scanning signal line Gate2 coupled to the 1st row of pixel driving circuits, the first scanning signal line Gate1 coupled to the 4th row of pixel driving circuits, and the first reset signal line R1 coupled to the 7th row of pixel driving circuits.

[0318] Based on this, when the pixel driving circuit Q in the 1st row receives the second scanning signal provided by the second scanning signal line Gate2, the pixel driving circuit Q in the 4th row may simultaneously receive the first scanning signal provided by the first scanning signal line Gate1, and the pixel driving circuit Q in the 7th row receives the first reset signal provided by the first reset signal line R1.

[0319] Thus, each node in the pixel driving circuits Q in the 7th row and the pixel driving circuits Q in the 4th row may be initialized before performing threshold compensation.

[0320] With such configuration, it may not only ensure the turn-on of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first scanning signal line Gate1, the second scanning signal line Gate2, and the first reset signal line R1, but also effectively reduce the number of signal terminals in the array substrate 100, which may be beneficial to reducing the area of the peripheral area SA, so as to facilitate the realization of a narrow bezel of the display panel 200.

[0321] FIG. 14 is a timing diagram of yet another pixel driving circuit, in accordance with some embodiments. FIG. 15 is a timing diagram of yet another pixel driving circuit, in accordance with some embodiments.

[0322] It will be noted that in a case where the second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits, the first scanning signal line Gate1 coupled to the (n+3)-th row of pixel driving circuits, and the first reset signal line R1 coupled to the (n+6)-th row of pixel driving circuits are set to respond to the same control signal, when driving the corresponding pixel driving circuits, in the corresponding timing diagram, as shown in FIGS. 14 and 15, the pulse widths of the signals transmitted by the first scanning signal line Gate1, the second scanning signal line Gate2, and the first reset signal line R1 are equal.

[0323] The timing diagram shown in FIG. 14 is similar to the timing diagram shown in FIG. 11, and the timing diagram shown in FIG. 15 is similar to the timing diagram shown in FIG. 12. That is, the timing diagram shown in FIG. 14 may be used to drive the pixel driving circuits shown in FIGS. 8 and 11, and the timing diagram shown in FIG. 15 may be used to drive the pixel driving circuit shown in FIG. 9. As for the specific driving method, reference may be made to the above embodiments, which will not repeated here.

[0324] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and variations or substitutions that any person skilled in the art may conceive of within the technical scope disclosed by the present disclosure, should fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the protection scope of the claims.

Claims

1. A pixel driving circuit, comprising: a driving sub-circuit, a light-emitting control sub-circuit, a writing sub-circuit, a compensation sub-circuit and a storage sub-circuit, wherein the driving sub-circuit is coupled to a first node, a second node and a third node; the driving sub-circuit is configured to transmit a voltage of the second node to the third node under control of a voltage of the first node; the light-emitting control sub-circuit includes a first branch, the first branch is coupled to a first power signal line, a first enable signal line, and the second node; the first branch is configured to, in a compensation phase, cooperate with the driving sub-circuit to transmit a first power signal received from the first power signal line to the third node under control of a first enable signal from the first enable signal line; the compensation sub-circuit is coupled to a first scanning signal line, a second scanning signal line, the first node, the third node, a fourth node and a second power signal line; the compensation sub-circuit is configured to: in the compensation phase, transmit a voltage of the third node to the first node under control of a first scanning signal received from the first scanning signal line, and transmit a second power signal received from the second power signal line to the fourth node under control of a second scanning signal received from the second scanning signal line; the writing sub-circuit is coupled to a third scanning signal line, a data writing signal line and the fourth node; the writing sub-circuit is configured to, in a writing phase, transmit a data writing signal received from the data writing signal line to the fourth node under control of a third scanning signal received from the third scanning signal line; and the storage sub-circuit is coupled to the first node and the fourth node; the storage sub-circuit is configured to, in the writing phase, couple a voltage of the fourth node to the first node.

2. The pixel driving circuit according to claim 1, wherein the driving sub-circuit includes a driving transistor; a control electrode of the driving transistor is coupled to the first node, a first electrode of the driving transistor is coupled to the second node, and a second electrode of the driving transistor is coupled to the third node.

3. The pixel driving circuit according to claim 1 or 2, wherein the compensation sub-circuit includes a second transistor and a ninth transistor; wherein a control electrode of the second transistor is coupled to the first scanning signal line, a first electrode of the second transistor is coupled to the third node, and a second electrode of the second transistor is coupled to the first node; and a control electrode of the ninth transistor is coupled to the third scanning signal line, a first electrode of the ninth transistor is coupled to the second power signal line, and a second electrode of the ninth transistor is coupled to the fourth node.

4. The pixel driving circuit according to any one of claims 1 to 3, wherein the writing sub-circuit includes a fourth transistor, a control electrode of the fourth transistor is coupled to the third scanning signal line, a first electrode of the fourth transistor is coupled to the data writing signal line, and a second electrode of the fourth transistor is coupled to the fourth node.

5. The pixel driving circuit according to any one of claims 1 to 4, wherein the storage sub-circuit includes a storage capacitor, a first plate of the storage capacitor is coupled to the fourth node, and a second plate of the storage capacitor is coupled to the first node.

6. The pixel driving circuit according to any one of claims 1 to 5, wherein the light-emitting control sub-circuit further includes a second branch, the second branch is coupled to the third node, a second enable signal line and a light-emitting device; the light-emitting control sub-circuit is configured to: in a light-emitting phase, cooperate with the driving sub-circuit to transmit the first power signal received from the first power signal line to the light-emitting device under the control of the first enable signal from the first enable signal line and control of a second enable signal from the second enable signal line.

7. The pixel driving circuit according to claim 6, wherein the first branch includes a fifth transistor; a control electrode of the fifth transistor is coupled to the first enable signal line, a first electrode of the fifth transistor is coupled to the first power signal line, and a second electrode of the fifth transistor is coupled to the second node; and the second branch includes a sixth transistor; a control electrode of the sixth transistor is coupled to the second enable signal line, a first electrode of the sixth transistor is coupled to the third node, and a second electrode of the sixth transistor is coupled to the light-emitting device.

8. The pixel driving circuit according to any one of claims 1 to 7, further comprising: a first reset sub-circuit, wherein the first reset sub-circuit is coupled to the first node, a first reset signal line and a first initialization signal line; the first reset sub-circuit is configured to transmit, under control of a first reset signal received from the first reset signal line, a first initialization signal received from the first initialization signal line to the first node to reset the first node.

9. The pixel driving circuit according to claim 8, wherein the first reset sub-circuit includes a first transistor; a control electrode of the first transistor is coupled to the first reset signal line, a first electrode of the first transistor is coupled to the first initialization signal line, and a second electrode of the first transistor is coupled to the first node.

10. The pixel driving circuit according to any one of claims 1 to 9, further comprising: a second reset sub-circuit, wherein the second reset sub-circuit is coupled to a light-emitting device, a second reset signal line, and a second initialization signal line; the second reset sub-circuit is configured to transmit, under control of a second reset signal received from the second reset signal line, a second initialization signal received from the second initialization signal line to the light-emitting device to reset the light-emitting device.

11. The pixel driving circuit according to claim 10, wherein the second reset sub-circuit includes a seventh transistor; a control electrode of the seventh transistor is coupled to the second reset signal line, a first electrode of the seventh transistor is coupled to the second initialization signal line, and a second electrode of an eighth transistor is coupled to the light-emitting device.

12. The pixel driving circuit according to any one of claims 1 to 11, further comprising: a third reset sub-circuit, wherein the third reset sub-circuit is coupled to the second node, a third reset signal line and a first reference voltage signal line; the third reset sub-circuit is configured to transmit, under control of a third reset signal received from the third reset signal line, a first reference voltage signal received from the first reference voltage signal line to the second node to reset the second node.

13. The pixel driving circuit according to claim 12, wherein the third reset sub-circuit includes an eighth transistor; a control electrode of the eighth transistor is coupled to the third reset signal line, a first electrode of the eighth transistor is coupled to the first reference voltage signal line, and a second electrode of the eighth transistor is coupled to the second node.

14. The pixel driving circuit according to any one of claims 1 to 13, wherein a voltage of the first power signal is equal to a voltage of the second power signal.

15. The pixel driving circuit according to any one of claims 1 to 14, wherein the first power signal line is also used as the second power signal line.

16. The pixel driving circuit according to any one of claims 1 to 15, wherein in a case where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor, at least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is a dual-gate transistor.

17. The pixel driving circuit according to any one of claims 1 to 16, wherein in a case where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor, at least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is an N-type transistor.

18. A driving method for a pixel driving circuit, wherein the pixel driving circuit includes a driving sub-circuit, a light-emitting control sub-circuit, a writing sub-circuit, a compensation sub-circuit and a storage sub-circuit; wherein the driving sub-circuit is coupled to a first node, a second node and a third node; the light-emitting control sub-circuit includes a first branch, the first branch is coupled to a first power signal line, a first enable signal line, and the second node; the compensation sub-circuit is coupled to a first scanning signal line, a second scanning signal line, the first node, the third node, a fourth node and a second power signal line; a voltage of the first power signal is equal to a voltage of the second power signal; the writing sub-circuit is coupled to a third scanning signal line, a data writing signal line and the fourth node; and the storage sub-circuit is coupled to the first node and the fourth node; the driving method comprises: a compensation phase and a writing phase; wherein in the compensation phase, the first branch cooperates with the driving sub-circuit to transmit a first power signal received from the first power signal line to the third node under control of a first enable signal from the first enable signal line, the compensation sub-circuit transmits a voltage of the third node to the first node under control of a first scanning signal received from the first scanning signal line and transmits a second power signal received from the second power signal line to the fourth node under control of a second scanning signal received from the second scanning signal line, and the storage sub-circuit receives a voltage of the first node and a voltage of the fourth node; and in the writing phase, the writing sub-circuit transmits a data writing signal received from the data writing signal line to the fourth node under control of a third scanning signal received from the third scanning signal line, and the storage sub-circuit couples the voltage of the fourth node to the first node.

19. The driving method according to claim 18, wherein the pixel driving circuit further includes a third reset sub-circuit; the third reset sub-circuit is coupled to the second node, a third reset signal line, and a first reference voltage signal line; the driving method further comprises a first reset phase, wherein in the first reset phase, the third reset sub-circuit transmits, under control of a third reset signal received from the third reset signal line, a first reference voltage signal received from the first reference voltage signal line to the second node to reset the second node.

20. The driving method according to claim 19, wherein the pixel driving circuit further includes a first reset sub-circuit, the first reset sub-circuit is coupled to the first node, a first reset signal line and a first initialization signal line; the driving method further comprises a first initialization phase, wherein in the first initialization phase, the first reset sub-circuit transmits, under control of a first reset signal received from the first reset signal line, a first initialization signal received from the first initialization signal line to the first node to initialize the first node.

21. The driving method according to claim 20, wherein the driving method further comprises a second initialization phase; wherein in the second initialization phase, the first reset sub-circuit transmits the first initialization signal received from the first initialization signal line to the first node under the control of the first reset signal received from the first reset signal line; the compensation sub-circuit transmits the voltage of the first node to the third node under control of the first scanning signal received from the first scanning signal line; and the driving sub-circuit transmits a voltage of the second node to the third node under control of the voltage of the first node, so as to initialize the first node, the second node, and the third node.

22. An array substrate, comprising a substrate and a plurality of pixel driving circuits each according to any one of claims 1 to 21, wherein the plurality of pixel driving circuits are located on the substrate.

23. The array substrate according to claim 22, wherein the plurality of pixel driving circuits are arranged in multiple rows and columns; the array substrate further comprises: a plurality of first scanning signal lines located on a side of the substrate, the plurality of first scanning signal lines all extending in a first direction and being arranged in a second direction, the second direction intersecting the first direction; a plurality of second scanning signal lines located on the side of the substrate, the plurality of second scanning signal lines all extending in the first direction and being arranged in the second direction; a plurality of first reset signal lines located on the side of the substrate, the plurality of first reset signal lines all extending in the first direction and being arranged in the second direction; wherein a second scanning signal line coupled to an n-th row of pixel driving circuits, a first scanning signal line coupled to an (n+3)-th row of pixel driving circuits, and a first reset signal line coupled to an (n+6)-th row of pixel driving circuits respond to control of a same control signal, where n is a positive integer.

24. A display panel, comprising: a light-emitting device layer including a plurality of light-emitting devices; and the array substrate according to claim 22 or 23, wherein a pixel driving circuit is coupled to a light-emitting device.

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