Methods and systems for power control

Abstract

A method for controlling a power load associated with an electric drive system includes receiving the power load at a plurality of metal-oxide-semiconductor field- effect transistors (MOSFETs), wherein the plurality of MOSFETs is comprised of a set of high-side MOSFETs and a set of low-side MOSFETs. A first MOSFET of the set of low-side MOSFETs is switched ON based on a positive cycle of the power load. A first MOSFET of the set of high-side MOSFETs and a second MOSFET of the set of low- side MOSFETs is switched ON-and-OFF based on the positive cycle of the power load. At least one boot capacitor associated with the plurality of MOSFETs is intermittently clamped.

Description

METHODS AND SYSTEMS FOR POWER CONTROLCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This international application claims priority to and the benefit of U.S. provisional application number 63 / 517,555 filed on August 3, 2023. The disclosure of the above application is incorporated herein by reference in its entirety.FIELD

[0002] The present disclosure relates to controlling power within an electric drive system.BACKGROUND

[0003] The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

[0004] Electric vehicles, which can include ground and aerial vehicles, are generally powered by an electric power system that provides power to an electric drive system having electric motors and to one or more power buses for powering additional devices of the electric vehicle. In some current architectures used for an electric power system, the current electric drive systems can require design customization for every model, which can result in slower component development and non-scalable electric power systems that can limit opportunities for simple upgrades. Furthermore, some current architectures use filtering units that can add size and weight to the overall system. The present disclosure addresses these and other issues related to electric power systems.SUMMARY

[0005] This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features.

[0006] The present disclosure provides a method for controlling a power load or supply associated with an electric drive system or a battery charging system comprising a plurality of electric powertrain modules configured as smart integrated modules (SIMs), the method comprising: providing each SIM with a digital controller configured to collect local measurements of the associated SIM, and sending signals to a string or a motor digital controller; providing each SIM with a controller area network transceiver configured to communicate between a SIM digital controller, andthe string or the motor digital controller; providing each SIM with a bi-directional DC- DC converter or a uni-directional DC-DC converter configured to supply a regulated DC output voltage to the one or more system auxiliary loads; providing each SIM with a bi-directional DC-AC inverter configured to receive a power load or supply at a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein the plurality of MOSFETs comprises of a set of high-side MOSFETs and a set of low-side MOSFETs; turning ON, based on a positive cycle of the power load, a first MOSFET of the set of low-side MOSFETs; switching ON-and-OFF, based on the positive cycle of the power load, a first MOSFET of the set of high-side MOSFETs and a second MOSFET of the set of low-side MOSFETs; and intermittently clamping, based on the first MOSFET of the set of low-side MOSFETs being turned ON and switching ON- and-OFF the first MOSFET of the set of high-side MOSFETs and the second MOSFET of the set of low-side MOSFETs, at least one boot capacitor associated with the plurality of MOSFETs, wherein the intermittent clamping provides for the at least one boot capacitor to remain above a lower threshold; wherein the first MOSFET of the set of high-side MOSFETs is ON when the second MOSFET of the set of low side MOSFETs is OFF and the first MOSFET of the set of high-side MOSFETs is OFF when the second MOSFET of the set of low side MOSFETs is ON; wherein the first MOSFET of the set of low-side MOSFETs remains on at a low frequency; wherein the switching ON-and-OFF of the first MOSFET of the set of high-side MOSFETs and the second MOSFET of the set of low-side MOSFETs is switched at a high frequency; further comprising: intermittently de-clamping, based on a distribution of the power load, the at least one boot capacitor associated with the plurality of MOSFETs; further comprising: determining, based on a failure of a battery module associated with the plurality of MOSFETs and the at least one boot capacitor, a fault, wherein the fault is one or more of a battery module fault, a high-side short circuit fault, a low-side short circuit fault, a high-side open circuit fault, a low-side open circuit fault, and an unknown fault; further comprising: balancing, based on an adaptive virtual resistance and a parallel connection between one or more DC-to-DC converters of the electric vehicle, output current sharing; and simultaneously balancing, based on virtual admittance and a series connection between the one or more DC-to-DC converters of the electric vehicle, output voltage sharing; further comprising: sending, to a controller area network transceiver, one or more signals, wherein the controller area network transceiver is configured to communicate with a microcontroller, and wherein themicrocontroller is connected to a primary ground shared with the plurality of MOSFETs or an inverter-side ground associated with the plurality of MOSFETs.

[0007] The present disclosure provides a system for controlling a power load associated with an electric vehicle, the system comprising: a plurality of electrically connected powertrain modules, wherein each of the plurality of electrically connected powertrain modules further comprises: a plurality of metal-oxide- semiconductor field-effect transistors (MOSFETs) configured to: receive the power load, wherein the plurality of MOSFETS is comprised of a set of high-side MOSFETS and a set of low-side MOSFETS, turn ON, based on a positive cycle of the power load, a first MOSFET of the set of low-side MOSFETS, and switch ON-and-OFF, based on the positive cycle, a first MOSFET of the set of high-side MOSFETS and a second MOSFET of the set of low-side MOSFETS; at least one boot capacitor configured to: intermittently clamp, based on the first MOSFET of the set of low-side MOSFETS being turned ON and switching ON-and-OFF the first MOSFET of the set of high-side MOSFETS and the second MOSFET of the set of low-side MOSFETS, at least one boot capacitor associated with the plurality of MOSFETS, wherein the clamping provides for the at least one boot capacitor to remain above a lower threshold; and one or more gate drivers configured to: cause based on a positive cycle of the power load, a first MOSFET of the set of low-side MOSFETS to turn ON, and cause, based on the positive cycle, a first MOSFET of the set of high-side MOSFETS and a second MOSFET of the set of low-side MOSFETS to switch ON-and-OFF; wherein the first MOSFET of the set of high-side MOSFETs is ON when the second MOSFET of the set of low side MOSFETs is OFF and the first MOSFET of the set of high-side MOSFETs is OFF when the second MOSFET of the set of low side MOSFETs is ON; wherein the first MOSFET of the set of low-side MOSFETs remains on at a low frequency; wherein the switching ON-and-OFF of the first MOSFET of the set of high- side MOSFETs and the second MOSFET of the set of low-side MOSFETs is switched at a high frequency; wherein the at least one boot capacitor is further configured to: intermittently de-clamp, based on a distribution of the power load, the at least one boot capacitor associated with the plurality of MOSFETs; wherein each of the plurality of electrically connected powertrain modules further comprises: a battery module configured to: determine, based on a failure of the battery module associated with the plurality of MOSFETs and the at least one boot capacitor, a fault, wherein the fault is one or more of a battery module fault, a high-side short circuit fault, a low-side shortcircuit fault, a high-side open circuit fault, a low-side open circuit fault, and an unknown fault; wherein each of the plurality of electrically connected powertrain modules further comprises: a control structure configured to: balance, based on an adaptive virtual resistance and a parallel connection between one or more DC-to-DC converters of the electric vehicle, output current sharing; and simultaneously balance, based on virtual admittance and a series connection between the one or more DC-to-DC converters of the electric vehicle, output voltage sharing; wherein each of the plurality of electrically connected powertrain modules further comprises: a DC-to-DC converter configured to: send, to a controller area network transceiver, one or more signals, wherein the controller area network transceiver is configured to communicate with a microcontroller, and wherein the microcontroller is connected to a primary ground shared with the plurality of MOSFETs or an inverter-side ground associated with the plurality of MOSFETs.

[0008] The present disclosure provides a method for controlling a power load associated with an electric vehicle, comprising: receiving the power load at a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein the plurality of MOSFETs is comprised of a set of high-side MOSFETs and a set of low- side MOSFETs; turning ON, based on a negative cycle of the power load, a second MOSFET of the set of low-side MOSFETs; switching ON-and-OFF, based on the negative cycle of the power load, a second MOSFET of the set of high-side MOSFETs and a first MOSFET of the set of low-side MOSFETs; and intermittently clamping, based on the second MOSFET of the set of low-side MOSFETs being turned ON and switching ON-and-OFF the send MOSFET of the set of high-side MOSFETs and the first MOSFET of the set of low-side MOSFETs, at least one boot capacitor associated with the plurality of MOSFETs, wherein the intermittent clamping provides for the at least one boot capacitor to remain above a lower threshold; wherein the second MOSFET of the set of high-side MOSFETs is ON when the first MOSFET of the set of low side MOSFETs is OFF and the second MOSFET of the set of high-side MOSFETs is OFF when the first MOSFET of the set of low side MOSFETs is ON; further comprising: intermittently de-clamping, based on a distribution of the power load, the at least one boot capacitor associated with the plurality of MOSFETs; further comprising: determining, based on a failure of a battery module associated with the plurality of MOSFETs and the at least one boot capacitor, a fault, wherein the fault is one or more of a battery module fault, a high-side short circuit fault, a low-side shortcircuit fault, a high-side open circuit fault, a low-side open circuit fault, and an unknown fault

[0009] Further areas of applicability will become apparent from the description provided herein. It should be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.DRAWINGS

[0010] In order that the disclosure may be well understood, there will now be described various forms thereof, given by way of example, reference being made to the accompanying drawings, in which:

[0011] FIG. 1 is a schematic diagram of a power conversion system in accordance with various implementations;

[0012] FIG. 2 is first embodiment of a schematic diagram of a component of the power conversion system in accordance with various implementations;

[0013] FIG. 3 is a graphical representation illustrating a system reference and carrier signals in accordance with various implementations;

[0014] FIG. 4 is second embodiment of a schematic diagram of a component of the power conversion system in accordance with various implementations;

[0015] FIG. 5 is third embodiment of a schematic diagram of a component of the power conversion system in accordance with various implementations;

[0016] FIG. 6 is further embodiment of a schematic diagram of a component of the power conversion system in accordance with various implementations;

[0017] FIG. 7 is a flowchart illustrating an example method for controlling power in an electric vehicle in accordance with various implementations; and

[0018] FIG. 8 is a flowchart illustrating another example method for controlling power in the electric vehicle in accordance with various implementations.

[0019] The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way.DETAILED DESCRIPTION

[0020] The following description is merely exemplary in nature and is not intended to limit the present disclosure, application, or uses. It should be understood that throughout the drawings, corresponding reference numerals indicate like or corresponding parts and features.

[0021] The present disclosure provides a means for controlling power of an electric vehicle. Various systems and methods associated with the controlling of power of the electric vehicle are illustrated and described in international application number PCT / US2023 / 011513, which is incorporated herein by reference in its entirety. For example, one or more of the systems and methods described herein provide a way to reduce the size and / or weight of a system (e.g., powertrain) implemented within an electric vehicle while expanding the range the electric vehicle can travel. As another example, one or more of the systems and methods allow for implementing the same electric drive system within any model of any electric vehicle, for example, within different models of an electric vehicle.

[0022] Referring to FIG. 1 , among other components, an electric power system 100 is provided in a vehicle (not shown), such as a car, an airplane, a boat, or any other electrical motorized vehicle. The electric power system 100 includes, among other components, a plurality of power control modules, configured in some examples as smart integrated modules (SIMs) 102a-102h. Each of the plurality of SIMs 102a- 102h include at least one battery module 104a-104h electrically connected to at least one powertrain module 106a-106h. While the electric power system 100 illustrated in FIG. 1 depicts a total of eight electrically connected SIMs 102a-102h, it is understood that the electric power system 100 may include additional or fewer SIMs as is necessary or desired for any application.

[0023] The plurality of SIMs 102a-102h are electrically connected to at least one bus bar. As another example, a set of SIMs of the plurality of SIMs 102a- 102h may be electrically connected to a bus bar 108a having a first voltage, such as 12V, while another set of SIMs of the plurality of SIMs 102a-102h may be electrically connected to another bus bar 108b having a second voltage different than the first voltage, such as 48V. It is understood that each of the set of SIMs of the plurality of SIMs 102a-102h and each of the bus bars 108a, 108b are included within the electric power system 100, and the bus bars can have different voltages. FIG. 1 also depicts that the AC power may feed into the electric motor and / or AC charger(s). Further, eachof the two bus bars 108a, 108b are connected to the vehicle’s auxiliary load(s). The electric power system 100 in various examples is configured to implement a singlephase, a three-phase, and / or a multi-phase application(s).

[0024] Each of the plurality of SIMs 102a-102h includes a DC-to-AC inverter, a DC-to-DC converter, an on-board DC and an on-board AC, a battery management system, and an electric controller. The DC-to-AC inverter is configured to generate AC power to a motor associated with the electric power system 100 from the battery modules. For example, the motor is an electric motor that powers the vehicle. In one embodiment, the DC-to-AC inverter is provided as a three-level inverter having power electronics composed of power electronic switches which could be a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a thyristor or a gate turn-off thyristor (GTO). The power electronic switches are operable by a power controller (not shown) to generate a desired drive power output. In one form, the DC-to-AC inverter is provided as a bidirectional inverter, where output terminals connect to one another in series and parallel configurations to provide power to the electric motor. It should be readily understood that the DC-to-AC inverter may include additional and / or other components and should not be limited to what has been described herein. For example, the DC-to-AC inverter may include filters and / or components to isolate the DC-to-AC inverter from the DC-to-DC converter.

[0025] The DC-to-DC converter is configured to generate DC power to an auxiliary load from the battery modules 104a-104h of each of the plurality of SIMs 102a-102h. The DC-to-DC converter is provided as an isolated converter having electronics such as, but not limited to, a flyback converter, half-bridge circuit, fullbridge circuit, and / or inductors and capacitor. In an embodiment, the DC-to-DC converter provides regulated DC output at 12V or 48V levels. However, the DC-to- DC converter can be configured in various suitable ways to individually or in association with other DC-to-DC converters provide auxiliary power output(s) to one or more power buses 108a, 108b, and should not be limited to the configuration illustrated in FIG. 1. In one form, the DC-to-DC converter is a bidirectional converter. It should be readily understood that the DC-to-DC converter may include additional and / or other components and should not be limited to what has been described herein. For example, the DC-to-DC converter may include filters, and / or may not include components to isolate the DC-to-DC converter from the DC-to-AC inverter.

[0026] Both of the on-board DC charger and the on-board AC charger are configured to charge the battery modules 104a-104h of each of the plurality of SIMs 102a-102h from an electric grid or any other electrical power source(s). The battery management system is configured to at least, control, monitor, and / or protect the battery modules 104a-104h of each of the plurality of SIMs 102a-102h. The electric controller(s) is configured to digitally control each of the subsystems associated with the electric power system 100 using local measurements. However, it is understood that the electric controller is configured to digitally control each of the subsystems associated with the electric power system 100 using any measurements.

[0027] Any of the aforementioned inverters disposed within each of the plurality of SIMs 102a-102h may include a gate driver and battery assembly 200 as is illustrated in FIG. 2. The gate driver and battery assembly 200 includes at least a nonisolated gate driver 202a, 202b, a bootstrap capacitor 204a, 204b, a high-side set of MOSFETs 206a, 206b and a low-side set of MOSFETs 208a, 208b. It is understood that the gate driver and battery assembly 200 may include additional and / or other components and should not be limited to the circuit configuration provided illustrated in FIG. 2.

[0028] A hybrid-frequency switching (HyFS) control scheme or method is implemented in some examples to operate the gate driver and battery assembly 200 so that the gate driver and battery assembly 200 is enabled to control ultra-high and ultra-low duty cycles associated with the auxiliary load(s). For example, the HyFS control scheme or method is implemented to operate the gate driver and battery assembly 200 so that the gate driver and battery assembly 200 is enabled to process ultra-high and ultra-low duty cycles associated with the auxiliary load(s). The HyFS provides that in the instance wherein the gate driver and battery assembly 200 operates in a positive cycle, a first low-side MOSFET 208a is configured to stay in an activated state (e.g., ON) while a second low-side MOSFET 208b and a first high-side MOSFET 206a are configured to switch ON and OFF at a high frequency. It is understood, however, that the second low-side MOSFET 208b and the first high-side MOSFET 206a are configured to switch ON and OFF at any frequency.

[0029] The HyFS also provides that in the instance wherein the gate driver and battery assembly 200 operates in a negative cycle, the second low-side MOSFET 208a is configured to stay in an activated state (e.g., ON) while the first low- side MOSFET 208b and a second high-side MOSFET 206a are configured to switchON and OFF at a high frequency. It is understood, however, that the first low-side MOSFET 208b and the second high-side MOSFET 206a are configured to switch ON and OFF at any frequency.

[0030] In various examples, because in each of the positive and the negative cycles, the low-side set of MOSFETs 208a, 208b remain in an activated state, the bootstrap capacitor 204a, 204b may deplete any stored charge therein. To mitigate this issue, the gate driver and battery assembly 200 implement a plurality of charging pulses so that the stored energy within the bootstrap capacitor 204a, 204b remains at least above a lower threshold. For example, the bootstrap capacitor 204a, 204b is clamped at a power interval as the bootstrap capacitor 204a, 204b is charged to a permissible threshold. As an alternative example, as the bootstrap capacitor 204a, 204b distributes power, the bootstrap capacitor 204a, 204b is unclamped at power intervals as the power level approaches the lower threshold.

[0031] Referring to FIG. 3, a graphical representation 300 of a reference signal 302 and a plurality of carrier signals 304a - 304d is depicted. The reference signal 302 is shown as a sinusoidal waveform representing the positive and negative status of the duty cycle entering each of the plurality of SIMs. An upward trajectory of the reference signal 302 equates to the positive cycle. A crest 306 of the reference signal 302 represents a duty cycle at 100% capacity. A downward trajectory of the reference signal 302 equates to the negative cycle. A trough 308 of the reference cycle 302 represents the duty cycle at 0% capacity. It is understood that the gate driver and battery assembly 200 may handle any load associated with any range within the duty cycle represented in FIG. 3 (i.e., 0% - 100%).

[0032] The carrier signals 304a - 304d are shown as a triangular waveform representing the clamping / unclamping of the bootstrap capacitor 204a, 204b. For example, the carrier signals 304a - 304d show that the bootstrap capacitor 204a, 204b is clamping when the triangular waveform is at an upward trajectory and that the bootstrap capacitor 204a, 204b is unclamping when the triangular waveform is at a downward trajectory. It is understood that the range of charge associated with the bootstrap capacitor 204a, 204b is limited to a lower threshold. It is further understood that the lower threshold may vary based on the particular bootstrap capacitor’s 204a, 204b association with a particular SIM of the plurality of SIMs 102a- 102h.

[0033] Any number of measures are implemented to protect an integrity of each of the plurality of SIMs 102a-102h and the associated battery modules 104a- 104h. A particular set of the measures that are implemented to protect the integrity of each of the plurality of SIMs 102a-102h and their associated battery modules 104a- 104h is now described. It is understood, however, that the particular set of the measures that are implemented to protect the integrity of each of the plurality of SIMs 102a-102h and the associated battery modules 104a-104h as is described below is a non-exhaustive list of measures. For example, the high-side set of MOSFETs 206a, 206b and the low-side set of MOSFETs 208a, 208b are configured to toggle ON and / or OFF to mitigate a fault that may arise within any of the plurality of SIMs 102a-102h. As another example, the high-side set of MOSFETs 206a, 206b and the low-side set of MOSFETs 208a, 208b may be configured to toggle ON and / or OFF to signal a particular fault in any of the plurality of SIMs 102a-102h.

[0034] In addition to the high-side set of MOSFETS 206a, 206b and the low-side set of MOSFETs 208a, 208b, each of the plurality of SIMs 102a-102h may include an extra-protection MOSFET 400, which may act as a back-up MOSFET and / or a security-sensing MOSFET, as is illustrated in FIG. 4. It is understood, however, that the extra-protection MOSFET 400 may operate in any way that is reasonable in association with the circuitry of the plurality of SIMs 102a-102h as shown in FIGS. 1 , 2, and / or 4.

[0035] For example, a battery module fault may be determined. In the instance wherein the battery module fault is determined, the affected battery module is isolated. In some examples, the high-side set of MOSFETs 206a, 206b and the low- side set of MOSFETs 204a, 204b indicates the battery module fault in one of three ways, as follows:1 )2)3)

[0036] As another example, a high side short circuit fault may be determined. In the instance wherein the high side short circuit fault is determined, the affected SIM of the plurality of SIMs 102a-102h is bypassed. In some examples, the high-side MOSFET 206a, 206b and the low-side MOSFET 204a, 204b indicates the high side short circuit fault in one of two ways, as follows:1)2)

[0037] As a further example, a low side short circuit fault may be determined. In the instance wherein the low side short circuit fault is determined, the affected SIM of the plurality of SIMs 102a-102h is bypassed. In some examples, the high-side MOSFET 206a, 206b and the low-side MOSFET 204a, 204b indicates the high side short circuit fault in one of two ways, as follows:1)2)

[0038] For example, a high side open circuit fault may be determined. In the instance wherein the high side open circuit fault is determined, the affected SIM of the plurality of SIMs 102a-102h is bypassed. In some examples, the high-side MOSFET 206a, 206b and the low-side MOSFET 204a, 204b indicates the high side short circuit fault in one of two ways, as follows:1 )

[0039] For example, a low side open circuit fault may be determined. In the instance wherein the low side open circuit fault is determined, the affected SIM of the plurality of SIMs 102a-102h is bypassed. In some examples, the high-side MOSFET 206a, 206b and the low-side MOSFET 204a, 204b indicates the high side short circuit fault in one of two ways, as follows:1 )2)

[0040] For example, in the instance wherein an unknown fault is determined, either in the high side of the circuit or the low side of the circuit, the affected SIM of the plurality of SIMs 102a-102h should also be bypassed. In someexamples, the high-side MOSFET 206a, 206b and the low-side MOSFET 204a, 204b indicates the high side short circuit fault in the following way:

[0041] A control structure 500 associated with each of the plurality of SIMs is shown in FIG. 5. The control structure 500 allows for an output power of the DC-to-DC converters of each of the plurality of SIMs 102a-102h to be shared among the electric power system 100 based on any of the needs, and / or applications, of the electric power system 100 to ultimately power the electric motor of the vehicle. It is understood that the output power of the DC-to-DC converters of each of the plurality of SIMs 102a-102h are shared among the electric power system 100 at any time to ultimately power the electric motor of the vehicle.

[0042] In various examples, the control structure 500 is configured based on an adaptive droop control theory as is shown in FIG. 5 and as is used in DC microgrid connected sources for DC-to-DC converters to allow for the DC-to-DC converters to be connected in parallel outputs or series outputs.

[0043] In an embodiment, an adaptive virtual resistance is used when the DC-to-DC converters are connected in parallel so that the output current sharing is balanced. By effect, the output power of the DC-to-DC converters is also balanced. In another embodiment, the adaptive virtual resistance is used when the DC-to-DC converters are connected in series so that the output voltage sharing is balanced. By effect, the output power of the DC-to-DC converters is also balanced. It is understood that the balancing of the current sharing and the voltage sharing may be simultaneously balanced. It is understood that the control structure 500 can utilize string controllers to coordinate power management between different SIMs of the plurality of SIMs 102a-102h. It is also understood that the control structure 500 can operate in a communication-less manner by using the DC-bus current and DC-bus voltage as reference signals for the DC-to-DC converters of each of the SIMs of the plurality of SIMs 102a-102h.

[0044] FIG. 6 illustrates an embodiment 600 wherein the DC-to-DC converter output from each of the SIMs of the plurality of SIMs 102a-102h is enabledto supply one or more integrated circuit chips on the control and the inverter sides of the respective SIM. For example, the isolated DC-to-DC converter supplies an isolated controller area network transceiver with one or more signals. The controller area network transceiver then communicates with a microcontroller that is connected to the primary ground or the inverter-side ground.

[0045] FIG. 7 is a flowchart illustrating an example method 700 for controlling a power load or a power supply. For example, the example method 700 is a method for controlling the power load or the power supply associated with an electric vehicle. At step 702, the power load or the power supply is received at a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, the plurality of MOSFETs is comprised of a set of high-side MOSFETs and a set of low- side MOSFETs. As another example, a plurality of electrically connected powertrain modules is configured as SIMs, wherein the SIMs are comprised of the plurality of MOSFETs.

[0046] At step 704, a first MOSFET of the set of low-side MOSFETs is switched ON. For example, the first MOSFET of the set of low-side MOSFETs is switched ON based on a positive cycle of the power load or the power supply. As another example, the first MOSFET of the set of low-side MOSFETs remains on at a low frequency and / or during the positive cycle and a second MOSFET of the set of high-side MOSFETs remains OFF during the positive cycle.

[0047] At step 706, a first MOSFET of the set of high-side MOSFETs and a second MOSFET of the set of low-side MOSFETs are switched ON-and-OFF. For example, the first MOSFET of the set of high-side MOSFETs and the second MOSFET of the set of low-side MOSFETs are switched ON-and-OFF based on the positive cycle. As another example, the first MOSFET of the set of high-side MOSFETs is ON when the second MOSFET of the set of low side MOSFETs is OFF and the first MOSFET of the set of high-side MOSFETs is OFF when the second MOSFET of the set of low side MOSFETs is ON. As an additional example, the switching ON-and-OFF of the first MOSFET of the set of high-side MOSFETs and the second MOSFET of the set of low-side MOSFETs is switched at a high frequency.

[0048] At step 708, at least one boot capacitor is intermittently clamped. For example, the at least one boot capacitor is associated with the plurality of MOSFETs. As another example, the intermittent clamping provides for the at least one boot capacitor to remain above a threshold (e.g., a lower threshold). As an additionalexample, the at least one boot capacitor is intermittently clamped based on the first MOSFET of the set of low-side MOSFETs being turned ON and switching ON-and- OFF the first MOSFET of the set of high-side MOSFETs and the second MOSFET of the set of low-side MOSFETs. As another example, at least one boot capacitor associated with the plurality of MOSFETs is intermittently de-clamped based on a distribution of the power load or the power supply.

[0049] In one or more embodiments, one or more gate drivers is configured to cause a first MOSFET of the set of low-side MOSFETS to switch ON. For example, the one or more gate drivers cause the first MOSFET of the set of low- side MOSFETS to switch ON based on the positive cycle of the power load or the power supply. In another one or more embodiments, the one or more gate drivers is also configured to cause the first MOSFET of the set of high-side MOSFETS and the second MOSFET of the set of low-side MOSFETs to switch ON-and-OFF. For example, the one or more gate drivers cause the first MOSFET of the set of high-side MOSFETS and the second MOSFET of the set of low-side MOSFETs to switch ON- and-OFF based on the positive cycle.

[0050] In an embodiment, a fault is determined based on a failure of a battery module associated with the plurality of MOSFETs and the at least one boot capacitor. For example, the fault is one or more of a battery module fault, a high-side short circuit fault, a low-side short circuit fault, a high-side open circuit fault, a low-side open circuit fault, an unknown fault, or a combination thereof.

[0051] In another embodiment, an output current sharing is balanced based on an adaptive virtual resistance and a parallel connection between one or more DC-to-DC converters of the electric vehicle. An output voltage sharing is simultaneously balanced based on virtual admittance and a series connection between the one or more DC-to-DC converters of the electric vehicle. It is understood that the output voltage sharing is concurrently balanced based on virtual admittance and the series connection between the one or more DC-to-DC converters of the electric vehicle

[0052] In an additional embodiment, one or more signals are sent to a controller area network transceiver. For example, the controller area network transceiver is configured to communicate with a microcontroller. As another example, the microcontroller is connected to a primary ground shared with the plurality of MOSFETs or an inverter-side ground associated with the plurality of MOSFETs.

[0053] In yet another embodiment, the switching ON-and-OFF of the first MOSFET of the set of high-side MOSFETs and the second MOSFET of the set of low- side MOSFETs is switched at a higher frequency compared to the switching frequency of the first MOSFET of the set of low-side MOSFETs, and the second MOSFET of the set high-side MOSFETs during the positive power cycle.

[0054] FIG. 8 is a flowchart illustrating an example method 800 for controlling a power load or a power supply. For example, the example method 800 is a method for controlling the power load or the power supply associated with an electric vehicle. At step 802, the power load or the power supply is received at a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, the plurality of MOSFETs is comprised of a set of high-side MOSFETs and a set of low- side MOSFETs. As another example, a plurality of electrically connected powertrain modules is configured as SIMs, wherein the SIMs are comprised of the plurality of MOSFETs.

[0055] At step 804, a second MOSFET of the set of low-side MOSFETs is switched ON. For example, the second MOSFET of the set of low-side MOSFETs is switched ON based on a negative cycle of the power load or the power supply. As another example, the second MOSFET of the set of low-side MOSFETs remains on at a low frequency and / or remains ON during the negative cycle while the first MOSFET of the set of high-side MOSFETs remains OFF.

[0056] At step 806, a second MOSFET of the set of high-side MOSFETs and a first MOSFET of the set of low-side MOSFETs are switched ON-and-OFF. For example, the second MOSFET of the set of high-side MOSFETs and the first MOSFET of the set of low-side MOSFETs are switched ON-and-OFF based on the negative cycle. As another example, the second MOSFET of the set of high-side MOSFETs is ON when the first MOSFET of the set of low side MOSFETs is OFF and the second MOSFET of the set of high-side MOSFETs is OFF when the first MOSFET of the set of low side MOSFETs is ON. As an additional example, the switching ON-and-OFF of the second MOSFET of the set of high-side MOSFETs and the first MOSFET of the set of low-side MOSFETs is switched at a higher frequency compared to the switching frequency of the second MOSFET of the set of low-side MOSFETs and the first MOSFET of the set of high-side MOSFETs during the negative cycle.

[0057] At step 808, at least one boot capacitor is intermittently clamped. For example, the at least one boot capacitor is associated with the plurality ofMOSFETs. As another example, the intermittent clamping provides for the at least one boot capacitor to remain above a threshold (e.g., a lower threshold). As an additional example, the at least one boot capacitor is intermittently clamped based on the second MOSFET of the set of low-side MOSFETs being turned ON and switching ON-and- OFF the second MOSFET of the set of high-side MOSFETs and the first MOSFET of the set of low-side MOSFETs. As another example, the at least one boot capacitor associated with the plurality of MOSFETs is intermittently de-clamped based on a distribution of the power load or power supply.

[0058] In one or more embodiments, one or more gate drivers is configured to cause a second MOSFET of the set of low-side MOSFETs to turn ON. For example, the one or more gate drivers cause the second MOSFET of the set of low-side MOSFETs to turn ON based on the negative cycle of the power load or the power supply. In another one or more embodiments, the one or more gate drivers is also configured to cause a second MOSFET of the set of high-side MOSFETs and a first MOSFET of the set of low-side MOSFETs to switch ON-and-OFF. For example, the one or more gate drivers cause the second MOSFET of the set of high-side MOSFETs and the first MOSFET of the set of low-side MOSFETs to switch ON-and- OFF based on the negative cycle of the power load or the power supply.

[0059] In an embodiment, a fault is determined based on a failure of a battery module associated with the plurality of MOSFETs and the at least one boot capacitor. For example, the fault is one or more of a battery module fault, a high-side short circuit fault, a low-side short circuit fault, a high-side open circuit fault, a low-side open circuit fault, an unknown fault, or a combination thereof.

[0060] In yet another embodiment, one or more protective measures may be implemented to protect the battery module and / or the SIMs. For example, the high-side MOSFETs or the low-side MOSFETs can be switched ON based on the fault. As another example, an additional switch connected between two MOSFET legs associated with the high-side MOSFETs or the low-side MOSFETs can be switched ON. As a further example, a series MOSFET associated with the high-side MOSFETs or the low-side MOSFETs connected between the battery module and the SIMs can be switched OFF during the fault.

[0061] In another embodiment, an output current sharing is balanced based on an adaptive virtual resistance and a parallel connection between one or more DC-to-DC converters of the electric vehicle. An output voltage sharing issimultaneously balanced based on virtual admittance and a series connection between the one or more DC-to-DC converters of the electric vehicle.

[0062] In an additional embodiment, one or more signals are sent to a controller area network transceiver. For example, the controller area network transceiver is configured to communicate with a microcontroller. As another example, the microcontroller is connected to a primary ground shared with the plurality of MOSFETs or an inverter-side ground associated with the plurality of MOSFETs.

[0063] Unless otherwise expressly indicated herein, all numerical values indicating mechanical / thermal properties, compositional percentages, dimensions and / or tolerances, or other characteristics are to be understood as modified by the word “about” or "approximately" in describing the scope of the present disclosure. This modification is desired for various reasons including industrial practice, material, manufacturing, and assembly tolerances, and testing capability.

[0064] As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B, and at least one of C.”

[0065] In this application, the term “controller” and / or “module” may refer to, be part of, or include: an Application Specific Integrated Circuit (ASIC); a digital, analog, or mixed analog / digital discrete circuit; a digital, analog, or mixed analog / digital integrated circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor circuit (shared, dedicated, or group) that executes code; a memory circuit (shared, dedicated, or group) that stores code executed by the processor circuit; other suitable hardware components (e.g., op amp circuit integrator as part of the heat flux data module) that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip.

[0066] The term memory is a subset of the term computer-readable medium. The term computer-readable medium, as used herein, does not encompass transitory electrical or electromagnetic signals propagating through a medium (such as on a carrier wave); the term computer-readable medium may therefore be considered tangible and non-transitory. Non-limiting examples of a non-transitory, tangible computer-readable medium are nonvolatile memory circuits (such as a flash memory circuit, an erasable programmable read-only memory circuit, or a mask readonly circuit), volatile memory circuits (such as a static random access memory circuitor a dynamic random access memory circuit), magnetic storage media (such as an analog or digital magnetic tape or a hard disk drive), and optical storage media (such as a CD, a DVD, or a Blu-ray Disc).

[0067] The apparatuses and methods described in this application may be partially or fully implemented by a special purpose computer created by configuring a general-purpose computer to execute one or more particular functions embodied in computer programs. The functional blocks, flowchart components, and other elements described above serve as software specifications, which can be translated into the computer programs by the routine work of a skilled technician or programmer.

[0068] The description of the disclosure is merely exemplary in nature and, thus, variations that do not depart from the substance of the disclosure are intended to be within the scope of the disclosure. Such variations are not to be regarded as a departure from the spirit and scope of the disclosure.

Claims

CLAIMSWhat is claimed is:1 . A method comprising: switching ON a first metal-oxide semiconductor field-effect transistor (MOSFET) of a set of low-side MOSFETs associated with one or more smart integrated modules (SIMs) based on a positive cycle of a power load; switching ON-and-OFF a first MOSFET of a set of high-side MOSFETs associated with the one or more SIMs and a second MOSFET of the set of low- side MOSFETs based on the positive cycle of the power load; and intermittently clamping at least one boot capacitor associated with each of the high-side MOSFETs and the low-side MOSFETs to cause the at least one boot capacitor to remain above a voltage threshold, wherein the intermittent clamping is based on the first MOSFET of the set of low-side MOSFETs being switched ON and switching ON-and-OFF the first MOSFET of the set of high-side MOSFETs and the second MOSFET of the set of low-side MOSFETs.

2. The method of claim 1 , wherein the first MOSFET of the set of high-side MOSFETs is ON when the second MOSFET of the set of low-side MOSFETs is OFF and the first MOSFET of the set of high-side MOSFETs is OFF when the second MOSFET of the set of low-side MOSFETs is ON.

3. The method of claim 1 , wherein the first MOSFET of the set of low-side MOSFETs remains ON, and the second MOSFET of the set of high-side MOSFETs remains OFF during the positive cycle of an electric drive system associated with a plurality of electric powertrain modules configured as smart integrated modules (SIMs).

4. The method of claim 1 , further comprising: intermittently de-clamping the at least one boot capacitor based on a distribution of the power load.

5. The method of claim 1 , wherein the switching ON-and-OFF of the first MOSFET of the set of high-side MOSFETs and the second MOSFET of the set of low-side MOSFETs is switched at a higher frequency compared to the switching frequency of the first MOSFET of the set of low-side MOSFETs and the second MOSFET of the set high-side MOSFETs during the positive power cycle.

6. The method of claim 1 , further comprising: switching ON a second MOSFET of the set of low-side MOSFETs based on a negative cycle of the power load; switching ON-and-OFF a second MOSFET of the set of high-side MOSFETs and a first MOSFET of the set of low-side MOSFETs based on the negative cycle of the power load; and intermittently clamping the at least one boot capacitor to cause the at least one boot capacitor to remain above the voltage threshold, wherein the intermittent clamping is based on the second MOSFET of the set of low-side MOSFETs being switched ON and switching ON-and-OFF the second MOSFET of the set of high-side MOSFETs and the first MOSFET of the set of low-side MOSFETs.

7. The method of claim 6, wherein the second MOSFET of the set of high- side MOSFETs is ON when the first MOSFET of the set of low-side MOSFETs is OFF and the second MOSFET of the set of high-side MOSFETs is OFF when the first MOSFET of the set of low-side MOSFETs is ON.

8. The method of claim 6, wherein the second MOSFET of the set of low- side MOSFETs remains ON, and the first MOSFET of the set of high-side MOSFETs remains OFF during the negative cycle.

9. The method of claim 6, further comprising: intermittently de-clamping the at least one boot capacitor based on a distribution of a power supply.

10. The method of claim 6, wherein the switching ON-and-OFF of the second MOSFET of the set of high-side MOSFETs and the first MOSFET of the set of low-side MOSFETs is switched at a higher frequency compared to the switching frequency of the second MOSFET of the set of low-side MOSFETs, and the first MOSFET of the set high-side MOSFETs during the negative power cycle.11 . The method of claim 1 , further comprising: determining a fault based on a failure of a battery module associated with each of the high-side MOSFETs and the low-side MOSFETs, wherein the fault is one or more of a battery module fault, a high-side short circuit fault, a low-side short circuit fault, a high-side open circuit fault, a low-side open circuit fault, or a combination thereof.

12. The method of claim 1 , further comprising: balancing output current sharing associated with a battery charging system comprising a plurality of electric powertrain modules configured as smart integrated modules (SIMs) based on an adaptive virtual resistance and a parallel connection between one or more DC-to-DC converters of the SIMs; and simultaneously balancing output voltage sharing associated with the SIMs based on virtual admittance and a series connection between the one or more DC-to-DC converters of the SIMs.

13. The method of claim 12, further comprising: sending, to an isolated controller area network transceiver, one or more signals, wherein the isolated controller area network transceiver is configured to communicate with a microcontroller associated with each SIM, and wherein the SIM microcontroller is connected to a primary ground shared with each of the high-side MOSFETs and the low-side MOSFETs or an inverter-side ground associated with each of the high-side MOSFETs and the low-side MOSFETs, while another ground of the isolated controller area network is connected to an output ground of a SIM DC-to-DC converter and to a common ground of a string digital controller or a motor digital controller.

14. A system comprising: a plurality of electrically connected powertrain modules configured as smart integrated modules (SIMs), wherein each of the SIMs further comprises: a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) configured to: receive a power load, wherein the plurality of MOSFETs is comprised of a set of high-side MOSFETS and a set of low-side MOSFETs, switch ON a first MOSFET of the set of low-side MOSFETs based on a positive cycle of the power load, and switch ON-and-OFF a first MOSFET of the set of high-side MOSFETS and a second MOSFET of the set of low-side MOSFETs based on the positive cycle of the power load; at least one boot capacitor configured to: intermittently clamp at least one boot capacitor associated with the plurality of MOSFETS to cause the at least one boot capacitor to remain above a voltage threshold, wherein the intermittent clamping is based on the first MOSFET of the set of low-side MOSFETs being turned ON and switching ON-and-OFF the first MOSFET of the set of high-side MOSFETS and the second MOSFET of the set of low-side MOSFETs; and one or more gate drivers configured to: cause a first MOSFET of the set of low-side MOSFETS to switch ON based on the positive cycle of the power load, and cause the first MOSFET of the set of high-side MOSFETS and the second MOSFET of the set of low-side MOSFETS to switch ON-and- OFF based on the positive cycle.

15. The system of claim 14, wherein the first MOSFET of the set of high-side MOSFETs is ON when the second MOSFET of the set of low-side MOSFETs is OFF, and the first MOSFET of the set of high-side MOSFETs is OFF when the second MOSFET of the set of low-side MOSFETs is ON.

16. The system of claim 14, wherein the first MOSFET of the set of low-side MOSFETs remains ON, and a second MOSFET of the set of high-side MOSFETs remains OFF during the positive cycle of an electric drive system associated with the SIMs.

17. The system of claim 14, wherein the at least one boot capacitor is further configured to: intermittently de-clamp the at least one boot capacitor based on a distribution of the power load.

18. The system of claim 14, wherein the switching ON-and-OFF of the first MOSFET of the set of high-side MOSFETs and the second MOSFET of the set of low-side MOSFETs is switched at a higher frequency compared to the switching frequency of the first MOSFET of the set of low-side MOSFETs and the second MOSFET of the set high-side MOSFETs during the positive power cycle.

19. A system comprising: a plurality of electrically connected powertrain modules configured as smart integrated modules (SIMs), wherein each of the SIMs further comprises: a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) configured to: receive a power load, wherein the plurality of MOSFETs is comprised of a set of high-side MOSFETS and a set of low-side MOSFETs; switch ON a second MOSFET of the set of low-side MOSFETs based on a negative cycle of the power load; switching ON-and-OFF a second MOSFET of the set of high-side MOSFETs and a first MOSFET of the set of low-side MOSFETs based on the negative cycle of the power load; and intermittently clamping at least one boot capacitor to cause the at least one boot capacitor to remain above a voltage threshold, wherein the intermittent clamping is based on the second MOSFET of the set of low-side MOSFETs being turned ON and switching ON-and-OFF thesecond MOSFET of the set of high-side MOSFETs and the first MOSFET of the set of low-side MOSFETs; and one or more gate drivers configured to: cause a second MOSFET of the set of low-side MOSFETs to turn ON based on the negative cycle of the power load, and cause a second MOSFET of the set of high-side MOSFETS and a first MOSFET of the set of low-side MOSFETS to switch ON-and-OFF based on the negative cycle.

20. The system of claim 19, wherein the second MOSFET of the set of high- side MOSFETs is ON when the first MOSFET of the set of low-side MOSFETs is OFF, and the second MOSFET of the set of high-side MOSFETs is OFF when the first MOSFET of the set of low-side MOSFETs is ON.21 . The system of claim 19, wherein the second MOSFET of the set of low- side MOSFETs remains ON, and the first MOSFET of the set of high-side MOSFETs remains OFF during the negative cycle of an electric drive system associated with the SIMs.

22. The system of claim 19, wherein the at least one boot capacitor is further configured to: intermittently de-clamp the at least one boot capacitor associated with the plurality of MOSFETs based on a distribution of the power load.

23. The system of claim 19, wherein the switching ON-and-OFF of the second MOSFET of the set of high-side MOSFETs and the first MOSFET of the set of low-side MOSFETs is switched at a higher frequency compared to the switching frequency of the second MOSFET of the set of low-side MOSFETs and the first MOSFET of the set of high-side MOSFETs during the negative power cycle.

24. The system of claim 19, wherein each of the plurality of electrically connected powertrain modules is electrically connected to one or more battery modules configured to:determine a fault based on a failure of the battery module associated with the plurality of MOSFETs and the at least one boot capacitor, wherein the fault is one or more of a battery module fault, a high-side short circuit fault, a low-side short circuit fault, a high-side open circuit fault, a low-side open circuit fault, a high side and low side short circuit fault, or a combination thereof.

25. The system of claim 24, wherein each of the battery module and the SIMs is protected from the fault by being configured to: switch ON the high-side MOSFETs or the low-side MOSFETs based on the fault; switch ON an additional switch connected between two MOSFET legs associated with the high-side MOSFETs or the low-side MOSFETs; or switch OFF a series MOSFET associated with the high-side MOSFETs or the low-side MOSFETs connected between the battery module and the SIMs during the fault.

26. The system of claim 19, wherein each of the plurality of electrically connected powertrain modules further comprises: a control structure configured to: balance output current sharing associated with an electric drive system associated with the SIMs based on an adaptive virtual resistance and a parallel connection between one or more DC-to-DC converters of the electric drive system; and simultaneously balance output voltage sharing associated with the electric drive system based on virtual admittance and a series connection between the one or more DC-to-DC converters of the electric drive system.

27. The system of claim 19, wherein each of the plurality of electrically connected powertrain modules further comprises: a DC-to-DC converter configured to: connect an output ground of the DC-to-DC converter to a secondary ground of an isolated controller area network transceiver, wherein the isolated controller area network transceiver is configured to communicate with amicrocontroller, and wherein the microcontroller is connected to a primary ground of the isolated controller area network transceiver shared with the plurality of MOSFETs or an inverter-side ground associated with the plurality of MOSFETs.

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