Circuit arrangement for DC voltage conversion and operating method for a circuit arrangement of this type

Abstract

The invention relates to a circuit arrangement for DC voltage conversion having at least two DC voltage converter units (1, 7, 9) which are connected in parallel on the output side and in series on the input side. The circuit arrangement is characterized in that the input of exactly one of the DC voltage converter units (7) has a step-down converter (8) with a step-up converter (2) connected downstream thereof. The invention further relates to an operating method for a circuit arrangement of this type.

Description

[0001] Circuit arrangement for DC voltage conversion and operating method for such a circuit arrangement

[0002] The invention relates to a circuit arrangement for DC-DC conversion comprising a plurality of DC-DC converter units connected in series on the input side and in parallel on the output side. The invention further relates to an operating method for such a circuit arrangement.

[0003] A DC / DC converter unit, also referred to as a DC (direct current) converter unit, converts an input DC voltage into an output DC voltage. To process high DC voltages in the range of several thousand volts on the input side, circuit arrangements are known in which at least two, and often more than two, DC / DC converter units are connected in series on the input side, which is also referred to as "cascaded."

[0004] The DC / DC converter units are designed to provide the same voltage on the output side and can be connected in parallel accordingly. The DC / DC converter units can provide a constant output voltage even with varying input voltages. The DC / DC converter units typically have a galvanically isolated DC / DC converter on the input side to allow the converter units to be connected in parallel on the output side.

[0005] If during operation the input voltage at the circuit arrangement becomes so high that the output voltage of the individual boost converters in the DC / DC converter units reaches their maximum permissible voltage, the output voltage of the circuit arrangement can no longer be adjusted to the desired value.

[0006] In order to process an input voltage of this magnitude with the known circuit arrangement, it is necessary to increase the number of series-connected DC / DC converter units to such an extent that the maximum input voltage, when evenly distributed among the cascaded DC / DC converter units, does not exceed the maximum input voltage of the boost converters. This maximum input voltage is limited by the maximum permissible blocking voltage of the clocked semiconductor switch in the boost converter. Semiconductor switches are generally only available up to certain technically achievable maximum permissible blocking voltages, and the price increases disproportionately as the technically achievable upper limit is approached.

[0007] However, each additional DC / DC converter unit increases the complexity and thus also the cost of the circuit arrangement, especially if an input voltage of the maximum level is only rarely reached and the working voltage is normally lower, so that an additional DC / DC converter unit is not required in normal operation.

[0008] It is an object of the present invention to provide a circuit arrangement of the type mentioned above that is capable of extending the permissible input voltage range to higher voltages with as few cascaded DC / DC converter units as possible and with as little additional component expenditure as possible. A further object is to describe an operating method for such a circuit arrangement.

[0009] This object is achieved by a circuit arrangement and an operating method having the features of the independent claim. Advantageous embodiments and further developments are the subject of the dependent claims.

[0010] A circuit arrangement according to the invention of the type mentioned at the outset is characterized in that exactly one of the DC-DC converter units has a buck converter at its input, followed by a boost converter.

[0011] If, in such a circuit arrangement, the input voltage exceeds the sum of the intermediate circuit voltages of the DC-DC converters, the buck converter is operated in a clocked manner, just such that its output voltage, i.e. the input voltage for the boost converter, essentially corresponds to the intermediate circuit voltage required to provide a desired output voltage.

[0012] From the input voltage, a voltage drop of a magnitude is thus created on the input side of the buck converter, so that the remaining differential voltage is equal to (N-1) times the desired intermediate circuit voltage, where N is the number of DC-DC converter units present. As a result, the intermediate circuit voltage is also present at the input of each of the additional DC-DC converter units (i.e., those without a buck converter), so that the desired output voltage can also be provided by these additional DC / DC converter units.

[0013] Thus, by using a single upstream buck converter unit, it can be ensured that all intermediate circuit voltages do not exceed the specified maximum voltage. It is sufficient to provide only one buck converter unit with one of the DC-DC converter units. The effort required to provide a buck converter is significantly lower than having to add one or more additional DC-DC converter units to process the higher input voltage through cascading.

[0014] In a further advantageous embodiment of the circuit arrangement, the buck converter and the boost converter have variable voltage transformation ratios. To enable parallel connection of the DC-DC converter units on the output side, they each have a galvanically isolating DC-DC converter, which preferably comprises a transformer. The galvanically isolating DC-DC converter can have a fixed voltage transformation ratio.

[0015] In a further advantageous embodiment of the circuit arrangement, the DC-DC converter units, which do not have a buck converter at their input, have a boost converter on the input side, which preferably has a variable voltage transformation ratio. A DC link capacitor is further preferably connected in parallel with the output of the boost converter.

[0016] In a further advantageous embodiment of the circuit arrangement, at least two DC-DC converter units are provided, which do not have a buck converter at their input, but whose boost converters are connected in series with each other on the input side and with a shared coil. This embodiment is structurally simpler and more cost-effective to implement than if each DC-DC converter unit were provided with a coil. Preferably, an input capacitor is connected in parallel with the series circuit.

[0017] Alternatively, in a further advantageous embodiment of the circuit arrangement, the DC-DC converter units that do not have a buck converter at their input have an intermediate circuit capacitor on the input side. The other DC-DC converter units (i.e., those that do not have a buck converter) are thus simplified in that, instead of a boost converter, they only have a simplified input stage comprising only an intermediate circuit capacitor. This can save costs; however, due to the lack of a boost function in the simplified DC-DC converter units, they cannot boost an input voltage that is too low to the intermediate circuit voltage. Therefore, this simplification comes at the expense of the operating range for the input voltage.

[0018] An operating method according to the invention for such a circuit arrangement comprises the following steps: The level of the input voltage of the circuit arrangement is measured, and at least one semiconductor switch of the buck converter is permanently switched on if the input voltage falls below a predetermined threshold voltage. Furthermore, the at least one semiconductor switch of the buck converter is switched on in a clocked manner if the input voltage does not fall below the predetermined threshold voltage. This results in the advantages stated in connection with the circuit arrangement.

[0019] In an advantageous embodiment of the method, at least one semiconductor switch of the boost converter is switched on in a clocked manner when the input voltage falls below the specified threshold voltage. However, the at least one semiconductor switch of the boost converter is permanently blocked if the input voltage does not fall below the specified threshold voltage. Further advantageously, the threshold voltage corresponds to the product of the number of DC-DC converter units and the level of the intermediate circuit voltage.

[0020] The invention is explained in more detail below using exemplary embodiments and figures. The figures show:

[0021] Fig. 1 is a schematic representation of a circuit arrangement for DC voltage conversion according to the prior art in a block diagram;

[0022] Fig. 2 shows a more detailed schematic diagram of the circuit arrangement according to Fig. 1; Fig. 3 shows a schematic representation of a circuit arrangement according to the invention for DC voltage conversion in a block diagram;

[0023] Fig. 4 shows a more detailed embodiment of a circuit arrangement according to the invention for DC voltage conversion;

[0024] Fig. 5 is a flowchart of an operating method for the circuit arrangement of Fig. 4;

[0025] Fig. 6 shows a further embodiment of a circuit arrangement according to the invention for DC voltage conversion, shown in more detail; and

[0026] Fig. 7 is a flowchart of an operating method for the circuit arrangement of Fig. 6.

[0027] Fig. 1 first shows the basic principle of circuit arrangements known from the prior art for DC voltage conversion, which are suitable for a high input voltage UE.

[0028] The circuit arrangement comprises a plurality N of DC-DC converter units 1, hereinafter abbreviated to DC / DC converter units 1. In Fig. 1, the DC / DC converter units 1 are numbered from top to bottom with an index n from n=1 to n=N.

[0029] Each of the identically constructed DC / DC converter units 1 comprises a first DC / DC converter on the input side, which in this case is designed as a boost converter 2. A galvanically isolating DC / DC converter 3 is connected downstream of this. On the input side, the boost converters 2 are connected in series and connected to an input 4, to which the input voltage UE is applied. On the output side, the DC / DC converters 3 are connected in parallel and connected to a common output 6, at which an output voltage UA is provided. Despite the series-connected boost converters 2, the parallel connection of the outputs of the DC / DC converters 3 is possible due to the galvanic isolation in the DC / DC converter.

[0030] The DC / DC converters 3 generally have a fixed transmission ratio between their input and output voltage, which is largely determined by the transmission ratio of a transformer used for galvanic isolation. For a desired output voltage UA of a predetermined value, this means that the input voltage at the DC / DC converters 3 must be set to the same value for all DC / DC converters. This task is performed by the respective boost converter 2 even if the input voltage UE varies to a certain extent. The output voltage of the boost converter 2, and thus the input voltage of the DC / DC converter 3, is also referred to below as the intermediate circuit voltage Uz.

[0031] In order to be able to apply an input voltage UE of a specified size to the circuit arrangement, the input voltage of the boost converter 2 must not be greater than the intermediate circuit voltage Uz. Assuming an even distribution of the input voltage UE among all boost converters 2 due to the series connection, the input voltage UE must therefore not be greater than the number N of DC-DC converter units 1 multiplied by the level of the intermediate circuit voltage Uz. In other words, according to the state of the art, the number N of DC-DC converter units 1 must be selected such that the aforementioned condition for the maximum occurring input voltage UE is met at all times.

[0032] Even if a higher input voltage UE only occurs in temporary and rare exceptional cases during operation, the number N must be selected accordingly.

[0033] Fig. 2 shows a possible implementation of the circuit arrangement according to Fig. 1 in a more detailed circuit diagram.

[0034] Each of the boost converters 2 comprises a semiconductor switch 21, represented here by the circuit diagram of a mechanical switch with a parallel-connected freewheeling diode. In one implementation, the semiconductor switch 21 can be, in particular, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor.

[0035] The semiconductor switch 21 is arranged in a circuit with a diode 22 and an intermediate capacitor 23, to which the intermediate circuit voltage Uz is applied. An input voltage for the boost converter is applied via a coil 20 in series with the semiconductor switch 21. A special feature of the circuit shown in Fig. 2 is that not every boost converter 2 is provided with a coil, but rather the coil 20, which is shown as an example in the boost converter 2 shown at the top of Fig. 2, is also functionally effective for the boost converters 2 connected in series. Instead of the coil 20 being used jointly in this way, separate coils connected in series could also be provided. However, the arrangement shown is structurally simpler and more cost-effective.

[0036] Furthermore, an input capacitor 5 is arranged in parallel to the input 4, which reduces a pulsating current load at the input 4.

[0037] Not shown in Fig. 2 is a control unit that controls the semiconductor switches 21 of the boost converters 2 such that the respective intermediate circuit voltage Uz assumes a specific value, which leads to a desired output voltage UA. The output voltage UA can be regulated to a desired value, taking into account that all boost converters 2 transmit the same current and thus the same power at the same voltage.

[0038] As already mentioned, the DC / DC converters 3 are each designed to be galvanically isolated and for this purpose comprise a transformer 35. On the primary side, this transformer 35 is controlled by two semiconductor switches 32 in a half-bridge configuration via an oscillating circuit formed by a capacitor 33 and a coil 34. The semiconductor switches 32 are again symbolically represented as mechanical switches and, in one implementation, are, for example, MOSFETs, IGBTs, or bipolar transistors. A further half-bridge branch is formed by two capacitors 31 in the illustrated embodiment. Alternatively, the further half-bridge branch can also comprise semiconductor switches, so that a switched full bridge is formed.

[0039] On the secondary side, the transformer 35 is connected to the output 5 via a rectifier formed from rectifier diodes 36, wherein a smoothing capacitor 37 is arranged in each DC-DC converter 3.

[0040] The DC / DC converter 3 can be operated as a resonant converter or at a frequency adjacent to the resonant frequency. It is characterized in particular by a fixed voltage transformation ratio between the input voltage (i.e., the intermediate circuit voltage Uz) and the output voltage UA. Fig. 3 shows a first embodiment of a circuit arrangement according to the invention in the same way as in Fig. 1, i.e., in a block diagram. In this and the following embodiments, the same reference numerals identify elements that are identical or have the same function as in Figs. 1 and 2.

[0041] For example, a number N of DC / DC converter units 1, 7 are again provided, cascaded on the input side and connected in parallel on the output side. The three lower DC / DC converters 1 in Fig. 3, with indices n=2 to n=N, are identical to one another and also constructed analogously to the DC / DC converters 1 in Fig. 2. Accordingly, they have a boost converter 2 on the input side, followed by a galvanically isolating DC / DC converter 3 on the output side.

[0042] The DC / DC converter unit 7 shown as the topmost unit in Fig. 3 with the index n=1 also has a boost converter 2 and a DC / DC converter 3. According to the invention, a buck converter 8 is additionally provided, which is connected upstream of the boost converter 2.

[0043] If, in this exemplary embodiment, the input voltage UE exceeds the sum of the intermediate circuit voltage Uz, in this case N times the intermediate circuit voltage Uz, the buck converter 8 is clocked such that its output voltage, i.e., the input voltage for the boost converter 2, essentially corresponds to the intermediate circuit voltage Uz required to provide the desired output voltage UA. The semiconductor switch 21 of the boost converter 2, which is connected downstream of the buck converter, is accordingly constantly blocked.

[0044] From the input voltage UE, a voltage UEI drops on the input side of the buck converter 8 at a level such that the remaining differential voltage (UE-UEI) is equal to (N-1) times the desired intermediate circuit voltage Uz. This allows the (N-1) DC / DC converter units 1 to also adjust the intermediate circuit voltage Uz, so that the output voltage UA provided by these DC / DC converter units corresponds to that of the DC / DC converter unit 7.

[0045] In summary, the upstream buck converter 8 ensures that all intermediate circuit voltages Uz do not exceed the specified maximum voltage. The effort required to provide a buck converter 8 is significantly lower than having to add one or more additional DC / DC converter units 1 to process the higher input voltage UE through cascading.

[0046] In Fig. 4, a possible implementation of the block diagram of Fig. 3 is shown as a second embodiment of a circuit arrangement according to the invention in the same way as in Fig. 2, i.e. in a more detailed circuit diagram.

[0047] As an example, four DC / DC converter units 1, 7 are again provided, cascaded on the input side and connected in parallel on the output side. The three lower DC / DC converters 1 in Fig. 4 are identical to one another and also constructed analogously to the DC / DC converters 1 in Fig. 2. For these three DC / DC converters, a common coil 20 is also assigned to the boost converters 2, analogously to Fig. 2.

[0048] The DC / DC converter unit 7, shown at the top in Fig. 4, also has a boost converter 2 and a DC / DC converter 3. According to the invention, a buck converter 8 is additionally provided, which is connected upstream of the boost converter 2. The buck converter 8 comprises an input-side semiconductor switch 81, which in turn is symbolically shown as a mechanical switch with a bypass diode connected in parallel. As explained in connection with the boost converter 2 in Fig. 2, a MOSFET, an IGBT or a bipolar transistor can be used as the semiconductor switch 81. The semiconductor switch 81 is arranged in series with a freewheeling diode 82, wherein this series connection is supplied with the input voltage of the buck converter 8 and thus of the DC / DC converter unit 7.

[0049] A separate input capacitor 5' is arranged parallel to the input of the buck converter 8. The input capacitor 5' is connected in series with the input capacitor 5, which is connected in parallel with the series connection of the boost converters 2 of the DC / DC converters 1, and is supplied with the input voltage UE of the circuit arrangement. The output of the buck converter 8 is connected to the input of the boost converter 2 of the DC / DC converter unit 7 at a center tap between the semiconductor switch 81 and the freewheeling diode 82. The boost converter 2 of this DC / DC converter unit 7 has a separate coil 20', since this boost converter 20 cannot utilize the inductance of the coil 20 assigned to the DC / DC converter units 1.If, in this exemplary embodiment, the input voltage UE exceeds the sum of the intermediate circuit voltages Uz, in this case four times the intermediate circuit voltage Uz, the buck converter 8 is clocked such that its output voltage, i.e. the voltage present across the freewheeling diode 82, essentially corresponds to the intermediate circuit voltage Uz required to provide the desired output voltage UA. A voltage of exactly the magnitude by which the input voltage UE exceeds the sum of the intermediate circuit voltages Uz, i.e. in this case four times the intermediate circuit voltage Uz, thus drops from the input voltage UE on the input side of the buck converter 8 and thus across the input capacitor 5'.For the remaining DC / DC converter units 1 designed according to the prior art, an input voltage remains at the input capacitor 5 which corresponds exactly to three times the desired intermediate circuit voltage Uz, so that the output voltage UA provided by these DC / DC converter units corresponds to that of the DC / DC converter unit 7.

[0050] In summary, the upstream buck converter unit 8 ensures that all four intermediate circuit voltages Uz do not exceed the specified maximum voltage. The effort required to provide a buck converter 8 is significantly lower than having to add one or more additional DC / DC converter units 1 to process the higher input voltage UE through cascading.

[0051] Fig. 5 shows an operating method according to the invention for the circuit arrangement according to Figs. 3 and 4 in the form of a flow chart.

[0052] After the start of the operating procedure, the level of the input voltage UE at the input 4 of the circuit arrangement is measured in a first step S1.

[0053] In a next step S2, this input voltage UE is compared with a threshold value whose level is N times the intermediate circuit voltage Uz.

[0054] If the input voltage UE is less than N times the intermediate circuit voltage Uz, the method continues in a step S3. If the input voltage UE is greater than or equal to N times the intermediate circuit voltage Uz, the method continues in a step S4. In addition, a boundary condition applies that the input voltage UE does not rise above a maximum voltage that exceeds N times the intermediate circuit voltage plus the blocking voltage of the arrangement comprising semiconductor switch 81 and freewheeling diode 82. A further query can be provided which checks whether the input voltage exceeds this maximum voltage or is approaching it. In this case, either a warning signal can be output or it can be provided to disconnect the circuit arrangement according to Fig. 4 from the input voltage source.

[0055] The two process steps S3 and S4 characterize different operating modes of the circuit arrangement. In the operating mode of process step S3, the semiconductor switch 81 of the buck converter 8 is constantly switched on. The semiconductor switches 21 of the boost converter 2 are operated with a variable pulse ratio, so that the desired intermediate circuit voltage Uz is established. The DC-DC converters 3 are operated with a fixed pulse ratio, so that the desired output voltage UA is established for the given intermediate circuit voltage.

[0056] During operation of the circuit arrangement according to method step S4, the semiconductor switch 81 of the buck converter 8 is operated with a variable pulse ratio such that the desired intermediate circuit voltage Uz is established when the boost converters 2 are inactive. The inactive boost converters 2 are characterized by the fact that their semiconductor switches 21 are constantly blocked.

[0057] Again, the DC-DC converters 3 are operated with a fixed pulse ratio in such a way that the desired output voltage UA is achieved at the given intermediate circuit voltage Uz.

[0058] The operating method shown in Fig. 5 is carried out continuously in that it branches back to step S1 and measures the input voltage UE again in order to adapt the operating mode (according to method step S3 or according to method step S4) to a changed input voltage UE if necessary.

[0059] Fig. 6 shows a modified embodiment of Fig. 4. In this embodiment, one of the DC / DC converter units 7, which is also shown here at the top in Fig. 6, is designed identically to that of the embodiment of Fig. 4.

[0060] However, the remaining DC / DC converter units are simplified in that, instead of a boost converter 2, they only have a simplified input stage 10, which includes only an intermediate circuit capacitor 101. These modified DC / DC converter units are designated by reference numeral 9.

[0061] Due to the lack of a boost function in the modified DC / DC converter units 9, these cannot boost a lower input voltage to the intermediate circuit voltage Uz. Accordingly, it is necessary that the input voltage UE does not fall below a value that corresponds to (N-1) times the intermediate circuit voltage Uz, in this case three times the intermediate circuit voltage Uz. An input voltage UE that is greater than three times but less than four times the intermediate circuit voltage Uz can be compensated for by appropriate operation of the boost converter 2. Finally, an input voltage UE that is greater than four times the intermediate circuit voltage can be compensated for by appropriate operation of the buck converter 8. The upper limit of the input voltage UE is the maximum dielectric strength in blocking operation of the arrangement comprising the semiconductor switch 81 and the freewheeling diode 82.The aforementioned arrangement of semiconductor switch 81 and freewheeling diode 82 is subjected to a voltage of magnitude UE-(N-1) ■ Uz. The maximum possible input voltage is then determined according to this relationship from the dielectric strength of the arrangement of semiconductor switch 81 and freewheeling diode 82.

[0062] Due to the fixed transformation ratio of the DC / DC converters 3, even in the modified DC / DC converter units 9, the intermediate circuit voltage Uz also follows the output voltage UA in these DC / DC converter units 9 and thus also assumes a constant value in the unregulated input stage 10, which ensures equal load distribution among the DC / DC converter units 7, 9.

[0063] In Fig. 7, analogous to Fig. 5, an operating method according to the invention for the circuit arrangement according to Fig. 6 is shown in the form of a flow chart.

[0064] After the start of the operating procedure, in a first step S1 the level of the input voltage UE at the input 4 of the circuit arrangement is again measured.

[0065] In a next step S21, this input voltage UE is compared with a threshold value whose level is N times the intermediate circuit voltage Uz. If the input voltage UE is less than this N-times the intermediate circuit voltage Uz, a second comparison is made in a step S22, in which the input voltage UE is compared with a further threshold value whose level is (N-1) times the intermediate circuit voltage Uz. If the input voltage UE is less than this further threshold value, the method branches back to step S1. Operation with the desired output voltage is not possible with such a low input voltage.

[0066] If, on the other hand, the input voltage UE exceeds the further threshold value, the method continues in a next step S3. If, on the other hand, the input voltage UE in step S21 was greater than or equal to N times the intermediate circuit voltage Uz, the method continues in a step S4. In addition, a boundary condition applies that the input voltage UE does not rise above a maximum voltage which - as explained above - results from the number of stages, the level of the intermediate circuit voltage Uz and the dielectric strength of the arrangement comprising semiconductor switch 81 and freewheeling diode 82. A further query can be provided which checks whether the input voltage exceeds this maximum voltage or is approaching it. In this case, either a warning signal can be output or it can be provided to disconnect the circuit arrangement according to Fig. 6 from the input voltage source.

[0067] The two process steps S3 and S4, in turn, characterize different operating modes of the circuit arrangement. In the operating mode of process step S3, the semiconductor switch 81 of the buck converter 8 is constantly switched on. The semiconductor switches 21 of the boost converter 2 are operated with a variable pulse ratio, so that the desired intermediate circuit voltage Uz is established. The DC-DC converters 3 can be operated with a fixed pulse ratio, so that the desired output voltage UA is established for the given intermediate circuit voltage.

[0068] During operation of the circuit arrangement according to method step S4, the semiconductor switch 81 of the buck converter 8 is operated with a variable pulse ratio such that the desired intermediate circuit voltage Uz is established when the boost converters 2 are inactive. The inactive boost converters 2 are characterized in that their semiconductor switches 21 are constantly blocked. Again, the DC / DC converters 3 are operated with a fixed pulse ratio such that the desired output voltage UA is established for the given intermediate circuit voltage Uz. As already mentioned, the DC / DC converters 3 have a substantially fixed transmission ratio between their input and output voltage, which is largely determined by the transmission ratio of the transformer 35 used for galvanic isolation.If, as in the present case, the DC / DC converters 3 are LLC converters, i.e., converters that have two inductors and a capacitor (here, capacitor 33, coil 34, and the primary coil of transformer 35), the transmission ratio of the DC / DC converters 3 can alternatively be varied to equalize the voltages of the series-connected DC / DC converter units 7, 9. For this purpose, the pulse width of the control of the semiconductor switches 32 is individually adjusted.

[0069] The operating method shown in Fig. 7 is carried out continuously in that it branches back to step S1 and measures the input voltage UE again in order to adapt the operating mode (according to method step S3 or according to method step S4) to a changed input voltage UE if necessary.

[0070] Reference symbol

[0071] 1 DC-DC converter unit (DC / DC converter unit)

[0072] 2 boost converters

[0073] 20, 20' spool

[0074] 21 semiconductor switches

[0075] 22 Diode

[0076] 23 DC link capacitor

[0077] 3 DC-DC converters (DC / DC converters)

[0078] 31 Capacitor

[0079] 32 semiconductor switches

[0080] 33 Capacitor

[0081] 34 coil

[0082] 35 Transformer

[0083] 36 Rectifier diode

[0084] 37 smoothing capacitor

[0085] 4 Entrance

[0086] 5.5' input capacitor

[0087] 6 Exit

[0088] 7 DC-DC converter unit (DC / DC converter unit)

[0089] 8 buck converters

[0090] 81 semiconductor switches

[0091] 82 freewheeling diode

[0092] 9 DC-DC converter unit (DC / DC converter unit)

[0093] UE input voltage

[0094] Uz intermediate circuit voltage

[0095] UA output voltage

[0096] S1-S4 process step

[0097] S21 , S22 Process step

Claims

Claims 1. Circuit arrangement for DC voltage conversion, comprising at least two DC voltage converter units (1 , 7, 9) connected in parallel on the output side and in series on the input side, characterized in that exactly one of the DC voltage converter units (7) has a buck converter (8) at its input, to which a boost converter (2) is connected.

2. Circuit arrangement according to claim 1, wherein the buck converter (8) and the boost converter (2) have variable voltage transformation ratios.

3. Circuit arrangement according to claim 1 or 2, wherein the DC voltage converter units (1 , 7, 9) each have a galvanically isolating DC voltage converter (3) on the output side.

4. Circuit arrangement according to claim 3, wherein the galvanically isolating DC voltage converter (3) comprises a transformer (35).

5. Circuit arrangement according to claim 3 or 4, wherein the galvanically isolating DC-DC converter (3) has a fixed voltage transfer ratio.

6. Circuit arrangement according to one of claims 1 to 5, wherein the DC voltage converter units (1) which do not have a buck converter (8) at their input have a boost converter (2) on the input side.

7. Circuit arrangement according to claim 6, wherein the boost converter (2) has a variable voltage transformation ratio.

8. Circuit arrangement according to claim 6 or 7, in which at least two DC voltage converter units (1) which do not have a buck converter (8) at their input are provided, wherein the boost converters (2) are connected in series with each other and with a common coil (20) on the input side.

9. Circuit arrangement according to claim 8, wherein an input capacitor (5) is connected in parallel to the series circuit.

10. Circuit arrangement according to one of claims 1 to 9, in which an intermediate circuit capacitor (23) is connected in parallel to the output of the boost converter (2).

11. Circuit arrangement according to one of claims 1 to 5, wherein the DC voltage converter units (1) which do not have a buck converter (8) at their input have an intermediate circuit capacitor (101) on the input side.

12. Operating method for a circuit arrangement according to one of claims 1 to 11, comprising the following steps: - Measuring the magnitude of an input voltage (UE) of the circuit arrangement; - Continuous activation of at least one semiconductor switch (81) of the buck converter (8) when the input voltage (UE) falls below a predetermined threshold voltage; and - Clocked switching of at least one semiconductor switch (81 ) of the buck converter (8) when the input voltage (UE) does not fall below the specified threshold voltage.

13. Operating method according to claim 12, wherein - at least one semiconductor switch (21) of the boost converter (2) is switched when the input voltage (UE) falls below the specified threshold voltage; and - at least one semiconductor switch (21 ) of the boost converter (2) is permanently blocked when the input voltage (UE) does not fall below the specified threshold voltage.

14. Operating method according to claim 12 or 13, wherein the circuit arrangement comprises a number of DC-DC converter units (1 , 7, 9) which are each operated with the same intermediate circuit voltage (Uz), wherein the threshold voltage corresponds to the product of the number of DC-DC converter units (1 , 7, 9) and the magnitude of the intermediate circuit voltage (Uz).

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