Radio frequency frontend circuit

Abstract

A radio frequency (RF) frontend circuit is provided. The RF frontend circuit can be provided in a wireless device to support concurrent time-division duplexing (TDD) and frequency-division duplexing (FDD) communications. Specifically, the RF frontend circuit shares multiple antennas between communicating TDD sounding reference signals (SRSs) in TDD uplink and communicating FDD signals in FDD downlink / uplink. In embodiments disclosed herein, the RF frontend circuit is configured to reduce a phase / gain jump in a downlink / uplink FDD signal while switching TDD SRS transmissions between the shared antennas. By reducing the phase / gain jump in the FDD signal during SRS transmissions, it is possible to improve error vector magnitude (EVM) and / or signal to noise ratio (SNR) of the downlink / uplink FDD signal to thereby maintain FDD throughput during FDD communications.

Description

RADIO FREQUENCY FRONTEND CIRCUITRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 594,395, filed on October 30, 2023, and U.S. provisional patent application serial number 63 / 572,664, filed on April 1 , 2024, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The technology of the disclosure relates generally to a radio frequency (RF) frontend circuit capable of supporting multiple RF bands.Background

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] A state-of-the-art mobile communication device must be able to communicate a radio frequency (RF) signal(s) in a variety of wireless communication systems, such as long-term evolution (LTE) and new radio (NR), based on a variety of transmit / receive configurations, such as multiple-input, multiple-output (MIMO), dual-connectivity (DC), and diversity receive. Moreover, the state-of-the-art mobile communication device is required to communicate the RF signal(s) across a wide range of RF spectrum that can be coarsely categorized into low band (LB), mid-high band (MHB), and ultra-high band (UHB). Conventionally, the LB refers to an RF spectrum below 1 GHz, the MHB refers to an RF spectrum between 1 and 3 GHz, and the UHB refers to an RFspectrum between 3 and 5 GHz. Among them, the MHB may be further divided into a medium band (MB) between 1 and 2 GHz and a high band (HB) between 2 and 3 GHz.

[0005] Each of the LB, MB, MHB, HB, and UHB RF spectrums can be further configured to include one or more RF bands. As an example, the LB can include RF bands 5 (Bn5), 8 (Bn8), 20 (Bn20), and 28 (Bn28), the MB can include RF bands 1 (Bn1 ), 3 (Bn3), 25 (Bn25), and 66 (Bn66), the HB can include RF bands 40 (Bn40) and 41 (Bn41), and the UHB can include RF bands 77 (n77) and 79 (n79).

[0006] In order to transmit or receive the RF signal(s) in the LTE or the NR system, the mobile communication device is required to report channel quality to a base station (e.g., eNB in LTE or gNB in NR) periodically. More specifically, in a time-division duplexing (TDD) system where channel reciprocity exists, the mobile communication device will measure channel quality (e.g., received power) of a downlink channel at all receiving antennas, and report such measurements to the base station using uplink in pre-defined, periodic uplink sounding reference signals (SRSs). Accordingly, the base station can figure out the quality of an uplink channel, such as a physical uplink shared channel (PUSCH), in each subcarrier section across the frequency domain. Moreover, thanks to channel reciprocity of TDD bands that occupy the same downlink and uplink RF frequency, the uplink SRSs can also be used by the base station to estimate channel state information and eigenmodes of a downlink channel, such as a physical downlink shared channel (PDSCH). Such estimation can help the base station determine downlink and uplink channel allocation as well as beamforming configuration for the mobile communication device. In this regard, it is mandatory for the mobile communication device to transmit the uplink SRSs on a periodic basis.

[0007] Figure 1 is a schematic diagram providing an exemplary illustration of a TDD frame(s) 10 wherein the mobile communication device can report downlink channel quality measurements in multiple SRS slots SRS0-SRS3.Herein, the TDD frame(s) 10 may be communicated in the HB (e.g., RF bands 40 (n40) and 41 (n41 )).

[0008] In this exemplary illustration, the TDD frame(s) 10 is divided into twenty orthogonal frequency division multiplexing (OFDM) slots (denoted as “0” to “19”). Among the OFDM slots, some are downlink slots (denoted as “D”), some are uplink slots (denoted as “U”), and some others are flexible slots (denoted as “F”). According to the third-generation partnership project (3GPP) standard, the mobile communication device is required to report uplink channel quality measurements in each of the flexible slots. For example, the mobile communication device will transmit SRS0, SRS1 , SRS2, and SRS3 during OFDM slots 3, 8, 13, and 18, respectively.

[0009] In addition, the mobile communication device is often required to simultaneously communicate in a frequency-division duplexing (FDD) frame(s) 12, which may not be time aligned with the TDD frame(s) 10. Herein, the FDD frame(s) 12 may be communicated in the MB (e.g., RF bands 1 (n1 ), 3 (n3), 25 (n25), and 66 (n66)).

[0010] Understandably, the variety of combinations of communication systems, transmit / receive technologies, and / or RF bands can substantially increase implementation complexity, bill-of-material (BoM) cost, and footprint of an RF frontend circuit. Moreover, given the coexistence of TDD and FDD, it is necessary to share limited resources (e.g., antennas, switches, etc.) between TDD and FDD to help reduce complexity, BoM cost, and footprint of the RF frontend circuit.

[0011] Embodiments of the disclosure relate to a radio frequency (RF) frontend circuit. The RF frontend circuit can be provided in a wireless device to support concurrent time-division duplexing (TDD) and frequency-division duplexing (FDD) communications. Specifically, the RF frontend circuit shares multiple antennas between communicating TDD sounding reference signals (SRSs) in TDD uplink and communicating FDD signals in FDD downlink / uplink.In embodiments disclosed herein, the RF frontend circuit is configured to reduce a phase / gain jump in a downlink / uplink FDD signal while switching TDD SRS transmissions between shared antennas. By reducing the phase / gain jump in the downlink / uplink FDD signal during SRS transmissions, it is possible to improve error vector magnitude (EVM) and / or signal to noise ratio (SNR) of the downlink / uplink FDD signal to thereby maintain FDD throughput during FDD communications.

[0012] In one aspect, an RF frontend circuit is provided. The RF frontend circuit includes a first antenna, a second antenna, a third antenna, and a fourth antenna. Each of the first antenna, the second antenna, the third antenna, and the fourth antenna is configured to transmit a respective one of a first SRS, a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, a third SRS slot, and a fourth SRS slot in each of multiple TDD frames. The RF frontend circuit also includes a first frontend module (FEM). The first FEM includes a first FDD transmit-receive filter coupled to the first antenna. The first FDD transmit-receive filter is configured to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively. The first FEM also includes a TDD transmit-receive filter. The TDD transmit-receive filter includes a TDD transmit filter togglable between the first antenna and the second antenna. The TDD transmit filter is configured to provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the plurality of TDD frames. The TDD transmit-receive filter also includes a TDD receive filter coupled to the first antenna. The TDD receive filter is configured to present, to the first antenna, a substantially identical impedance as the TDD transmit filter at the FDD receive frequency when the first FEM switches from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

[0013] In another aspect, an RF frontend circuit is provided. The RF frontend circuit includes a first antenna, a second antenna, a third antenna, and a fourth antenna. Each of the first antenna, the second antenna, the third antenna, andthe fourth antenna is configured to transmit a respective one of a first SRS, a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, a third SRS slot, and a fourth SRS slot in each of multiple TDD frames. The RF frontend circuit also includes a first FEM. The first FEM includes an FDD transmit-receive filter coupled to the first antenna. The FDD transmit-receive filter is configured to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively. The first FEM also includes an FDD low-noise amplifier (LNA) coupled to the FDD transmit-receive filter. The first FEM also includes an input tuning circuit coupled to the first antenna. The first FEM also includes an output tuning circuit coupled to an output of the FDD LNA. The first FEM also includes a TDD transmitreceive filter coupled to the first antenna and the second antenna. The TDD transmit-receive filter is configured to provide the first SRS to the first antenna for transmission in the first SRS slot in each of the multiple TDD frames. The TDD transmit-receive filter is also configured to provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the multiple TDD frames.

[0014] In another aspect, a wireless device is provided. The wireless device includes an RF frontend circuit. The RF frontend circuit includes a first antenna, a second antenna, a third antenna, and a fourth antenna. Each of the first antenna, the second antenna, the third antenna, and the fourth antenna is configured to transmit a respective one of a first SRS, a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, a third SRS slot, and a fourth SRS slot in each of multiple TDD frames. The RF frontend circuit also includes a first FEM. The first FEM includes a first FDD transmit-receive filter coupled to the first antenna. The first FDD transmit-receive filter is configured to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively. The first FEM also includes a TDD transmit-receive filter. The TDD transmit-receive filter includes a TDD transmit filter togglable between the first antenna and the second antenna. The TDD transmit filter is configured to provide the second SRS to the secondantenna for transmission in the second SRS slot succeeding the first SRS slot in each of the plurality of TDD frames. The TDD transmit-receive filter also includes a TDD receive filter coupled to the first antenna. The TDD receive filter is configured to present, to the first antenna, a substantially identical impedance as the TDD transmit filter at the FDD receive frequency when the first FEM switches from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

[0015] In another aspect, a wireless device is provided. The wireless device includes an RF frontend circuit. The RF frontend circuit includes a first antenna, a second antenna, a third antenna, and a fourth antenna. Each of the first antenna, the second antenna, the third antenna, and the fourth antenna is configured to transmit a respective one of a first SRS, a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, a third SRS slot, and a fourth SRS slot in each of multiple TDD frames. The RF frontend circuit also includes a first FEM. The first FEM includes an FDD transmit-receive filter coupled to the first antenna. The FDD transmit-receive filter is configured to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively. The first FEM also includes an FDD LNA coupled to the FDD transmit-receive filter. The first FEM also includes an input tuning circuit coupled to the first antenna. The first FEM also includes an output tuning circuit coupled to an output of the FDD LNA. The first FEM also includes a TDD transmit-receive filter coupled to the first antenna and the second antenna. The TDD transmit-receive filter is configured to provide the first SRS to the first antenna for transmission in the first SRS slot in each of the multiple TDD frames. The TDD transmit-receive filter is also configured to provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the multiple TDD frames.

[0016] In another aspect, a method for configuring an RF frontend circuit is provided. The method includes configuring each of a first antenna, a second antenna, a third antenna, and a fourth antenna to transmit a respective one of a first SRS, a second SRS, a third SRS, and a fourth SRS in a respective one of afirst SRS slot, a second SRS slot, a third SRS slot, and a fourth SRS slot in each of multiple TDD frames. The method also includes coupling a first FDD transmitreceive filter to the first antenna to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively. The method also includes coupling a TDD transmit filter to the second antenna to provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the multiple TDD frames. The method also includes coupling a TDD receive filter to the first antenna to present, to the first antenna, a substantially identical impedance as the TDD transmit filter at the FDD receive frequency during a switch from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

[0017] In another aspect, a method for configuring an RF frontend circuit is provided. The method includes configuring each of a first antenna, a second antenna, a third antenna, and a fourth antenna to transmit a respective one of a first SRS, a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, a third SRS slot, and a fourth SRS slot in each of multiple TDD frames. The method also includes coupling an FDD transmitreceive filter to the first antenna to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively. The method also includes coupling an FDD LNA to the FDD transmit-receive filter. The method also includes coupling an input tuning circuit to the first antenna. The method also includes coupling an output tuning circuit to an output of the FDD LNA. The method also includes coupling a TDD transmit-receive filter to the first antenna and the second antenna to provide the first SRS to the first antenna for transmission in the first SRS slot in each of the multiple TDD frames and provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the multiple TDD frames.

[0018] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0019] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0020] Figure 1 is a schematic diagram providing an exemplary illustration of a time-division duplexing (TDD) frame(s) and slots wherein a mobile communication device can report downlink channel quality measurements in multiple sounding reference signal (SRS) symbols;

[0021] Figure 2 is a schematic diagram of an exemplary existing radio frequency (RF) frontend circuit wherein a large phase / gain jump may occur at an output of a frequency-division duplexing (FDD) low-noise amplifier (LNA) while switching TDD uplink SRS transmissions between multiple antennas;

[0022] Figure 3 is a table illustrating a potential impact of the large phase / gain jump on overall FDD system throughput;

[0023] Figure 4 is a schematic diagram of an exemplary RF frontend circuit configured according to an embodiment of the present disclosure to reduce the large phase / gain jump in the existing RF frontend circuit of Figure 2;

[0024] Figure 5 is a schematic diagram providing an exemplary illustration of a high-band (HB) transmit-receive filter that can be provided in the RF frontend circuit of Figure 2 to help reduce the large phase / gain jump;

[0025] Figure 6 is a schematic diagram of an exemplary RF frontend circuit configured according to another embodiment of the present disclosure;

[0026] Figure 7 is a schematic diagram of an exemplary RF frontend circuit configured according to another embodiment of the present disclosure;

[0027] Figure 8 is a schematic diagram of an exemplary communication device wherein the RF frontend circuits of Figures 4, 6, and 7 can be provided;

[0028] Figure 9 is a flowchart of an exemplary process for configuring the RF frontend circuits of Figures 4 and 6; and

[0029] Figure 10 is a flowchart of an exemplary process for configuring the RF frontend circuit of Figure 7.Detailed Description

[0030] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0031] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an elementis referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0033] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0036] Embodiments of the disclosure relate to a radio frequency (RF) frontend circuit. The RF frontend circuit can be provided in a wireless device to support concurrent time-division duplexing (TDD) and frequency-division duplexing (FDD) communications. Specifically, the RF frontend circuit shares multiple antennas between communicating TDD sounding reference signals (SRSs) in TDD uplink and communicating FDD signals in FDD downlink / uplink. In embodiments disclosed herein, the RF frontend circuit is configured to reducea phase / gain jump in a downlink / uplink FDD signal while switching TDD SRS transmissions between shared antennas. By reducing the phase / gain jump in the downlink / uplink FDD signal during SRS transmissions, it is possible to improve error vector magnitude (EVM) and / or signal to noise ratio (SNR) of the downlink / uplink FDD signal to thereby maintain FDD throughput during FDD communications.

[0037] Before discussing the RF frontend circuit of the present disclosure, starting at Figure 4, a brief overview of an existing RF frontend circuit is first provided with reference to Figures 2 and 3 to help explain the technical problems to be solved by the RF frontend circuit of the present disclosure.

[0038] Figure 2 is a schematic diagram of an exemplary existing RF frontend circuit 14 wherein the phase / gain jump may occur at an output 16 of an FDD medium band (MB) low-noise amplifier (LNA) 18 while switching multiple TDD uplink SRS transmissions SRS0-SRS3 between multiple antennas ANT0-ANT3. The existing RF frontend circuit 14 includes a first frontend module (FEM) 20 and a second FEM 22. The first FEM 20 is coupled to the antenna ANT0 (a.k.a. first antenna) and the antenna ANTI (a.k.a. second antenna). The second FEM 22 is coupled to the antenna ANT2 (a.k.a. third antenna) and the antenna ANT3 (a.k.a. fourth antenna). The antennas ANT0-ANT3 are shared between transmitting the SRSs SRS0-SRS1 in a TDD high-band (HB), such as band 40 / 41 , and transmitting / receiving an FDD signal 24 in the FDD MB, such as band 1 / 3 / 25 / 66.

[0039] In the FDD MB, the existing RF frontend circuit 14 is configured to transmit and receive the FDD signal 24 via the first antenna ANT0, the second antenna ANT 1 , the third antenna ANT2, and the fourth antenna ANT3 based on a multiple-input multiple-output (MIMO) scheme. The existing RF frontend circuit 14 is also configured to receive the FDD signal 24 via the first antenna ANT0 based on a diversity receive (DRX) scheme. Herein, the first antenna ANT0 is coupled to the FDD MB LNA 18 (a.k.a. MB LNA) via a first FDD MB transmitreceive filter 26 (a.k.a. first FDD transmit-receive filter) configured to pass signals in MB, such as the FDD signal 24. In this regard, the first FDD MB transmitreceive filter 26 can also be called an FDD MB transmit-receive filter. Thesecond antenna ANT 1 , the third antenna ANT2, and the fourth antenna ANT3 are coupled to a second FDD MB transmit-receive filter 28 (a.k.a. second FDD transmit-receive filter), a third FDD MB transmit-receive filter 30A (a.k.a. third FDD transmit-receive filter), and a fourth FDD MB transmit-receive filter 30B (a.k.a. fourth FDD transmit-receive filter), respectively. The second FDD MB transmit-receive filter 28, the third FDD MB transmit-receive filter 30A, and the fourth FDD MB transmit-receive filter 30B are configured to pass exclusively the FDD signal 24 in the MB. More specifically, the first FDD MB transmit-receive filter 26 and the second FDD MB transmit-receive filter 28 are coupled to the first antenna ANTO and the second antenna ANTI , respectively, via a first antenna switching circuit 32, whereas the third FDD MB transmit-receive filter 30A, and the fourth FDD MB transmit-receive filter 30B are coupled to the third antenna ANT2 and the fourth antenna ANT3, respectively, via a second antenna switching circuit 34.

[0040] In the TDD HB, the existing RF frontend circuit 14 is configured to transmit the SRSO during the OFDM slot 3 in Figure 1 via the first antenna ANTO, transmit the SRS1 during the OFDM slot 8 in Figure 1 via the second antenna ANT 1 , transmit the SRS2 during the OFDM slot 13 in Figure 1 via the third antenna ANT2, and transmit the SRS3 during the OFDM slot 18 in Figure 1 via the fourth antenna ANT3. As illustrated in Figure 1 , each of the OFDM slots 3, 8, 13, and 18 is the flexible slot (F). In this regard, the existing RF frontend circuit 14 needs to switch sequentially between the first antenna ANTO, the second antenna ANT 1 , the third antenna ANT2, and the fourth antenna ANT3 based on a sequential order of the OFDM slots 3, 8, 13, 18 in the TDD frame(s) 10.

[0041] The existing RF frontend circuit 14 also includes a TDD HB transmitreceive filter 36, which is also coupled to the first antenna ANTO and the second antenna ANTI via the first antenna switching circuit 32. Herein, the TDD HB transmit-receive filter 36 is configured to provide the SRSO and the SRS1 to the first antenna ANTO and the second antenna ANTI for transmission in the OFDM slot 3 and the OFDM slot 8 in the TDD frame(s) 10, respectively. In addition, the TDD HB transmit-receive filter 36 is also configured to provide the SRS2 and theSRS3 to the third antenna ANT2 and the fourth antenna ANT3 via the second antenna switching circuit 34 for transmissions in the OFDM slots 13 and 18 in the TDD frame(s) 10, respectively.

[0042] Notably, the phase / gain jump can occur at the output 16 particularly when the existing RF frontend circuit 14 switches from transmitting the SRSO via the first antenna ANTO to transmitting the SRS1 via the second antenna ANTI . This is because, during switching from the first antenna ANTO to the second antenna ANTI , the TDD HB transmit-receive filter 36 at the first antenna ANTO is momentarily decoupled from the first FDD MB transmit-receive filter 26 to thereby cause an impedance mismatch for the first FDD MB transmit-receive filter 26 with the absence of the TDD HB transmit-receive filter 36. Such momentary impedance mismatch can result in the phase / gain jump at the output 16 of the FDD MB LNA 18 that can negatively impact the throughput of the FDD signal 24 due to EVM and / or SNR degradation in the FDD signal 24. Moreover, since each of the antennas ANT0-ANT3 is also switched between transmitting in a respective one of the SRS slots SRS0-SRS3 and transmitting / receiving in non- SRS slots (e.g., FDD TX / RX / DRX), multiple phase / gain jumps may occur at the output 16 of the FDD MB LNA 18 during each SRS cycle (SRSO^SRSI ->SRS2- SRS3).

[0043] Figure 3 is a table 38 illustrating a potential impact of the phase / gain jump at the output 16 of the FDD MB LNA 18 on the throughput of the FDD signal 24 in a specific scenario involving only the first antenna ANTO and the second antenna ANT 1 . As shown herein, the throughput of the FDD signal 24 will suffer when the phase jump is more than two degrees (2°) and / or when the gain jump is more than two decibels (2 dB). Thus, it is desirable to limit the phase jump below 2° and the gain jump below 2 dB when switching from transmitting the SRSO via the first antenna ANTO to transmitting the SRS1 via the second antenna ANTI and returning to the first antenna ANTO from the fourth antenna ANT3 at the end of each SRS cycle (SRS0->SRS1 ->SRS2->SRS3).

[0044] In this regard, Figure 4 is a schematic diagram of an exemplary RF frontend circuit 40 configured according to an embodiment of the presentdisclosure to reduce the phase / gain jump experienced in the existing RF frontend circuit 14 of Figure 2. Notably, the RF frontend circuit 40 is configured to reuse as many components and / or circuitries of the existing RF frontend circuit 14 as possible to maximize backward compatibility and minimize design changes. As such, common elements between Figures 2 and 4 are shown therein with common element numbers and will not be re-described herein.

[0045] Herein, the RF frontend circuit 40 includes a first FEM 42 and a second FEM 44. The first FEM 42 includes a first antenna switching circuit 46, which is coupled to the first antenna ANTO and the second antenna ANTI . The second FEM 44 includes a second antenna switching circuit 48, which is coupled to the third antenna ANT2, the fourth antenna ANT3, and optionally to a fifth antenna ANT4. As illustrated below, the optional fifth antenna ANT4 may be removed in some embodiments of the present disclosure.

[0046] Each of the first antenna switching circuit 46 and the second antenna switching circuit 48 can include any number and type of switches configured to provide required switching functionality in the embodiments of the present disclosure. In other words, the first antenna switching circuit 46 and the second antenna switching circuit 48 can be configured using any suitable number and type of switches based on any suitable layout without changing the operating principles of the RF frontend circuit 40.

[0047] The first FEM 42 differs from the first FEM 20 in the existing RF frontend circuit 14 in that a TDD HB transmit-receive filter 50 in the first FEM 42 replaces the TDD HB transmit-receive filter 36 in the first FEM 20. Herein, the TDD HB transmit-receive filter 50 includes a TDD HB receive filter 52 and a TDD HB transmit filter 54, which are separate from one another. Specifically, the TDD HB receive filter 52 can be coupled to the first antenna ANTO via the first antenna switching circuit 46, whereas the TDD HB transmit filter 54 can be toggled between the first antenna ANTO and the second antenna ANTI via the first antenna switching circuit 46 simultaneously.

[0048] In an embodiment, the RF frontend circuit 40 reuses the first FDD MB transmit-receive filter 26, the second FDD MB transmit-receive filter 28, the thirdFDD MB transmit-receive filter 30A, and the fourth FDD MB transmit-receive filter 30B from the existing RF frontend circuit 14 of Figure 2 to maximize component reuse and enable backward compatibility. Specifically, the first FDD MB transmit-receive filter 26 and the second FDD MB transmit-receive filter 28 are coupled to the first antenna ANTO and the second antenna ANTI , respectively, via the first antenna switching circuit 46, whereas the third FDD MB transmitreceive filter 30A and the fourth FDD MB transmit-receive filter 30B are coupled to the fifth antenna ANT4 and the fourth antenna ANT3, respectively, via the second antenna switching circuit 48.

[0049] The RF frontend circuit 40 may further include a second TDD HB receive filter 56, a third TDD HB receive filter 58, and a fourth TDD HB receive filter 60. The second TDD HB receive filter 56 is coupled to the second antenna ANTI by the first antenna switching circuit 46, whereas the third TDD HB receive filter 58 and the fourth TDD HB receive filter 60 are coupled to the third antenna ANT2 and the fourth antenna ANT3, respectively, via the second antenna switching circuit 48. In an embodiment, each of the first FDD MB transmitreceive filter 26, the second FDD MB transmit-receive filter 28, the third FDD MB transmit-receive filter 30A, and the fourth FDD MB transmit-receive filter 30B can include a respective FDD transmit filter 62T and a respective FDD receive filter 62R. In other words, each of the first FDD MB transmit-receive filter 26, the second FDD MB transmit-receive filter 28, the third FDD MB transmit-receive filter 30A, and the fourth FDD MB transmit-receive filter 30B can be a duplexer filter or a multiplexer filter. In this regard, the FDD transmit filter 62T and the FDD receive filter 62R can be configured to share a respective one of the antennas ANTO, ANTI , ANT2, ANT3 via a respective common antenna port (not shown) for each FDD TRX filter. For example, Bn1 TX, Bn1 RX, Bn3 TX, and Bn3 RX filters can share the respective one of the antennas ANTO, ANTI , ANT2, ANT3 via the antenna port.

[0050] When the RF frontend circuit 40 is switching from transmitting the SRS0 via the first antenna ANTO to transmitting the SRS1 via the second antenna ANTI , the TDD HB receive filter 52 is switched to the first antennaANTO. In one embodiment, the TDD HB receive filter 52 can be switched to the first antenna ANTO via a switch 64. The switch 64, which was opened before the RF frontend circuit 40 switched from the first antenna ANTO to the second antenna ANTI , is closed while the RF frontend circuit 40 switches from the first antenna ANTO to the second antenna ANTI . By coupling the TDD HB receive filter 52 to the first antenna ANTO via the switch 64, the TDD HB receive filter 52 can provide a similar loading to the FDD receive filter 62R in the first FDD MB transmit-receive filter 26, thus helping to reduce the phase / gain jump at the output 16 of the FDD MB LNA 18.

[0051] Figure 5 is a schematic diagram providing an exemplary illustration of the TDD HB transmit-receive filter 50 in the RF frontend circuit 40 of Figure 4. Common elements between Figures 4 and 5 are shown therein with common element numbers and will not be re-described herein.

[0052] In an embodiment, the TDD HB receive filter 52 includes an RX filter 66 and an RX matching circuit 68. Likewise, the TDD HB transmit filter 54 includes a TX filter 70 and a TX matching circuit 72. Understandably, to provide the matching impedance to the first HB transmit filter 54, the TDD HB receive filter 52 needs to have an identical, or substantially identical, impedance as the TDD HB transmit filter 54 at FDD MB transmit and receive frequencies that pass through the FDD transmit filter 62T and the FDD receive filter 62R, respectively. Herein, the impedance provided by the TDD HB receive filter 52 is considered as being substantially identical to the impedance of the TDD HB transmit filter 54 when a difference between the two impedances is less than 7%. In this regard, in an embodiment, the TDD HB receive filter 52 and the TDD HB transmit filter 54 are integrated into a single filter die to help eliminate any potential material variance. Moreover, the TDD HB receive filter 52 and the TDD HB transmit filter 54 need to have proper topology, layout, and component values. In addition, the RX matching circuit 68 and the TX matching circuit 72 must be fine-tuned to present an identical, or substantially identical, effective capacitance at the MB (e.g., bands 1 / 3 / 25 / 66) transmit and receive frequencies. Specifically, the RX matching circuit 68 and the TX matching circuit 72 must be as symmetric aspossible. At the same time, the RX matching circuit 68 and the TX matching circuit 72 must be able to compensate for the difference between RX trace (denoted as TRACERX) and TX trace (denoted as TRACETX).

[0053] With reference back to Figure 4, the first FEM 42 further includes a TDD HB LNA 74 and a TDD HB PA 76. The TDD HB LNA 74 is coupled to the TDD HB receive filter 52, thus making it possible for the RF frontend circuit to receive HB signals via the first antenna ANTO. The TDD HB PA 76 is coupled directly to the TDD HB transmit filter 54 for transmission of the SRS1 and other HB signals.

[0054] Figure 6 is a schematic diagram of an exemplary RF frontend circuit 78 configured according to another embodiment of the present disclosure. Common elements between Figures 4 and 6 are shown therein with common element numbers and will not be re-described herein.

[0055] Herein, the RF frontend circuit 78 includes a first FEM 80 and a second FEM 82. A major difference between the RF frontend circuit 40 of Figure 4 and the RF frontend circuit 78 herein is that the RF frontend circuit 78 no longer has the fifth antenna ANT4. Notably, this is made possible by making certain rearrangements in the first FEM 80 and the second FEM 82. Specifically, in the first FEM 80, an HB switch 84 is added between the TDD HB PA 76 and an input86 of the HB transmit filter 54. The HB switch 84 is also coupled to the third antenna ANT2 and the fourth antenna ANT3 via a second TDD HB transmit filter87 and the second antenna switching circuit 48. The second TDD HB transmit filter 87 and any one of the third TDD HB receive filter 58 and the fourth TDD HB receive filter 60 can be configured in the same way as the TDD HB transmitreceive filter 50 to thereby provide impedance match between the second TDD HB transmit filter 87 and the third FDD MB transmit-receive filter 30A and the fourth FDD MB transmit-receive filter 30B at MB FDD frequency and minimize phase and amplitude jumps at the third antenna ANT2 or at the fourth antenna ANT3 during switching from transmitting SRS3 to transmitting SRS4.

[0056] In an embodiment, the first FEM 80 may further include an input tuning circuit 88 and an output tuning circuit 90. In a non-limiting example, each of theinput tuning circuit 88 and the output tuning circuit 90 can be a shunt inductorcapacitor (LC) circuit. Specifically, the input tuning circuit 88 is coupled to the first antenna ANTO and the output tuning circuit 90 is coupled to the output 16 of the FDD MB LNA 18. Together, the input tuning circuit 88 and the output tuning circuit 90 can further compensate loading in MB frequency and minimize the phase / gain jump at the output 16 of the FDD MB LNA 18.

[0057] Figure 7 is a schematic diagram of an exemplary RF frontend circuit 92 configured according to another embodiment of the present disclosure.Compared to the RF frontend circuit 40 of Figure 4 and the RF frontend circuit 78 of Figure 6, the RF frontend circuit 92 involves a minimum amount of change from the existing RF frontend circuit 14 of Figure 2. Common elements between Figures 2, 4, 6, and 7 are shown therein with common element numbers and will not be re-described herein.

[0058] Specifically, the RF frontend circuit 92 reuses the second FEM 22 in the existing RF frontend circuit 14 of Figure 2. The RF frontend circuit 92 includes a first FEM 94, which is modified from the first FEM 20 in Figure 2 by adding the input tuning circuit 88 and the output tuning circuit 90 from Figure 6. Herein, the TDD HB transmit-receive filter 36 is coupled to the first antenna ANTO and the second antenna ANTI via the first antenna switching circuit 32. Accordingly, the TDD HB transmit-receive filter 36 is configured to provide the SRS0 and the SRS1 to the first antenna ANTO and the second antenna ANTI for transmission during the OFDM slot 3 and the OFDM slot 8, respectively, in the TDD frame(s) 10 of Figure 1 .

[0059] The RF frontend circuit 40 of Figure 4, the RF frontend circuit 78 of Figure 6, and the RF frontend circuit 92 of Figure 7 can be provided in a communication device to support the embodiments described above. In this regard, Figure 8 is a schematic diagram of an exemplary communication device 100 wherein the RF frontend circuit 40 of Figure 2, the RF frontend circuit 78 of Figure 6, and the RF frontend circuit 92 of Figure 7 can be provided.

[0060] Herein, the communication device 100 can be any type of communication device, such as mobile terminal, smart watch, tablet, computer,navigation device, access point, base station (e.g., eNB, gNB, etc.), and any other wireless communication device that supports wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 1 10, multiple antennas 112, and user interface circuitry 1 14. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing.Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0061] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0062] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a levelappropriate for transmission, and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 1 10. The multiple antennas 112 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0063] In an embodiment, each of the RF frontend circuit 40, the RF frontend circuit 78, and the RF frontend circuit 92 may be provided between the antenna switching circuitry 110 and the transmit circuitry 106 and / or between the antenna switching circuitry 110 and the receive circuitry 108. In another embodiment, each of the RF frontend circuit 40, the RF frontend circuit 78, and the RF frontend circuit 92 may be provided in the antenna switching circuitry 110. Understandably, the antennas 1 12 can include the first antenna ANT0, the second antenna ANT 1 , the third antenna ANT2, the fourth antenna ANT3. The antennas 112 may further include the fifth antenna ANT4.

[0064] The RF frontend circuit 40 of Figure 4 and the RF frontend circuit 78 of Figure 6 can each be configured according to a process. In this regard, Figure 9 is a flowchart of an exemplary process 200 for configuring the RF frontend circuit 40 of Figure 4 and the RF frontend circuit 78 of Figure 6.

[0065] Herein, the process 200 includes configuring each of the first antenna ANT0, the second antenna ANTI , the third antenna ANT2, and the fourth antenna ANT3 to transmit a respective one of the first SRS SRS0, the second SRS SRS1 , the third SRS SRS2, and the fourth SRS SRS3 in a respective one of the first SRS slot, the second SRS slot, the third SRS slot, and the fourth SRS slot in each of the TDD frames 10 (step 202). The process 200 also includes coupling the first FDD MB transmit-receive filter 26 to the first antenna ANT0 to transmit and receive the FDD signal 24 in an FDD transmit frequency and an FDD receive frequency, respectively (step 204). The process 200 also includes coupling the TDD transmit filter 54 to the second antenna ANTI to provide the second SRS SRS1 to the second antenna ANTI for transmission in the second SRS slot succeeding the first SRS slot in each of the TDD frames 10 (step 206). The process 200 also includes coupling the TDD receive filter 52 to the firstantenna ANTO to present, to the first antenna ANTO, a substantially identical impedance as the TDD transmit filter 54 at the FDD receive frequency during a switch from transmitting the first SRS SRSO from the first antenna ANTO to transmitting the second SRS SRS1 from the second antenna ANTI (step 208).

[0066] The RF frontend circuit 92 of Figure 7 can also be configured according to a process. In this regard, Figure 10 is a flowchart of an exemplary process 210 for configuring the RF frontend circuit 92 of Figure 7.

[0067] Herein, the process 210 includes configuring each of the first antenna ANTO, the second antenna ANTI , the third antenna ANT2, and the fourth antenna ANT3 to transmit a respective one of the first SRS SRSO, the second SRS SRS1 , the third SRS SRS2, and the fourth SRS SRS3 in a respective one of the first SRS slot, the second SRS slot, the third SRS slot, and the fourth SRS slot in each of the TDD frames 10 (step 212). The process 210 also includes coupling the first FDD MB transmit-receive filter 26 to the first antenna ANTO to transmit and receive the FDD signal 24 in an FDD transmit frequency and an FDD receive frequency, respectively (step 214). The process 210 also includes coupling the FDD LNA 18 to the first FDD MB transmit-receive filter 26 (step 216). The process 210 also includes coupling the input tuning circuit 88 to the first antenna ANTO (step 218). The process 210 also includes coupling the output tuning circuit 90 to the output 16 of the FDD LNA 18 (step 220). The process 210 also includes coupling the TDD HB transmit-receive filter 36 to the first antenna ANTO and the second antenna ANTI to provide the first SRS SRSO to the first antenna ANTO for transmission in the first SRS slot in each of the TDD frames 10 and provide the second SRS SRS1 to the second antenna ANTI for transmission in the second SRS slot succeeding the first SRS in each of the TDD frames 10 (step 222).

[0068] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A radio frequency (RF) frontend circuit comprising: a first antenna, a second antenna, a third antenna, and a fourth antenna each configured to transmit a respective one of a first sounding reference signal (SRS), a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, a third SRS slot, and a fourth SRS slot in each of a plurality of timedivision duplexing (TDD) frames; and a first frontend module (FEM) comprising: a first frequency division duplexing (FDD) transmit-receive filter coupled to the first antenna and configured to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively; and a TDD transmit-receive filter comprising: a TDD transmit filter togglable between the first antenna and the second antenna and configured to provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the plurality of TDD frames; and a TDD receive filter coupled to the first antenna and configured to present, to the first antenna, a substantially identical impedance as the TDD transmit filter at the FDD receive frequency when the first FEM switches from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

2. The RF frontend circuit of claim 1 , wherein the first FDD transmit-receive filter and the TDD transmit-receive filter are provided in different filter dies.

3. The RF frontend circuit of claim 1 , wherein the TDD transmit filter and the TDD receive filter are provided in a same filter die to eliminate material variance.

4. The RF frontend circuit of claim 1 , wherein: the TDD transmit filter comprises a transmit matching circuit; and the TDD receive filter comprises a receive matching circuit; wherein the transmit matching circuit and the receive matching circuit are symmetric and tuned to present a substantially identical capacitance at the FDD transmit frequency and the FDD receive frequency.

5. The RF frontend circuit of claim 1 , wherein: the TDD transmit filter comprises a transmit matching circuit; and the TDD receive filter comprises a receive matching circuit; wherein the transmit matching circuit and the receive matching circuit are asymmetric but tuned to present a substantially identical capacitance at the FDD receive frequency.

6. The RF frontend circuit of claim 1 , further comprising a second FEM coupled to the third antenna and the fourth antenna and configured to: provide the third SRS to the third antenna for transmission in the third SRS slot succeeding the second SRS slot in each of the plurality of TDD frames; and provide the fourth SRS to the fourth antenna for transmission in the fourth SRS slot succeeding the third SRS slot in each of the plurality of TDD frames.

7. The RF frontend circuit of claim 6, wherein the TDD transmit filter is further configured to forward the third SRS and the fourth SRS to the second FEM for transmission via the third antenna and the fourth antenna, respectively.

8. The RF frontend circuit of claim 6, wherein the second FEM is further configured to receive the third SRS and the fourth SRS via a high-band switch coupled to an input of the TDD transmit filter.

9. The RF frontend circuit of claim 8, wherein the second FEM further comprises: an FDD transmit-receive filter coupled to the third antenna; and a TDD receive filter coupled to the third antenna.

10. The RF frontend circuit of claim 1 , wherein: the first FEM further comprises an FDD transmit-receive filter coupled to the second antenna and configured to transmit and receive the FDD signal in the FDD transmit frequency and the FDD receive frequency; an FDD low-noise amplifier (LNA) coupled to the FDD transmit-receive filter and configured to amplify the FDD signal received via the first antenna; a TDD LNA coupled to the TDD receive filter; and a TDD power amplifier (PA) coupled to the TDD transmit filter.11 . The RF frontend circuit of claim 10, wherein the first FEM further comprises: an input tuning circuit coupled to the first antenna; and an output tuning circuit coupled to an output of the FDD LNA.

12. A radio frequency (RF) frontend circuit comprising: a first antenna, a second antenna, a third antenna, and a fourth antenna each configured to transmit a respective one of a first sounding reference signal (SRS), a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, athird SRS slot, and a fourth SRS slot in each of a plurality of timedivision duplexing (TDD) frames; and a first frontend module (FEM) comprising: a frequency division duplexing (FDD) transmit-receive filter coupled to the first antenna and configured to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively; an FDD low-noise amplifier (LNA) coupled to the FDD transmitreceive filter; an input tuning circuit coupled to the first antenna; an output tuning circuit coupled to an output of the FDD LNA; and a TDD transmit-receive filter coupled to the first antenna and the second antenna and configured to: provide the first SRS to the first antenna for transmission in the first SRS slot in each of the plurality of TDD frames; and provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the plurality of TDD frames.

13. The RF frontend circuit of claim 12, wherein the TDD transmit-receive filter is provided in a single filter die separate from the FDD transmit-receive filter.

14. A wireless device comprising a radio frequency (RF) frontend circuit, the RF frontend circuit comprises: a first antenna, a second antenna, a third antenna, and a fourth antenna each configured to transmit a respective one of a first sounding reference signal (SRS), a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, a third SRS slot, and a fourth SRS slot in each of a plurality of timedivision duplexing (TDD) frames; anda first frontend module (FEM) comprising: a first frequency division duplexing (FDD) transmit-receive filter coupled to the first antenna and configured to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively; and a TDD transmit-receive filter comprising: a TDD transmit filter togglable between the first antenna and the second antenna and configured to provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the plurality of TDD frames; and a TDD receive filter coupled to the first antenna and configured to present, to the first antenna, a substantially identical impedance as the TDD transmit filter at the FDD receive frequency when the first FEM switches from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

15. The wireless device of claim 14, wherein the first FDD transmit-receive filter and the TDD transmit-receive filter are provided in different filter dies.

16. The wireless device of claim 14, wherein the TDD transmit filter and the TDD receive filter are provided in a same filter die to eliminate material variance.

17. A wireless device comprising a radio frequency (RF) frontend circuit, the RF frontend circuit comprises: a first antenna, a second antenna, a third antenna, and a fourth antenna each configured to transmit a respective one of a first sounding reference signal (SRS), a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, athird SRS slot, and a fourth SRS slot in each of a plurality of timedivision duplexing (TDD) frames; and a first frontend module (FEM) comprising: a frequency division duplexing (FDD) transmit-receive filter coupled to the first antenna and configured to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively; an FDD low-noise amplifier (LNA) coupled to the FDD transmitreceive filter; an input tuning circuit coupled to the first antenna; an output tuning circuit coupled to an output of the FDD LNA; and a TDD transmit-receive filter coupled to the first antenna and the second antenna and configured to: provide the first SRS to the first antenna for transmission in the first SRS slot in each of the plurality of TDD frames; and provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the plurality of TDD frames.

18. A method for configuring a radio frequency (RF) frontend circuit comprising: configuring each of a first antenna, a second antenna, a third antenna, and a fourth antenna to transmit a respective one of a first sounding reference signal (SRS), a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, a third SRS slot, and a fourth SRS slot in each of a plurality of timedivision duplexing (TDD) frames; coupling a first frequency division duplexing (FDD) transmit-receive filter to the first antenna to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively;coupling a TDD transmit filter to the second antenna to provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the plurality of TDD frames; and coupling a TDD receive filter to the first antenna to present, to the first antenna, a substantially identical impedance as the TDD transmit filter at the FDD receive frequency during a switch from transmitting the first SRS from the first antenna to transmitting the second SRS from the second antenna.

19. The method of claim 18, further comprising providing the TDD transmit filter and the TDD receive filter a same filter die to eliminate material variance.

20. A method for configuring a radio frequency (RF) frontend circuit comprising: configuring each of a first antenna, a second antenna, a third antenna, and a fourth antenna to transmit a respective one of a first sounding reference signal (SRS), a second SRS, a third SRS, and a fourth SRS in a respective one of a first SRS slot, a second SRS slot, a third SRS slot, and a fourth SRS slot in each of a plurality of timedivision duplexing (TDD) frames; coupling a frequency division duplexing (FDD) transmit-receive filter to the first antenna to transmit and receive an FDD signal in an FDD transmit frequency and an FDD receive frequency, respectively; coupling an FDD low-noise amplifier (LNA) to the FDD transmit-receive filter; coupling an input tuning circuit to the first antenna; coupling an output tuning circuit to an output of the FDD LNA; and coupling a TDD transmit-receive filter to the first antenna and the second antenna to provide the first SRS to the first antenna for transmission in the first SRS slot in each of the plurality of TDDframes and provide the second SRS to the second antenna for transmission in the second SRS slot succeeding the first SRS slot in each of the plurality of TDD frames.

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