EXCHANGE ELECTRODES FOR QUANTUM ISLAND NETWORKS

Abstract

Implementation of a quantum electronic device comprising: - a substrate (10) coated with at least one semiconductor block (14), - isolation zones (15A, 15B) on either side of the semiconductor block (14), - gate electrodes (22a, 22b, 22c, 22d, 22e) positioned on regions (14A, 14B, 14C, 14D, 14E) of the semiconductor block (14), each forming a quantum island, - one or more exchange electrodes (671, 672, 673, 674, 675, 676, 677, 678) arranged around and at a distance from said semiconductor block (14), at least one of the exchange electrodes (671) being provided so as to allow modulation of a tunnel barrier between a first quantum island and a second quantum island this first exchange electrode (671) being formed of a first conducting pad passing through an insulating layer (50) covering said semiconductor block (14), said insulation zones (15A, 15B) and the gate electrodes,said first conductive pad having a so-called "lower" end disposed in contact with the first insulation zone (15A). Figure for the abbreviation: 10C.,

Description

Title of the invention: EXCHANGE ELECTRODES FOR QUANTUM ISLAND NETWORKS

[0001] TECHNICAL FIELD AND PRIOR TECHNOLOGY

[0002] The present application relates to the field of quantum electronic devices with quantum bits (also called quantum bits or "qubits" or "Qbits") formed from regions of semiconductor quantum islands and using, in addition to control gate electrodes called "front" and located above the islands, one or more exchange electrodes to allow coupling between two islands or between an island and a charge reservoir.

[0003] Quantum islands (sometimes also called quantum boxes or quantum dots) form the basic building blocks of a quantum electronic device. Quantum islands are typically formed in a region of semiconductor material in which potential wells are implemented to confine carriers, electrons or holes, in the three dimensions of space. Quantum information is then encoded via the spin of the carrier. These are then referred to as spin qubits.

[0004] Quantum devices with spin qubits formed using a semiconductor region have the advantage of allowing the fabrication of a high density of qubits and of being able to co-integrate these qubits with other components, such as transistors.

[0005] According to one approach, electrons are confined by field effect under gate electrodes similar to those of transistor structures, and information is encoded in the spin of these electrons. These so-called "front" gates are arranged above the quantum islands.

[0006] To allow improved control and to be able to achieve tunnel coupling between neighboring islands and thus to be able to modify a tunnel barrier between these neighboring quantum islands, additional electrodes, called exchange electrodes, may be provided.

[0007] Thus, the document "A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22-nm FD-SOI" by Bashir et al., IEEE SOLID-STATE CIRCUITS LETTERS, VOL. 3, 2020, provides for example an additional upper electrode formed above the grid electrodes and at the level of the first metallic level of interconnections in order to control the tunnel coupling between two adjacent islands.

[0008] The effectiveness of such an additional electrode, in terms of the potential modulation it enables, proves insufficient. This is due in particular to the excessive distance between the additional electrode located in the first level metallic and the semiconductor layer or "active zone" in which the qubits are formed.

[0009] This is also due to an electrostatic shielding effect because the grids are located in the stack between the additional electrode at the first metallic level and the active area.

[0010] The paper "A new FDSOI spin qubit platform with 40 nm effective control pitch," by T. Bédécarrats et al., IEDM 2021, also describes exchange electrodes called "J-gates" to control tunneling coupling between two adjacent quantum islands. These exchange electrodes are in the form of conductive pads arranged above and opposite the active region. Control of coupling between islands is improved by bringing the lower ends of the pads closer together, but implementing such electrodes presents cost problems and difficulties in pad positioning. It is indeed difficult to position these pads at a sufficiently small distance from the active region to improve coupling while avoiding contact with the gate electrodes and the islands themselves. A "shielding" effect from the gates persists with this configuration.

[0011] The problem arises of creating a new quantum device with one or more exchange electrodes and which is improved with respect to at least one of the disadvantages mentioned above. Description of the invention

[0012] According to one aspect, the present invention relates to a quantum electronic device comprising:

[0013] - a substrate coated with at least one semiconductor block, said semiconductor block extending mainly in a first direction, said semiconductor block comprising a semiconductor layer;

[0014] - insulation zones arranged on either side of the semiconductor layer of said semiconductor block,

[0015] - a plurality of front grids, each front grid comprising a portion extending on regions of the semiconductor layer of said semiconductor block, each of said regions forming a quantum island,

[0016] - one or more exchange electrodes, said one or more electrodes exchange electrode(s) being arranged opposite and above one of said insulation zones and each exchange electrode has a lower end in direct contact with an insulating material of this insulation zone or disposed on this insulation zone.

[0017] Such an arrangement of the exchange electrode makes it possible to get closer to the active area and consequently to the adjacent islands or the quantum island and the dopant reservoir without experiencing a screening effect from the front gates. Improved control of the A tunnel barrier between adjacent islands or between a quantum island and a dopant reservoir can then be obtained.

[0018] The production of such exchange electrodes can also be carried out without risking contact with the semiconductor block.

[0019] Advantageously, at least one front grille or each front grille comprises another part extending over one of the insulation zones.

[0020] Advantageously, at least one exchange electrode or each exchange electrode is disposed between two of said front grids.

[0021] The device may be provided with at least one first exchange electrode among said exchange electrodes extends above the first isolation zone and at a distance from a first region of said semiconductor block forming a first quantum island, the first exchange electrode being provided at a distance from a second region of said semiconductor block forming a second quantum island and so as to allow modulation of a tunnel barrier between said first quantum island and said second quantum island.

[0022] The first exchange electrode may be formed of a conductive pad, said second conductive pad having a so-called "lower" end disposed in contact with the second insulation zone or with an insulating material formed on said second insulation zone. The conductive pad typically passes through an insulating layer covering said semiconductor block and said insulation zones.

[0023] According to one possible implementation, said second region of said semiconductor block forms a second quantum island, the first exchange electrode being juxtaposed to a part of said semiconductor block arranged between said first region and said second region of said semiconductor block.

[0024] According to one possible embodiment, a second exchange electrode arranged above a second isolation zone and at a distance from said first region forms a first quantum island and from the second region forms a second quantum island so as to allow modulation of the tunnel barrier between said first quantum island and said second quantum island, said second exchange electrode being formed of a second conductive pad, said second conductive pad having a so-called "lower" end disposed in contact with the second isolation zone or with an insulating material formed on said second isolation zone.

[0025] According to one possible embodiment, the first exchange electrode is arranged between a first grid block and a second grid block, the first grid block and the second grid block extending mainly in a second direction orthogonal to the first direction.

[0026] According to one possible embodiment, the device may further comprise at least one other exchange electrode for modulating the tunnel barrier between the second island quantum and a third quantum island formed in a third region of the semiconductor block, the other exchange electrode being formed of a third conductive pad, the third conductive pad being able to be through-hole having a lower end in contact with the first insulation zone or the second insulation zone or an insulating material disposed on the first insulation zone or the second insulation zone.

[0027] According to an embodiment in which the third conductive pad can be arranged above and opposite the first isolation zone and form a third exchange electrode, the device further includes a fourth exchange electrode to modulate the tunnel barrier between the second quantum island and a third quantum island, the fourth exchange electrode being formed by a fourth conductive pad above and opposite said second isolation zone.

[0028] According to one possible implementation in which the first exchange electrode is provided to control the tunnel barrier between the first quantum island and the second quantum island, the device can further be provided with at least one additional exchange electrode provided to modulate a tunnel barrier between one of said quantum islands and a charge reservoir.

[0029] Advantageously, the device can be provided with an additional exchange electrode intended to modulate a tunnel barrier between one of said quantum islands and a dopant reservoir formed on and / or in an end portion of the semiconductor block.

[0030] According to one possible embodiment, said lower end of each exchange electrode may be in contact with an etching stop layer or a dielectric layer in which insulating spacers of the front grids are formed.

[0031] Advantageously, the device may further include charge reservoirs formed on or in said semiconductor block, the reservoirs being arranged on either side of said front grids.

[0032] Advantageously, the device may further comprise a plurality of charge reservoir electrodes, each charge reservoir electrode contacting a charge reservoir formed on and / or in said semiconductor block.

[0033] According to one possible embodiment, the substrate is a semiconductor-on-insulator type substrate, said semiconductor block being formed in a superficial semiconductor layer of the substrate.

[0034] According to another possible embodiment, the substrate is a bulk semiconductor substrate.

[0035] The semiconductor block can be formed by etching a surface semiconductor layer of the substrate or by etching a semiconductor layer deposited on this substrate, or by growth on this substrate.

[0036] According to another aspect, the present invention relates to a method for manufacturing a quantum electronic device as defined above.

[0037] According to another aspect, the present invention relates to a method for manufacturing a quantum device comprising, in this order, steps consisting of:

[0038] - to form on a substrate a semiconductor block, and isolation zones on either side and on the other side of the semiconductor block, then

[0039] - form gate blocks on the semiconductor block, then,

[0040] - to form one or more exchange electrodes by: • Deposition of an insulating layer covering the semiconductor block, the insulation zones and the gate blocks • creation of one or more openings, at least one initial opening penetrating the insulating layer and reaching the first insulation zone or an insulating material formed on the first insulation zone • Deposition of at least one conductive material in the openings.

[0041] The process may further include, prior to the formation of the insulating layer, the following steps:

[0042] - deposition of at least one dielectric layer,

[0043] - etching of the dielectric layer on end portions of the semi-block conductors arranged on either side of all the grid blocks so as to retain said dielectric layer on a central portion of the semiconductor block and to form insulating spacers against the grid blocks.

[0044] According to one possible implementation of the openings, said insulating material formed on the first insulation zone is that of said dielectric layer.

[0045] According to one possible embodiment, the process may further include, prior to the formation of the insulating layer and after the etching of the dielectric layer, the formation of doped regions on the end portions of the semiconductor block arranged on either side of the set of gate blocks.

[0046] According to one possible implementation of the method, among the openings, at least one other opening reveals a doped region of the semiconductor block.

[0047] The production of the exchange electrode(s) can thus be concomitant with the production of contacts on the charge reservoirs. Brief description of the drawings

[0048] The present invention will be better understood upon reading the description of the exemplary embodiments given, by way of illustration only and in no way limiting, with reference to the accompanying drawings in which:

[0049] [Fig. 1] serves to illustrate an example of a possible starting substrate for implementation a quantum device according to the invention;

[0050] [Fig.2A], [Fig.2B] serve to illustrate an embodiment of a semiconductor bar in which a plurality of quantum islands is destined to be formed;

[0051] [Fig.3A], [Fig.3B], [Fig.3C], serve to illustrate an implementation of a plurality of electrostatic control grids of quantum islands;

[0052] [Fig.4A], [Fig.4B], [Fig.5A], [Fig.5B], serve to illustrate an implementation of a dielectric layer to protect a central portion of the semiconductor bar in which the quantum islands are formed;

[0053] [Fig. A], [Fig. B], serve to illustrate the implementation of charge reservoirs on the semiconductor bar and on either side of the central portion of the semiconductor bar and of the entire set of control grids;

[0054] [Fig.7], [Fig.8A], [Fig.8B], serve to illustrate the implementation of metal and semiconductor alloy zones on the charge reservoirs and grids in order to form ohmic contacts;

[0055] [Fig.9A], [Fig.9B], [Fig.9C], [Fig.9D], [Fig.lOA], [Fig.lOB], [Fig.lOC], [Fig.lOD], [Fig.l 1] serve to illustrate the formation of exchange electrodes to enable tunnel coupling between neighboring quantum islands;

[0056] [Fig. 12A], [Fig. 12B], serve to illustrate the realization of exchange electrodes this time between dopant reservoir and quantum island;

[0057] [Fig. 13A], [Fig. 13B], serve to illustrate an alternative embodiment for which in a central portion of the semiconductor block is divided into two separate branches, with quantum islands being formed in at least one of said branches;

[0058] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0059] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0060] In addition, in the description below, terms which depend on the orientation of the structure such as "above", "below", "rear", "front", "peripheral" apply considering that the structure is oriented in the manner illustrated in the figures.

[0061] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0062] We refer first of all to [Fig.1] which gives an example of a possible starting material for the realization of a quantum device according to the invention and which is here in the form of a substrate 10 of the semiconductor on insulator type.

[0063] The substrate 10 thus comprises a support layer 11 made of semiconductor material, a buried insulating layer 12 disposed on the support layer 11, and a semiconductor surface layer 13 disposed on the insulating layer. The substrate 10 is typically an SOI substrate whose surface layer 13 is made of silicon, in particular to 28Si when this layer is used to accommodate quantum islands forming spin qubits of electrons.

[0064] The insulating layer 12 and the support layer 11 are typically, respectively, a silicon oxide layer commonly called a "BOX" layer (for "Buried Oxide") and a semiconductor layer, for example, silicon-based. The thickness of the surface layer 13 is, for example, between 5 nm and 50 nm, typically on the order of 10 nm. The thickness of the buried insulating layer 12 is, for example, between 15 nm and 150 nm.

[0065] Other semiconductor materials can be considered for the surface semiconductor layer 13. For hole spin qubits, silicon can also be used or, according to a variant, one can opt for a relaxed SiGe / constrained Germanium / relaxed SiGe heterostructure, the hole qubit layer being the germanium one.

[0066] Next, at least one active zone pattern can be defined in the surface layer 13, here in the form of a semiconductor block 14, typically oblong or bar-shaped, for example parallelepiped-shaped, and extending mainly in a first direction. This can be achieved by photolithography and etching of the surface layer 13, in particular plasma etching with a stop on the insulating layer 12.

[0067] Isolation zones 15A, 15B are then formed on either side of the active zone. The isolation zones 15A and 15B can be of the STI type (for "Shallow Trench Isolation"). For example, the isolation zones 15A and 15B are made of silicon oxide. The isolation zones 15A and 15B can be created by etching and then depositing insulating material. This can be followed by planarization to remove a layer of insulating material and bring the top surfaces of the isolation zones 15A and 15B to the same level, or nearly the same level, as the top surface of the semiconductor block 14.

[0068] In the particular embodiment illustrated in Figures 2A, 2B (giving respectively a cross-sectional view and a perspective view) a small level difference, for example between 0 and 20 nm, is provided between on the one hand the upper faces of the insulation zones 15A, 15B and on the other hand the upper face of the semiconductor block 14.

[0069] A grid stack covering the semiconductor block 14 and the insulation zones 15A, 15B is then produced. This stack is typically formed of at least one layer of grid dielectric and one or more layers of doped and / or metallic semiconductor grid material(s).

[0070] For example, the gate dielectric is formed from silicon dioxide. A so-called "high-k" dielectric, in other words, one with a high dielectric constant k, such as HfO2, can also be used. The dielectric itself can be topped with a metallic layer such as, for example, TiN, topped with a layer of doped polysilicon to form the grid materials.

[0071] The grid stack can be coated with at least one masking layer, in particular with at least one hard mask layer typically formed of at least one insulating layer, for example in SiN and / or SiO2.

[0072] Next, a plurality of masking blocks 24a, 24c, 24d, 24e are defined by etching in the masking layer in order to create a plurality of distinct blocks 22a, 22b, 22c, 22d, 22e in the grid stack. Anisotropic etching, and in particular using a plasma, is performed to create the masking blocks 24a, 24b, 24c, 24d, 24e, and then the distinct grid blocks 22a, ..., 22e beneath them, reproducing the patterns of the latter.

[0073] A structure obtained at the end of this step is illustrated in Figures 3A and 3B, respectively showing a perspective view and a cross-sectional view along axis A (given in the top view of [Fig. 3C]). In this example, the grid blocks 22a, ..., 22e each have a parallelepiped-shaped bar. These grid blocks 22a, ..., 22e typically extend in a direction (measured parallel to the x-axis of the orthogonal coordinate system [O; x; y; z]) orthogonal to the direction in which the semiconductor block 14 extends. The grid blocks 22a, ..., 22e are preferably regularly spaced with a dense distribution, for example, such that the distribution pitch Pr is on the order of 20 to 100 nm. Each grid block 22a, 22b, 22c, 22d, 22e includes a central portion 121 located on a region of the semiconductor block 14, this region being intended to form a quantum island.Each grid block 22a, 22b, 22c, 22d, 22e also has end portions 123, 122 on either side of the central portion 121, located respectively on the isolation zone 15B and the isolation zone 15A. Therefore, in this example, there are as many quantum islands 14A, 14B, 14C, 14D, 14E as there are grid blocks.

[0074] A dielectric mask 27 can then be formed on and between the grid blocks. The dielectric mask 27 can be achieved here by depositing a dielectric layer, arranged to cover the semiconductor block 14, the grid blocks 22a, ..., 22e, and the spaces between the grid blocks 22a, ..., 22e. In the example illustrated in Figures 4A and 4B (showing, respectively, a perspective view and a cross-sectional view along the longitudinal axis A), the dielectric mask 27 also covers the insulation areas 15A and 15B.

[0075] The dielectric mask material 27 is, for example, chosen from one of the following materials: SiO2, SiN, SiCO, SiBCN, SiOCN. The deposition process for the dielectric mask 27 is preferably conformal, and in particular of the ALD type (for "Atomic Layer Deposition") in order to fill the inter-grid spaces without creating filling defects.

[0076] Next (Figures 5A, 5B, respectively showing a perspective view and a cross-sectional view along the longitudinal axis A), this dielectric layer is etched so as to preserve the dielectric mask 27 only over a region 125 of the grid blocks 22a, ..., 22e, which includes the central portion 121 and part of the end portions 122, 123 of the grid blocks. The dielectric mask 27 is also preserved between the respective regions 125 of these grid blocks 22a, ..., 22e.

[0077] The dielectric mask 27 is removed from the upper faces of end portions 223 of blocks 22a, ..., 22e and of portions 148, 149, referred to as end portions, of the semiconductor block 14 located on either side of a central portion 140 of the semiconductor block 14 and of the entire grid of blocks 22a, ..., 22e, and which are intended to house charge reservoirs. The dielectric mask 27 is preserved on a central portion 140 of the semiconductor block 14 in which the islands are intended to be formed.

[0078] To complete the formation of charge reservoirs on portions 148, 149 of the semiconductor block 14, one or more layers of semiconductor material(s) 33 can then be grown epitaxially on the exposed portions 14', 14" of the semiconductor block 14 (Figures 6A and 6B). After etching the gate blocks 24a, 24b, 24c, 24d, 24e, in a particular embodiment where gate dielectric covers portions 14', 14" of the semiconductor block 14, this layer of gate dielectric is removed, if necessary, prior to the epitaxial growth of the charge reservoirs. For this purpose, a pre-epitaxial cleaning step is typically performed, for example, using dilute HF.

[0079] In particular, one can carry out epitaxial growth of silicon or CVD (for "Chemical Vapor Deposition") deposition, for example of germanium. Doping is then performed. This doping can be carried out by ion implantation and / or by in situ doping performed concurrently with the growth of the layer(s) of semiconductor material(s) 33.

[0080] For example, to form reservoirs 33a, 33b doped with N-type doping, Si:P (phosphorus-doped silicon) growth can be carried out. According to another example, to form reservoirs 33a, 33b doped with P-type doping, SiGe:B (boron-doped silicon germanium) growth can be carried out.

[0081] Due in particular to the presence of the dielectric layer 27 on a central portion 140 of the semiconductor block 14, doping of this central portion 140 is avoided, this central portion 140 preferably remaining undoped.

[0082] In the case where one or more ion implantation(s) are carried out to form the reservoirs, a lithographic resin is preferably used to mask the central portion 140 and protect this portion from the implantation(s).

[0083] According to an optional step illustrated in Figures 7 and 8A-8B, metal-semiconductor alloy-based zones 331 can then be formed on the doped reservoirs 33a, 33b, in order to make ohmic contacts on these reservoirs 33a, 33b. It is also possible to make metal-semiconductor alloy-based zones 229 and such ohmic contacts on the ends of the gate blocks 22a, ..., 22e.

[0084] For this purpose, portions of the masking blocks 24a, ..., 24e arranged at the ends of the grid blocks 22a,...,22e are removed ([Fig.7]) so as to reveal an upper face of these ends.

[0085] Then, a step of deposition of at least one layer of metal, for example Ni, Pt, W, Co, Ti, or V, can be carried out. The metal layer can optionally be covered with an encapsulation layer, which can be metallic. An example of encapsulation is formed by the deposition of TiN, for example, with a thickness on the order of 10 nm.

[0086] A heat treatment is then carried out to achieve silicification. Such a treatment can be performed at a temperature between 200°C and 900°C and for a duration adapted according to the treatment temperature. Removal of the unreacted metal can then be carried out, for example, by wet etching using a hot SPM (Sulfuric Peroxide Mix) solution. A second silicification anneal can also be performed.

[0087] In the embodiment illustrated in Figures 8A-8B, regions 331 of metal alloy and semiconductor, in particular of silicide, are thus formed respectively on the dopant reservoirs 33a, 33b, while regions 229 of metal alloy and semiconductor ([Fig.8A]) are made on the upper ends of the gate blocks 22a,...,22e.

[0088] The quantum device produced here has the particularity of being equipped with exchange electrodes allowing to implement a quantum coupling between neighboring or adjacent regions of the semiconductor block 14 and each intended for a quantum island.

[0089] Thus, to produce such exchange electrodes, at least one insulating layer 50 is formed beforehand. The insulating layer 50 formed is intended to cover the semiconductor block 14, the said insulation zones 15A, 15B, and the grid blocks 22a,... ,22e.

[0090] In the embodiment illustrated in Figures 9A, 9B, 9C (giving respectively a perspective view, a cross-sectional view along the longitudinal axis A shown in the top view of [Fig. 9D], a cross-sectional view along an axis B orthogonal to axis A), the insulating layer 50 is formed from a stack of several sublayers 51, 52.

[0091] A first sublayer 51 of insulating material, for example silicon nitride, is first produced and forms here an etching stop layer. A PECVD (Plasma-Assisted Chemical Vapor Deposition) type deposition process can, for example, be used to form such a stop layer 51.

[0092] A second sublayer 52, for example of silicon oxide (SiO2) is made on the first sublayer 51 and forms an encapsulation.

[0093] The first sub-layer 51 or etching stop layer is preferably chosen in a different material from that of the second sub-layer 52 and the isolation zones in order to better control the depth of the openings.

[0094] One or more openings 57b 572, 573, 574, 575, 576, 577, 578 are then made through the insulating layer 50 on either side of the semiconductor block 14. The openings can be made up to reaching the insulation zones 15A, 15B. The making of the openings 57b 572, 573, 574, 575, 576, 577, 578 is typically carried out by photolithography and then by means of one or more etchings made through a masking (not shown).

[0095] In the embodiment illustrated in [Fig.9B] (giving a view in couple along axis B), the openings 575, 577 have a fund located at the level of a top face, respectively of the first insulation zone 15A and of the second insulation zone 15B.

[0096] According to an alternative embodiment (not shown), these openings can be extended into the insulation zones 15A, 15B. The bottom of these openings 575, 577 can then be located within the thickness of the insulation zones 15A, 15B.

[0097] According to another possibility, the openings 57b 572, 573, 574, 575, 576, 577, 578 may have a bottom located at the level of an insulating material disposed on the insulation areas 15A, 15B, for example at the level of the dielectric masking layer 27 or a layer of type.

[0098] In either case, making the openings 57b 572, 573, 574, 575, 576, 577, 578 opposite an insulation zone 15A or 15B rather than above the active zone allows in particular to get closer to the active zone without having to control very precisely the height at which their bottom is located.

[0099] In the particular embodiment illustrated in Figures 9A and 9D, the first openings 57b, 573, 575, 577 are formed on one side and at a distance from the semiconductor block 14 and have a bottom exposing the first insulation zone 15A, while the second openings 572, 574, 576, 578 are formed on a second side and at a distance from the semiconductor block 14 and have a bottom exposing the second isolation zone 15B. Each opening 57b 572, 573, 574, 575, 576, 577, 578 is in this particular embodiment arranged between a pair of blocks 22e and 22d, (respectively 22d and 22c, 22c and 22b, 22b and 22a) of grid blocks.

[0100] Advantageously, concurrently with the creation of the openings 57b, 572, 573, 574, 575, 576, 577, 578 for receiving the exchange electrodes, one or more other openings can be made through the insulating layer 50, and in particular openings 58, 59 for making contact with the dopant reservoirs 33a, 33b. These openings 58, 59 thus have a bottom reaching the dopant reservoirs 33a, 33b or the silicified zones formed on these reservoirs.

[0101] Conductive pads 67b 672, 673, 674, 675, 676, 677, 678 68, 69 are then formed by filling the openings 57b 572, 573, 574, 575, 576, 577, 578, 58, 59 with one or more conductive materials (Figures 10A, 10B, 10C, 10D). One particular embodiment involves filling with a stack of Ti, TiN and W.

[0102] The conductive pads 67b 672, 673, 674, 675, 676, 677, 678 each form an exchange electrode. The conductive pads 67b 672, 673, 674, 675, 676, 677, 678 have a lower end 681 in contact with one of the insulation zones 15A, 15B.

[0103] The exchange electrodes 67b 672, 673, 674, 675, 676, 677, 678 are intended to modulate the potential barriers and consequently a tunnel barrier between two adjacent or neighboring quantum islands near which these exchange electrodes are arranged.

[0104] The function of the exchange electrodes 67b, 672, 673, 674, 675, 676, 677, 678 is distinct from that of the front grids; these exchange electrodes 67b, 672, 673, 674, 675, 676, 677, 678 are therefore not connected to the front grids 22a, ..., 22e. The exchange electrodes 67b, 672, 673, 674, 675, 676, 677, 678 are not in contact with the semiconductor block 14 in which the islands are formed.

[0105] Depending on the voltage levels applied to them, they therefore modulate the quantum coupling between quantum islands and thus allow control of the exchange energy between neighboring quantum islands.

[0106] The conductive pads 68, 69 serve as contact points on the dopant reservoirs 33a, 33b. This allows for the advantageous simultaneous production of contact points on both the charge reservoirs and the exchange electrodes, without requiring any additional steps specifically for manufacturing these exchange electrodes, and in particular without any additional lithography step.

[0107] Fig. 11 gives, for the sake of simplification, a cross-sectional view of the device without an upper part of the insulating layer 50 through which the exchange electrodes 67b 672, 673, 674, 675, 676, 677, 678 pass.

[0108] As illustrated in [Fig. 100], the realized spin qubit quantum device comprises a first exchange electrode 671 positioned near a first region 14A of the semiconductor block 14, forming a first quantum island, and a second region 14B of the semiconductor block 14, forming a second quantum island. The first exchange electrode 671 allows modulation of the tunnel barrier between the first region 14A, forming the first quantum island, and the second region 14B, forming the second quantum island. The exchange electrode is positioned to approach the active region, i.e., the semiconductor block 14, as laterally as possible, without actually contacting the block or creating a leakage current between the electrode and the active region.The distance separating the electrode and the active area must typically ensure that the leakage current measured between these two elements is less than 10 pA, for potential differences between these two elements of up to 5 Volts.

[0109] By "in the vicinity", we mean here at a non-zero distance and preferably less than 20 nm and typically between 3 nm and 20 nm, preferably 3 nm and 10 nm, advantageously between 3 nm and 5 nm.

[0110] Each exchange electrode 67b 672, 673, 674, 675, 676, 677, 678 is also positioned at a non-zero minimum distance Amin from the semiconductor block preferably sufficient to prevent tunneling current from passing between this exchange electrode and the semiconductor block 14. A distance Amin of at least 3 nm is preferably provided for this purpose.

[0111] The first exchange electrode 671 is here juxtaposed to a portion 141 of the central portion 140 of said semiconductor block 14, preferably undoped, which is arranged between the first region 14A forming the first island and the second region 14B forming the second island. In this particular configuration where the gate blocks 22e, 22d protrude respectively from regions 14A, 14B, the first exchange electrode 67i is arranged between a first gate block 22e and a second gate block 22d, these gate blocks 22e, 22d extending mainly in a direction orthogonal to that in which the semiconductor block 14 extends mainly. Such an arrangement also allows for conductive pads close to the active area while avoiding a screening effect on the gates.

[0112] An advantageous use can be made of a pair of electrodes 67b 672 to better modulate the tunnel barriers between a pair of neighboring or adjacent islands.

[0113] Thus, in the particular embodiment illustrated, a second exchange electrode 672 located on the other side of the semiconductor block 14 is also disposed near the first region 14A forming the first quantum island and the second region 14B forming a second quantum island. The second exchange electrode 672, arranged above the second isolation zone 15B, is also positioned at a given distance from the islands 15A and 15B, chosen to allow modulation of the potential barrier between the first and second quantum islands. The exchange electrode 672 is positioned at a sufficient distance Amin from the semiconductor block to preferably prevent any tunneling current from passing between this electrode 672 and the semiconductor block 14.

[0114] The exchange electrodes 67b 672 can in this case be driven independently of each other, so that the first electrode 671 can be set to a first potential while the second electrode 672 is set to a second potential different from the first potential.

[0115] A third exchange electrode 673 and a fourth exchange electrode 674 are here arranged on either side of a part 142 of the semiconductor block 14 located between the second quantum island, and a third island formed in a third region 14C of this semiconductor block 14. The third exchange electrode 673 and the fourth electrode 674, arranged respectively on the first isolation zone 15A and on the second isolation zone 15B, are provided, depending on the respective potentials applied to them, to allow modulation of the tunnel barrier between the second quantum island formed in the region 14B and the third quantum island formed in the region 14C.

[0116] In the illustrated embodiment, the electrodes 675, 676, arranged between region 14C and region 14D, are intended to modulate the tunneling barrier between the neighboring quantum islands formed respectively in these regions 14C, 14D. Similarly, the electrodes 677, 678 allow the tunneling barrier between a quantum island formed in a region 14D and an adjacent quantum island, here an end quantum island of the succession or series of islands formed in the central portion of the semiconductor block 14 to be modulated.

[0117] In addition to one or more exchange electrodes between islands, the quantum device can also be provided with one or more additional exchange electrodes this time between at least one quantum island 14A or 14E located at one end of the succession of islands 14A, 14B, 14C, 14D, 14E and one of the dopant reservoirs RI, R2 located on either side of this succession of islands and formed in and / or from the semiconductor block 14.

[0118] In an example of an embodiment illustrated in Figures 12A, 12B (giving respectively a top view and a cross-sectional view along an axis C), an additional pair of exchange electrodes 81, 82 is provided to modulate the potential barrier between the first quantum island 14A and a first dopant reservoir RI formed in or on an end portion 148 of the semiconductor block 14. Another additional pair of exchange electrodes 83, 84 can also be provided to modulate the potential barrier between another end quantum island 14E and a second dopant reservoir R2 located opposite the first RI reservoir in the other end portion 149 of the semiconductor block 14.

[0119] The additional exchange electrodes 81, 82, 83, 84 are typically formed during the same process steps as the exchange electrodes 67b 672, 673, 674, 675, 676, 677, 678, as described previously in connection with Figures 9A-9D and 10A-10D.

[0120] To make these exchange electrodes 81, 82, 83, 84, openings are formed in the insulating layer 50, each reaching the insulation zone 15A or the insulation zone 15B, and then these openings are filled with at least one conductive material to form conductive pads in these openings.

[0121] The exchange electrodes 81, 82, 83, 84 are arranged on an isolation zone 15A or 15B and sufficiently close to the dopant reservoir RI or R2, so that, depending on the potential level applied to them, the coupling between this dopant reservoir RI, R2 and the quantum island 15A, 15E of the end juxtaposed to this reservoir RI, R2 can be modulated.

[0122] An alternative embodiment is shown in Figures 13A-13B. The semiconductor block 14 here has a central portion 140' with a different configuration than that described previously, formed of a first semiconductor bar 1410 in which a row of quantum islands 14A, 14B, 14C, 14D, 14E is provided and a second semiconductor bar 1420, in which another row of islands 14A', 14B', 14C', 14D', 14E'

[0123] The semiconductor bars 1410, 1420 have an oblong shape, for example parallelepiped, and are separated from each other by means of a region 1450 typically made of insulating material.

[0124] This configuration of the central portion 140 of the semiconductor block can be obtained by making a trench in the latter, this trench can then be filled with insulating material.

[0125] Above each island in the first row, a front control grid 221 is arranged, and opposite this grid 221, above each island in the second row of detection islands, a control grid 222 is provided.

[0126] The islands of the first bar 1410 can be provided to form a first row of data qubits, while the islands of the second bar 1420 can form a second row of sensing elements for reading the coded value of the data qubits of the first row.

[0127] In either of the embodiments described above, the semiconductor block in which the quantum islands are formed is made from the surface layer of a substrate, in particular a semiconductor-on-insulator substrate. However, it is also possible to start from a different substrate, for example a bulk substrate, to form this block.

[0128] The semiconductor block(s) in which the quantum islands are formed can also be formed in one or more separate semiconductor layers of a surface semiconductor layer of a substrate. Alternatively, it is possible to form the semiconductor block hosting the quantum islands by etching a pattern made from one or more layers or regions formed by epitaxy.

[0129] According to a particular implementation, the semiconductor block in which the quantum islands are provided can be in the form of a bar and implemented in a manner similar to that in which the semiconductor bar ("fin" according to Anglo-Saxon terminology) of a finFET type transistor is made.

[0130] A quantum device implemented according to the invention is not limited to a number of quantum islands and front gates such as those shown, for example, in Figures 12A-12B. A larger number N (where N is an integer that may be greater than 5) of quantum gates and islands may be provided. In this case, at least Nl electrodes and, preferably, Nl pairs of exchange electrodes are typically provided, arranged between each pair of neighboring quantum islands.

[0131] A device such as the one described above can be provided with an electronic circuit for driving the qubits and is suitable for implementation on the same substrate of transistors for this driving circuit. The transistors of the driving circuit can be of CMOS (Complementary Metal-Oxide-Semiconductor) technology, and in particular cryogenic CMOS, or cryo-CMOS, operating at low temperature and typically below 1 Kelvin in order to best preserve the quantum states of the qubits.

Claims

Demands

1. Quantum electronic device comprising: - a substrate (10) coated with at least one semiconductor block (14), said semiconductor block extending mainly in a first direction, the semiconductor block (14) comprising a semiconductor layer (13); - isolation zones (15A, 15B) arranged on either side of the semiconductor layer (13) of said semiconductor block (14), - a plurality of front gates (22a, 22b, 22c, 22d, 22e), each front gate comprising a part extending over regions (14A, 14B, 14C, 14D, 14E) of the semiconductor layer (13) of said semiconductor block (14), each of said regions forming a quantum island, each front gate comprising another part extending over one of the isolation zones (15A, 15B);- one or more exchange electrodes (67b 672, 673, 674, 675, 676, 677, 678,), characterized in that said one or more exchange electrodes (67b 672, 673, 674, 675, 676, 677, 678,) are arranged between two front grids, opposite and above one of said insulation zones and each exchange electrode (67b 672, 673, 674, 675, 676, 677, 678,) has a lower end in direct contact with an insulating material of this insulation zone or disposed on this insulation zone.;

2. Quantum electronic device according to claim 1, wherein at least a first exchange electrode (671) among said exchange electrodes extends over a first isolation zone (15A) among said isolation zones (15A, 15B) and at a distance from a first region (14A) of said semiconductor block (14) forming a first quantum island, the first exchange electrode (67J) being provided at a distance from a second region (14B) of said semiconductor block (14) forming a second quantum island and so as to allow modulation of a tunnel barrier between said first quantum island and said second quantum island.

3. Device according to claim 2, wherein said second region (14B) of said semiconductor block (14) forms a second quantum island, the first exchange electrode (67i) being juxtaposed to a portion (141) of said semiconductor block (14) arranged between said first region (14A) and said second region (14B) of said semiconductor block (14).

4. A device according to any one of the preceding claims, wherein the first exchange electrode is formed of a first conductive pad and comprising at least a second exchange electrode (672) arranged above a second isolation zone (15B) and in the vicinity of said first region (14A) forming a first quantum island and a second region (14B) forming a second quantum island so as to allow modulation of the tunnel barrier between said first quantum island and said second quantum island, said second exchange electrode (672) being formed of a second conductive pad having a so-called "lower" end disposed in contact with a second isolation zone (15B) or with an insulating material formed on said second isolation zone.

5. Device according to claim 4, wherein the first exchange electrode (67i) is arranged between a first grid block (22e) covering said first region and a second grid block (22d) covering said second region, the first grid block and the second grid block extending mainly in a second direction orthogonal to the first direction opposite the first insulation zone (15A).

6. Device according to any one of claims 4 or 5, further comprising at least one other exchange electrode (673,674) for modulating the tunnel barrier between said second quantum island and a third quantum island formed in a third region (14C) of said semiconductor block (14), said other exchange electrode (673,674) being formed of a third conductive pad, said third conductive pad being formed opposite and above the first isolation zone (15A) or the second isolation zone (15B).

7. Device according to any one of claims 2 to 6, wherein the first exchange electrode (67i) is provided for controlling the tunnel barrier between said first quantum island and said second quantum island, the device further being provided with at least one additional exchange electrode (81, 82, 83, 84) provided for modulating a tunnel barrier between one of said quantum islands (14A, 14E) and a dopant reservoir (33a, 33b) formed on and / or in an end portion (148, 149) of the semiconductor block (14).

8. Device according to any one of claims 1 to 7, wherein said lower end of each exchange electrode is in contact with an etching stop layer (51) or a dielectric layer (27) in which insulating spacers of the front grids are formed.

9. Device according to any one of claims 1 to 8, wherein said semiconductor block (14) is formed in a surface semiconductor layer (13) of a semiconductor-on-insulator type substrate (10), or rests on a bulk semiconductor substrate.

10. Device according to any one of claims 1 to 9, further comprising charge reservoirs formed on or in said semiconductor block (14).

11. Device according to any one of claims 1 to 10, further comprising a plurality of charge reservoir electrodes, each contacting a charge reservoir formed on and / or in said semiconductor block (14).

12. A method for manufacturing a quantum device according to any one of claims 1 to 11, the method comprising, in this order, the steps of: - forming said semiconductor block (14) on said substrate (10), and isolation zones (15A, 15B) on either side of said semiconductor block (14), then - forming the grid blocks (22a, 22b, 22c, 22d, 22e) on the semiconductor block (14), said grid blocks (22a, 22b, 22c, 22d, 22e) extending principally in a direction orthogonal to a principal direction in which said semiconductor block (14) extends, then - forming said one or more exchange electrodes by: • deposition of an insulating layer (50) covering said semiconductor block (14), said isolation zones (15A, 15B) and the grid blocks (22a, 22b, 22c, 22d, 22e), • making one or more openings (57b 572, 573, 574, 575, 576, 577, 578, 58, 59) through said insulating layer (50),at least one first opening (57i) passing through said insulating layer (50) and being made so as to reach the first insulation zone (15A) or an insulating material formed on the first insulation zone, • deposition of at least one conductive material in said openings (57b 572, 573, 574, 575, 576, 577, 578 58, 59).

13. A method according to claim 12, further comprising, prior to the formation of the insulating layer (50), the steps of: - deposition of at least one dielectric layer (27), - etching said dielectric layer (27) on end portions (148, 149) of the semiconductor block (14) arranged on either side of all the grid blocks (22a, 22b, 22c, 22d, 22e) so as to retain said dielectric layer (27) on a central portion (140) of said semiconductor block and to form insulating spacers against the grid blocks (22a, 22b, 22c, 22d, 22e).

14. A method according to claim 13, further comprising, after etching said dielectric layer (27) and prior to the formation of the insulating layer (50), the formation of doped regions (33a, 33b) on said portions (148, 149) of the semiconductor block (14) arranged on either side of the set of gate blocks (22a, 22b, 22c, 22d, 22e).

15. A method according to any one of claims 12 to 14, wherein among said openings, at least one other opening (58, 59) exposes a doped region (33a, 33b) of the semiconductor block (14) or formed on said semiconductor block (14).

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