Memory circuit comprising electronic cells and a control circuit

Abstract

Memory circuit comprising electronic cells and a control circuit This description relates to a memory circuit comprising: - a memory matrix comprising a plurality of electronic cells (200), in which at least one electronic cell (200) comprises an integrated stack successively comprising: i) a first electrode (205); ii) an intermediate layer (204') comprising an oval threshold switching layer (204);and iii) a resistor (202) connected to the intermediate layer (204'), and - a control circuit connected to at least one electronic cell (200), the control circuit being structured and configured to apply, between the first electrode (205) and the resistor (202), a first voltage pulse of a first polarity to fix a first logic state of the electronic cell and a second voltage pulse of a second polarity opposite to the first polarity, to fix a second logic state of the electronic cell. Figure for the abbreviation: Fig. 2;

Description

Title of the invention: Memory circuit comprising electronic cells and a control circuit technical field

[0001] This description relates to the field of electronic devices, and more specifically to integrated electronic cells arranged in matrices. This description specifically relates to electronic devices comprising an ovoid threshold switching material (OTS). Previous technique

[0002] Among chalcogenide materials, two categories are currently being studied for their use in electronic devices, and more particularly in the manufacture of switches and memories. In particular, a distinction is made between threshold ovoid switching materials (OTS materials) and phase-change materials. Both materials can be used as thin films in integrated electronic devices.

[0003] An OTS material alternates between an "on" state and an "off" state depending on the voltage applied across the terminals of the electronic cell. The state of the oval threshold switch changes when the voltage across its terminals exceeds a threshold voltage. Once the threshold voltage is reached, the "on" state is triggered and the oval threshold switch is in a fundamentally conducting state. If the current or voltage falls below the threshold value, the oval threshold switch returns to the "off" state.

[0004] Phase-change materials are materials that can alternate, under the effect of heat, between a crystalline phase and an amorphous phase. Since the electrical resistance of an amorphous material is significantly greater than the electrical resistance of a crystalline material, such a phenomenon can be useful for defining two memory states differentiated by the resistance measured across the phase-change material. The most common phase-change materials used in phase-change memories are germanium-antimony-tellurium (GST) based.

[0005] Fig. 1 illustrates two simplified cross-sectional views (A) and (B) of an example of a memory cell known as illustrated in French patent application No. FR2100747 previously filed by the applicant.

[0006] The electronic cell 100 comprises a resistor 102 or a resistive element having a fixed resistance value, a first electrode 105, also called the first electrode, and an additional layer 106. The electronic cell 100 comprises in in addition to an intermediate layer 104' comprising an oval threshold switching (OTS) layer 104, a memory layer 108 and a barrier layer 110. The intermediate layer 104' is, for example, located between the resistor 102 and the first electrode 105, for example with the OTS layer 104 in contact with the resistor 102. For example, the additional layer 106 is connected to the first electrode 105. The memory layer 108 is, for example, located above the OTS layer 104 and between the OTS layer 104 and the first electrode 105. The barrier layer 110 is arranged between the memory layer 108 and the OTS layer 104.

[0007] When the voltage applied to the electronic cell is greater than a threshold voltage of the OTS layer 104, an electric current can pass through the OTS layer 104 and the memory layer 108 in the electronic cell 100 and can cause a change in the resistivity of the layer 108. This change can alter the memory state in the layer 108, thus altering the electrical characteristic of the electronic cell 100.

[0008] The high resistivity state can be associated with a "reset" state or a logic value "0", while a low resistivity state can be associated with a "set" state or a logic value "1".

[0009] There is a need for improvement of integrated electronic cells containing an oval threshold switch. Summary of the invention

[0010] The applicant faced the problem of manufacturing an electronic cell for use in a matrix (memory) having a simplified structure, but capable at the same time of functioning efficiently and / or properly and / or having the desired overall properties.

[0011] According to the applicant, the above problem can be solved by a memory circuit according to at least one of the following embodiments.

[0012] One embodiment provides a memory circuit comprising: - a memory matrix comprising a plurality of electronic cells, in which at least one electronic cell comprises an integrated stack successively comprising: i) a first electrode; (ii) an intermediate layer comprising a threshold ovonic switching layer; and iii) a resistor connected to the intermediate layer, and - a control circuit connected to at least one electronic cell, the control circuit being structured and configured to apply, between the first electrode and the resistor, a first voltage pulse of a first polarity to fix a first logic state of the electronic cell and a second voltage pulse of a second polarity opposite to the first polarity, to fix a second logic state of the electronic cell.

[0013] According to one embodiment, the threshold ovonic switching layer is made of a chalcogenide material.

[0014] According to one embodiment, at least one electronic cell comprises only the intermediate layer between the first electrode and the resistor, and the intermediate layer comprises only the threshold oval switching layer.

[0015] According to one embodiment, the threshold ovonic switching layer has a thickness between 15 nm and 50 nm.

[0016] According to one embodiment, the control circuit comprises a plurality of bit lines and a plurality of word lines, and at least one electronic cell is connected to a respective word line by its resistance, and to a respective bit line by its first electrode.

[0017] According to one embodiment, the integrated stack further includes a transistor connected to the resistor on the opposite side of the intermediate layer.

[0018] According to one embodiment, the transistor is a MOSFET transistor.

[0019] According to one embodiment, the transistor is a FinFET transistor.

[0020] According to one embodiment, the threshold ovoid switching layer has a thickness between 5 nm and 10 nm.

[0021] According to one embodiment, the control circuit comprises a plurality of bit lines and a plurality of word lines, and at least one electronic cell is connected to a respective word line by its transistor, and to a respective bit line by its first electrode.

[0022] According to one embodiment, the transistor comprises a drain and a gate and is connected by its drain to the resistor, and by its gate to the respective word line.

[0023] According to one embodiment, the control circuit comprises, for each bit line and word line, a respective inverter comprising a respective p-MOS transistor and a respective n-MOS transistor. Brief description of the figures

[0024] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0025] Fig. 1 illustrates two simplified cross-sectional views (A) and (B) of a known memory cell;

[0026] Fig. 2 illustrates two simplified cross-sectional views (A) and (B) of an electronic cell according to a first embodiment;

[0027] The [Fig.3] illustrates a voltage-current characteristic of the electronic cell of the [Fig.2];

[0028] Figure 4 illustrates a simplified schematic view of a memory circuit according to a first embodiment of the present description;

[0029] Figure 5 illustrates a simplified cross-sectional view of an electronic cell according to a second embodiment; and

[0030] Figure 6 illustrates a simplified schematic view of a memory circuit according to a second embodiment of the present description. Description of the implementation methods

[0031] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0032] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, certain connections between electronic cells arranged in a matrix, and the selection circuits, have not been detailed, as the described embodiments are compatible with existing switch matrices and with all the corresponding control circuits.

[0033] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0034] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures or to a ... in a normal position of use.

[0035] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0036] In the context of the present invention, “logic state” means either a “set” state of the intermediate layer (or threshold oval switching layer) characterized by a first threshold voltage, or a “reset” state of the intermediate layer (or threshold oval switching layer) characterized by a second threshold voltage. Typically, the intermediate layer (or threshold oval switching layer) threshold) in the "set" state is conductive for voltage values ​​between the first and second threshold voltage, while the intermediate layer (or threshold oval switching layer) in the "reset" state is resistive for voltage values ​​between the first and second threshold.

[0037] In the context of the present invention, a “conducting” element means that this element (namely the intermediate layer or the threshold oval switching layer), when an electric field intensity greater than or equal to 2 MV / cm or less than or equal to 4 MV / cm is applied to it (the voltage difference being applied along the direction of the thickness of the element, typically on the order of a few nanometers), allows the passage of a current of intensity less than or equal to 5 mA, preferably less than or equal to 2 mA (the intensity being limited by the presence of the resistance, typically having a resistance value on the order of 5-10 kQ).Within the framework of the present invention, a “resistive” element means that this element (namely the intermediate layer or the threshold oval switching layer), when an electric field intensity greater than or equal to 4 MV / cm or less than or equal to 10 MV / cm is applied to it, allows the passage of a current of intensity less than or equal to 50 pA, preferably less than or equal to 25 pA, more preferably less than or equal to 10 pA.

[0038] The applicant has advantageously understood that the control circuit allows for the implementation of dual-polarity operation of the intermediate layer. In particular, the applicant has experimentally verified (through a large test campaign) that in this way, it is possible to exploit the intermediate layer comprising the OTS layer both as a memory element (i.e., an element that can be programmed in a logic state and that can retain the transferred logic state) and as a selector leakage element (i.e., an element capable of allowing / preventing the passage of current through the electronic cell).

[0039] Figure 2 illustrates an electronic cell 200 according to a first embodiment. Note that Figure 2 represents only a single electronic cell 200, but typically the electronic cell is part of a memory matrix including a large number of integrated electronic cells using thin films of chalcogenides, semiconductor materials, resistive materials, insulating materials, conductive materials, etc.

[0040] For the sake of simplicity, the term "layers" is used to designate the corresponding elements of a stack forming the electronic cell. It should nevertheless be understood that the corresponding layers, in practice, correspond to thin films deposited and etched to form individual switching elements separated by insulating grooves and arranged, for example, in matrices. The terminals or electrodes of each electronic cell can be interconnected, for example in rows and columns, by corresponding layers of the stack.

[0041] The electronic cell 200 includes a resistor 202, for example with a fixed resistance value (i.e. independent of the crystalline state).

[0042] The electronic cell 200 includes a first electrode (205).

[0043] The electronic cell 200 comprises an intermediate layer 204', for example interposed in direct contact between the resistance 202 and the first electrode 205.

[0044] For example, the intermediate layer 204' comprising only an oval threshold switching layer (OTS) (204). In this way, the structure of the electronic cell is simplified, with advantages in terms of cost and / or production time, and / or the size of the electronic cell is reduced, with a consequent reduction in the overall dimensions of the memory circuit (i.e., savings in terms of silicon area and associated costs).

[0045] For example, the electronic cell 200 further comprises an additional layer 206 connected to the first electrode 205 on the side opposite the OTS layer 204 (in other words, the first electrode is interposed between the additional layer and the intermediate layer). Preferably, the additional layer is made of a material with a conductivity greater than or equal to 20 S / pm, more preferably greater than or equal to 40 S / pm.

[0046] For example, in [Fig.2], the first electrode 205 forms one electrode of the electronic cell 200 while the resistor 202 forms another electrode of the electronic cell 200.

[0047] The resistor 202 has, for example, an L-shaped cross-section, that is, the resistor 202 has a horizontal portion 2020 and a vertical portion 2022. The resistor 202 is, for example, surrounded by an insulating layer (not shown). The thickness of this insulating layer is such that the upper surface of the vertical portion 2022 of the resistor 202 is coplanar with the upper surface of the insulating layer. The resistor 202 has an L-shaped cross-section, but the shape of the resistor 202 can easily be adapted to a square cross-section or any other shape (not shown). The resistor 202 is connected to the OTS layer 204, for example, in contact with the OTS layer 204.

[0048] The electronic cells of figures 2 and 4 to 6 are represented in space according to an orthogonal XYZ spatial system in which the Z axis is orthogonal to the upper face of the additional layer 206 of the electronic cell.

[0049] In the embodiment of [Fig. 2], the additional upper layer 206 extends horizontally in the X direction. In the example of Figure 2A, the vertical part 2022 of the resistor 202 is preferably centered with respect to the electronic cell 200 and extends vertically in the Y direction. In the example of the In Figure 2B, the vertical portion 2022 of the resistor 202 is preferentially centered with respect to the electronic cell 200 and extends vertically in the X direction.

[0050] The difference between views (A) and (B) of [Fig. 2] is therefore the orientation of the resistor in L. View (A) is called a “self-aligned wall” cell architecture, in which the width of the resistor 202 is equal to the width of the additional layer 206. In view (A), the resistor 202 and the additional layer 206 are, for example, formed using the same masking layer and in the same direction.

[0051] View (B) represents a different application of “self-aligning wall technology” in that the width of the resistor 202 is not equal to the width of the additional layer 206. In view (B), the resistor 202, the OTS layer 204, and the first electrode 205 are, for example, formed using the same masking layer as that used to form the additional layer 206, but oriented perpendicular to the direction of the additional layer 206. The electronic cell architecture of view (B) allows a resistor 202 to be integrated into an OTS device without loss of surface area, at the cost of a non-critical additional mask and a few additional process steps.

[0052] In both views (A) and (B), the interconnection (not shown) of the part 2020 of the resistors 202 is perpendicular to the interconnection of the additional layers 206. In other words, if the additional layer 206 is arranged in columns, the lower electrode is arranged in rows.

[0053] In [Fig.2], the vertical part 2022 of the resistor 202 is preferably centered with respect to the electronic cell 200 and extends vertically along the X direction. Alternatively, the vertical part 2022 of the resistor 202 is preferably centered with respect to the electronic cell 200 and extends vertically along the Y direction.

[0054] The first electrode 205 and the resistor 202 are, for example, made of the same metallic material, namely tungsten. Alternatively, the first electrode 205 and the resistor 202 may be made of two different metallic materials. For example, the resistor and / or the first electrode is / are made of a metallic (refractory) material, preferably chosen from the group consisting of: carbon (C), carbon nitride ((CN)n), titanium (Ti), titanium nitride (TiN), titanium-silicon nitride (TiSiN), tungsten (W), tungsten nitride (W2N, WN, WN2), tungsten-carbon nitride, tungsten-silicon nitride, tantalum (Ta), tantalum nitride (TaN), tantalum-silicon nitride, tantalum-tungsten, or any combination or alloy of these materials.

[0055] The first electrode 205 is connected to the additional layer 206. The first electrode 205 and the additional layer 206 are, for example, in contact direct. The additional layer 206 is, for example, connected to the first electrode 205 by a conductor via smaller than the first electrode 205 and made, for example, of tungsten.

[0056] The additional layer 206 has, for example, a width greater than or equal to one of the dimensions of the first electrode 205.

[0057] The additional layer 206 is, for example, made of copper.

[0058] The OTS layer 204 has the property of exhibiting a significant drop in resistivity when the voltage applied between the additional layer 206 and the resistor 202 exceeds a threshold voltage VTH. The decrease (or increase) triggered by the voltage applied between the top and bottom of the layer allows the layer to be considered as forming a switch between an "off" state and an "on" state. If the voltage applied to the OTS layer 204 is below the threshold VTH of the OTS layer 204, the OTS layer 204 remains in its "off" state of high resistivity. In this state, only a leakage current flows through the electronic cell 200. If a voltage above the threshold VTH is applied, the OTS layer 204 switches to the "on" state and operates in a state of relatively low resistivity. In the "on" state, current flows through the electronic cell 200. The threshold voltage VTh of the OTS layer 204 is, for example, between 0.5 V and 5 V inclusive.

[0059] The OTS 204 layer is, for example, made of a chalcogenide material, e.g., germanium. Alternatively, the OTS layer is made of any other chalcogenide material, chosen, for example, from the following group: germanium (Ge), tellurium (Te), selenium (Se), arsenic (As), and any combination or alloy of these materials. The OTS layer may also, for example, be doped, preferably with antimony (Sb), indium (In), or silicon (Si).

[0060] Other examples of ovoid materials suitable for forming an OTS 204 layer can be found in European patent application no. EP09180927, previously filed by the applicant.

[0061] Typically, the chalcogenide material of the OTS layer is not a phase-change material; that is, the OTS layer consists of an amorphous material regardless of the energy applied. In other words, a chalcogenide material is always an amorphous material. This means that the intermediate layer 204' is free of any phase-change material.

[0062] The OTS 204 layer, for example, has a thickness of 30 nm. More generally, the OTS layer may have a thickness greater than or equal to 10 nm, more preferably greater than or equal to 15 nm, even more preferably greater than or equal to 25 nm, and / or less than or equal to 100 nm, plus preferably less than or equal to 50 nm, even more preferably greater than or equal to 40 nm.

[0063] The OTS layer 204 and the first electrode 205 of each electron cell are separated from the respective OTS layers 204 and first electrodes 205 of adjacent cells by an insulating layer (not shown). In other words, the OTS layer 204 is “totally confined”. The OTS layer 204 and the first electrode 205 have, for example, a parallelepiped shape, having, for example, the same length and width for both layers.

[0064] Fig. 3 is a graph illustrating the evolution of the intensity as a function of the voltage applied to the electrodes of the electronic cell 200.

[0065] In dual-polarity operation, when the voltage applied to the electronic cell exceeds a first threshold voltage VTH0 in a positive or first polarity, the OTS 204 layer becomes conductive in an "on" state and is programmed as a "0" or in a first logic state, then becomes resistive again in a "off" state when the applied voltage decreases. Similarly, when the voltage applied to the electronic cell exceeds a threshold voltage VTH1 in a negative or second polarity, the OTS 204 layer becomes conductive in an "on" state and is programmed as a "1" or in a second logic state, then becomes resistive again in a "off" state when the applied voltage decreases.

[0066] The inventors discovered that when an electronic cell is programmed twice consecutively as a "1", the threshold voltage VTH1 is lower in absolute value than when an electronic cell is programmed as a "0" and then as a "1". In other words, if an electronic cell has been programmed as a "1" and then reprogrammed as a "1" (without being programmed as a "0" in between), the threshold voltage VTh1 is equal to VthsameI, whereas if the same electronic cell has been programmed as a "0" and then reprogrammed as a "1", the threshold voltage VTH1 is equal to VTHoppo1, which is greater, in absolute value, than VthsameI. For example, the voltage VTHsame1 is approximately equal, in absolute value, to the voltage VTh0.

[0067] To take advantage of this memory effect, it is proposed to read the electronic cells 200, during a read phase, with a voltage Vread corresponding to a negative voltage whose value is between VthsameI and VthoppoL. With this type of read voltage, if the current measurement in the electronic cell determines that the OTS layer 204 is conductive, it means that the threshold voltage VTH1 corresponded to VTHsame1 which has been exceeded, and that the electronic cell had just been programmed to the value "1". Conversely, if the current measurement of the current in the electronic cell determines that the OTS 204 layer is resistive, this means that the threshold voltage VTH1 corresponded to VTHoppo1 which was not exceeded and that the electronic cell had just before been programmed as an "O".

[0068] It should be noted that reading an electronic cell does not overwrite the programming, because programming a value of "1" means reprogramming to the value "1" and reading a value of "0" means not reprogramming the electronic cell.

[0069] Figure 4 illustrates a simplified cross-sectional view of an electronic cell array 200.

[0070] The cell matrix 200 comprises, for example, a plurality of electronic cells 200 as illustrated in [Fig. 2]. The matrix is, for example, associated with the control circuit 405 (CTRL) adapted to apply to each electronic cell a voltage between the two electrodes, and more precisely between the resistor 202 and the first electrode 205.

[0071] The electronic cells 200 are, in [Fig.4], positioned between a plurality of bit lines 401 and word lines 403. In [Fig.4], the bit lines 401 are illustrated by vertical lines and the word lines 403 are illustrated by horizontal lines.

[0072] For example, the control circuit 405 includes (not shown), for each bit line 401 and word line 403 pair, a respective inverter (i.e., one inverter connected to the bit line of the pair and another inverter connected to the word line of the pair). Preferably, each inverter includes a respective p-MOS transistor and a respective n-MOS transistor. In this way, the control circuit is structurally simple and / or has relatively high performance.

[0073] Preferably, the control circuit 405 (also with reference to [Fig.6], as will be discussed later) is structured and configured to apply, between the first electrode and the resistor, a reading voltage pulse (of the first or second polarity) having a voltage value between the first and second threshold voltage to determine a current logic state of the electronic cell.

[0074] For example, each electronic cell 200 is connected to the respective word line 403 by the first electrode 205 and to the respective bit line 401 by the resistor 202. Alternatively, at least one electronic cell is connected to the respective bit line by its electrode, and to a respective word line by its resistor. The described connection is called a “crossbar scheme”. The applicant realized that the electronic cell embodiment in a crossbar scheme allows the selector element to be outside the silicon substrate, thus advantageously introducing additional logic circuits and / or components into the silicon substrate. Furthermore, the crossbar scheme allows for improved modularity of the memory circuit, with advantages for embedded applications (e.g., automotive).

[0075] To be programmed, an electronic cell 200 must see a potential difference between its two electrodes connected respectively to the bit line 401 and the word line 403. In fact, to program an electronic cell 200 to "0", its bit line 401 is set to a voltage corresponding to a value of -V / 2 and its word line 403 to a voltage corresponding to a value of +V / 2 so that the electronic cell in question sees a voltage V. Similarly, to program an electronic cell 200 to "1", its bit line 401 is set to a voltage corresponding to a value of +V / 2 and its word line 403 to a voltage corresponding to a value of -V / 2 so that the electronic cell in question sees a voltage -V.

[0076] For either program, the other electronic cells see a voltage of 0, V / 2, or -NU. By choosing the value of V such that its absolute value is greater than VTHoppo1 and the absolute value of V / 2 is less than VTHsame1 and VTH0, the electronic cells that see 0, V / 2, or -V / 2 are not programmed.

[0077] For example, the operating voltage is between 4 V and 6 V.

[0078] Figure 5 illustrates a simplified cross-sectional view of an electronic cell 500 according to a second mode of implementation.

[0079] The electronic cell 500 illustrated in [Fig. 5] is similar to the electronic cell 200 illustrated in [Fig. 2], except that the electronic cell 500 also includes a transistor 502. For example, the transistor 502 is connected to the resistor 202 on the opposite side of the intermediate layer 204'. The applicant observed that in this way, it is possible to reduce the operating voltage of the entire electronic cell, with advantages in terms of power consumption. Furthermore, the applicant observed that the transistor can act as a selector element, thus allowing the OTS layer to perform only the memory function. In this way, it is possible to use an OTS layer with a relatively small thickness.

[0080] Alternatively, the transistor can be connected to the first electrode on the opposite side of the intermediate layer.

[0081] For example, transistor 502 is an n-MOS FinFET transistor. The applicant has verified that an n-MOS FinFET transistor can be easily controlled, which simplifies the overall operation of the memory circuit. In general, transistor 502 is a MOSFET transistor, preferably of the FinFET type. The applicant has verified that the MOSFET transistor (in particular a FinFET transistor) has high performance in terms of small size (i.e., small footprint of the electronic cell) and / or high frequency range. This favors the use of the electronic cell for embedded applications, e.g., automotive applications.

[0082] For example, in the 500 electronic cell, the OTS 204" layer has a thickness of 8 nm.

[0083] More generally, when the electronic cell includes the transistor, the OTS 204" layer can have a thickness greater than or equal to 2 nm, more preferably greater than or equal to 5 nm, and / or less than or equal to 15 nm, more preferably less than or equal to 10 nm. As mentioned above, the transistor allows the use of relatively thin OTS layers, which increases the range of applicability of the memory circuit due to its greater integrability into a wide variety of devices.

[0084] As can be seen schematically in [Fig.6], transistor 502 is connected by its gate 502g to a word line (WL).

[0085] In this example, transistor 502 has its gate 502d connected to resistor 202, and more specifically connected to the horizontal part 2020 of resistor 202. In this example, transistor 502 has its source 502s connected to ground.

[0086] Figure 6 illustrates a simplified cross-sectional view of an array of 500 electronic cells (with a plurality of 500 electronic cells).

[0087] The electronic cells 500 are, in [Fig.6], positioned between a plurality of bit lines 401 and word lines 403.

[0088] For example, each electronic cell 500 is connected to the bit line 401 by the first electrode 205 and to the word line 403 by the gate 502g of its transistor 502.

[0089] The memory matrix is, for example, associated with the control circuit 405.

[0090] To be programmed, the electronic cell 500 must be traversed by a non-zero voltage. To program the electronic cell 500 to "0", its bit line 401 is set to a voltage corresponding to a value of +V and its word line 403 to a voltage corresponding, for example, to a value of 0 V, so that the transistor 502 turns on and the electronic cell in question sees a voltage V. To program the electronic cell 500 to "1", its bit line 401 is set to a voltage corresponding to a value of -V and its word line 403 to a voltage corresponding, for example, to a value of 0 V, so that the transistor 502 turns on and the electronic cell in question sees a voltage -V.

[0091] For either program, the other electronic cells in the memory circuit either have their respective transistors 502 turned on and see a voltage of, for example, 0 V, or their transistor 502 is turned off. Consequently, these electronic cells are not programmed.

[0092] In one embodiment, the control circuit comprises, for each pair of bit row 401 and word row 403, a respective inverter (i.e., an inverter connected to the bit line of the pair and another inverter connected to the word line of the pair), including for example a p-MOS transistor and an n-MOS transistor.

[0093] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0094] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Memory circuit comprising: - a memory matrix comprising a plurality of electronic cells (200; 500), in which at least one electronic cell (200; 500) comprises an integrated stack successively comprising: i. a first electrode (205); ii. an intermediate layer (204') comprising an oval threshold switching layer (204; 204"); and iii.a resistor (202) connected to the intermediate layer (204'), and - a control circuit connected to at least one electronic cell (200; 500), wherein the control circuit (405) is structured and configured to apply, between the first electrode (205) and the resistor (202), a first voltage pulse of a first polarity to fix a first logic state of the electronic cell and a second voltage pulse of a second polarity opposite to the first polarity, to fix a second logic state of the electronic cell, wherein the threshold oval switching layer (204; 204") is made of a chalcogenide material, and wherein the at least one electronic cell (200) comprises only the intermediate layer (204') between the first electrode (205) and the resistor (202), and wherein the intermediate layer (204') comprises only the threshold oval switching layer (204; 204").

2. Memory circuit according to claim 1, wherein the threshold oval switching layer (204) has a thickness between 15 nm and 50 nm.

3. Memory circuit according to claim 1 or 2, wherein the control circuit (405) comprises a plurality of bit lines (401) and a plurality of word lines (403), wherein at least one electronic cell (200) is connected to a respective bit line (401) by its resistor (202), and to a respective word line (403) by its first electrode (205).

4. A memory circuit according to any one of claims 1 to 3, wherein the integrated stack further comprises a transistor (502) connected to the resistor (202) on the opposite side with respect to the intermediate layer (204').

5. Memory circuit according to claim 4, wherein the transistor (502) is a MOSFET transistor.

6. Memory circuit according to claim 4, wherein the transistor (502) is a FinFET transistor.

7. Memory circuit according to any one of claims 4 to 6, wherein the threshold oval switching layer (204") has a thickness between 5 nm and 10 nm.

8. Memory circuit according to any one of claims 4 to 7, wherein the control circuit (405) comprises a plurality of bit lines (401) and a plurality of word lines (403), wherein at least one electronic cell (500) is connected to a respective word line (403) by its transistor (502), and to a respective bit line (401) by its first electrode (205).

9. Memory circuit according to claim 8, wherein the transistor (502) comprises a drain (502d) and a gate (502g) and is connected by its drain (502d) to the resistor (202), and by its gate (502g) to the respective word line (403).

10. Memory circuit according to any one of claims 1 to 9, wherein the control circuit (405) comprises, for each pair of bit lines (403) and word lines (401), a respective inverter comprising a respective p-MOS transistor and a respective n-MOS transistor.