Memory system

Abstract

Memory system The present description relates to a memory system comprising a memory comprising memory blocks; a first logic block (406) configured to perform an exclusive OR function (XOR) of a current value of a data addressing mode (md) and at least one bit of a first data packet comprising an error correction code of a data item to be written, a second data packet, resulting from the first logic block, being stored in one of the memory blocks; and a second logic block (416) configured to perform an exclusive OR function of at least one bit of the second packet as read from said one of the memory blocks and of the current value of the addressing mode (md), when reading the second packet or subsequently, a weight of said bit of the first data packet corresponding to a weight of said at least one bit of the second data packet read. Figure for abstract: Fig. 4

Description

Title of the invention: Memory system Technical field

[0001] The present description relates generally to memory systems and the methods implemented by these memory systems. Prior art

[0002] Many applications use memory systems to implement data storage in volatile or non-volatile memories. These systems can implement several linear or interleaving addressing modes of data within different memory blocks. Successive changes in the addressing mode can nevertheless result, under certain conditions, in a reduction in the security of the stored data. Summary

[0003] There is a need to obtain memory systems that allow stored data to be kept secure when the addressing mode is changed.

[0004] One embodiment overcomes all or part of the drawbacks of known memory systems.

[0005] One embodiment provides a memory system comprising: - a memory comprising memory blocks; - a first logic block configured to perform an exclusive OR function of a current value of a data addressing mode and at least one bit of a first data packet comprising an error correction code of a data item to be written or said data item to be written or said error correction code of a data item to be written and said data item to be written; a second data packet, resulting from the first logical block, being stored in one of the memory blocks; and - a second logic block configured to perform an exclusive OR function of at least one bit of the second packet as read from said one of the memory blocks and of the current value of the addressing mode when reading the second packet or after this, a weight of said at least one bit of the first data packet corresponding to a weight of said at least one bit of the second data packet read.

[0006] One embodiment provides a method for securing a memory system, the system having a memory comprising memory blocks, the method comprising: - carry out, with a first logic block, an exclusive OR function of a value current of a data addressing mode and at least one bit of a first data packet comprising an error correction code of a data to be written or said data to be written or said error correction code of a data to be written and said data to be written; - store, in one of the memory blocks, a second data packet resulting from the first logical block; - carry out, with a second logic block, an exclusive OR function of at least one bit of the second packet as read from said one of the memory blocks, and of the current value of the addressing mode when reading the second packet or after this, a weight of said at least one bit of the first data packet corresponding to a weight of said at least one bit of the second data packet read.

[0007] In one embodiment, such a system or method further comprises an error correction code decoder configured to decode a third data packet resulting from the second logic block.

[0008] In one embodiment, such a system or method further comprises an error correction code encoder configured to calculate said error correction code associated with said data to be written.

[0009] In one embodiment, the first logic block is configured to perform an exclusive OR function from a bit of the first data packet; and - the second logic block is configured to perform an exclusive OR function from a bit of the second packet as read from said one of the memory blocks; the weight of the bit of the first data packet corresponding to the respective weight of the bit of the second data packet after reading.

[0010] In one embodiment, the error correction code encoder and decoder are of the SED type.

[0011] In one embodiment, the first logic block is configured to perform an exclusive OR function from two bits of the first data packet; and the second logic block is configured to perform an exclusive OR function from two bits of the second packet as read from said one of the memory blocks; the weight of said two bits of the first data packet corresponding to the respective weight of said two bits of the second data packet after reading.

[0012] In one embodiment, the error correction code encoder and decoder are of the SECDED type.

[0013] In one embodiment, the first logic block is configured to perform an exclusive OR function from three bits of the first data packet; and the second logic block is configured to perform an exclusive OR function from three bits of the second packet as read from said one of the memory blocks; the weight of said three bits of the first data packet corresponding to the respective weight of said three bits of the second data packet after reading.

[0014] In one embodiment, the error correction code encoder and decoder are of the DECTED type.

[0015] In one embodiment, if the error correction code decoder detects an error then the memory system generates an error value.

[0016] In one embodiment, if the error correction code decoder detects two errors then the system generates an error value.

[0017] In one embodiment, if the error correction code decoder detects three errors then the memory system generates an error value.

[0018] In one embodiment, the value of the addressing mode corresponds to an interleaved mode or a linear mode of writing data in said memory blocks.

[0019] In one embodiment, the first data packet further comprises the data to be written. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.l] represents an example of an integrated circuit of the type to which the described embodiments apply;

[0022] [Fig.2] illustrates an example of a memory system of the integrated circuit of [Fig.l];

[0023] [Fig.3] illustrates an example of memory of the integrated circuit of [Fig.l];

[0024] [Fig.4] illustrates an example of a memory system of the integrated circuit of [Fig.l] according to one embodiment; and

[0025] [Fig.5] illustrates a method of securing the memory system of [Fig.4] according to one embodiment. Description of the embodiments

[0026] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0027] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed.

[0028] Unless otherwise specified, when referring to two elements connected between them, it means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") between them, it means that these two elements can be connected or be linked by through one or more other elements.

[0029] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0030] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0031] [Fig.l] represents an example of an integrated circuit of the type to which the described embodiments apply.

[0032] More specifically, [Fig.l] represents an example of an integrated circuit device 100 integrating a memory system 130. The memory system 130 integrates a volatile memory 104 (Memory), for example of the RAM type or non-volatile, for example of the FLASH type. The memory 104 comprises for example several memory blocks 107, 109 (CUTI, CUT2). The memory 104 is capable of communication, via one or more communication buses 103, 105, with a control circuit 106 (Memory controller) configured to write or read data in or from the memory 104. In one example the bus 105 is dedicated to the memory block 107, and the bus 103 is dedicated to the memory block 109. The buses 103 and 105 are for example grouped into a single bus.

[0033] The memory system 130 integrates for example the control circuit 106 which comprises a dedicated hardware encoder circuit which, when activated, is configured to calculate an error correction code (ECC) when writing each element in one of the memory blocks 107, 109. The communication buses 103, 105 are for example address buses, and data packet buses comprising data to be written and their associated error correction code (Data+ECC, Addr c2 and Data+ECC, Addr cl respectively). The control circuit implements for example several linear or interleaving addressing modes to write data within different memory blocks. The control circuit 106 receives, for example via the bus 114 or via another bus, information (md), for example in the form of a bit, on the addressing mode to be used to write and / or read the data in the different memory blocks 107, 109.

[0034] The device 100 further comprises, for example, a processing unit 110 (CPU) comprising one or more processors under the control of instructions stored in an instruction memory 112 (INSTR MEM). The instruction memory 112 is for example of the random access type (RAM). The processing unit 110 and the memory 112 communicate, for example, via a system bus 140 (data, addresses and control). The control circuit 106 is for example connected to the system bus 140 via a firewall 113 and one or more several communication buses 114. The communication bus 114 allows for example the exchange of addresses, data, and data relating to errors on error correction codes (Data, Addr, ECC Error).

[0035] The firewall 113 protects sensitive data by filtering them based on their address. The firewall processes, in collaboration with for example the bus 140, data and system addresses (Data, System Addr).

[0036] The device 100 further comprises an input / output interface 108 (I / O INTERFACE) connected to the system bus 140 for communicating with the outside.

[0037] The device 100 can integrate other circuits implementing other functions (for example, one or more volatile and / or non-volatile memories, other processing units), symbolized by a block 116 (FCT) in [Fig.l].

[0038] [Fig.2] illustrates an example of a memory system 130 of the integrated circuit of [Fig.l].

[0039] In the example shown, the control circuit 106 of the memory system 130 comprises an error correction code encoder circuit 206 (ECC encoder) configured to calculate an error correction code (ECC WR TO mem) associated with a data item to be written (Data WR in) provided on the bus 114 for example. The data item (Data WR TO mem), as well as its associated error correction code ECC WR TO mem, are provided to the bus 105, for example in the form of one or more data packets, for writing in the memory 104. When the data item and its associated error correction code are arranged in a data packet, otherwise called a word, they can be arranged in the form ECC_Data.

[0040] In one example, the encoder and decoder 206, 216 apply a Hamming code or a Golay code.

[0041] In the example shown, the control circuit 106 of the memory system 130 further comprises an error correction code decoder circuit 216 (ECC decode) configured to decode the error correction code (ECC RD from mem) of the data packet (ECC RD from mem + Data RD from mem) resulting from the reading of the data packet which had previously been written in the memory 104. The decoder 216 raises, for example on the bus 114, a flag (ECC Error) indicating that an error has been detected in the data packet read and comprising for example the error correction code (ECC RD from mem) and the data read (Data RD in).

[0042] Circuits 206 and 216 are, for example, hardware circuits.

[0043] In certain cases, it may happen that, when writing the data packet(s) to memory, one or more bits of the data packet are inverted (i.e. for a given bit of weight, the inverse value is recorded) (a phenomenon called bit flip in English). In this case, the ECC error correcting code can be used.

[0044] The error correcting code may be used to correct one or more errors in a data packet read into memory, during a decoding step.

[0045] There are different types of error correcting code: - SED, for Single Error Detection, is an error-correcting code that only detects one error per packet read from memory. When an error is detected in the packet read from memory, an error code or a zero value is returned. - SECDED, for Single Error Correction and Double Error Detection, is an error-correcting code that can correct one error and detect up to two errors per data packet read from memory. When two errors are detected in the packet read from memory, an error code or a zero value is returned. - DECTED, for Double Error Correction and Triple Error Detection, is an error-correcting code that can correct up to two errors and detect up to three errors per data packet read from memory. When three errors are detected in the packet read from memory, an error code or a zero value is returned.

[0046] Thus, the encoder and the decoder 206, 216, when they are of the SED type, allow the correction of an inversion on a bit of the data packet. When they are of the SECDED type, they allow the correction of an inversion on a bit of the data packet and the detection of two bit modifications. When they are of the DECTED type, they allow the correction of two bit inversions and the detection of three bit modifications.

[0047] To summarize, for a SECDED type encoder 206 and decoder 216, if one bit is inverted either in the error correction code or in the data read, then the Data RD in data is equal to the Data WR in data because the decoder has corrected the data or the ECC code of the packet read. If two bits are inverted, then the Data RD in data is set to 0 and the ECC Error flag is raised by the decoder. In the case where 3 or more bits are inverted, the result of the decoder 216 is unpredictable.

[0048] [Fig.3] illustrates an example of memory 104 of the integrated circuit of [Fig.l].

[0049] More precisely, the example of [Fig.3] illustrates the memory blocks 107 and 109 in the case where the addressing mode is of the linear type (Linear mode) (case illustrated on the left) and in the case where the addressing mode is of the interleaved type (Interleaved mode) (case illustrated on the right).

[0050] In the case of linear mode, the memory block 107 is filled with data according to system addresses (System Addr) incremented linearly for example from 0x0 to 0x7. The rest of the data is copied with the system addresses 0x8 to OxF in the same way.

[0051] In the case of interlaced mode, the data is for example written with addresses incremented by two. In the example shown, the addresses in the first memory block 107 are 0x0 then 0x2 then 0x4 etc. up to OxE and the addresses in the second memory block 109 are 0x1 then 0x3 then 0x5 etc. up to OxF.

[0052] The firewall defines, in the example represented in linear mode, the data of addresses 0x4, 0x5, 0x6, 0x7 of block 107 (zone 310) and 0x8, 0x9, OxA, OxB to OxB of block 109 (zone 320) as being data to be secured, for example encryption keys.

[0053] When changing an addressing mode, for example from linear addressing mode to interleaved addressing mode, the system addresses are used differently in the memory blocks 107 and 109.

[0054] For each addressing mode, secure address areas are defined and intended for the storage of secure data. Also, non-secure address areas are defined and intended for the storage of non-secure data.

[0055] Some addresses may, in linear mode, be part of a secure area of addresses and, in interleaved mode, be part of an unsecured area of addresses.

[0056] In the example shown, addresses 0x4 and 0x6, as well as 0x9 and OxB, are not included in address zones 310 and 320 defining the secure data, whereas they are in linear mode. When changing the addressing mode, from a linear mode to an interleaved mode, addresses 0x4 and 0x6 as well as 0x9 and OxB thus become accessible, so that a pirate (hacker) could take advantage of this change of mode to access secure data.

[0057] To overcome these problems, it is possible to erase the memory blocks. However, this erasure requires a significant amount of time, particularly in the case of non-volatile memories. In another solution, the error correction code can be based on the data and its address. This nevertheless requires an increase in hardware resources and impacts the execution speed. An alternative solution is to add an additional bit to store the addressing mode used during the write operation, but this results in an increase in the size of the memory 104.

[0058] The embodiments provide a memory system comprising a first logic block configured to perform an exclusive OR (XOR) function of a current value of a data addressing mode and at least one bit of a first data packet comprising an error correction code of a data item to be written, a second data packet, resulting from the first logic block, being stored in one of the memory blocks; and a second logic block configured to perform an exclusive OR function of at least one bit of the second packet as read from said one of the memory blocks and the current value of the addressing mode, when reading the second packet or subsequently thereto, a weight of said at least one bit of the first data packet corresponding to a weight of said at least one bit of the second data packet after reading.

[0059] Thanks to such a memory system, if the addressing mode changes (from a linear mode to an interlaced mode or vice versa), between the writing of the data to be written and its associated error correction code in memory, and the reading of this data with its error correction code, it is possible to detect, with the decoder, an error which will for example prohibit access to the written data. This also makes it possible to make the secure data inaccessible during a change of the addressing mode and this without increasing the memory size.

[0060] Indeed, if the addressing mode changes between writing and reading the data, and the value of the addressing mode is different, at least one error will be contained in the data packet read. In the case where the error correction code is of the SED type, then an error detection flag will be raised, and during reading an error code or a zero value will be returned.

[0061] When the error correcting code is of another type, for example SECDED or DECTED, the logic blocks are then configured to perform operations on two and three bits respectively, so that an error code or a zero value is returned in the event of a change in addressing mode between writing and reading.

[0062] The XOR operation is performed on a first packet which may be the error correcting code or the data to be written or a concatenation of the error correcting code and the data to be written.

[0063] [Fig.4] illustrates an example of a memory system 130 of the integrated circuit of [Fig.l] according to one embodiment.

[0064] The memory system of [Fig.4] is similar to that of [Fig.2] except that the driver circuit 106 comprises a first logic block 406 (XOR one or more bits with md) and a second logic block 416 (XOR one or more bits with md) configured to perform an exclusive OR function (XOR) on at least one chosen bit of what they receive as input. In the case of SED type encoders and decoders 206, 216 then the exclusive OR operation is applied to a single bit. In the case of SECDED type encoders and decoders 206, 216 then the exclusive OR operation is applied to two chosen bits. In the case of DECTED type encoders and decoders 206, 216 then the exclusive OR operation is applied to three chosen bits. The bits chosen and which will undergo the exclusive OR operation are either on the error correcting code, or on the data or on both.

[0065] The first logic block 406 performs the exclusive OR function from the current value of the addressing mode md, i.e. the value md at the time of ECC encoding or until the XOR operation is performed. The exclusive OR function is also performed from at least one bit of the data packet comprising the data to be written Data WR in and its associated error correction code ECCin. The error correction code associated with the data to be written Data WR in is obtained with the encoder 206.

[0066] By way of illustration, in the case where the encoder 206 and the decoder 216 are of the SECDED type, if ECCin=1 11 and Data WR in=0101 then the associated data packet is for example in the form 111_0101 (or 0101_111). If the current addressing mode is for example interleaved and the value 1 is arbitrarily associated with this mode, and if we want the exclusive OR function of the first logic block 406 to be applied to the least significant bit of ECCin 1H and the most significant bit of Data WR in 0 101, then at the output of the first logic block we obtain a data XOR Data WR TO mem=l 101 and an error correcting code XOR ECC WR TO mem=l 10. The data packet at the output of block 406 before writing to one of the memory blocks is then 110_1101.

[0067] The data XOR Data WR TO mem and the ECC code, XOR ECC WR TO mem, resulting from the logic block 406, are either provided separately on the bus 105 or provided on the bus 105 in the form of a data packet, for example in the form 110_l 101 as in the previous example.

[0068] The data XOR Data WR TO mem and the ECC code, XOR ECC WR TO mem, are then stored in one of the memory blocks of the memory 104.

[0069] This data and its associated error code are then read and are called at that time for example Data RD from mem and ECC RD from mem.

[0070] The data Data RD from mem and its associated error code ECC RD from mem which have been read are then used, for example in the form of a packet ECC RD from mem_Data RD from mem at the input of the second logic block 416. The second logic block 416 then performs an exclusive OR (XOR) function of at least one bit of the packet ECC RD from mem_Data RD from mem and the current value of the addressing mode md. The current value md corresponds to the value of the addressing mode when reading the data Data RD from mem and its associated error code ECC RD from mem (or the data packet formed by them), or after this reading at the time of performing the exclusive OR operation for example.

[0071] The exclusive OR function is performed on the same bit(s) as those which were used in the first logic block 406. In other words, the operation of the second logic block 406 applies to the bits of the same weight as those used to apply the exclusive OR function on the data Data WR in and / or on ECCin.

[0072] To return to the previous illustrative example, if the current addressing mode has been changed during or after reading and becomes, for example, linear and the value 0 is arbitrarily associated with this linear mode, the exclusive OR function of the second logic block 416 is applied, for example, to the least significant bit of ECC RD from mem and the most significant bit of Data RD from mem, then, at the output of the second logic block 416, we obtain a data XOR Data RD in=l 101 and the error correcting code XOR ECC RD=110. XOR Data RD in and XOR ECC RD are for example arranged in a data packet at the output of block 416 and in the present example with the form 110_l 101.

[0073] The decoder 216 analyzes the error correction code XOR ECC RD and the data XOR Data RD. At the output of the decoder 216, if the addressing mode md has not been changed between block 206 and block 416, and no write or read error has occurred, the ECC Error flag is not raised and the data Data RD in will be the same as Data WR in. If, on the other hand, as in the illustrative example, the addressing mode md has been changed between block 206 and block 416, then the decoder will raise the ECC Error flag - for example by setting it to 1 - because the error correction code XOR ECC RD and the data XOR Data RD are not consistent with each other. In this case, the Data RD in data is set to 0 for example and an error of the bus error type or a zero value is sent to the processing unit 110. This makes it possible to make the secure data inaccessible when changing the addressing mode without increasing the memory size.

[0074] [Fig.5] illustrates a method of securing the memory system of [Fig.4] according to one embodiment.

[0075] In this example, a first step 502 (Start) signals the start of the security process.

[0076] In a subsequent step 504 (Provide word comprising ECCin from Data to write), the error correction code ECCin is calculated by the encoder 206 from the data to be written Data WR in.

[0077] In a subsequent step 506 (XOR one or more bits of the word with address mode value md), an exclusive OR XOR function is performed of the current value of the data addressing mode md and at least one bit of a first data packet, for example in the form ECCin_Data WR in, comprising the error correction code ECCin and the data Data WR in to be written.

[0078] In a subsequent step 508 (Store word resulting from XOR operation in memory) a second data packet, for example in the form XOR ECC WR TO mem_X0R Data WR TO mem, resulting from the first logical block 406, is stored in one of the memory blocks 107, 109.

[0079] In a subsequent step 510 (XOR one or more bits of read word with address mode value md), an exclusive OR XOR function of at least one bit of the second packet as read from said one of the memory blocks 107, 109, and the current value of the addressing mode md during the reading of the second packet or after this is performed with the second logic block 416. The weight of the bit(s) of the first data packet undergoing the XOR function corresponds to a weight of the bit(s) of the second data packet undergoing the XOR function after reading.

[0080] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, the bit(s) on which the XOR operations are performed are for example only on the ECCin and ECC RD from mem codes, or only on the Data RD from mem and Data WR in data.

[0081] Finally, the practical implementation of the described embodiments and variants is within the reach of the person skilled in the art from the functional indications given above. In particular, as regards the arrangement of the error correction code and the corresponding data, which can be processed either in packet form as in the illustrative example, or individually. Furthermore, the number of bits involved in the logic blocks 406 and 416 are a function of the type of encoding and decoding SED, SECDED, DECTED. On the other hand, other types of codes, other than Hamming or Golay, can be used for the error correction code.

Claims

Claims

1. Memory system comprising: - a memory comprising memory blocks (107, 109); - a first logic block (406) configured to perform an exclusive OR function (XOR) of a current value of an addressing mode (md) of data and at least one bit of a first data packet (ECCin_Data WR in) comprising an error correction code (ECCin) of a data item to be written (Data WR in) or said data item to be written (Data WR in) or said error correction code (ECCin) of a data item to be written (Data WR in) and said data item to be written (Data WR in); a second data packet (XOR ECC WR TO mem_X0R Data WR TO mem), resulting from the first logic block (406), being stored in one of the memory blocks (107, 109);and - a second logic block (416) configured to perform an exclusive OR function (XOR) of at least one bit of the second packet as read from said one of the memory blocks (ECC RD from mem_Data RD from mem) and of the current value of the addressing mode (md) when reading the second packet or after this, a weight of said at least one bit of the first data packet (ECCin_Data WR in) corresponding to a weight of said at least one bit of the second data packet read (ECC RD from mem_Data RD from mem).;

2. The system of claim 1, further comprising an error correction code decoder (216) configured to decode a third data packet (XOR Data RD in_XOR ECC RD) resulting from the second logic block (416).

3. The system of claim 2, further comprising an error correction code encoder (206) configured to calculate said error correction code (ECCin) associated with said data to be written (Data WR in).

4. The system of claim 3, wherein: - the first logic block (406) is configured to perform an exclusive OR function (XOR) from a bit of the first data packet (ECCin_Data WR in); and - the second logic block (416) is configured to perform an exclusive OR function (XOR) from a bit of the second packet as read from said one of the memory blocks (ECC RD from mem_Data RD from mem).

5. System according to claim 4, wherein the error correction code encoder (206) and decoder (216) are of the SED type.

6. System according to claim 3, wherein: - the first logic block is configured to perform an exclusive OR function (XOR) from two bits of the first data packet (ECCin_Data WR in); and - the second logic block is configured to perform an exclusive OR function (XOR) from two bits of the second packet as read from said one of the memory blocks (ECC RD from mem_Data RD from mem); the weight of said two bits of the first data packet (ECCin_Data WR in) corresponding to the respective weight of said two bits of the second data packet after reading (ECC RD from mem_Data RD from mem).

7. System according to claim 6, wherein the error correction code encoder and decoder are of the SECDED type.

8. System according to claim 3, wherein: - the first logic block is configured to perform an exclusive OR function (XOR) from three bits of the first data packet (ECCin_Data WR in); and - the second logic block is configured to perform an exclusive OR function (XOR) from three bits of the second packet as read from said one of the memory blocks (ECC RD from mem_Data RD from mem); the weight of said three bits of the first data packet (ECCin_Data WR in) corresponding to the respective weight of said three bits of the second data packet after reading (ECC RD from mem_Data RD from mem).

9. System according to claim 8, wherein the error correction code encoder and decoder are of the DECTED type.

10. The system of claim 4 or 5, wherein if the error correction code decoder (216) detects an error then the memory system (130) generates an error value (ECC Error).

11. The system of claim 6 or 7, wherein if the error correction code decoder (216) detects two errors then the system generates an error value (ECC Error).

12. A system according to claim 8 or 9, wherein if the decoder of error correction code (216) detects three errors then the memory system generates an error value (ECC Error).

13. System according to any one of claims 1 to 12, wherein the value of the addressing mode (md) corresponds to an interleaved mode or a linear mode of writing data in said memory blocks (107, 109).

14. The system of any one of claims 1 to 13, wherein the first data packet (ECCin_Data WR in) further comprises the data to be written (Data WR in).

15. Method for securing a memory system according to any one of claims 1 to 14, the system being provided with a memory comprising memory blocks (107, 109), the method comprising: - carrying out, with a first logic block (406), an exclusive OR function (XOR) of a current value of an addressing mode (md) of data and of at least one bit of a first data packet (ECCin_Data WR in) comprising an error correction code (ECCin) of a data item to be written (Data WR in) or said data item to be written (Data WR in) or said error correction code (ECCin) of a data item to be written (Data WR in) and said data item to be written (Data WR in); - storing, in one of the memory blocks (107, 109), a second data packet (XOR ECC WR TO mem_X0R Data WR TO mem) resulting from the first logical block;- performing, with a second logic block (416), an exclusive OR function (XOR) of at least one bit of the second packet as read from said one of the memory blocks (ECC RD from mem_Data RD from mem), and of the current value of the addressing mode (md) during the reading of the second packet or after this, a weight of said at least one bit of the first data packet (ECCin_Data WR in) corresponding to a weight of said at least one bit of the second data packet read (ECC RD from mem_Data RD from mem).;

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