Contactless communication device using active load modulation with a dynamic threshold clock signal extraction circuit

Abstract

Active Load Modulation Contactless Communication Device with a Dynamic Threshold Clock Signal Extraction Circuit This description relates to an active load modulation contactless communication device (100) comprising at least: - a clock signal extraction circuit (106) configured to receive a receive signal as input and output a clock signal having a first value when the receive signal is greater than a threshold of the clock signal extraction circuit and a second value when the receive signal is less than the threshold; - a threshold value modification circuit (108) configured to decrease the threshold value when the clock signal value is equal to the first value, or to increase the threshold value when the clock signal value is equal to the second value. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Contactless communication device by active charge modulation provided with a clock signal extraction circuit with dynamic threshold Technical field

[0001] The present description relates generally to the field of wireless communications between a reader and a contactless communication device by active charge modulation, in particular between a reader and such a device emulated in card mode (or CE for “Card Emulation” in English). The present description may relate in particular to the field of contactless communications implemented in NFC technology (“Near Field Communication” in English, or near field communication). Prior art

[0002] Near field communication, or NFC, is a wireless connectivity technology enabling communication over a short distance, for example of the order of ten centimeters, between electronic devices, such as a contactless smart card and a reader, or a CE device (for example a mobile phone or a connected object) and a reader.

[0003] A contactless communication device is a device capable of exchanging information via an antenna with another contactless device, for example a reader, according to a contactless communication protocol.

[0004] An NFC device, which is a contactless device, is a device compatible with NFC technology. NFC technology is an open technology platform standardized in ISO / IEC 18092 and ISO / IEC 21481 but incorporates many already existing standards such as for example the type A and type B protocols defined in ISO-14443 which can be communication protocols usable in NFC technology.

[0005] A CE device may be used to exchange information with another contactless device, for example a contactless reader, using a contactless communication protocol usable in NFC technology.

[0006] When transmitting information between a reader and a CE device or an NFC card, the reader generates an electromagnetic field via its antenna which is generally, according to the standards conventionally used, a sinusoidal wave with a frequency equal to 13.56 MHz. Each of the NFC devices (reader and CE device) transmits data using a modulation scheme, for example amplitude shift keying or ASK (Amplitude Shift Keying) or OOK (On Off Keying).

[0007] Two operating modes are possible: a passive mode, which corresponds to the mode used by an NFC card, or an active mode, which generally corresponds to the mode used by a CE device.

[0008] In passive mode, also called PLM or Passive Load Modulation, only the reader generates the electromagnetic field and the card is then passive. The card antenna modulates the electromagnetic field generated by the reader via a modification of a load connected to the terminals of the card antenna, which modifies the output impedance of the reader antenna due to the magnetic coupling between the two antennas. This results in a change in the amplitudes and / or phases of the voltages and currents present at the reader and card antennas. Information is thus transmitted from the card to the reader by load modulation to the reader antenna currents.

[0009] In the active mode, also called ALM or Active Load Modulation, both the reader and the CE device generate an electromagnetic field. This operating mode is used when the CE device is provided with its own power source, for example a battery.

[0010] Generally, a CE device has a smaller antenna than that of an NFC card, and this is the reason why active load modulation is often used in such a device.

[0011] During active load modulation, the electromagnetic fields emitted by the reader and the CE device are in phase with each other so that the detection sensitivity of the device is not reduced. The CE device may in particular comprise a phase-locked loop, or PLL, and a transmission circuit whose output is electrically coupled to the antenna.

[0012] The CE device can be configured to extract a clock signal from the electromagnetic field emitted by the reader and lock the PLL on the rising or falling edges of this signal. This clock signal extraction is for example carried out by a differential comparator electrically coupled to the output of the passive network of the antenna of the CE device and comprising for example a high-gain amplifier operating in saturation. The output signal of the PLL can then be used to implement a digital conversion making it possible to decode the modulation signal of the reader.

[0013] In order for the CE device to respond to the reader, the response signal from the CE device must be in phase with the electromagnetic field emitted by the reader. The clock signal extracted from the electromagnetic field emitted by the reader must therefore follow the phase and frequency of the electromagnetic field emitted by the reader, and must not contain parasitic variations.

[0014] In the case of an OOK type modulation, the electromagnetic field comprising the modulation signal alternates between a high state and a low state. However, noise may be present in the electromagnetic field received in the CE device when the modulation signal is in the low state, due to the coupling between the reader and the CE device. The clock signal extracted from this field may in this case contain parasitic variations, or instabilities, which can cause phase shifts and errors in the resulting output signal. Summary of the invention

[0015] There is a need to propose a solution to address the problems encountered with existing solutions.

[0016] One embodiment overcomes all or part of the drawbacks of known solutions and proposes a contactless communication device by active charge modulation, comprising at least:

[0017] - a clock signal extraction circuit configured to receive as input a receiving signal and outputting a clock signal having a first value when the receiving signal is greater than a threshold of the clock signal extraction circuit and having a second value when the receiving signal is less than the threshold;

[0018] - a threshold value modification circuit, configured to reduce the value of the threshold when the clock signal value is equal to the first value, or to increase the threshold value when the clock signal value is equal to the second value.

[0019] According to a particular embodiment, the threshold of the clock signal extraction circuit has a zero value.

[0020] According to a particular embodiment, the clock signal extraction circuit and the threshold value modification circuit are configured such that the reduced threshold value is between 10% and 20% of a minimum amplitude of the reception signal.

[0021] According to a particular embodiment, the clock signal extraction circuit comprises a differential pair.

[0022] According to a particular embodiment, the clock signal extraction circuit further comprises a first current mirror electrically coupled in parallel to the differential pair.

[0023] According to a particular embodiment, the threshold value modification circuit is configured to unbalance a bias of the first current mirror of the clock signal extraction circuit or a bias of the differential pair and the first current mirror of the clock signal extraction circuit.

[0024] According to a particular embodiment, the clock signal extraction circuit further comprises an amplifier, one input of which is electrically coupled to one of the branches of the first current mirror.

[0025] According to a particular embodiment, the circuit for modifying the threshold value comprises a second current mirror electrically coupled to one of the branches of the first current mirror and switches configured to electrically couple the second current mirror to an electrical supply potential of the device and to a current source, itself coupled to a reference electrical potential of the device, according to the value of the clock signal.

[0026] According to a particular embodiment, the threshold value modification circuit comprises a transistor and a switch configured to electrically couple the transistor of the threshold value modification circuit in parallel to a transistor of the differential pair when the value of the clock signal is equal to the first value or the second value.

[0027] According to a particular embodiment, the device further comprises a phase-locked loop, one input of which is electrically coupled to an output of the clock signal extraction circuit.

[0028] According to a particular embodiment, the device may further comprise:

[0029] - a digital conversion circuit comprising an electrically coupled input to an output of the phase-locked loop;

[0030] - a transmission circuit comprising an output electrically coupled to the antenna and on which a modulation signal in phase with the reception signal is intended to be delivered, and comprising a first input electrically coupled to an output of the phase-locked loop and a second input electrically coupled to an output of the digital conversion circuit. Brief description of the drawings

[0031] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular exemplary embodiments given without limitation in relation to the attached figures among which:

[0032] - [Fig.l] schematically represents an example of a communication device contactless by active charge modulation communicating with a contactless reader, according to a particular embodiment;

[0033] - [Fig.2] schematically represents the operation of an extraction circuit of clock signal and of a circuit for modifying the value of the threshold of the extraction circuit in a contactless communication device by active load modulation, according to a particular embodiment;

[0034] - [Fig.3] schematically represents a first example of the realization of a clock signal extraction circuit and a circuit for modifying the value of the extraction circuit threshold;

[0035] - [Fig.4] schematically represents a second example of the embodiment of a clock signal extraction circuit and a circuit for modifying the threshold value of the extraction circuit;

[0036] - [Fig.5] schematically represents a variant of the second example of rea lization of a clock signal extraction circuit and a circuit for modifying the threshold value of the extraction circuit. Description of the embodiments

[0037] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0038] For the sake of clarity, only the steps and elements useful for understanding the described embodiments and examples have been shown and are detailed. In particular, the production of the various elements and circuits (adaptation circuit, phase-locked loop, digital conversion circuit, transmission circuit, etc.) of the device is not detailed. Those skilled in the art will be able to produce the various functions of the device in detail from the functional description given here.

[0039] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0040] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0041] An example of a contactless communication device 100 by active load modulation according to a particular embodiment is described below in connection with [Fig.l],

[0042] The device 100 is of the NFC type, that is to say is configured to use a communication protocol compatible with NFC technology. In the example described, the device 100 corresponds to a device emulated in card mode (CE). In [Fig.l], the device 100 is shown during communication with a contactless reader 200 of the NFC type.

[0043] In the described embodiment, the device 100 and the reader 200 communicate with each other using OOK type modulation. Thus, the electromagnetic field emitted by the reader 200 and received by the device 100 is caused to change state, and to be either in a high state, transmitted in the form of a sinusoidal signal for example of frequency equal to 13.56 MHz (carrier frequency), or in a low state transmitted in the form of a zero signal.

[0044] In the exemplary embodiment described, the device 100 comprises an antenna 102 intended to exchange data with an antenna 202 of the reader 200 via the emission of electromagnetic fields by these antennas 102, 202 and the magnetic coupling between these antennas 102, 202.

[0045] In the particular configuration shown in [Fig.l], the device 100 further comprises an adaptation circuit 104 electrically coupling the antenna 102 to the other elements of the device 100. The circuit 104 may comprise passive components, and may be used in particular to adapt the impedance of the antenna 102 to interface the input and output signals of the antenna 102.

[0046] The device 100 further comprises a clock signal extraction circuit 106 configured in particular to receive as input a reception signal originating from a magnetic field intended to be received by the antenna 102 and delivered as output from the adaptation circuit 104. The circuit 106 is also configured to deliver as output a clock signal having a first value, for example “1” or high state, when the reception signal is greater than a value of a threshold of the circuit 106 and having a second value, for example “0” or low state, when the reception signal is less than the value of the threshold of the circuit 106. In this example, the circuit 106 therefore forms a comparator delivering as output a clock signal extracted from the reception signal applied to its input.

[0047] In the example described, when the signal received by the antenna 102 corresponds to a high state transmitted in the form of a sinusoidal signal, the value of the clock signal delivered at the output of the circuit 106 alternates between the first and second values ​​at a frequency equal to the frequency of the sinusoidal signal throughout the duration of this high state. When the signal received by the antenna 102 corresponds to a low state transmitted in the form of a zero signal, the value of the clock signal delivered at the output of the circuit 106 is also zero throughout the duration of this low state.

[0048] The device 100 also comprises a circuit 108 for modifying the value of the threshold of the circuit 106, configured to reduce the value of the threshold when the value of the clock signal delivered at the output of the circuit 106 is equal to the first value, or to increase the value of the threshold when the value of the clock signal is equal to the second value. In the example of [Fig.l], an input of the circuit 108 is electrically coupled to the output of the circuit 106, and an output of the circuit 108 is electrically coupled to an input of the circuit 106.

[0049] In the exemplary embodiment described, the device 100 further comprises a phase-locked loop 110, or PLL, one input of which is electrically coupled to the output of circuit 106. The PLL 110 is intended to receive as input the clock signal emitted at the output of circuit 106 and to deliver as output a signal synchronized and in phase with the clock signal received at its input.

[0050] The device 100 may also comprise a digital conversion circuit 112 comprising an input electrically coupled to an output of the PLL 110. The circuit 112 is notably intended to decode the signal transmitted by the reader 200.

[0051] In the described embodiment, the device 100 further comprises a transmission circuit 114 comprising an output electrically coupled to the antenna 102 and on which a modulation signal intended to be transmitted by the antenna 102 and in phase with the reception signal is intended to be delivered. The circuit 114 may further comprise a first input electrically coupled to an output of the PLL 110 and a second input electrically coupled to an output of the digital conversion circuit 112.

[0052] In the diagram of [Fig.l], only some of the elements of the device 100 are shown. The device 100 comprises, in addition to those visible in [Fig.l], other circuits and elements not described here.

[0053] The operation of an exemplary embodiment of the circuit 106 and of the circuit 108 for modifying the value of the threshold of the circuit 106 is described below in connection with [Fig.2],

[0054] Reference 120 designates a first example of reception signal received at the input of circuit 106. This first example of reception signal can be obtained when the antennas of reader 200 and device 100 are close and strongly coupled to each other, and has for example a peak-to-peak amplitude of the order of 1 V.

[0055] Reference 122 designates a square signal representing the clock signal used by the reader 200 for transmitting data. The phase and frequency of the signal 120 are therefore similar to those of the signal 122 used to obtain the unmodulated electromagnetic field emitted by the reader 200.

[0056] In the exemplary embodiment described in connection with [Fig. 2], the circuit 106 is configured such that the clock signal delivered at the output of the circuit 106 is in the state “1”, or high state, when the reception signal is greater than the threshold of the circuit 106 (the value of which is equal to 0 V in this example), and is in the state “0”, or low state, when the reception signal is less than the threshold of the circuit 106. In addition, in this exemplary embodiment, the circuit 108 is configured to reduce the value of the threshold of the circuit 106 when the clock signal delivered at the output of the circuit 106 is in the state “1”. For example, the reduced value of the threshold may be between 10% and 20% of the minimum amplitude of the reception signal (which is for example of the order of 0.2 V).

[0057] Reference 124 designates the clock signal obtained at the output of circuit 106 when reception signal 120 is applied at the input of circuit 106.

[0058] In this example, because the threshold value of the circuit 106 is equal to 0 when the clock signal delivered by the circuit 106 is in the state “0”, the transition from the state “0” to the state “1” of the clock signal 124 occurs at the same time as the transition from a negative value to a positive value of the reception signal 120. On the other hand, because the threshold value of the circuit 106 is reduced when the clock signal delivered by the circuit 106 is in the state “1”, the transition from the state “1” to the state “0” of the clock signal 124 occurs with a delay relative to the transition from a positive value to a negative value of the reception signal 120. When the peak-to-peak amplitude of the signal 120 is large (as is the case here), this delay is very small.

[0059] Reference 126 designates a second example of reception signal received at the input of circuit 106. This second example of reception signal can be obtained when the antennas of reader 200 and device 100 are distant and weakly coupled to each other, and has for example a peak-to-peak amplitude of the order of 0.2 V.

[0060] Reference 128 designates the clock signal obtained at the output of circuit 106 when reception signal 126 is applied at the input of circuit 106.

[0061] As when the reception signal 126 is applied to the input of the circuit 106, the transition from the state "0" to the state "1" of the signal 128 occurs at the same time as the transition from a negative value to a positive value of the signal 126, and the transition from the state "1" to the state "0" of the signal 128 occurs with a delay relative to the transition from a positive value to a negative value of the signal 126. Because the peak-to-peak amplitude of the signal 126 is low, this delay is greater than in the case of a reception signal with a high peak-to-peak amplitude such as the signal 120. In [Fig. 2], this greater delay results in a state "1" of the signal 128 of longer duration at each period of the signal 128.

[0062] Whether the amplitude of the reception signal is high or low, the lowering of the threshold of the circuit 106 carried out by the circuit 108 when the clock signal delivered by the circuit 106 is in the state "1" makes it possible to avoid having, in the clock signal delivered by the circuit 106, the appearance of parasitic variations or switching, or instabilities, corresponding for example to self-oscillations, when the information transmitted by the reception signal is in the low state, such parasitic variations being able to be generated due to glitches, or failures, generated by the noise in the reception signal at that moment in the absence of the circuit 108. In [Fig. 2], parasitic transient phenomena correspond to the attenuation occurring on the reception signal due to the fact that the transition from the high state to the low state of the information transmitted on the reception signal is not instantaneous.This lowering of the threshold of the circuit 106 carried out by the circuit 108 when the clock signal is at state “1” also makes it possible to avoid parasitic switching of the clock signal delivered by the circuit 106 when noise is present in the reception signal, for example when its value is close to 0.

[0063] Furthermore, because the threshold value is unchanged when the clock signal is in the “0” state, the transition from the “0” state to the “1” state of the clock signal obtained at the output of the circuit 106 occurs without delay relative to the transition from a negative value to a positive value of the reception signal. Thus, when the PLL 110 is synchronized relative to the rising edges of the signal applied to its input (which corresponds to the clock signal delivered at the output of the circuit 106), this absence of delay makes it possible to ultimately have a response signal from the device 100 which is in phase with the electromagnetic field emitted by the reader 200. Furthermore, the delay obtained in the output clock signal of the circuit 106 during the transition from a positive value to a negative value of the reception signal has no impact when the PLL 110 is synchronized relative to the rising edges of the clock signal.

[0064] In the above examples, the circuit 108 is configured to reduce the threshold value of the circuit 106 when the clock signal is in the state “1”. In this case, when the clock signal is in the state “0”, the circuit 108 does not modify the threshold value of the circuit 106 which operates at its nominal precision, which makes it possible not to degrade the intrinsic phase shift of the device 100. In this example, only the falling edges of the clock signal are affected by a phase shift which has no impact when the PLL 110 is synchronized with respect to the rising edges of the clock signal.

[0065] According to another example, for example when the PLL 110 is synchronized with respect to the falling edges of the clock signal, the circuit 108 can be configured to increase the threshold value of the circuit 106 when the clock signal is in the “0” state. In this case, when the clock signal is in the “1” state, the circuit 108 does not modify the threshold value of the circuit 106 which operates at its nominal precision (threshold value for example equal to 0 V), which makes it possible not to degrade the intrinsic phase shift of the device 100. In this case, only the rising edges of the clock signal are affected by a phase shift which has no impact when the PLL 110 is synchronized with respect to the falling edges of the clock signal.

[0066] A first example of embodiment of circuit 106 and circuit 108 is described below in connection with [Fig.3].

[0067] In this first example, the circuit 106 comprises a differential pair formed of two first transistors 130, 132 each comprising a first of their source / drain electrodes electrically coupled to a first current source 134. In the example of [Fig. 3], the first transistors 130, 132 are for example NMOS transistors and their first source / drain electrode corresponds to the source electrode. In this first example, the reception signal received at the input of the circuit 106 is applied to the gate of the transistor 130, and the signal opposite to the reception signal is applied to the gate of the transistor 132.

[0068] The circuit 106 according to this first example further comprises a first mirror of current comprising two second transistors 136, 138 each comprising a first of their source / drain electrodes electrically coupled to a second of the source / drain electrodes of the first two transistors 130, 132. In the example of [Fig.3], the second transistors 136, 138 are for example NMOS transistors and their first source / drain electrode corresponds to the drain electrode, and the second of the source / drain electrodes of the first transistors 130, 132 correspond to the drain electrodes. The first of the source / drain electrodes of the second transistor 136 is also coupled to the gate of the second transistor 136.The first of the source / drain electrodes of the second transistors 136, 138 are also electrically coupled to second current sources 140, 142 ensuring the polarization of this first current mirror and providing the current necessary for the correct polarization of the differential pair formed by the first two transistors 130, 132.

[0069] The circuit 106 according to this first example further comprises a high-gain amplifier 144 whose input is electrically coupled to the first source / drain electrode of the transistor 138, and whose output forms the output of the circuit 106 on which the clock signal is intended to be delivered. The amplifier 144 can operate in saturation so that the clock signal obtained corresponds to a square wave.

[0070] The differential pair formed by the first two transistors 130, 132 makes it possible to convert the potential difference applied to the gates of the transistors 130, 132 into a current difference appearing at the junction of the input of the amplifier 144 with one of the branches of the first current mirror formed by the two second transistors 136, 138 (the one comprising the transistor 138 in [Fig. 3]). The use of the first current mirror therefore makes it possible to deliver at the input of the amplifier 144 a voltage whose value is proportional to this current difference. Finally, amplifier 144, which has high gain and operates in saturation, converts the voltage applied to its input into a square signal (clock signal in state “1” when the input voltage of amplifier 144 is positive, and in state “0” when the input voltage of amplifier 144 is negative).

[0071] The circuit 108 may be configured to unbalance a bias of the first current mirror formed by the second transistors 136, 138.

[0072] In this first example, the circuit 108 comprises third transistors 146, 148 forming a second current mirror electrically coupled to one of the branches of the first current mirror formed by the second transistors 136, 138. In the example of [Fig. 3], the third transistors 146, 148 are for example PMOS transistors.

[0073] The circuit 108 according to this first example also comprises a first switch 150 configured to electrically couple or not the electrical potential supply of the device 100 to the gates of the third transistors 146, 148 forming the second current mirror, and a second switch 152 configured to electrically couple or not the second current mirror to the reference electrical potential of the device 100 through a third current source 154.

[0074] In this first example, the circuits 106 and 108 can be electrically powered between a first electrical potential V1 (applied to the first switch 150, the third transistors 146, 148 and the second current sources 140, 142) and a second electrical potential V2 (applied to the third current source 154, the second transistors 136, 138 and the first current source 134). By choosing these electrical potentials such that VI = -V2, the common mode voltage, corresponding to the midpoint of the amplifier, is zero. More generally, the common mode voltage Vmc is expressed by the equation:

[0075] [Math.l] Vmc = (V1+V2) / 2

[0076] In the example shown in [Fig. 3], the first switch 150 is in the open state when the clock signal delivered by the circuit 106 and applied to its control input is in the “1” state, and is in the closed state when the clock signal is in the “0” state. On the other hand, the second switch 152 is in the open state when the clock signal applied to its control input is in the “0” state, and is in the closed state when the clock signal is in the “1” state.

[0077] Thus, when the clock signal is at state "0", circuit 108 has no impact on the threshold value of circuit 106 (circuit 106 operates as if circuit 108 were absent). No current flows through the current mirror of circuit 108 shown in [Fig.3].

[0078] When the clock signal is in state “1”, the connection of the circuit 108 to one of the branches of the first current mirror formed by the second transistors 136, 138 modifies the threshold value of the circuit 106. Indeed, when the first switch 150 is in the open state and the second switch 152 is in the closed state, the electrical coupling of the circuit 108 to one of the branches of the first current mirror adds an additional current in this branch compared to the other branch of the first current mirror. This current asymmetry in the branches of the first current mirror is found at the junction between the input of the amplifier 144 and one of the branches of the differential pair, which generates an offset, or shift, of the threshold value of the circuit 106.

[0079] The voltage at the input of the amplifier 144 is proportional to the difference in currents (il40 - il30) - (il42 - il32), with il30, il40, il32 and il42 corresponding to the currents flowing in the components 130, 140, 132 and 142 respectively. Thus, the modification of the threshold voltage of the circuit 106 is obtained thanks to the difference in current between the source formed by the current source 140 + circuit 108 and the source 142.

[0080] When the circuit 108 is inactive (first switch 150 in the closed state), the bias current flowing in the drain of the second transistor 136 is equal to the current supplied by the current source 140 from which the bias current flowing in the transistor 130 is subtracted, and which is then equal to the current supplied by the current source 142 from which the bias current flowing in the transistor 132 is subtracted. The threshold voltage of the circuit 106 is then not modified.

[0081] When the circuit 108 is active (first switch 150 in the open state), the bias current flowing in the drain of the second transistor 136 is equal to the current supplied by the current source 140 from which the bias current flowing in the transistor 130 is subtracted, and to which the current supplied by the circuit 108 is added. The current supplied by the current source 140 is in this case no longer equal to that supplied by the current source 142 from which the bias current flowing in the transistor 132 is subtracted, which causes the modification of the threshold voltage of the circuit 106.

[0082] Alternatively, the circuit 108 according to this first example can be configured to increase the threshold value of the circuit 106 when the clock signal is in the state “0”, and not to modify the threshold value of the circuit 106 when the clock signal is in the state “1”. The circuit 108 according to this alternative comprises for example the same elements as those shown in [Fig. 3], with the exception of the first switch 150 which is in this case configured to be in the closed state when the clock signal applied to its control input is in the state “1”, and to be in the open state when the clock signal is in the state “0”. In this alternative, the second switch 152 is also configured such that it is in the closed state when the clock signal applied to its control input is in the state “0”, and in the open state when the clock signal is in the state “1”. Furthermore, in this variant, compared to the example previously described in connection with [Fig.3], the output of circuit 108 is not electrically coupled to the branch of the first current mirror formed by transistor 136 but is electrically coupled to the output branch of the first current mirror formed by transistor 138, and therefore to the input of amplifier 144.

[0083] A second example of embodiment of circuit 106 and circuit 108 is described below in connection with [Fig.4].

[0084] In this second example, the circuit 106 comprises the same components as those of the circuit 106 of the first embodiment example previously described.

[0085] The circuit 108 according to this second example comprises a fourth transistor 156 and a switch 158 configured to electrically couple or not the fourth transistor 156 in parallel with the transistor 132 of the circuit 106. More particularly, in In this example, switch 158 is configured to be in the open state when the clock signal is in the "0" state, and to be in the closed state when the clock signal is in the "1" state.

[0086] In this second example, an unbalancing of one of the branches of the differential pair is achieved by connecting the fourth transistor 156 in parallel with the transistor 132, increasing the transconductance of the transistor seen at this branch of the differential pair, and modifying the value of the threshold of the circuit 106.

[0087] Alternatively, the circuit 108 according to this second example can be configured to increase the threshold value of the circuit 106 when the clock signal is in the state “0”, and not to modify the threshold value of the circuit 106 when the clock signal is in the state “1”. The circuit 108 according to this variant comprises for example the same elements as those shown in [Fig. 4], with the exception of the fourth transistor 156 and the switch 158 which is configured to electrically couple or not the fourth transistor 156 in parallel with the transistor 130 of the circuit 106, the switch 158 being configured to be in the closed state when the clock signal applied to its control input is in the state “0”, and to be in the open state when the clock signal is in the state “1”. Such a variant of the circuits 106 and 108 is shown in [Fig. 5]

[0088] In the example of circuit 106 described above in connection with FIGS. 3 to 5, it is possible to modify the value of the threshold of the circuit 106 by modifying the values ​​of the currents delivered by each of the current sources 140, 142. Thus, when the currents delivered by the sources 140, 142 are equal, the value of the nominal threshold (i.e. without the intervention of the circuit 108) of the circuit 106 may be equal to 0. When the current delivered by the source 140 is greater than that delivered by the source 142, the value of the nominal threshold of the circuit 106 may be less than 0. When the current delivered by the source 140 is less than that delivered by the source 142, the value of the nominal threshold of the circuit 106 may be greater than 0.

[0089] In the various examples previously described, circuit 108 and circuit 106 can be seen as together forming a dynamic threshold comparator, in which a variation of the threshold is present only when the output signal of the comparator is in the high or low state.

[0090] In the examples of figures 3 and 4 previously described, each of the source / drain electrodes of one of the transistors can correspond to the source electrode or the drain electrode of this transistor, depending on the type, or the conductivity, n or p of the transistor.

[0091] Furthermore, one or more components different from the circuit 106 and / or the circuit 108 described above may be used to perform functions similar to those described.

[0092] In the various embodiments previously described, each of the com- mutators 150, 152, 158 can correspond to a MOS transistor.

[0093] In the various embodiments, the state “1” of a signal may correspond to an amplitude equal to the supply voltage of the device 100, and the state “0” of a signal may correspond to an amplitude equal to the reference potential of the device 100, for example the ground whose electrical potential is zero.

[0094] In the above description, the device 100 corresponds to a contactless communication device by active charge modulation which is, during communication with a reader, emulated in card mode. The device 100 may be provided with functionalities other than those described above. The device 100 may correspond, for example, to a mobile telephone or a connected object such as a watch.

[0095] Various exemplary embodiments and variations have been described. Those skilled in the art will understand that certain features of these various exemplary embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0096] Finally, the practical implementation of the exemplary embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Device (100) for contactless communication by active load modulation, comprising at least: - a clock signal extraction circuit (106) configured to receive as input a reception signal and deliver as output a clock signal having a first value when the reception signal is greater than a threshold of the clock signal extraction circuit (106) and having a second value when the reception signal is less than the threshold; - a circuit (108) for modifying the threshold value, configured to reduce the threshold value when the value of the clock signal is equal to the first value, or to increase the threshold value when the value of the clock signal is equal to the second value.

2. Device (100) according to one of the preceding claims, wherein the threshold of the clock signal extraction circuit (106) has a zero value.

3. Device (100) according to one of the preceding claims, in which the clock signal extraction circuit (106) and the circuit (108) for modifying the threshold value are configured such that the reduced threshold value is between 10% and 20% of a minimum amplitude of the reception signal.

4. Device (100) according to one of the preceding claims, wherein the clock signal extraction circuit (106) comprises a differential pair (130, 132).

5. The device (100) of claim 4, wherein the clock signal extraction circuit (106) further comprises a first current mirror (136, 138) electrically coupled in parallel to the differential pair (130, 132).

6. The device (100) of claim 5, wherein the threshold value modification circuit (108) is configured to unbalance a bias of the first current mirror (136, 138) of the clock signal extraction circuit (106) or a bias of the differential pair (130, 132) and the first current mirror (136, 138) of the clock signal extraction circuit (106).

7. Device (100) according to one of claims 5 or 6, wherein the clock signal extraction circuit (106) further comprises an amplifier (144) having an input electrically coupled to one of the branches of the first current mirror (136, 138).

8. Device (100) according to one of claims 4 to 7, in which the circuit (108) for modifying the threshold value comprises a second current mirror (146, 148) electrically coupled to one of the branches of the first current mirror (136, 138) and switches (150, 152) configured to electrically couple the second current mirror (146, 148) to an electrical supply potential of the device (100) and to a current source, itself coupled to a reference electrical potential of the device (100), according to the value of the clock signal.

9. Device (100) according to one of claims 4 to 7, wherein the threshold value modification circuit (108) comprises a transistor (156) and a switch (158) configured to electrically couple the transistor (156) of the threshold value modification circuit (108) in parallel to a transistor (130) of the differential pair (130, 132) when the value of the clock signal is equal to the first value or the second value.

10. Device (100) according to one of the preceding claims, further comprising a phase-locked loop (110) having an input electrically coupled to an output of the clock signal extraction circuit (106).

11. Device (100) according to claim 10, further comprising: - a digital conversion circuit (112) comprising an input electrically coupled to an output of the phase-locked loop (110); - a transmission circuit (114) comprising an output electrically coupled to the antenna (102) and on which a modulation signal in phase with the reception signal is intended to be delivered, and comprising a first input electrically coupled to an output of the phase-locked loop (110) and a second input electrically coupled to an output of the digital conversion circuit (112).

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