Method for manufacturing a resistive memory cell of the OxRAM type and associated OxRAM type memory cell

Abstract

The invention relates to a method for manufacturing an OxRAM resistive memory cell, comprising the following steps: - formation of a lower electrode in TiN, - first implantation of Si atoms in the lower electrode with a first implantation dose and a first implantation acceleration voltage, said first implantation dose being strictly positive and strictly less than 0.7.1014 cm-2, - second implantation of Si atoms in the lower electrode with a second implantation dose and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, said second implantation dose being strictly positive and strictly less than 0.6.1014 cm-2, the first and second accelerating voltages being chosen to obtain an implantation profile following the first and second implantations exhibiting a maximum Si concentration at a depth between 1 and 3 nm from the upper surface of the lower electrode, - deposition of an active layer on the implanted lower electrode, - deposition of an upper electrode on the active layer. Figure to be published with the abbreviation: None.

Description

Title of the invention: Method for manufacturing a resistive memory cell of the OxRAM type and associated OxRAM type memory cell. Technical field

[0001] The present invention relates generally to the field of microelectronics. It relates more particularly to the field of non-volatile resistive memories of the filamentary type.

[0002] In particular, the present invention relates to a method for manufacturing an OxRAM-type resistive memory cell. It also relates to such an OxRAM-type resistive memory cell obtained by the manufacturing method. STATE OF THE ART

[0003] Resistive memories, in particular oxide-based resistive memories (or OxRAM, for "Oxide-based Random Access Memories" according to the commonly used Anglo-Saxon acronym), are non-volatile memories intended to replace Flash-type memories. In addition to a high integration density, they exhibit high operating speed and good compatibility with the manufacturing processes currently used in the microelectronics industry, in particular with the back-end-of-line (BEOL, for "Back-End Of Line" according to the commonly used Anglo-Saxon acronym) process of CMOS technology (for "Complementary Metal Oxide Semiconductor" according to the commonly used Anglo-Saxon acronym).

[0004] OxRAM resistive memories comprise a multitude of memory cells, also called memory points. Each OxRAM memory cell consists of a MIM (Metal-Insulator-Metal) capacitor comprising an active material of variable electrical resistance, generally a transition metal oxide (e.g., HfO₂, Ta₂O₅, TiO₂...), arranged between two metallic electrodes. The memory cell switches reversibly between two resistance states, which correspond to logic values ​​"0" and "1" used to encode a bit of information. In some cases, more than two resistance states can be generated, making it possible to store several bits of information in the same memory cell.

[0005] Information is written to the memory cell by switching it from a highly resistive state (or HRS, for "High Resistance State," according to the commonly used Anglo-Saxon acronym), also called the "OFF" state, to a low resistive state (or LRS, for "Low Resistance State"), or the "ON" state. Conversely, for erasing the information from the memory cell, it is switched from the low resistance state ("OFF") to the high resistance state ("ON").

[0006] The change in resistance of the memory cell is governed by the formation and breaking of a conductive filament with a nanometric cross-section between the two electrodes. This conductive filament is created by the presence of oxygen vacancies in the active layer of the memory cell. By modifying the potentials applied to the electrodes, it is possible to change the distribution of the filament, and thus modify the electrical conduction between the two electrodes. In the active layer, the electrically conductive filament is either broken or, conversely, reformed to vary the resistance level of the memory cell during write and reset cycles of this cell (SET operations, when the filament is reformed resulting in the LRS state, and RESET operations resulting in the HRS state, when the filament is broken again by applying a SET voltage, VSEt, or a RESET voltage, VRESEt, to the electrode terminals, respectively).

[0007] Immediately after its manufacture, the resistive memory cell is in a blank state characterized by a very high (so-called initial) resistance. This initial resistance is much higher than the cell's resistance when it is in its highly resistive state. The oxide layer is indeed insulating in its initial state. For the memory cell to be usable, a so-called "forming" step must be performed. This step consists of a partially reversible breakdown of the oxide to generate the conductive filament for the first time (and thus place the memory cell in its low-resistance state). After this breakdown, the initially insulating oxide layer becomes active, and the cell can switch between the low-resistance and high-resistance states through erase and write operations.The forming stage is accomplished by applying between the two electrodes of the memory cell a voltage (called "forming") of a value much higher than the nominal operating voltage of the memory cell (used during subsequent write-erase cycles), for example a voltage of around 2.5 V for a nominal voltage of around 1.5 V.

[0008] The endurance of OxRAM memory cells is a crucial requirement, particularly for certain applications requiring very high endurance, beyond 1000 cycles, or even up to 10,000 cycles (a cycle is defined as a write / erase operation, and endurance as the ability to distinguish an HRS state from an LRS state beyond a given number of cycles). Summary of the invention

[0009] The present invention therefore aims to improve OxRAM type resistive memory cells, in particular by improving their endurance.

[0010] The invention then relates to a method for manufacturing a resistive memory cell of the OxRAM type, comprising the following steps: - formation of a lower electrode in titanium nitride,

[0011] - first implantation of silicon atoms in the lower electrode with a first dose of silicon implantation and a first implantation acceleration voltage, said first dose of silicon implantation being strictly positive and strictly less than 0.7 x 10¹⁴ cm²,

[0012] - second implantation of silicon atoms in the lower electrode with a second dose of silicon implantation and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, said second dose of silicon implantation being strictly positive and strictly less than 0.6 x 10¹⁴ cm²,

[0013] the first and second accelerating voltages being chosen to have an implantation profile following the first and second implantation exhibiting a maximum silicon concentration at a depth of between 1 and 3 nm from the upper surface of the lower electrode,

[0014] - deposition of an active layer on the implanted lower electrode,

[0015] - deposition of a top electrode on the active layer.

[0016] Surprisingly, doping the lower TiN electrode of the OxRAM cell with silicon atoms significantly improves the cell's endurance under certain silicon implantation conditions in the TiN. This unexpected technical effect requires, firstly, two implantations: one at a lower silicon accelerating voltage to implant the silicon on the surface of the lower electrode of the OxRAM cell, and the other at a higher silicon accelerating voltage to implant the silicon deeper within the lower electrode. It also requires a specific implantation profile in the lower electrode with a maximum silicon concentration at a depth of between 1 and 3 nm from the upper surface of the lower electrode.We will see later that, under such conditions, the bit error rate (BER) on a set of memory cells obtained by the process according to the invention decreases with the number of cycles, whereas it tends to increase for other types of cells and to exhibit unsatisfactory values ​​for applications requiring high endurance. The lower the bit error rate, the better the LRS and HRS states are distinguished at the scale of a memory cell matrix.

[0017] By definition, this error rate corresponds to the percentage of memory cells in the set of memory cells considered that will not exhibit satisfactory properties.

[0018] It should be noted that the order of the first and second implantations can be reversed so that it is possible to perform the first implantation before the second or vice versa. Preferably, however, the first implantation is performed before the second implantation.

[0019] In addition to the characteristics mentioned in the preceding paragraphs, the manufacturing process according to the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • The first and second acceleration voltages are chosen to have an implantation profile following the first and second implantation exhibiting a maximum silicon concentration at a depth between 1 and 1.6 nm from the upper surface of the lower electrode and an implantation profile width at half the value of the maximum silicon implantation concentration between 1.6 nm and 2 nm. • The first and second acceleration voltages are chosen to have an implantation profile following the first and second implantation exhibiting a maximum silicon concentration at a depth between 1.1 and 1.5 nm from the top surface of the lower electrode and an implantation profile width at half the value of the maximum silicon implantation concentration between 1.7 nm and 1.9 nm. • The deposition of the upper electrode onto the active layer includes: • The deposition of a first conductive layer, in contact with the active layer and chosen to create oxygen vacancies in the active layer, and • The deposition of a second conductive layer placed on top of the first conductive layer. • The material of the first conductive layer is titanium and the conductive material of the second conductive layer is titanium nitride. • the first acceleration voltage is between 0.3 kV and 0.7 kV and the second acceleration voltage is between 1 kV and 2 kV. • the first acceleration voltage is equal to 0.5 kV and the second acceleration voltage is equal to 1.5 kV. • the first dose of silicon implantation is equal to 0.5.1014cm2 and the second dose of silicon implantation is equal to 0.3.1014cm2. • The deposition of the active layer onto the implanted lower electrode involves the following steps: • deposition of a layer of active material on the implanted lower electrode, • deposition of a dielectric oxide layer on the active material layer, • implantation of silicon atoms through the dielectric oxide layer, the implantation dose and implantation acceleration voltage being chosen so that the silicon atoms are implanted at least partially in the active material layer. • The active material is hafnium dioxide based. • The dielectric oxide is based on aluminum oxide. • the silicon implantation step through the dielectric oxide layer is implemented at an implantation acceleration voltage of between 1.5 and 3.5 kilovolts, and preferably equal to 2.5 kV, and a silicon implantation dose of between 1015cm2 and 5.1015cm2, and preferably equal to 2.1015cm2. • The material of the first conductive layer is titanium and the conductive material of the second conductive layer is titanium nitride. • The thickness of the lower titanium nitride electrode is chosen between 10 and 200 nm.

[0020] The invention also relates to a resistive memory cell of the OxRAM type that can be obtained by the process according to the invention.

[0021] At this stage, it is not possible to structurally characterize the OxRAM-type resistive memory cell according to the invention other than by its manufacturing process. However, the manufacturing process according to the invention gives the OxRAM-type memory cell according to the invention particularly advantageous endurance properties compared to those of prior art OxRAM-type resistive cells. BRIEF DESCRIPTION OF THE FIGURES

[0022] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which:

[0023] Figure 1 represents, in the form of a flowchart, the different steps of the process according to the invention.

[0024] Figures [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7] and [Fig.8] represent the different stages of the process of [Fig.1],

[0025] Figure 9 represents the different implantation profiles in the lower electrode of the OxRAM-type memory cell according to the invention,

[0026] Figure 10 represents the BER error rate as a function of the number of cycles for different categories of OxRAM type memory cells, including the memory cells according to the invention.

[0027] Figures [Fig. 11] and [Fig. 12] represent the evolution of the fraction of memory cells requiring one or more programming repetitions, in set and reset, as a function of the number of cycles.

[0028] For clarity, identical or similar elements are identified by identical reference signs throughout the figures.

[0029] DETAILED DESCRIPTION OF AT LEAST ONE IMPLEMENTATION METHOD

[0030] Fig. 1 represents the flowchart illustrating the different steps of the process 100 of manufacturing an OxRAM memory cell according to the invention.

[0031] As shown in [Fig. 2], the process 100 begins with a step 101 of forming a first electrode 1 made of a titanium nitride layer corresponding to the lower electrode 1 of the OxRAM memory cell. This step therefore aims to form the lower electrode 1, for example on a substrate (substrate not shown in the figures). The lower electrode 1 has, for example, a thickness of between 10 and 200 nm, here 60 nm.

[0032] In practice, the lower electrode 1 is for example formed by reactive cathodic sputtering in a vacuum deposition chamber.

[0033] Alternatively, the lower electrode 1 can be formed by chemical vapor deposition or according to a Damascus structure.

[0034] The process 100 continues with a step 102 ([Fig.3]) corresponding to a first implantation of silicon atoms Si in the lower electrode 1.

[0035] According to this first implantation, the Si is implanted in the TiN layer of the lower electrode 1, according to a specific profile 201 shown in [Fig. 9]. The implantation dose DI and the implantation acceleration voltage VI are chosen to achieve implantation on the surface of the lower electrode 1. The silicon implantation dose DI is strictly positive and strictly less than 0.7 x 10¹⁴ cm²; according to a preferred embodiment, the dose DI is equal to 0.5 x 10¹⁴ cm². The acceleration voltage VI of the Si ions is between 0.3 kV and 0.7 kV; according to a preferred embodiment, the acceleration voltage is equal to 0.5 kV.

[0036] Figure 9 shows in particular the different implantation profiles in the TiN layer corresponding to the lower electrode 1, the upper surface of which is delimited by the dotted lines 200: the first implantation at dose DI and voltage VI is represented by profile 201, which has a maximum Si concentration at a depth of 1.2 nm from the top surface of the lower electrode and an implantation profile width of 201 equal to half the maximum silicon implantation concentration value of 1.5 nm. The implantation profiles represent a normalized value of implanted ions (ratio of implanted ion volume concentration to implanted ion dose) as a function of depth in the implanted layers.

[0037] The process 100 continues with a step 103 ([Fig.4]) corresponding to a second implantation of silicon atoms Si in the lower electrode 1.

[0038] According to this second implantation, the Si is implanted in the TiN layer of the lower electrode 1, according to a specific profile 202 shown in [Fig. 9] exhibiting a maximum Si concentration at a depth of 2.2 nm from the upper surface of the lower electrode and an implantation profile width equal to half the value of the maximum silicon implantation concentration, 3.0 nm. The implantation dose D2 and the implantation acceleration voltage V2 of this second implantation are chosen to obtain a deeper implantation of the lower electrode 1. The silicon implantation dose D2 is strictly positive and strictly less than 0.6 x 10¹⁴ cm²; according to a preferred embodiment, the dose D2 is equal to 0.3 x 10¹⁴ cm². The Si ion acceleration voltage V2 is between 1 kV and 2 kV; In a preferred embodiment, the acceleration voltage is equal to 1.5 kV.

[0039] Following steps 102 and 103, the overall profile resulting from the first and second implantations is illustrated by reference 203, which has a maximum silicon concentration Cmax at a depth of between 1 and 3 nm from the upper surface of the lower electrode (and preferably between 1 and 1.6 nm, and even more preferably between 1.1 and 1.5 nm, and here equal to 1.3 nm) and an implantation profile width Wp at half the value of the maximum silicon implantation concentration, which is between 1.6 nm and 2 nm (and preferably between 1.7 and 1.9 nm, and here equal to 1.86 nm). The area implanted by the first and second implantations of the lower electrode 1 is illustrated by reference ZA in [Fig. 4].

[0040] Then, the process continues with a step 104 ([Fig. 5]) of depositing a layer of active material 2. This layer of active material 2 is formed on the lower electrode 1. The deposition of the layer of active material 2 is carried out in such a way that this layer has a substantially constant thickness at every point. In this description, "substantially constant" means a thickness not varying by more than 20%, preferably by more than 10%, and even more preferably by more than 5%. Preferably, the active material layer 2 is based on amorphous hafnium dioxide (HfO2). In this description, the term "based on" means that the layer in question comprises more than 50% of the element mentioned after that term (for example, here it means that the active material layer 2 comprises more than 50% hafnium dioxide). The active material layer 2 has a thickness of between 3 and 10 nm, for example, 5 nm.

[0041] In practice, the active material layer 2 is deposited by an atomic layer deposition method (or ALD for "Atomic Layer Deposition" according to the commonly used Anglo-Saxon acronym).

[0042] Alternatively, the active material layer can be deposited by sputtering. Alternatively, the active material layer can be deposited by a physical vapor deposition (PVD) method. Alternatively still, the active material layer can be deposited by an ion beam deposition (IBD) method.

[0043] As shown in [Fig. 6], optionally, the process 100 This is followed by step 105, which involves deposition of a dielectric oxide layer 3. This dielectric oxide layer 3 is formed on the active material layer 2. The dielectric oxide layer 3 comprises, for example, a metal oxide or a semiconductor oxide. Preferably, it is aluminum oxide (Al₂O₃). Alternatively, it can also be silicon dioxide (SiO₂).

[0044] The dielectric oxide layer 3 here has a thickness between 0.3 and 1.5 nm, for example here 0.5 nm.

[0045] In practice, the dielectric oxide layer 3 is deposited by an atomic layer deposition (ALD) method. Alternatively, the dielectric oxide layer 3 can be deposited by sputtering. Alternatively still, the dielectric oxide layer can be deposited by a physical vapor deposition (PVD) method. Alternatively still, the dielectric oxide layer can be deposited by an ion beam deposition (IBD) method.

[0046] This dielectric oxide layer 3, deposited on the layer containing the active material, is positioned between the active material layer and the layer forming the upper electrode. This layer then acts as a diffusion barrier for oxygen vacancies (relative to the filament) and thus improves the switching properties of the memory cell. In particular, this configuration improves the implementation of write and erase cycles. As mentioned previously, it is possible to eliminate this step 105 of depositing the dielectric oxide layer and proceed directly from step 104 of depositing the active material layer to step 106 of implanting silicon into the active material layer.

[0047] As illustrated in [Fig. 7], the process 100 continues with a step 106 of silicon implantation in the active layer formed by the dielectric oxide layer 3 of Al₂O₃ and the active material layer 2 of HfO₂ formed in steps 104 and 105. The silicon is implanted according to a specific profile illustrated by reference numeral 204 in [Fig. 9]. Thus, depending on whether or not the deposition 105 of the dielectric oxide layer takes place, the so-called active layer comprises either only the active material layer 2 or the stacking of the active material layer and the dielectric oxide layer 3.

[0048] Advantageously, the implantation step 106 is implemented at an implantation acceleration voltage V3 between 1.5 and 3.5 kV, here equal to 2.5 kV, for an implantation dose D3 of the order of 2.1015 cm2.

[0049] As shown in [Fig.9], the implantation profile 204 extends into the already implanted ZA zone of the lower electrode 1.

[0050] The process continues with a step 107 of deposition of a second electrode 4 forming the upper electrode ([Fig. 8]). The upper electrode 4 is formed on the active layer formed, as previously described, of the active material layer 2 and the dielectric oxide layer 3. More specifically, the upper electrode 4 is deposited on the dielectric oxide layer 3.

[0051] The upper electrode 4 comprises a first conductive layer 41, for example of titanium Ti, and a second conductive layer 42, for example of titanium nitride TiN. The deposition step of the upper electrode 4 therefore comprises two substeps: a first substep of deposition of the first conductive layer 41 and a second substep of deposition of the second conductive layer 42.

[0052] The first conductive layer 41 is therefore first deposited on the dielectric oxide layer 3. The first conductive layer 41 is for example formed by sputtering in a vacuum deposition chamber.

[0053] The first conductive layer 41 of Ti has the particularity of being a layer adapted to create oxygen vacancies in the active layer when this first conductive layer 41 is in contact with the active layer. According to the commonly used Anglo-Saxon term, the first conductive layer 41 is an "oxygen scavenging layer". Since the mechanism of formation of the conductive filament in the dielectric oxide layer 3 generally involves a reorganization of oxygen vacancies within the dielectric oxide, the first conductive layer 41 facilitates oxygen exchange with the active layer. It should be noted that this first conductive layer 41 makes it possible to create oxygen vacancies in the active material layer 2 even when this first conductive layer is deposited on the dielectric oxide layer 3. In other words, the first conductive layer 41 creates vacancies oxygen in the active material layer 2 with or without deposition of the dielectric oxide layer 3.

[0054] Then, the second conductive layer 42 is deposited on the first conductive layer 41 formed. The second conductive layer 42 is formed, for example, by reactive sputtering in a vacuum deposition chamber.

[0055] The first conductive layer 41 has a thickness of between 3 and 20 nanometers, here 5 nm. The second conductive layer 42 has a thickness of between 10 and 200 nanometers, here 150 nm.

[0056] At the end of this step 107, the OxRAM-type memory cell 5 is obtained and takes the form of a stack of layers extending along a z-axis. The lower electrode 1, the active material layer 2, the dielectric oxide layer 3, and the upper electrode 4 form the different layers of this stack. The different layers extend parallel to each other (and parallel to a substrate, not shown, on which the memory cell 5 rests). The z-axis is perpendicular to the plane of the different layers of the stack forming the memory cell 5.

[0057] We will now show the advantages (in particular the better endurance performance) of the OxRAM type memory cell as represented in [Fig.8].

[0058] To do this, we will use an indicator, the bit error rate (BER, or Bit Error Rate, according to the commonly used Anglo-Saxon acronym), evaluated on a set of memory cells (here, approximately 16,000 cells). By definition, this bit error rate corresponds to the percentage of memory cells in the set of memory cells considered that will not exhibit satisfactory properties.

[0059] In practice, this error rate is evaluated by plotting the distributions of the memory cells in the system under consideration as a function of the resistance R (in Ohms Q) for the LRS and HRS states. The memory cell distributions are considered cumulatively (this is a cumulative distribution function, or CDF, according to the commonly used Anglo-Saxon acronym). The error rate then corresponds to the point of intersection of the distributions representing the LRS and HRS states.

[0060] Figure 10 shows the BER error rate for 6 types of C1 to C6 memory cells as a function of the number of cycles performed on these cells, one cycle corresponding to one set and one reset step. The C6 type cells are the OxRAM type memory cells according to the invention and as obtained by process 100 illustrated in Figures 1 to 8. The other C1 to C5 cells have a layer stacking identical to the C6 type cells and differ from them only in the doping of the lower electrode. The implantation characteristics of the lower electrode of the C6 cells according to the invention are as follows: • First implantation at an acceleration voltage of 0.5 kV and an implantation dose of 0.5 x 10¹⁴ cm². • Second implantation at an acceleration voltage of 1.5 kV and an implantation dose of 0.3 x 10¹⁴ cm².

[0061] Type Cl cells have a lower electrode having undergone a single implantation with a low accelerating voltage (here 0.5 kV) and an implantation dose of 1.1014 cm2.

[0062] Type C2 cells have a lower electrode that has undergone a double implantation: • First implantation at an acceleration voltage of 0.5 kV and an implantation dose of 1.1014cm2. • Second implantation at an acceleration voltage of 1.5 kV and an implantation dose of 0.6 x 10¹⁴ cm².

[0063] Type C3 cells have a lower electrode that has undergone a double implantation: • First implantation at an acceleration voltage of 0.5 kV and an implantation dose of 1.1014cm2. • Second implantation at an acceleration voltage of 4 kV and an implantation dose of 7.1014cm2.

[0064] C4 type cells have a lower electrode that has undergone a double implantation: • First implantation at an acceleration voltage of 0.5 kV and an implantation dose of 2.1014cm2. • Second implantation at an acceleration voltage of 1.5 kV and an implantation dose of 1.2 x 10¹⁴ cm².

[0065] C5 type cells have a lower electrode that has not undergone any implantation.

[0066] As illustrated in [Fig. 10], apart from the C6 type cells according to the invention, the error rate of all cell types C1 to C5 degrades with the number of cycles. Conversely, the memory cells according to the invention exhibit an error rate that gradually decreases with the number of cycles until it stabilizes after approximately one hundred cycles. The error rate of the memory cells according to the invention remains generally stable even after 10,000 cycles, while it degrades, including for the C5 type cells with a non-implanted lower electrode.

[0067] Surprisingly, it is found that simply implanting the lower electrode in Si is not sufficient to improve the endurance performance of an OxRAM type memory cell, since Cl-type cells with C4 also exhibit The implantation of the lower electrode and the resulting degraded endurance performance are observed. Therefore, the specific implantation conditions of the process according to the invention must be met to achieve the endurance performance of the memory cell according to the invention, the intrinsic characteristics of which cannot be defined at this stage other than by its manufacturing process. Furthermore, it is observed that the error rate of OxRAM-type memory cells according to the invention initially decreases with the number of cycles. It may therefore be advantageous to perform a preliminary step (after its manufacture and before use) consisting of cycling the memory cell according to the invention for a number N of cycles (where N is an integer greater than or equal to 100) in order to obtain a lower error rate, which then stabilizes.

[0068] Figures 11 and 12 illustrate another advantage of OxRAM-type memory cells according to the invention. These figures are based on the so-called "intelligent programming" mechanism. This method consists of verifying, after each operation, that the memory cell exhibits the resistance level corresponding to the state in which it was programmed (set or reset). If this is not the case, the programming operation (set or reset) is repeated as many times as necessary until a resistance level conforming to expectations is obtained: the required number of iterations is called the repetition. More precisely, in [Fig. 11] (set), the repetition consists of repeating the same set pulse. In [Fig. 12] (reset), the repetition consists of increasing the pulse voltage with each repetition.

[0069] Thus, [Fig. 11] shows the fraction of memory cells according to the invention C6 and of memory cells without implantation of the lower electrode C5 that had to be reprogrammed with a given number of repetitions (ranging from 2 to 5) for the set operations as a function of the number of cycles. As an example, it can be seen that in the case where two repetitions are necessary, approximately one cell in 10,000 of type C5 or C6 was rewritten twice at the 100th cycle. [Fig. 12] shows the fraction of memory cells according to the invention C6 and of memory cells without implantation of the lower electrode C5 that had to be reprogrammed with a given number of repetitions (ranging from 2 to 5) for the reset operations as a function of the number of cycles.

[0070] In the case of reset operations ([Fig. 12]), it is observed that the more cycling operations are performed with the C6 memory cells according to the invention, the fewer reprogramming pulses are needed. Conversely, C5 type memory cells with an undoped lower electrode require more repetitions beyond a hundred cycles. This initial result confirms the very good endurance of the memory cells according to the invention. Indeed, the fact of being less "stressed" "The memory cells, due to the lower number of repetitions required, result in better endurance of the memory cells."

[0071] In the case of set operations ([Fig. 11]), a certain stability is observed, confirming once again the endurance performance of the memory cells according to the invention.

Claims

Demands

1. A method for manufacturing a resistive memory cell of the OxRAM type, comprising the following steps: - forming a lower electrode of titanium nitride, - first implantation of silicon atoms in the lower electrode with a first dose of silicon implantation and a first implantation acceleration voltage, said first dose of silicon implantation being strictly positive and strictly less than 0.7.1014 cm2, - second implantation of silicon atoms in the lower electrode with a second dose of silicon implantation and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, said second dose of silicon implantation being strictly positive and strictly less than 0.6.1014 cm 2, the first and second acceleration voltages being chosen to have an implantation profile following the first and second implantation presenting a maximum concentration of silicon at a depth between 1 and 3 nm from the upper surface of the lower electrode, - deposition of an active layer on the implanted lower electrode, - deposition of an upper electrode on the active layer.

2. A method according to claim 1 wherein the first and second accelerating voltages are chosen to have an implantation profile following the first and second implantation having a maximum silicon concentration at a depth of between 1 and 1.6 nm from the upper surface of the lower electrode and an implantation profile width at half the value of the maximum silicon implantation concentration of between 1.6 nm and 2 nm.

3. A method according to claim 2 wherein the first and second accelerating voltages are chosen to have an implantation profile following the first and second implantations having a maximum silicon concentration at a depth of between 1.1 and 1.5 nm from the upper surface of the lower electrode and an implantation profile width at the half of the maximum silicon implantation concentration value between 1.7 nm and 1.9 nm.

4. A method according to any one of the preceding claims characterized in that the deposition of the upper electrode on the active layer comprises: - The deposition of a first conductive layer, in contact with the active layer and being chosen to create oxygen vacancies in the active layer, and - The deposition of a second conductive layer disposed on the first conductive layer.

5. A method according to the preceding claim, wherein the material of the first conductive layer is titanium and the conductive material of the second conductive layer is titanium nitride.

6. A method according to any one of the preceding claims wherein the first acceleration voltage is between 0.3 kV and 0.7 kV and the second acceleration voltage is between 1 kV and 2 kV.

7. A method according to any one of the preceding claims wherein the first accelerating voltage is equal to 0.5 kV and the second accelerating voltage is equal to 1.5 kV.

8. A method according to any one of the preceding claims, wherein the first silicon implantation dose is equal to 0.5 x 10¹⁴ cm² and the second silicon implantation dose is equal to 0.3 x 10¹⁴ cm²

9. A method according to any one of the preceding claims wherein the deposition of the active layer on the implanted lower electrode comprises the following steps: - deposition of a layer of active material on the implanted lower electrode, - deposition of a layer of dielectric oxide on the layer of active material, - implantation of silicon atoms through the dielectric oxide layer, the implantation dose and the implantation acceleration voltage being chosen so that the silicon atoms are implanted at least partially in the layer of active material.

10. A method according to the preceding claim wherein the active material is based on hafnium dioxide.

11. A method according to claim 9 or 10 wherein the dielectric oxide is based on aluminum oxide.

12. A method according to any one of claims 6 to 8, wherein the silicon implantation step through the dielectric oxide layer is carried out at an implantation acceleration voltage of between 1.5 and 3.5 kilovolts, and preferably equal to 2.5 kV, and a silicon implantation dose of between 1015cm2 and 5.1015 cm2, and preferably equal to 2.1015cm2.

13. A method according to any one of the preceding claims characterized in that the thickness of the lower titanium nitride electrode is chosen to be between 10 and 200 nm.

14. OxRAM type memory cell obtained by the process according to any one of claims 1 to 13.

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