DUAL-FEED IR EMITTER PIXEL

Abstract

IR display device for displaying a scene and comprising a plurality of pixels, each pixel being provided with: - an IR emitter (105), - a storage stage (120) coupled to the control stage (110), the storage stage comprising at least one storage capacitor (Cmem, Cmem1) which, during phases known as "writing in the first storage capacitor", charges to the set voltage (Vcons) and during phases known as "display phases" delivers the set voltage (Vcons) to the control stage, the first pixel being further provided with a coupling circuit (130, 430, 730), comprising one of the switch elements (131, 132; 431, 432, 433, 434;731, 732, 733, 734, 735, 736, 737, 738) the coupling circuit (130, 430, 730) being configured to: during the writing phases in the storage capacity: decouple the storage capacity (Cmem, Cmem1) from said first supply line (191) while coupling the storage capacity to another supply line (187), during display phases: couple the first storage capacity (Cmem, Cmem1) to the first supply line (191) while decoupling the storage capacity (Cmem, Cmem1) from the other supply line. Figure for the abstract: 3A;

Description

Title of the invention: DUAL-FEED IR EMITTING PIXEL TECHNICAL FIELD AND PRIOR ART

[0001] The present invention relates to the field of matrix devices for projecting images or scenes, also called display devices, and applies in particular to infrared display devices which generate images in the infrared part of the electromagnetic spectrum.

[0002] For certain particular applications, such as testing an associated IR camera, rapid analysis of scenes, monitoring of high-temperature scenes, for example involving fire or high-temperature materials, it may indeed be desirable to use a display device equipped with infrared (IR) emitting elements.

[0003] Infrared scene display devices generally comprise a set of thermal pixels, typically arranged in a matrix, which converts electrical input signals into a desired thermal or infrared image. The emitter in each pixel may be in the form of a membrane through which a higher or lower Imembrane current is passed depending on the intensity that is to be displayed. The Imembrane current heats the membrane which emits, by Joule effect, IR radiation whose intensity depends on that of the Imembrane current.

[0004] [Fig.l] gives an example of a conventional structure of an IR imager pixel P, the membrane being schematically represented by a resistor Rmemb. The pixel is also provided with a pixel control transistor Ti which converts a set electrical input voltage Vcons into a control current of the resistor Rmemb, which consequently dissipates a corresponding quantity of heat, or thermal energy, depending on the amplitude of this input voltage Vcons. This input voltage Vcons is commonly recorded across a storage capacitor (not shown in this figure) provided upstream of the transistor TL

[0005] Thus, by precisely adjusting the input voltage Vcons of each pixel, its infrared emission is controlled and an infrared image is thus defined.

[0006] It is preferable to seek to maintain good display dynamics, this parameter being able to be defined here by the maximum voltage that can be applied to the terminals of the membrane Vmemb.

[0007] The power dissipated by the membrane is calculated with the voltage at its terminals (Vmemb) and the resistivity at the terminals of the membrane (Rmemb) according to the formula: Pmemb = Vmemb 2 / Rmemb [1].

[0008] We also seek to obtain good precision, this parameter being able to be defined as the smallest variation in voltage Vmemb controllable at the terminals of the membrane. To be able to display the hottest parts of a scene this typically requires that the membrane can emit IR radiation equivalent to several hundred degrees. However, a pixel has a display dynamic typically dependent on the technology with which it is produced. In CMOS technology, this limit is of the order of 3~5V which can prove very limiting.

[0009] From formula [1] given above, it is deduced that to reach high temperatures, a low resistive membrane is preferably required.

[0010] Furthermore, to be able to distinguish certain details of a current scene, at low temperature, for example below 50°C, high precision with low emissions is preferably necessary. This precision constraint is also all the more important when the need to reach high temperatures is important: so that the higher a display dynamic is required, the greater a high control precision is required.

[0011] If we take a particular example with Rmemb planned to target 500°C (and which we assume to be constant for reasons of simplification of the calculations), we may then need a precision of 15 bits and a control step of:

[0012] Vstep = 4V / 32768 = 122pV (32768 = 15 bits)

[0013] Tstep = 500 / 32768 = 0.015°C

[0014] If one wishes to display a hot scene such as a fire, many pixels of the display device will have to emit a strong current in their respective membranes. However, to heat a membrane to several hundred degrees, the necessary current (which depends on the resistivity of the chosen membrane, and its emitting properties) can be of the order of several hundred pA. In the case of a large matrix, for example 1024x1024 pixels or larger, the corresponding total consumption can then be measured in thousands of watts.

[0015] Given the powers involved, a current draw in the matrix may vary from a very low value when a cold scene is displayed, to several hundred amperes when a large proportion of the pixels are used to display a hot scene.

[0016] Furthermore, since the power supply grids inside the matrix are not perfect, significant power supply variations are observed, whether on the high power supply lines delivering a power supply potential Vdd which may be several volts, for example around 5V, or on the low power supply lines at a low power supply potential GND, for example around 0V.

[0017] A dynamic AV variation from one image to another of the power supplies of the order of several mV can be observed. This distorts the value that we are trying to display. The power dissipated in the membrane is not exact, since the voltage at its terminals has varied by AV.

[0018] Document US 6,316°777B1 presents an example of a known display device formed from a matrix of IR emitting elements.

[0019] The problem arises of finding a new display device which is improved with respect to at least one of the aforementioned drawbacks. Statement of the invention

[0020] It is therefore an aim of the present invention to provide a display device, in particular infrared, for displaying a scene and comprising a plurality of pixels, each pixel of the plurality of pixels being provided with:

[0021] - of a transmitter, in particular an infrared transmitter, the transmitter comprising a first terminal coupled to a first supply line and a second terminal coupled to an output of a control stage,

[0022] - said transmitter control stage, this transmitter control stage comprising a voltage-current conversion element for receiving a set voltage and delivering a control current based on this set voltage,

[0023] - of a storage stage coupled to an input of the control stage, the stage of storage comprising at least one storage capacity which, during phases known as "writing into the storage capacity", charges to the set voltage and during phases known as "display phases of value stored by the storage capacity", delivers the set voltage to the control stage,

[0024] the first pixel being further provided with a coupling circuit comprising switch elements, the coupling circuit being configured to: - during the “writing into the storage capacity” phases: decoupling the storage capacity from said first power supply line while coupling the storage capacity to another power supply line, - during the “display of value stored by the storage capacity” phases: couple the first storage capacity to the first supply line while decoupling the storage capacity from the other supply line.

[0025] Thus, during the writing phases in the storage capacity, the latter is isolated from the power supply of the transmitters which is likely to be subject to voltage drops and this capacity is supplied by means of another power supply which is less likely to be subject to voltage drops.

[0026] This makes it possible to gain precision in the transmission of the set voltage and / or to avoid power supply disturbances / drops.

[0027] Typically, the voltage-current conversion element may comprise a transistor having an electrode, source or drain, connected to the emitter.

[0028] Advantageously, the control stage is provided with a follower formed by an amplifier comprising a first input coupled to the storage stage and a feedback on a second input of the amplifier, the amplifier having an output coupled to the transmitter.

[0029] According to one possible implementation, the storage stage also comprises a second storage capacity.

[0030] In this case, said storage capacity is a first storage capacity and the coupling circuit can be further configured to, during phases called "writing in the second storage capacity", decouple the second capacity from the control stage, and during phases called "displaying the value stored by the second storage capacity", couple the second capacity to the control stage.

[0031] Advantageously, according to a particular embodiment, the coupling circuit can comprise:

[0032] - a switch element between a first electrode of the storage capacitor and the first supply line

[0033] - a switch element between the first electrode of the storage capacitor and the other power line,

[0034] - a switch element between the second electrode of the storage capacitor and an input node of the transmitter driver stage,

[0035] - a switch element between a second electrode of the first capacitance of storage and an input node of the storage stage.

[0036] When the pixel is provided with a second storage capacity, the coupling circuit can also comprise:

[0037] - a switch element between a first electrode of the second capacitance of memorization and the first power line,

[0038] - a switch element between the first electrode of the second capacitor of memory and the other power line,

[0039] - a switch element between the second electrode of the second capacitor of memorization and the input node of the memorization stage,

[0040] - a switch element between the second electrode of the second capacitor of storage and the input node of the transmitter driver stage.

[0041] According to one possible embodiment of the display device and in which a first pixel of said plurality of pixels belongs to a first row of pixels and in which a second pixel of a second row of pixels belongs to a second row of pixels distinct from the first row, and in which the display phases are concomitant display phases of the pixels of the first row and of the second row of pixels, the coupling circuit of the second pixel can be further configured to, during said display phases, couple the storage capacity of the second pixel to said first supply line while decoupling the storage capacity of the second pixel from said other supply line and to, during writing phases in the storage capacity of the second pixel, decouple the storage capacity of the second pixel from said first supply line while coupling the storage capacity of the second pixel to said other supply line.

[0042] Alternatively, according to another possible implementation of the display device in which a first pixel of said plurality of pixels belongs to a first row of pixels and in which a second pixel of a second row of pixels belongs to another plurality of pixels and in which display phases of pixels of the second row are at least partially offset from the display phases of the first row,the second pixel may have a coupling circuit configured to, during display phases of the second pixel, couple a storage capacity of the second pixel to the first supply line while decoupling the storage capacity of the second pixel from said other supply line and to, during writing phases in the storage capacity of the second pixel, decouple the storage capacity of the second pixel from the first supply line while coupling the storage capacity of the second pixel to said other supply line.

[0043] According to one possible embodiment of the display device, when the pixels are each provided with two storage capacities, the writing phases in the storage capacity and the writing phases in the second storage capacity can be carried out concomitantly and the end of the writing phases in the storage capacity and the end of the writing phases in the second storage capacity are triggered respectively by a first end-of-write trigger signal and a second end-of-write trigger signal, the first end-of-write trigger signal and the second end-of-write trigger signal being offset in time.

[0044] According to a possible embodiment of the display device, when the pixels are each provided with two storage capacities, the phases of displaying the value stored in the storage capacity and the phases of displaying the value stored in the second storage capacity are carried out concomitantly and in which the start of the phases of displaying the value stored in the storage capacity and the start of the writing phases in the second storage capacity are triggered respectively by a first display phase start trigger signal and a second display phase start trigger signal, the first display phase start trigger signal and the second display phase start trigger signal being offset in time.

[0045] Advantageously, the transmitter can be powered between the first power supply line provided to carry a given polarization potential and a second polarization line provided to carry a reference or ground potential, the other line being provided to carry a potential substantially equal to the given potential, the control stage and the storage stage being connected to the second polarization line.

[0046] Advantageously, the other potential line can be provided to convey a potential with a small offset relative to the potential of the first supply line to allow compensations, for example offset or linked to technological dispersions.

[0047] The first supply line may be connected to one supply network while the other supply line is connected to another supply network isolated from the first supply network.

[0048] According to one possible implementation, the switching elements of the coupling circuit are transistors, in particular MOS transistors.

[0049] Throughout the document, the expression “couple” is used to designate an electrical connection or link, which may be direct or indirect (i.e. made through one or more intermediate element(s) / component(s)). Brief description of the drawings

[0050] The present invention will be better understood on the basis of the description which follows and the appended drawings in which:

[0051] - [Fig.l] serves to illustrate a pixel circuit structure of a display device infrared as implemented according to the prior art;

[0052] - [Fig.2] serves to illustrate an example of a matrix arrangement of a display provided with IR emitters, here in the form of suspended membranes;

[0053] - [Fig.3A]

[0054] [Fig.3B] serves to illustrate different phases of operation of an example of a pixel circuit comprising an IR emitter as implemented according to the invention and in which a storage stage is alternately coupled to a power supply separate from that of the IR emitter when it is a question of storing a setpoint value. then coupled to the same power supply as that of the IR transmitter when it comes to transmitting the set value to the transmitter so that it emits corresponding infrared radiation;

[0055] - [Fig.4] serves to illustrate a particular embodiment of the IR pixel circuit;

[0056] - [Fig.5] serves to illustrate a first method of displaying that a device display according to the invention is capable of implementing;

[0057] - [Fig.6] serves to illustrate a second display method that a device display according to the invention is capable of implementing;

[0058] - [Fig.7] serves to illustrate pairs of supply lines for different rows of pixels to enable the storage capacity of the pixels of the same row to be supplied by means of a different power supply during certain operating phases than that with which they are coupled during other operating phases;

[0059] - [Fig.8] serves to illustrate a third display method that a device display according to the invention is capable of implementing;

[0060] - [Fig.9] serves to illustrate a particular example of an embodiment of a circuit of pixel having a first storage capacity and a second storage capacity;

[0061] - [Fig.10] serves to illustrate a particular example of operation of the circuit of display pixel with two memory capacities;

[0062] - [Fig.l 1] serves to illustrate a display pixel circuit with two capacitors of memory and a reset block;

[0063] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0064] We now refer to [Fig.2] giving a schematic representation of an example of an infrared display device formed from a plurality of pixels, here arranged in a matrix M of several lines (i.e. horizontal rows) and several columns (i.e. vertical rows) of pixels 10.

[0065] Each pixel 10 is provided with an emitter 105, in this example comparable to a heating resistor and which can be for example formed of a membrane 17 supported above a substrate 12 by means of thermally insulating elements 19 which also provide electrical connections for supplying the membrane 17 with current. The infrared power emitted by the emitter 105 increases monotonically with the temperature. An electric current passing through the emitting element 105 determines its temperature and therefore the infrared power that it emits. Each pixel comprises a circuit integrated into the substrate 12 associated with its emitting element 105.

[0066] This integrated circuit provides in particular a control signal to its transmitter 105 which can be produced for example in CMOS technology. As regards the power supply of the matrix M, each transmitter 105 is coupled to a network of power distribution (not shown) called "high" distributing a power supply potential noted Vdd_memb, for example of the order of several volts (if we do not take into account the voltage drop phenomena described previously) and a network (not shown) for distributing a power supply voltage called "low", distributing a potential lower than the power supply potential, for example of the order of OV (without taking into account the voltage drop phenomena described previously) this network serving as a reference or ground.

[0067] An electrical diagram of an integrated circuit 100 of pixel 10 of the display device is given in FIGS. 3A and 3B.

[0068] The infrared emitter 105 is controlled by a control stage 110 comprising a voltage-current conversion element here a transistor 112, in this illustrated example of the NMOS type, one electrode of which, here the drain electrode, is connected to the emitter 105. A feedback amplifier 115 is advantageously connected to the gate of the transistor 112 and comprises a looped input and connected to an output node Ns connected to the emitter 105. This amplifier 115, here optional, makes it possible to compensate for the possible lack of linearity of the conversion transistor 112.

[0069] The transmitter 105 is coupled to a first power supply line 191, here a high power supply line delivering the power supply potential Vdd_memb, for example of the order of a few volts. This power supply line 191 is itself connected to the high power distribution network to which the other IR transmitters of the other pixels of the matrix are connected and which is typically in the form of a grid provided to convey the power supply potential Vdd_memb. The first power supply line 191 is thus here an emitter power supply line.

[0070] The pixel circuit is also provided with a so-called “memorization” stage 120 comprising here a memorization capacitor Cmem to deliver a reference voltage Vcons at the input of the control stage 110, here the input of the amplifier 115. This voltage itself typically comes from a control block (not shown in this figure) with which the row of the pixel 10 in question is associated and which may comprise for example an amplifier, a multiplexer and at least one digital-analog converter.

[0071] The circuit 100 also has the particularity of being provided with a particular coupling circuit 130, here arranged on the one hand between the storage stage 120 and on the other by the first supply line 191 and another supply line 187. The coupling circuit 130 comprises a plurality of switching elements 131, 132, in particular formed from transistors, for example of the MOS type and of a size typically much smaller, for example twenty times smaller than that of the voltage-current conversion transistor 112.

[0072] The circuit 100 of pixel 10 also has the particularity here of being provided with this other specific supply line 187, which is distinct from the first line of the first supply line 191, that is to say, in this case, neither connected nor coupled to the first supply line 191 and is isolated from this first supply line 191.

[0073] This other power supply line 187, also called the reference power supply line, is thus not connected to the high power supply distribution network to which the first power supply line 191 is itself connected, but can be connected to another high power supply distribution network or to other means making it possible to provide a second high power supply potential Vdd_ref, and which, if voltage drop phenomena are not taken into account, has a theoretical value equal to or of the order of the theoretical value of the first high power supply potential Vdd_memb.

[0074] [Fig.3A] represents a first operating phase of the pixel 100 called the “write” phase which corresponds to a first configuration of the coupling circuit 130. During this write phase, the storage capacitor Cmem charges to a setpoint voltage Vcons itself coming from the aforementioned input control block (not shown). This input control block is for example provided with a digital-to-analog converter and is typically shared by the other pixels of the same row as that of the pixel whose circuit 100 is shown here.

[0075] During this writing phase, the coupling circuit 130 is provided to couple the other supply line 187 Vdd_ref to the storage capacitor Cmem, here by means of a closed switch element 131 connecting the other supply line 187 Vdd_ref to an electrode of the capacitor Cmem and to decouple the first supply line 191 Vdd_ref from the storage capacitor Cmem, here by means of an open switch element 132 disconnecting (i.e. isolating) the first supply line 191 from this same electrode of the storage capacitor Cmem.

[0076] Thus, during the writing phase, the storage stage 120 and in particular the power supply capacitor Cmem is powered by means of a power supply separate from that of the transmitter 105. By isolating the capacitor Cmem from the power supply to which the transmitter 105 is connected during this phase, the setpoint value Vcons is loaded into the capacitor without the latter undergoing any significant voltage drops to which the power supply of the transmitter 105 is likely to be subjected. The accuracy of this voltage Vcons is therefore maintained here.

[0077] [Fig.3B] represents a second operating phase of the pixel called “display” which corresponds to a second configuration of the coupling circuit 130. During this display phase, the coupling circuit 130 is configured this time to couple the first supply line 191 Vdd_memb to the storage capacitor Cmem, here by means of the closed switch element 132, and to decouple the Cmem storage capacity of the other supply line 187 Vdd_ref, here via the open switch element 131.

[0078] Thus, during the display phase, the potential difference stored by the power supply capacitor Cmem supplied at the input of the control stage 110 is translated into a control current of the transmitter 105. The storage capacitor Cmem is supplied via the same power supply as that of the transmitter 105. Any disturbances on the first power supply line 191 are also translated into the storage capacitor Cmem which is then coupled and here directly connected to this first power supply line 191. Since the potential difference across the capacitor is constant, a disturbance on the first line 191 will be reflected in the setpoint. We remain referenced to the potential of the first line 191 and the storage capacitor follows any voltage drops.

[0079] According to a variant of the embodiment described above, the transistor 112 can be replaced by a transistor of a different type, in particular by a PMOS. The emitter 105 is then in this case arranged between the drain electrode of the PMOS transistor and a low power supply line, in particular serving as ground GND.

[0080] Just as the storage capacitor Cmem is connected to the high supply line 191 of the transmitter 105 during the transmission phase and the storage capacitor Cmem is connected to the other high supply line 187 during the writing phase, it is possible, as a variant or in combination, to provide for connecting the storage capacitor Cmem to a low supply line, in particular to the same ground to which the transmitter 105 is referenced during the transmission phase and connecting the storage capacitor Cmem to another low supply line during the writing phase which is distinct from that GND_memb of the transmitter. It is thus possible to couple the storage capacitor Cmem to a ground GND_ref dissociated from the ground GND_memb to which the transmitter 105 is connected. Thus, in this case, two low-power or reference power supply networks can be provided, separate and not connected to each other.

[0081] Another exemplary embodiment is given in [Fig.4], where a reset block 170 typically formed by a reset switch 171 at the terminals of the storage capacity Cmem can also be integrated to empty the storage capacity Cmem. The coupling circuit 430 is here provided with 4 switches 431, 432, 433, 434 whose respective states are controlled according to the different operating phases.

[0082] In the writing phase, switches 432, 434 are open, while switches 431 and 433 are closed (i.e. passing).

[0083] In the display phase, switches 432, 434 are closed (i.e. passing), while switches 431 and 433 are open.

[0084] A display device as implemented according to the invention can be applied to a display of the so-called “global display” type of pixels, similar to a so-called “global shutter” operating mode (i.e. “global shutter”) implemented for a detection device. Thus, on the timing diagram of [Fig.5], after successive writing phases Ow on different rows linel, line2, line3, line4, the pixel emitters 105 of the different rows linel, line2, line3, line4 of pixels are simultaneously placed in the display phase Od, these display phases Od then being simultaneous.

[0085] The pixels of the rows linel, line2, line3, line4 have, during respective writing phases Ow, their storage capacity decoupled from the power supply of the IR emitters while being coupled to another power supply and during the display phases Od, these pixels have their storage capacity coupled to the power supply of the IR emitters while being decoupled from this other power supply.

[0086] For this type of display, it is possible to provide, as in [Fig.7], a supply line 191 of the emitters delivering the supply potential Vdd_memb common to several pixels 10n, 102[, 103[ ..., of the same vertical row and of distinct horizontal rows. Another reference supply line 187 delivering the potential Vdd_ref, common to these same pixels 10n, 102i, 103i is provided to supply their respective storage capacities in the writing phase.

[0087] Another pair of supply lines respectively delivering the potential Vdd_memb and the supply potential Vdd_ref are provided here for other pixels 10[2, 1022, 103 2,.... of the same vertical row.

[0088] As a variant of the particular embodiment of [Fig.7], it is also possible to provide supply lines 187, 191 respectively delivering the supply potential Vdd_ref and the supply potential Vdd_memb and which are common this time to given pixels of the same horizontal row, these given pixels belonging to distinct vertical rows.

[0089] According to another variant, a first of the supply lines 187 and 191 is provided to be common to several pixels of the same horizontal row and the other of the lines 187 and 191 this time common to several pixels of the same vertical row.

[0090] For one or other of these variants, the pixels of the same row, here vertical, share the same track 901 by which the respective setpoint voltages Vcons intended for the different pixels of this vertical row are successively applied. A selection switch element at the input of each pixel is provided and this switch of a given pixel is activated individually to allow the pixel to receive the setpoint voltage Vcons intended for it.

[0091] A display device such as implemented according to the invention can also be applied to a display of the so-called “rolling shutter” type (i.e. “rotating shutter”, this expression being more commonly used in the context of detectors), where as in the timing diagram of [Fig.8], the display phases on the different rows line1, line2, line3, line4, the emitters 105 of pixels are offset while partially overlapping.

[0092] According to another embodiment variant, a pixel circuit is provided whose storage stage is this time provided with two storage capacities Cmeml and Cmem2. Such an embodiment makes it possible, as illustrated in the timing diagram of [Fig.8], to have no dead time. Thus, during first display phases Od I, a setpoint value previously written in the first storage capacity Cmeml is displayed, and during second display phases cpd2, a setpoint value written in the second storage capacity Cmem2 is displayed. The writing phases Ow 1 in the first capacity Cmeml are carried out during the second display phases Od2, while the writing phases Ow2 in the second capacity Cmem2 are carried out during the first display phases Od1.

[0093] A particular embodiment of the coupling circuit 730 of a pixel provided with two storage capacities Cmeml and Cmem2 is illustrated in [Fig.9] with its switching elements in the form of transistors 731, 732, 733, 734, 735, 736, 737, 738, here for example of PMOS type, whose respective passing (switch closed) and blocked (switch open) states, and the different corresponding operating phases are controlled respectively by signals wl_ping, rl_ping, w2_ping, r2_ping, wl_pong, rl_pong, w2_pong, r2_pong applied to their respective gates.

[0094] During a writing phase of the first capacitor Cmeml, a transistor 731 controlled by the signal wl_ping couples an electrode 721 of this capacitor Cmeml to the power supply 187 delivering the power supply potential Vdd_ref, while the transistor 732 whose state is controlled by the signal rl_ping decouples this same electrode 731 of the capacitor Cmeml from the power supply 191 Vdd_memb of the emitter and the control stage (the control circuit being, for reasons of simplification, represented by a broken line frame) delivering a power supply potential Vdd_ref.

[0095] The other electrode 722 of the first storage capacitor Cmeml is coupled via a controlled transistor 733 to the input IN of the circuit to allow the charging of the capacitor Cmeml while being decoupled from the input node NE of the control block (represented by a broken line frame in this figure) by means of a transistor 734.

[0096] During a first display phase during which the value stored by the first capacitor Cmeml is read, the transistor 731 decouples from the power supply 187 delivering the power supply potential Vdd_ref, while the transistor 732 couples this capacitor Cmeml to the power supply 191 Vdd_memb of the emitter and the control stage.

[0097] During a writing phase of the second capacitor Cmem2, the transistor 735 couples an electrode 728 of this capacitor Cmem2 to the power supply 187 delivering the power supply potential Vdd_ref, while the transistor 736 decouples this same electrode 728 of the second capacitor Cmem2 from the power supply 191 Vdd_memb of the emitter and the control stage. The other electrode 729 of the second storage capacitor Cmem2 is then coupled via a transistor 737 to the input IN of the circuit while being decoupled from the input node NE of the control block by means of a transistor 738.

[0098] Then, during a second display phase during which the value stored by the second capacitor Cmem2 is read, the transistor 735 decouples the electrode 728 of the second capacitor Cmem2 from the power supply 187 delivering the power supply potential Vdd_ref, while the transistor 736 couples this electrode 728 of the capacitor Cmem2 to the power supply 191 Vdd_memb of the emitter and the control stage. The other electrode 729 is then coupled via the transistor 738 to the input of the control block and decoupled (transistor 737 blocked) from the input IN of the circuit.

[0099] A device as described previously may also provide on its input node NE a reset block 170 as described previously and typically formed of a reset switch 171.

[0100] A particular operating mode of a display device provided with pixels comprising a circuit as illustrated previously in connection with [Fig. 9] is given in [Fig. 10], by means of timing diagrams of signals writel for writing control in the first capacitor Cmeml, write2 for writing control in the second capacitor Cmem2, readl for display control of value stored in the first capacitor Cmeml, read2 for display control of value stored in the second capacitor Cmem2, and this, respectively, for a pixel of a 1st line (“line 1”), for a pixel of a 2nd line (“line2”) of the matrix of the matrix, and for a pixel of an N-th line (“lineN”) of the matrix.

[0101] The signals represented in this example correspond to a particular embodiment which differs from the example previously described in connection with [Fig.9], in that the switching elements are this time NMOS type transistors.

[0102] A write can be performed at the same time in the first capacity Cmeml and in the second capacity Cmem2.

[0103] Here, a synchronization of the triggering of the writing in the first capacity Cmeml and in the second capacity Cmem2 (corresponding to an alignment of the portions Ci i and C2i of the signals writel and write2) is not obligatory.

[0104] A shift between the respective end triggers of the write operation in the first capacity Cmeml and in the second capacity Cmem2 (corresponding to a shift of the respective portions Ci2 and C22 of the signals writel and write2) can be provided.

[0105] In the particular embodiment illustrated, the end of writing in the first capacity Cmeml is provided before that in the second capacity Cmem2, but a reverse order can be provided.

[0106] A shift between the triggering of the respective starts of the operation of displaying the value stored in the first capacity Cmeml and the value stored in the second capacity Cmem2 (corresponding to a shift of the respective portions C3i and C4i of the signals readl and read2) can also be provided.

[0107] Such offsets between trigger signals make it possible to avoid or at least reduce disturbances due to switching and likely to generate untimely charge injections.

[0108] In the illustrated embodiment, provision is also made for activating a reset signal before starting a display. This makes it possible to empty residual charges from a previous sample before displaying a new value.

[0109] Another example of a pixel integrated circuit arrangement with two storage capacities Cmeml and Cmem2 is given in [Fig. 11].

[0110] Its coupling circuit 430 comprises switching elements 431, 432, 433, 434 associated with the first capacitor Cmeml, as well as switching elements 443, 441, 442, 444 associated with the second capacitor Cmem2.

[0111] A particular mode of operation of such a circuit will now be given.

[0112] A first phase of writing in the first capacitor Cmeml can here be carried out simultaneously with a phase of display by the transmitter 105 of a setpoint value stored in the second capacitor Cmem2. These phases are distinct from a first phase of display by the transmitter 105 of a setpoint value stored in Cmeml and from a phase of writing a setpoint in the second capacitor Cmem2.

[0113] For this, the switch elements 432 and 434 are open to decouple the first capacitor Cmeml from the control of the transmitter 105 and the switch elements 431 and 433 are closed (passing) to allow writing in the first capacitor Cmeml. At the same time, the elements 442 and 444 are closed (passing) to allow coupling the second capacitor Cmem2 to the input and the switch elements 441 and 443 are open to decouple the second capacitor Cmem2 from the control stage of the transmitter 105.

[0114] For a subsequent writing phase in the second capacitor Cmem2 carried out here simultaneously with a display phase of the value stored in the first capacitor Cmeml, the switch elements 432 and 434 are closed in order to allow the first capacitor Cmeml to be coupled to the transmitter 105, while the elements 431 and 433 are open to disconnect the first capacitor Cmeml from the input of the circuit. At the same time, the elements 442 and 444 are open in order to allow the second capacitor Cmem2 to be decoupled from the control stage of the transmitter 105 and the elements 441 and 443 are closed to allow writing in the second capacitor Cmem2, this capacitor then being coupled to the input of the circuit.

[0115] The invention applies particularly to infrared display devices for which the phenomenon of voltage drops can prove particularly significant. It also applies to near infrared display devices with emitters producing radiation typically in a wavelength range of 0.78 and 2.5 pm. It can also be adapted to other matrix devices, and in particular to displays operating in the visible range.

Claims

Claims

1. Display device, in particular infrared, for displaying a scene and comprising a plurality of pixels, each pixel of said plurality of pixels being provided with: - an emitter (105), in particular an infrared emitter, the emitter (105) comprising a first terminal coupled to a first supply line (191) and a second terminal coupled to an output of a driving stage, - said emitter driving stage (110), this emitter driving stage comprising a voltage-current conversion element (112) for receiving a setpoint voltage (Vcons) and delivering a control current based on this setpoint voltage (Vcons), - a storage stage (120) coupled to an input of the driving stage, the storage stage comprising at least one storage capacity (Cmem, Cmeml) which,during phases called "writing in the storage capacity" charges to the set voltage (Vcons) and during phases called "display phases of value stored by the storage capacity" delivers the set voltage (Vcons) to the control stage, the first pixel being further provided with a coupling circuit (130, 430, 730), comprising switch elements (131, 132; 431, 432, 433, 434; 731, 732, 733, 734, 735, 736, 737, 738) the coupling circuit (130, 430, 730) being configured to: - during the "writing in the storage capacity" phases: decouple the storage capacity (Cmem, Cmem 1) from said first supply line (191) while coupling the storage capacity to another supply line (187), - during the “display of value stored by the storage capacity” phases: couple the first storage capacity (Cmem,Cmeml) to the first supply line (191) while decoupling the storage capacity (Cmem, Cmeml) from the other supply line.

2. A display device according to claim 1, wherein the voltage-current conversion element comprises a transistor (112), having a source or drain electrode connected to the emitter (105).

3. A display device according to one of claims 1 or 2, wherein the driver stage (110) is provided with an amplifier (115) having a first input coupled to the storage stage (120), a feedback on a second input of the amplifier (115), and an output coupled to the transmitter (105).

4. Display device according to one of claims 1 to 3, wherein said storage capacity is a first storage capacity (Cmeml) and wherein the storage stage also comprises a second storage capacity (Cmem2), the coupling circuit (430, 730) being further configured to, during phases called "writing in the second storage capacity", decouple the second capacity from the control stage (110), and during phases called "displaying the value stored by the second storage capacity" couple the second capacity to the control stage (110).

5. Display device according to one of claims 1 to 4, wherein said storage capacity is a first storage capacity (Cmeml) and wherein the storage stage also comprises a second storage capacity (Cmem2), and wherein the coupling circuit (430) comprises: - a first switch element (432) between a first electrode of the first storage capacity (Cmeml) and the first power supply line (191) - a second switch element (431) between the first electrode of the first storage capacity (Cmeml) and the other power supply line (187), - a third switch element (442) between a first electrode of the second storage capacity (Cmem2) and the first power supply line (191) - a fourth switch element (441) between the first electrode of the second storage capacity (Cmem2) and the other power supply line (187),- a fifth switching element (433) between a second electrode of the first storage capacity (Cmeml) and an input node (IN) of the storage stage, - a sixth switching element (443) between a second electrode of the second storage capacity (Cmem2) and the input node (IN) of the storage stage, - a seventh switching element (434) between the second electrode of the first storage capacity (Cmeml) and an input node (NE) of the transmitter control stage, - an eighth switching element (444) between the second electrode of the second storage capacity (Cmem2) and the input node (NE) of the transmitter control stage.

6. Display device according to one of claims 1 to 5, in which a first pixel of said plurality of pixels belongs to a first row of pixels and in which a second pixel of a second row of pixels belongs to a second row of pixels distinct from the first row, and in which the display phases are concomitant display phases of the pixels of the first row and of the second row of pixels, the coupling circuit of the second pixel being further configured for during said display phases,coupling the storage capacity of the second pixel to said first supply line while decoupling the storage capacity of the second pixel from said other supply line and for, during writing phases in the storage capacity of the second pixel, decoupling the storage capacity of the second pixel from said first supply line while coupling the storage capacity of the second pixel to said other supply line.

7. A display device according to one of claims 1 to 5, wherein a first pixel of said plurality of pixels belongs to a first row of pixels and wherein a second pixel of a second row of pixels belongs to another plurality of pixels and wherein display phases of pixels of the second row are at least partially offset from display phases of the first row,the second pixel having a coupling circuit configured to, during display phases of the second pixel, couple a storage capacity of the second pixel to the first supply line while decoupling the storage capacity of the second pixel from said other supply line and to, during writing phases in the storage capacity of the second pixel, decouple the storage capacity of the second pixel from the first supply line while coupling the storage capacity of the second pixel to said other supply line.

8. A display device according to claim 4 or 5, wherein said phases of writing in the storage capacity and said phases of writing in the second storage capacity are carried out concomitantly and wherein the end of said phases of writing in the storage capacity and the end of said phases of writing in the second storage capacity are triggered respectively by a first end-of-write trigger signal and a second end-of-write trigger signal, the first end-of-write trigger signal and the second end-of-write trigger signal being offset in time,and / or wherein said phases of displaying the value stored in the storage capacity and said phases of displaying the value stored in the second storage capacity are carried out concomitantly and wherein the start of said phases of displaying the value stored in the storage capacity and the start of said phases of writing in the second storage capacity are triggered respectively by a first display phase start trigger signal and a second display phase start trigger signal, the first display phase start trigger signal and the second display phase start trigger signal being offset in time.,

9. Display device according to one of claims 1 to 8, wherein the transmitter (105) is powered between said first power supply line provided to carry a given polarization potential (Vdd_memb) and a second polarization line provided to carry a reference or ground potential (GND), said other line (187) being provided to carry a potential (Vdd_ref) substantially equal to the given potential, the storage stage (130) being connected to the second polarization line.

10. A display device according to one of claims 1 to 9, wherein the first power supply line is connected to a power supply network and wherein said other power supply line is connected to another power supply network isolated from the first power supply network.

11. Display device according to one of claims 1 to 10, wherein the switching elements of the coupling circuit are transistors, in particular MOS transistors.

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