INTERRUPT HANDLING OF AN INTEGRATED CIRCUIT MEMORY CONTROLLER

Abstract

According to one aspect, there is provided an integrated circuit (IC) comprising a memory controller (MEM_CTRL) configured to transmit information stored in a memory (ECC_MEM) to a processing unit (UT), the memory controller (MEM_CTRL) comprising: - an error detection circuit (ECC_CTRL) configured to detect an error in said information by implementing an error correction code algorithm, and to generate an interrupt signal (INT) in case of detection of at least one error in said information, - a transmission control circuit (INT_CTRL) configured to transmit the interrupt signal (INT) to the processing unit (UT) only when the error is detected for the first time in said information by the error detection circuit. Figure for abstract: Fig 1

Description

Title of the invention: INTERRUPT MANAGEMENT OF AN INTEGRATED CIRCUIT MEMORY CONTROLLER

[0001] Embodiments and implementations relate to an integrated circuit memory controller, and more particularly to memory controller interrupt management within an integrated circuit.

[0002] A memory controller allows a processor to access information, such as instructions or data, stored in a memory. The memory controller may in particular detect an error in information by implementing an error-correcting code when transmitting this information to the processor.

[0003] When an error in information is detected by the memory controller, the latter can generate an interrupt to indicate to the processor that the transmitted information contains an error.

[0004] However, it may be envisaged to correct the error in the information read by the memory controller instead of correcting this error directly in the memory. Indeed, correcting the error in the memory may require erasing and rewriting the information which may be relatively long operations, in particular when the memory is a non-volatile memory. Error correction carried out by the memory controller is therefore generally faster and preferred, in particular in the case of real-time applications.

[0005] Furthermore, when the memory stores several instructions of a sequence of instructions, the processor can provide a pre-loading mechanism making it possible to read each of these instructions in advance from this memory in parallel with the execution of other instructions of the sequence of instructions in order to improve the performance of the processor.

[0006] More particularly, this pre-loading mechanism can trigger an interrupt when the instruction read in advance contains an error, thus temporarily stopping the execution of the sequence of instructions.

[0007] As long as the instruction is not executed before the instruction sequence is interrupted, the processor will continue to read the same instruction after processing the interrupt.

[0008] The pre-loading mechanism therefore causes the interrupt to be triggered repeatedly until the error contained in this instruction has been corrected in the memory.

[0009] In other words, repeatedly triggering the interrupt prevents the processor from continuing to execute the instruction sequence because the processor will always attempt to access the same location in memory of the faulty instruction after each interrupt.

[0010] In this regard, a deactivation of interrupts can be envisaged in order to prevent repeated triggering of the interrupt for the same error contained in an instruction, but this solution does not make it possible to determine the location in the memory of the erroneous instruction. Consequently, when this solution is envisaged, erroneous instructions whose location in the memory cannot be found by the processing unit cannot be corrected.

[0011] Thus, there is a need to propose solutions making it possible to detect and correct an error in information while avoiding repeated access to the same location in the memory by the processor during interrupts generated by the memory controller.

[0012] According to one aspect, there is provided an integrated circuit comprising a memory controller configured to transmit information, an instruction or data for example, stored in a memory to a processing unit, such as a processor for example, the memory controller comprising: - an error detection circuit configured to detect an error, or possibly several errors, in said information by implementing an error correction code algorithm, and to generate an interrupt signal in the event of detection of an error in said information, - a transmission control circuit configured to transmit the interrupt signal to the processing unit only when the error is detected for the first time in said information by the error detection circuit.

[0013] By transmitting the interrupt signal to the processing unit only the first time the error is detected, repeated triggering of the interrupt signal is avoided, which causes the processing unit to enter an infinite loop in which this same interrupt signal is processed by the processing unit.

[0014] Thus, in the absence of repeated triggering of the interrupt signal, it is no longer necessary to deactivate the interrupts to terminate this infinite loop and it becomes possible to correct errors in the instructions stored in the memory during maintenance.

[0015] According to one embodiment, the transmission control circuit comprises a storage circuit configured to store the address of the location in the memory of the last information having triggered a transmission of the interrupt signal, and a logic circuit configured to compare the address stored by the storage circuit with the address of the location in the memory of the next information, for which an error is detected, transmitted by the memory controller after said last information so as to transmit the interrupt signal to the processing unit only when the address of the location in the memory of said next information does not correspond to the address stored by the storage circuit.

[0016] The term "next information" means any instruction or data stored in the memory which is transmitted to the processing unit after the last information in the order of transmission of the information, which may for example be the same order as that of the sequence of instructions executed by the processing unit.

[0017] The next information and the last information may be the same information stored in a memory location, for example if the same instruction is transmitted twice consecutively to the processing unit, or two pieces of information stored in two different memory locations.

[0018] The storage circuit is configured to store one address at a time so that the logic circuit can compare the address of the location in the memory of the next information with a single stored address which is that of said last information.

[0019] The address of the location in the memory of the last information having triggered a transmission of the interrupt signal is memorized to prevent each new interrupt generated during the detection of an error in this information from being transmitted to the processing unit.

[0020] The transmission control circuit advantageously has a logic circuit making it possible to transmit the interrupt if the address of said next information is different from the stored address or to block the interrupt if the address of said next information and the stored address correspond.

[0021] According to one embodiment, the storage circuit comprises: - a first register configured to store the address of the location in the memory of said information in the event of detection of an error in said information by the error detection circuit, - a second register configured to store the address contained in the first register before an error is detected in the next information.

[0022] Such a storage circuit can therefore be produced simply from two registers for example.

[0023] The logic circuit comprises a comparison circuit configured to generate a control signal having a value corresponding to the result of the comparison between the address contained in the first register and the address contained in the second register, and a conditional transmission circuit configured to transmit the interrupt signal only when the address stored in the first register does not match the address stored in the second register.

[0024] The conditional transmission circuit, for example an “AND” logic gate, makes it possible to filter, according to the comparison result of the comparison circuit, the interruptions generated by the error detection circuit in order to transmit only the interruption generated when the error is detected for the first time in said information.

[0025] According to one embodiment, the processing unit is configured to control the logic circuit so that the logic circuit compares the stored address with the address of the location in the memory of the next information as soon as the address of the last information is stored by the storage circuit.

[0026] This prevents a new transmission of the interrupt signal by the logic circuit when the address of the last information has not yet been stored by the storage circuit. For example, the same stored address which is compared more than once before being updated risks triggering a transmission of several interrupt signals generated for the same error, for example for an error in the same information transmitted several times before the stored address is updated.

[0027] According to one embodiment, the memory controller comprises an additional conditional transmission circuit configured to block the transmission of the interrupt signal by the transmission control circuit as long as the address of said last information is not stored by the storage circuit.

[0028] The additional conditional transmission circuit can be considered in particular when the conditional transmission circuit can no longer ensure the blocking of certain interruptions.

[0029] According to one embodiment, the processing unit is configured, upon receipt of the interrupt signal, to read the address contained in the second register and to store the read address in an additional memory.

[0030] The additional memory therefore makes it possible to store a unique address for each item of information for which an error was detected during the execution of the instruction sequence by the processing unit.

[0031] According to one embodiment, the integrated circuit further comprises a correction circuit, which may be for example the processing unit, configured to correct the information stored in the memory at the corresponding addresses stored in the additional memory.

[0032] These addresses, once stored in the additional memory, make it possible to find all erroneous information directly in the memory and to correct it during a maintenance operation, and thus make it possible to avoid correcting this information during each interruption.

[0033] According to one embodiment, the processing unit is configured to erase the contents of the second register after the correction of said information stored in the memory by the processing unit.

[0034] Thus, the contents of the second register can be erased after the maintenance operation, for example during a restart of the integrated circuit. This makes it possible to prevent the address of information already corrected during the maintenance operation from remaining stored in the second register after the maintenance operation.

[0035] According to another aspect, there is provided a method of transmitting at least one piece of information stored in a memory to a processing unit, comprising: - detecting an error in said information by implementing an error correction code algorithm and, in the event of detecting an error in said information, generating an interrupt signal, - transmission of the interrupt signal only when the error is detected for the first time in said information by the error detection circuit.

[0036] According to one embodiment, the method comprises storing the address of the location in the memory of the last item of information having triggered a transmission of the interrupt signal and comparing the stored address with the address of the location in the memory of each item of information, for which an error is detected, transmitted after said last item of information so as to transmit the interrupt signal to the processing unit only when the address of the location in the memory of said item of information does not correspond to the address stored by the storage circuit.

[0037] According to one embodiment, the storage comprises: - storage in a first register of the address of the location in the memory of said information in the event of detection of an error in said information, - storage in a second register of the address contained in the first register before an error is detected in the next information.

[0038] Said comparison comprises a generation of a control signal having a value corresponding to the result of the comparison between the address contained in the first register and the address contained in the second register, and a transmission of the interrupt signal only when the address stored in the first register does not correspond to the address stored in the second register.

[0039] According to one embodiment, said comparison of the stored address with the address of the location in the memory of the next information is carried out as soon as the address of the last information is stored.

[0040] According to one embodiment, the method comprises blocking the transmission of the interrupt signal until the address of said last information is stored.

[0041] According to one embodiment, the method comprises, upon receipt of the interrupt signal by the processing unit, a reading of the address stored in the second register by the processing unit and a storage in an additional memory of the address read by the processing unit.

[0042] According to one embodiment, comprising an erasure of the contents of the second register after the correction of said information stored in the memory by the processing unit.

[0043] Other advantages and characteristics of the invention will appear on examining the detailed description of the embodiment and implementation, which is in no way limiting, and the appended drawings in which:

[0044] [Fig.l] ;

[0045] [Fig.2] ; and

[0046] [Fig.3] schematically illustrate methods of implementation and realization of the invention.

[0047] [Fig.l] schematically illustrates an integrated circuit IC according to an embodiment of the invention. The integrated circuit IC comprises an ECC_MEM memory, such as a non-volatile memory, and an additional MEM memory, such as a “RAM” memory for example (for “Random access memory” in English and known as “memory vive” in French).

[0048] The integrated circuit IC also comprises a memory controller MEM_CTRL and a processing unit UT, such as a processor for example.

[0049] The ECC_MEM memory typically allows information to be stored, such as an instruction or data, as well as an error correction code (known by the acronym “ECC” for “Error-correcting code” in English).

[0050] The memory controller MEM_CTRL is configured to transmit the information stored in the memory ECC_MEM to the processing unit UT.

[0051] The information stored in the ECC_MEM memory, for example the MEM_DAT instruction of a sequence of instructions executed by the processing unit UT or a piece of data, may contain errors.

[0052] In this regard, the memory controller MEM_CTRL comprises an error detection circuit ECC_CTRL configured to detect one or more errors in said information by implementing an error correction code algorithm, and to generate an interrupt signal INT in the event of detection of an error in said information MEM_DAT.

[0053] Such an ECC_CTRL error detection circuit is well known to those skilled in the art who will be able to determine an error correction code algorithm for detecting the presence of an error in an instruction or data as a function of the error correction code contained in the MEM_ECC memory. These error correction code algorithms Error correction algorithms can be based on the Hamming code or the Golay code, although these examples of algorithms are not exhaustive.

[0054] The error detection circuit ECC_CTRL makes it possible, for example, to read the instruction MEM_DAT in the memory ECC_MEM and to correct this instruction MEM_DAT before transmitting it to the processing unit UT.

[0055] The error detection circuit ECC_CTRL is configured to generate an interrupt signal INT upon detection of an error in the information.

[0056] The interrupt signal INT can be generated in the form of a pulse corresponding to a logic level "high" for a given duration when an error is detected by the error detection circuit ECC_CTRL.

[0057] The interrupt signal INT temporarily interrupts the execution of the sequence of instructions by the processing unit UT in order to allow the processing unit UT to react in the event of detection of an error in the MEM_DAT information.

[0058] The memory controller MEM_CTRL also comprises a transmission control circuit INT_CTRL. The transmission control circuit INT_CTRL is configured to transmit the interrupt signal INT only when the error is detected for the first time in said information by the error detection circuit ECC_CTRL.

[0059] For example, when the error detection circuit ECC_CTRL detects for the first time an error in the information MEM_DAT, the transmission control circuit INT_CTRL transmits the interrupt signal INT to the processing unit UT but prevents the transmission of interrupt signals which could be generated subsequently in the event of error detection in the same information MEM_DAT.

[0060] The transmission control circuit INT_CTRL thus makes it possible to prevent an interruption from being transmitted to the processing unit UT when an error is detected again by the error detection circuit ECC_CTRL for the same information.

[0061] By transmitting the interrupt signal INT to the processing unit UT only the first time the error is detected, repeated triggering of the interrupt signal is avoided, which causes the processing unit UT to enter an infinite loop in which this same interrupt signal is processed by the processing unit.

[0062] Therefore, the processing unit UT, which has for example the pre-loading mechanism described above, can continue the execution of the sequence of instructions without undergoing repeated triggering of an interrupt.

[0063] [Fig.2] schematically illustrates an example of a transmission control circuit INT_CTRL of the memory controller MEM_CTRL as previously described in relation to [Fig.l].

[0064] The transmission control circuit INT_CTRL includes a memo- MEM_REG and a LOG_TX logic circuit.

[0065] The MEM_REG storage circuit is configured to store the address of the location in the ECC_MEM memory of the last information having triggered a transmission of the INT interrupt signal.

[0066] The storage circuit MEM_REG comprises hardware elements making it possible to read the ADD address of the information for which an error has been detected, for example via the error detection circuit ECC_CTRL and to store this ADD address.

[0067] The logic circuit LOG_TX is configured to compare the address stored by the storage circuit MEM_REG with the address of the location in the memory ECC_MEM of the next information, for which an error is detected, transmitted after said last information.

[0068] During the comparison by the logic circuit LOG_TX, if the address of the location in the memory ECC_MEM of said next information does not correspond to the address stored by the storage circuit MEM_REG, then the interrupt signal INT is transmitted to the processing unit UT.

[0069] In other words, the logic circuit LOG_TX uses the address stored by the storage circuit as a basis for comparison with each address transmitted by the error detection circuit ECC_CTRL in the event of an error being detected in the information, so as to prevent the interrupt signal INT from being transmitted again for an error detected in the same information.

[0070] The transmission control circuit INT_CTRL further comprises a control register ENB_CTRL. The processing unit UT is configured to control the logic circuit LOG_TX according to the value stored in the control register ENB_CTRL.

[0071] More particularly, the processing unit UT is configured to modify the value of the control register ENB_CTRL when the address of the last information having triggered the interrupt signal INT is stored by the storage circuit MEM_REG. The processing unit UT generates an activation signal ENB from the value stored in the control register ENB_CTRL, so as to allow the logic circuit LOG_TX to carry out the comparison as soon as the address of the last information is stored by the storage circuit MEM_REG.

[0072] The MEM_REG storage circuit comprises a first register ERR_ADD_REG and a second register ADD_TAG_REG.

[0073] The first register ERR_ADD_REG is configured to store the ADD address of the location in the ECC_MEM memory of said information in the event of detection of an error in said information by the error detection circuit ECC_CTRL. Each new address transmitted by the error detection circuit ECC_CTRL can be automatically stored in the first ERR_ADD_REG register in case of error detection in the information, for example by replacing the address contained in the first ERR_ADD_REG register with the new address.

[0074] The second register ADD_TAG_REG is configured to store the address contained in the first register ERR_ADD_REG before an error is detected in the next information.

[0075] For example, the storage of the address in the second register ADD_TAG_REG can be performed by the processing unit UT in response to the interrupt signal INT.

[0076] When initializing the integrated circuit IC, the second register ADD_TAG_REG stores an initialization value which may be different from the values of the addresses of the ECC_MEM memory.

[0077] The logic circuit LOG_TX comprises a comparison circuit COMP configured to generate a control signal COMP_CTRL having a value corresponding to the result of the comparison between the address contained in the first register ERR_ADD_REG and the address contained in the second register ADD_TAG_REG.

[0078] The comparison circuit COMP may be a digital comparator of conventional design making it possible to carry out a bit-by-bit comparison between the address stored in the first register ERR_ADD_REG and the address stored in the second register ADD_TAG_REG.

[0079] The control signal COMP_CTRL generated by such a comparator COMP may be a signal whose voltage value corresponds to a different logic level depending on the result of the comparison. For example, the control signal COMP_CTRL may have a “high” logic level if the addresses respectively stored in the first register ERR_ADD_REG and the second register ADD_TAG_REG are identical and a “low” logic level if these addresses are different.

[0080] The logic circuit LOG_TX also comprises a conditional transmission circuit AND2 configured to transmit the interrupt signal INT only when the address stored in the first register ERR_ADD_REG does not correspond to the address stored in the second register ADD_TAG_REG.

[0081] The conditional transmission circuit may be a logic gate configured to perform the logic operation "AND" between the interrupt signal INT and the control signal COMP_CTRL. In particular, an inverter may be connected to an input of the logic gate AND2 so as to transmit the inverse logic level of the control signal COMP_CTRL to the logic gate AND2.

[0082] The interrupt signal INT is then retransmitted at the output of the logic gate AND2 according to the logic level of the control signal COMP_CTRL. More particularly, if the inverse logic level of the control signal COMP_CTRL at the input of the logic gate AND2 is the “high” level, for example when the address ADD of the MEM_DAT information is different from the stored address, then the INT interrupt signal is transmitted to the UT processing unit. Otherwise, i.e. if the inverse logic level of the COMP_CTRL control signal at the input of the AND2 logic gate is the "low" level, then the INT interrupt signal is not transmitted to the UT processing unit.

[0083] The memory controller MEM_CTRL comprises an additional conditional transmission circuit AND1 configured to block the transmission of the interrupt signal INT by the transmission control circuit INT_CTRL as long as the address of the last information is not stored by the storage circuit MEM_REG.

[0084] The additional conditional transmission circuit AND1 may be a logic gate configured to perform the logical operation "AND" between the interrupt signal INT and the activation signal ENB.

[0085] Upon receipt of the interrupt signal INT, the processing unit UT can read the address stored in the second register ADD_TAG_REG and store this address in an additional memory MEM.

[0086] The additional memory MEM makes it possible to store the address of each piece of information for which an error was detected during the execution of the instruction sequence by the processing unit UT. These addresses, once stored in the additional memory, can be used to carry out a maintenance operation during which each erroneous piece of information which is stored in the memory ECC_MEM is corrected.

[0087] In this regard, the integrated circuit further comprises a correction circuit, which may be for example the processing unit UT, configured to correct the information stored in the memory at the corresponding addresses stored in the additional memory.

[0088] During the maintenance operation, the processing unit UT can retrieve all the erroneous information stored in the memory ECC_MEM from the addresses stored in the additional memory MEM and correct this information. Such a maintenance operation can in particular take place after the end of the execution of the sequence of instructions by the processing unit UT, so as to avoid correcting this information during each interruption for example.

[0089] The integrated circuit IC can then restart after the maintenance operation. However, the address of the last information that triggered the interrupt signal INT is still stored in the second register ADD_TAG_REG after the restart of the integrated circuit IC even though this information was corrected during the maintenance operation. The interrupt signal INT that would be generated by the error detection circuit ECC_CTRL when a new error is detected in this information may not be transmitted to the processing unit UT if the address of this information is still stored in the second register ADD_TAG_REG.

[0090] To avoid this risk, the processing unit UT is configured to erase the contents of the second register ADD_TAG_REG after the correction of said information stored in the memory ECC_MEM by the processing unit UT.

[0091] In particular, the transmission control circuit INT_CTRL comprises a clear register CLR_REG configured to store a user-defined value.

[0092] For example, an initialization value may be stored in the erase register CLR_REG when the integrated circuit IC is first used so that, upon each restart of the integrated circuit IC, the processing unit UT reads the initialization value stored in the erase register CLR_REG and replaces the value stored in the second register ADD_TAG_REG with this initialization value.

[0093] [Fig.3] schematically illustrates a method of transmitting at least one piece of information stored in the memory ECC_MEM to the processing unit UT.

[0094] The method comprises a step 100 of detecting an error in said information by implementing an error correction code algorithm and, in the event of detection of an error, or several errors, in said information, a generation of an interrupt signal INT.

[0095] The method comprises a step 101 of transmitting the interrupt signal INT, for example by the transmission control circuit INT_CTRL as described previously in relation to FIGS. 1 and 2, only when the error is detected for the first time in said information by the error detection circuit.

[0096] The method also comprises a step 102 of storing the address of the location in the ECC_MEM memory of the last information having triggered a transmission of the interrupt signal INT.

[0097] Step 102 comprises storing in a first register ERR_ADD_REG the address of the location in the memory ECC_MEM of said information in the event of detection of an error in said information.

[0098] Step 102 also includes storing in a second register ADD_TAG_REG the address contained in the first register ERR_ADD_REG before an error is detected in the next information. An initialization value, which may be different from the values of the addresses of the ECC_MEM memory, may be stored in the second register ADD_TAG_REG by default if none of the addresses of the ECC_MEM memory have been stored, for example during the initialization of the integrated circuit IC.

[0099] The method comprises a step 103 of comparison, for example by a logic circuit LOG_TX, of the stored address with the address of the location in the ECC_MEM memory of the next information, for which an error is detected, transmitted after said last information. If, at the end of this comparison, the address of the location in the ECC_MEM memory of said next information does not correspond to the address stored by the MEM_REG storage circuit, then the interrupt signal INT is transmitted to the processing unit UT.

[0100] Step 103 comprises a detection of the storage of the address of the last information having triggered a transmission of the interrupt signal INT and a generation of an activation signal ENB from the value stored in the control register ENB_CTRL so as to allow the logic circuit LOG_TX to carry out the comparison as soon as the address of the last information is stored by the storage circuit MEM_REG.

[0101] Step 103 comprises a generation of a control signal COMP_CTRL. The control signal COMP_CTRL has a value corresponding to the result of the comparison between the address contained in the first register ERR_ADD_REG and the address contained in the second register ADD_TAG_REG.

[0102] Step 103 also includes transmitting the interrupt signal INT only when the address stored in the first register ERR_ADD_REG does not match the address stored in the second register ADD_TAG_REG.

[0103] The method comprises a step 104 of blocking the transmission of the interrupt signal INT by the transmission control circuit INT_CTRL as long as the address of said last information is not stored.

[0104] The method comprises a step 105 of receiving the interrupt signal INT by the processing unit UT.

[0105] Step 105 comprises a reading of the address stored in the second register ADD_TAG_REG by the processing unit UT and a storage in an additional memory MEM of the address read by the processing unit UT.

[0106] The method further comprises a step 106 of correcting the information stored in the ECC_MEM memory at the corresponding addresses stored in the additional memory. The correction of step 107 can for example be carried out by the processing unit UT.

[0107] The method comprises a step 107 of erasing the contents of the second register ADD_TAG_REG after the correction of said information stored in the memory ECC_MEM by the processing unit UT. Such erasure may comprise, for example, a reading of an initialization value stored in the erasure register CLR_REG and a replacement of the address stored in the second register ADD_TAG_REG by this initialization value.

Claims

1.

2.

3. Claims Integrated circuit (IC) comprising a memory controller (MEM_CTRL) configured to transmit information stored in a memory (ECC_MEM) to a processing unit (UT), the memory controller (MEM_CTRL) comprising: - an error detection circuit (ECC_CTRL) configured to detect an error in said information by implementing an error correction code algorithm, and to generate an interrupt signal (INT) in case of detection of an error in said information, - a transmission control circuit (INT_CTRL) configured to transmit the interrupt signal (INT) to the processing unit (UT) only when the error is detected for the first time in said information by the error detection circuit. Integrated circuit according to claim 1, in which the transmission control circuit (INT_CTRL) comprises a storage circuit (MEM_REG) configured to store the address of the location in the memory (ECC_MEM) of the last information having triggered a transmission of the interrupt signal (INT), and a logic circuit (LOG_TX) configured to compare the address stored by the storage circuit with the address of the location in the memory (ECC_MEM) of the next information, for which an error is detected, transmitted after said last information so as to transmit the interrupt signal (INT) to the processing unit (UT) only when the address of the location in the memory (ECC_MEM) of said next information does not correspond to the address stored by the storage circuit. Integrated circuit according to claim 2, in which the storage circuit (MEM_REG) comprises: - a first register (ERR_ADD_REG) configured to store the address of the location in the memory (ECC_MEM) of said information in the event of detection of an error in said information by the error detection circuit (ECC_CTRL), - a second register (ADD_TAG_REG) configured to store the address contained in the first register (ERR_ADD_REG) before an error is detected in the next information, the logic circuit (LOG_TX) comprising a comparison circuit (COMP) configured to generate a control signal having a value corresponding to the result of the comparison between the address contained in the first register and the address contained in the second register, and a conditional transmission circuit (AND2) configured to transmit the interrupt signal (INT) only when the address stored in the first register does not correspond to the address stored in the second register.

4. Integrated circuit according to one of claims 2 or 3, in which the processing unit is configured to control the logic circuit (LOG_TX) so that the logic circuit compares the stored address with the address of the location in the memory of the next information as soon as the address of the last information is stored by the storage circuit (MEM_REG).

5. Integrated circuit according to one of claims 2 to 4, in which the memory controller (MEM_CTRL) comprises an additional conditional transmission circuit (AND1) configured to block the transmission of the interrupt signal (INT) by the transmission control circuit (INT_CTRL) as long as the address of said last information is not stored by the storage circuit (MEM_REG).

6. Integrated circuit according to one of claims 3 to 5, in which the processing unit (UT) is configured, upon receipt of the interrupt signal, to read the address stored in the second register (ADD_TAG_REG) and to store in an additional memory (MEM) the address read by the processing unit (UT).

7. Integrated circuit according to claim 6, comprising a correction circuit configured to correct the information stored in the memory (ECC_MEM) at the corresponding addresses stored in the additional memory (MEM).

8. Integrated circuit according to claim 7, wherein the processing unit (UT) is configured to erase the contents of the second register (ADD_TAG_REG) after correcting said information stored in the memory (ECC_MEM).

9. Method for transmitting at least one piece of information stored in a memory (ECC_MEM) to a processing unit (UT), comprising: - detecting an error in said information by implementing an error correction code algorithm and, in the event of detection of an error in said information, generating an interrupt signal (INT), - transmission of the interrupt signal to the processing unit (UT) only when the error is detected for the first time in said information by the error detection circuit.

10. Method according to claim 9, comprising a storage of the address of the location in the memory (ECC_MEM) of the last information having triggered a transmission of the interrupt signal (INT) and a comparison of the stored address with the address of the location in the memory (ECC_MEM) of the next information, for which an error is detected, transmitted after said last information so as to transmit the interrupt signal (INT) to the processing unit (UT) only when the address of the location in the memory (ECC_MEM) of said next information does not correspond to the stored address.

11. Method according to claim 10, wherein the storage comprises: - storing in a first register (ERR_ADD_REG) the address of the location in the memory (ECC_MEM) of said information in the event of detection of an error in said information, - storing in a second register (ADD_TAG_REG) the address contained in the first register (ERR_ADD_REG) before an error is detected in the next information, said comparison comprising generating a control signal having a value corresponding to the result of the comparison between the address contained in the first register and the address contained in the second register, and transmitting the interrupt signal (INT) only when the address stored in the first register does not correspond to the address stored in the second register.

12. Method according to one of claims 10 or 11, wherein said comparison of the stored address with the address of the location in the memory (ECC_MEM) of the next information is carried out as soon as the address of the last information is stored.

13. Method according to one of claims 10 to 12, comprising blocking the transmission of the interrupt signal (INT) until the address of said last information is stored.

14. Method according to one of claims 10 to 13, comprising, upon receipt of the interrupt signal (INT) by the processing unit (UT), a reading of the address stored in the second register (ADD_TAG_REG) by the processing unit (UT) and a storage in an additional memory (MEM) of the address read by the processing unit (UT).

15. Method according to claim 14, comprising correcting the information stored in the memory (ECC_MEM) at the corresponding addresses stored in the additional memory (MEM).

16. Method according to claim 15, comprising erasing the contents of the second register (ADD_TAG_REG) after correction of said information stored in the memory (ECC_MEM) by the processing unit (UT).

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