Input-output processing system for serial digital architectures and associated method

Abstract

One aspect of the invention relates to a method for memory access in a computer network included in an aircraft, the computer network comprising at least a first and a second device, the method comprising: Sending at least one sequential access request, by the first device, to a memory of the second device via a serial bus, the sequential access request comprising a plurality of contiguous memory addresses, Receiving, by an address conversion module included in the network and connected to the first device by the serial bus, the sequential access request, For each address of the plurality of contiguous memory addresses, converting, by the address conversion module of the network, the address into an address converted from predefined descriptors, Sending, by the address conversion module of the network, a request for access to the memory of the second device, each access request comprising at least one converted memory address.Figure to be published with the abstract: Figure 3.

Description

Title of the invention: Input-output processing system for serial digital architectures and associated method TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of the architecture of computer systems, and in particular in aeronautics.

[0002] The present invention relates to an input-output processing system for serial digital architectures and in particular such a system for use in aeronautics. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] Integrated components, in ASICs (Application-specific integrated circuit) or FPGAs (Field-Programmable Gate Array), dedicated to the processing of low-performance inputs / outputs such as CAN (Controller Area Network), UART (Universal Asynchronous Receiver-Transmitter), discrete signals, and A429 (ARINC 429, an avionics communication standard), have historically been characterized by register interfaces requiring frequent small read / write accesses to ensure their operation. This approach, functional in earlier architectures, is now faced with the challenges of modern architectures which favor the use of high-bandwidth serial buses, but with significant latency.

[0004] In the current context, the most relevant state-of-the-art solutions involve the widespread use of interrupt-based software, combined with DMAs (Direct Memory Access). This combination offers the possibility of offloading the processor during data transfers, thus allowing the processor to process other tasks simultaneously.

[0005] However, a significant limitation of this approach emerges in the aeronautical field. The specific requirements of this industry make it more difficult to operate and certify interrupt-based software architectures. In the aeronautical field, software architectures are more oriented towards the use of operating systems with deterministic and non-interruptible behavior. This orientation aims to strengthen the overall robustness of the architecture and to simplify the certification process, essential in this critical sector.

[0006] There is therefore a need for a solution that improves the performance of the prior art while having an uninterrupted architecture. Summary of the invention

[0007] The invention offers a solution to the problems mentioned above, by allowing, in an uninterrupted computer architecture, high-performance memory access between two devices connected by a high-speed, high-latency serial bus.

[0008] One aspect of the invention relates to a method of memory access in a computer network included in an aircraft, the computer network comprising at least a first and a second device, the method comprising: • Sending at least one sequential access request, by the first device, to a memory of the second device via a serial bus, the sequential access request comprising a plurality of contiguous memory addresses, • Reception, by an address conversion module included in the network and connected to the first device by the serial bus, of the sequential access request, • For each address of the plurality of contiguous memory addresses, conversion, by the network address conversion module, of the address into an address converted from predefined descriptors, • Transmission, by the network address conversion module, of a request for access to the memory of the second device, each access request comprising at least one converted memory address.

[0009] Thanks to the invention, the first device, for example a processor, performs sequential memory accesses, these sequential memory accesses then being converted on arrival, that is to say downstream of the serial bus separating the two devices, therefore as close as possible to the second device, for example an input / output manager, to which the first device wishes to have access. This makes it possible in particular to use the full capacities of the serial buses by performing sequential memory accesses while respecting the memory architecture of the input / output managers which impose non-sequential memory accesses. The address conversion module, thanks to predefined descriptors, is thus capable of converting the contiguous address sequences required by the first device into fragmented, non-contiguous addresses, corresponding to the actual location of the data required by the first device in the memory of the second device.

[0010] In addition to the characteristics which have just been mentioned in the preceding paragraph, the memory access method according to one aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations: • each predefined descriptor among the predefined descriptors includes a number of contiguous addresses to be converted, a converted starting address, and an offset information to be added to the converted starting address for get a next converted address matching the next contiguous address. • memory access is a memory read or a memory write. • the sequential access request is a memory write request, in which the sequential access request further comprises at least one data segment to be written in the memory of the second device and in which the access request issued by the address conversion module comprises the data segment to be written in the memory of the second device.

[0011] Another aspect of the invention relates to a system comprising at least a first and a second device, the system being included in an aircraft, the system being characterized in that it comprises an address conversion module and in that it is configured to implement the memory access method according to the invention.

[0012] In addition to the characteristics which have just been mentioned in the preceding paragraph, the system according to one aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations: • the first device is a processor and the second device is an input / output manager, the conversion module being included in the input / output manager. • the processor is a central computing unit or a microcontroller included in a first physical component, and the input / output manager is an FPGA included in a second physical component, the conversion module being included in the second physical component. • the system is a multi-chiplet component and the first device is a chiplet dedicated to computing, the second device is an input / output management chiplet, and in which the address conversion module is allocated to the input / output management chiplet. • the first device comprises a first direct memory access controller of the first device and the second device comprises a second direct memory access controller of the second device, the first direct memory access controller carrying out the step of transmitting the sequential access request to the second direct memory access controller. • the system further comprises a plurality of data acquisition devices connected to the second device. • the serial bus is mapped to the memory of the first device. • the serial bus is not of a memory-mapped type of the first device, • the first device is configured to issue the access request according to a predefined protocol, the predefined protocol defining a start and a size of memory space to be accessed, and • the conversion module is configured to decode the access request into the predefined protocol.

[0013] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0014] The figures are presented for information purposes only and in no way limit the invention. • [Fig.l] shows a schematic representation of a system according to the invention, • [Fig.2] shows a schematic representation of a first embodiment of a method according to the invention, • [Fig.3] shows a schematic representation of an address conversion in a method according to the invention, • [Fig.4] shows a schematic representation of an address conversion method included in a method according to the invention, • [Fig.5] shows a schematic representation of memory access comparison with and without the implementation of a system and method according to the invention, • [Fig.6] shows a schematic representation of a second embodiment of a method according to the invention, • [Fig.7] shows a schematic representation of a first embodiment of a system according to the invention, • [Fig.8] shows a schematic representation of a second embodiment of a system according to the invention, • [Fig.9] shows a schematic representation of a third embodiment of a system according to the invention. DETAILED DESCRIPTION

[0015] Unless otherwise specified, the same element appearing in different figures presents a unique reference.

[0016] [Fig.l] shows a schematic representation of a system according to a first aspect of the invention.

[0017] The system 10 according to the invention comprises a first device 11 and a second device 12. The system 10 according to the invention further comprises an address conversion module 13.

[0018] The first device 11 and the second device 12 each comprise a memory 111 and 121 respectively and a processor 112 and 122 respectively. When an action is assigned to a device, this action is in fact implemented by the processor of this device, by executing instructions stored in the memory of the device, the execution of the instructions by the processor leading the device to implement the action assigned to the device.

[0019] The system 10 is a computer network formed of the devices 11 and 12, but is also preferably included in a larger computer network, comprising other computer devices. In particular, the invention relates to an aircraft computer network, aircraft computer networks being characterized in that they rely on operating systems executed by processors with deterministic and non-interruptible behavior, the invention addresses the technical problem by taking this constraint into account.

[0020] The invention allows the first device 11 to make access requests to the memory 121 of the second device 12, via a serial bus 14. A serial bus is a type of computer bus configured to transmit data element by element, requiring serialization of the information for transmission and an inverse operation for reception. This type of bus transmits data sequentially, and is very present in recent architectures, in particular in aircraft computer networks. This invention makes it possible to maintain, in the aircraft computer network, the existing serial buses, while making the most of them. In the invention, the serial bus 14 can be for example of the PCIExpress or Ethernet type, and can be parallel or internal to the electronic components.

[0021] The invention notably allows better reading and writing performances than the prior art, the first device carrying out sequential access requests via the serial bus 14, memory addresses included in these sequential access requests being converted by the address conversion module 13 to access in a non-sequential manner the fragmented memory locations in the memory 121 of the second device 12.

[0022] To obtain these effects, the invention relates more particularly to a memory access method, the access being required by the first device 11, intended for the second device 12, for access to the memory 121 of the second device 12.

[0023] By "memory access" is meant an operation carried out in a memory, at a particular memory location, accessible via a particular memory address. Such an operation is for example an operation of reading the memory location at the specified memory address, i.e. acquiring the data stored at this memory location, or an operation of writing to the memory location, i.e. storing data at the memory location at the memory address specified. In a memory read operation, a memory access request is sent. In a memory write operation, a memory access request is sent along with the data segment to be stored at the specified memory location.

[0024] [Fig. 2] shows a schematic representation of a first embodiment of the method according to the invention, in which the memory access is a writing of the memory. [Fig.2] therefore schematically represents a first method 20, according to a first embodiment of the method according to the invention.

[0025] The memory access method 20 comprises a first step 21 of sending at least one write request, by the first device 11, to the memory 121 of the second device 12. According to the invention, the write request is a sequential access request, sent via the serial bus 14. The access request therefore complies with the sequential format for which the serial bus is the most efficient, guaranteeing better data transfer performance than in the state of the art.

[0026] A “sequential access” request is a request comprising a plurality of contiguous memory addresses, i.e. starting at a given starting memory address, and comprising a plurality of these memory addresses whose subsequent addresses are separated by a fixed increment. For example, and as shown in the left column of [Fig. 3], all the memory addresses are contiguous, the sequence of memory addresses starting at memory address 0x00100, and comprising a plurality of memory addresses incremented by 1 up to address OxOO10B. Thus, a single sequential access request comprises a plurality of contiguous memory addresses, making it possible to perform a single “burst” type access from the point of view of the first device 11.

[0027] This sequential access request is sent on the serial bus 14 by the first device 11 and received, at a step 22 of the method 20, by the address conversion module 13. The address conversion module 13 is preferably a physical module, but may also, without departing from the invention, be a software module. This will be described in more detail later.

[0028] Upon receipt of the sequential access request, the address conversion module 13 performs the conversion, in a step 23, of each memory address of the plurality of contiguous memory addresses included in the sequential access request, into a destination address in the memory of the second device. To perform this conversion 23, the conversion module 13 stores or accesses a table of descriptors, the descriptors defining how and into which destination address to convert each address of a sequence of contiguous addresses. To use this table, the address conversion module 13 implements an address conversion method 40 and access. An example of an address conversion and memory access process is shown in [Fig.4].

[0029] This conversion method 40 comprises a plurality of steps 41 to 56.

[0030] In a first step 41, the starting address of the sequence of contiguous memory addresses of the access request is received and read, and a descriptor table address is deduced therefrom, from a predefined offset applied to the received address.

[0031] In step 42, the descriptor type stored at the descriptor address is read.

[0032] In step 43, depending on the type of the descriptor, one of steps 44 to 47 is implemented. artwork.

[0033] If the descriptor is of type “DUMP”, the “dump” mode is implemented in step 44 and the memory writes are ignored. This descriptor makes it possible to indicate the end memory address. The method 40 must then be restarted with a new sequential access request.

[0034] If the descriptor is of type "TARGET_ADDRESS", i.e. "target address", step 45 is implemented, i.e. a step during which the conversion address is defined as a fixed address predefined in the descriptor. The method 40 then moves on to the next descriptor in the descriptor table by incrementing the descriptor address in step 50.

[0035] If the descriptor is of type "NEXT_DESCRIPTOR_LENGTH_LIMIT", i.e. "length limit of the next descriptor", step 46 is implemented. Step 46 then defines the value of a data segment length limit parameter to be written, the value of the parameter being a value included in the descriptor of this type. The method 40 then moves on to the next descriptor in the descriptor table by incrementing the descriptor address in step 50. The next descriptor of type "DATA_SEGMENT" will then be limited in size for writing and / or reading in the memory by the length limit parameter.

[0036] Finally, if the descriptor is of type "DATA_SEGMENT", that is to say if the descriptor corresponds to a data segment to be read or written, step 47 is implemented. In step 47, from the descriptor, the length of the data segment, the offset, and the conversion address are defined. An example is notably represented in the central column of [Fig.3], which shows a descriptor table. For example, the descriptor table associated with the address 0x0100 indicates that the most significant bit (MSB for "Most Significant Bit" in English) is 0x00000, then that the first memory address ("data len" corresponding to the number of addresses converted, "start" corresponding to the conversion start address) of the sequence of contiguous memory addresses must be converted to address 0x0500. The address 0x00100 received in the sequential access request is therefore converted to 0x00500. This same descriptor table then indicates that the following two addresses must be associated with addresses whose starting address is 0x0520, that is, respectively with memory addresses 0x00520 and 0x00521. Then, the following three addresses (data len = 3) are converted to addresses whose starting address is 0x05A0, with a high-order bit at 0x00000 and with an offset of 4 (“Stride 4”). This offset information depends on the type of the descriptor, also indicated in the descriptor table but not shown. Thus, the conversion addresses of the three addresses 0x00103, 0x00104 and 0x00105 are 0x005A0, 0x005A4 and 0x005A8, all separated by an offset of 4 symbol sizes of bus 14. The descriptor table then indicates a change of the most significant bit (MSB). Thus, the next two addresses (data len = 2) are converted to addresses whose starting address is 0x10000. The conversion addresses of the two addresses 0x00106 and 0x00107 are therefore 0x10000 and 0x10001.The descriptor table then indicates another change of the most significant bit (MSB). Thus, the next hundred addresses (data len = 100) are converted to addresses whose starting address is 0x70000. The conversion addresses of the next hundred addresses in the sequential access request therefore start at 0x7A000 and are incremented by 1.

[0037] To perform these conversions, and to change descriptors (i.e., to move to the next descriptor), once the descriptor has been read, the starting conversion address, the offset and the segment length have been determined from the descriptor in step 47, step 48 includes a check that the length of the segment remaining to be written and / or read is not zero. If the length of the data segment remaining to be written and / or read is zero, the data segment length limit parameter is disabled in step 49 and the descriptor address in the descriptor table is incremented in step 50 to read the next descriptor, because the data segment has been completely written and / or read.

[0038] On the contrary, if the length of the segment remaining to be written and / or read is not zero, step 51 is carried out. Step 51 is a step called “run”, which consists of applying the decoded address to the internal memory of the address conversion module or of the device implementing the address conversion module.

[0039] Step 52 includes a check whether the data segment length limit parameter has been activated or not. If it has been activated (for example because the previous descriptor was of type "NEXT_DESCRIPTOR_LENGTH_LIMIT"), it is checked in step 53 whether this limit is 0. If this limit is 0, the access limit size defined by the length limit parameter has been reached and the user goes directly to step 56. On the contrary, if this limit is not 0, the limit size has not been reached, and the value of the parameter is decremented in step 54 by a predefined value, then step 55 is carried out.

[0040] Similarly, if the length limit parameter has not been activated, access to the conversion address is authorized in a step 55 of executing the required memory access (reading and / or writing).

[0041] In step 56, the length of the segment read from the descriptor is decremented, to write and / or read the rest of the segment. The method then resumes at step 48 with the length of the segment decremented, until the length of the segment reaches 0, or the value of the length limit parameter reaches 0.

[0042] This method 40 for address conversion and memory access makes it possible to carry out step 23 of the method 20 for address conversion, but also step 24 of the method 20. Step 24 of the method 20 is a step of transmission, by the address conversion module 13, of a request for access to the memory of the second device 12, each access request comprising at least one converted memory address. This corresponds in particular to step 55 of the method 40, which carries out the accesses to the memory at the conversion address for the data segments.

[0043] The invention therefore makes it possible, from a request for sequential access to the memory of the second device 12 sent by the first device 11 via a serial bus 14, to convert, downstream of the bus 14, i.e. as close as possible to the second device 12, the sequence of contiguous memory addresses into fragmented memory addresses, i.e. into real memory addresses of the second device 12, in order to achieve efficient memory access.

[0044] The performances of the method and the system according to the invention are represented in [Fig. 5]. Diagram A of [Fig. 5] shows a schematic representation of the number of memory accesses achievable with current architectures, i.e. in the state of the art. On the contrary, the solution of the present invention makes it possible to carry out a much greater number of accesses than the state of the art in the same time window, as represented in diagrams B and C, which respectively represent the memory accesses seen from the first device 11, and the memory accesses carried out by the conversion module 13, i.e. actually carried out in the memory of the second device 12.Indeed, unlike the state of the art, the serial bus 14 is not a factor limiting the data exchanges since sequential accesses are carried out via this bus 14, which allows numerous successive accesses to the memory of the second device 12, even if the data in the memory of the second device 12 are not accessible sequentially.

[0045] In a second embodiment of the memory access method according to the invention, shown in [Fig. 6], the memory access performed is a reading. The method 60 therefore comprises steps 21 to 24 of the method 20, and an additional step 61 of transmitting the data to the first device 11, the data having been read at the memory addresses specified in the memory 121 of the second device 12.

[0046] The methods 20 and 60 can be implemented by the system 10 of [Fig. 1]. More specifically, several embodiments of the system according to the invention will now be described.

[0047] As shown in [Fig. 7], the system 70 is a first embodiment of the system 10 according to the invention, configured to implement the memory access method according to the invention. This system 70 comprises the first device 11 and a second device 72. In this embodiment, the first device 11 is a processor, for example a CPU (Central Processing Unit) or a microcontroller. For example, the first device 11 is a CPU of the QorlQ® T1042 type, comprising memories 111, a core 112, a bus controller 113, a DMA controller 114 (for Direct Access Memory), and an interconnect 115.

[0048] In this embodiment, the address conversion module 13 is included in the second device 72. Thus, the second device 72 differs from the second device 12 only in that it includes the address conversion module 13. In this embodiment, the second device 72 is an input / output manager of the aircraft. In the context of aircraft, the input / output manager 72 is designed to temporarily store data from acquisition devices of the aircraft. In [Fig. 7], the devices 151 and 152 are data acquisition devices, for example sensors. For example, in an onboard data acquisition system, the input / output manager may be responsible for collecting and routing data from sensors or other acquisition devices to the CPU or other components of the system.This temporary storage may be necessary to ensure the consistency and reliability of the data before they are processed or transmitted to other systems on board the aircraft. In addition, the input / output manager 72 comprises, for example, a function for acquiring discrete inputs DSI (for “Discrete Signal Input”) and generating discrete outputs DSO (for “Discrete Signal Output”), data that the input / output manager 72 stores in memory. It is, for example, this type of data that the processor 11 wishes to access by making a memory access request. For example, the input / output manager 72 is an FPGA (from the English “Field-Programmable Gate Array” for “network of programmable gates in situ” in French).

[0049] In the embodiment of [Fig.7], the two devices 11 and 72 are included in different physical components, that is to say they are separate physical devices. The address conversion module 13 is then for example a software module implemented by the FPGA 72. The two devices 11 and 72 are connected in communication via the serial bus 14, for example in PCIExpress® format. The CPU 11 can then use its DMA controller 114 to carry out large sequential access requests, for example having a size greater than or equal to 64 bytes, therefore efficient, access requests whose addresses will then be converted into fragmented addresses intended for the memory of the input / output manager 12.

[0050] [Fig. 8] shows a schematic representation of a second embodiment of the system according to the invention. The system 80 of [Fig. 8] comprises a first device 81, and a second device 82 which differs from the first device 81 only in that it comprises the address conversion module 13. In this embodiment, the two devices are chiplets, that is to say “fragmented chips”, that is to say electronic chips dedicated to a function. Thus, the chiplet 81 is dedicated to a calculation function. In this, it is a calculation chiplet. The 82 chiplet is dedicated to an input / output management function.In this, it is an aircraft input / output manager chiplet. The chiplets 81 and 82 are connected in communication via a chiplet communication bus 14.

[0051] The chiplet 81 can then use its DMA controller 114 to carry out large sequential access requests, for example preferably of a size greater than or equal to 64 bytes, therefore efficient, access requests whose addresses will then be converted into fragmented addresses intended for the memory of the input / output chiplet 82.

[0052] [Fig. 9] shows a schematic representation of a third embodiment of the system according to the invention. The system 90 shown in [Fig. 9] comprises two devices 91 and 92. The first device 91 is a CPU of the QorlQ® T1042 type, comprising memories 111, a core 112, a bus controller 113, a DMA controller 114, and an interconnect 115. In this embodiment, the particularity is that the second device 92 also comprises a DMA controller 123. The second device 92 is for example an FPGA, input / output manager of an aircraft, making it possible to avoid read accesses which are more bandwidth-intensive. Both DMA controllers 114 and 123 perform write memory accesses to the other device: DMA 114 of CPU 91 writes to DMA 123 of FPGA 92 and DMA 123 of FPGA 92 writes to DMA 114 of CPU 91.This finds for example an interesting application in imaging, the second device 92 being a camera comprising the DMA controller 123, making it possible to improve the reading bandwidth. Indeed, the camera 92 then writes directly to the CPU 91, which makes it possible to avoid readings from the CPU 91 to the camera 92 and therefore to reduce the bandwidth.

[0053] In an embodiment of the system 10 compatible with the three embodiments of the system described previously in [Fig. 6] to 9, the bus is a memory-mapped bus, which makes it possible not to require a communication protocol. particular, the memory addresses being converted on the fly upon receipt of the sequential access requests by the address conversion module 13. A “memory mapped” bus is understood here as a bus making it possible to make the memory addresses of the second device 12 into memory addresses directly accessible by the bus master, that is to say by the first device 11.

[0054] In another embodiment of the system 10 compatible with the three embodiments of the system described previously in [Fig. 6] to 9, the bus is a non-memory mapped bus, for example Ethernet or RS422, which requires the implementation of a communication protocol between the first device 11 and the second device 12. Indeed, the memory addresses of the second device 12 are then not directly accessible by the first device 11. The first device, when it issues a sequential access request in step 21, must then issue its request in a protocol indicating a start address and a size of memory space to be accessed (read or write). In the same way, during read operations, the second device 12 sends its data segments in the predefined protocol, allowing identification of the data segments, their start and their size.For example, in Ethernet, the second device 12 can be configured to automatically send frames according to a predefined protocol, identifying the data segments sent, which makes it possible to avoid read requests from the first device 11.

Claims

Claims

1. Method (2) for memory access in a computer network included in an aircraft, the computer network comprising at least a first (11) and a second (12) device, the method (2) comprising: - Transmission (21) of at least one sequential access request, by the first device (11), to a memory of the second device (12) via a serial bus (14), the sequential access request comprising a plurality of contiguous memory addresses, - Reception (22), by an address conversion module (13) included in the network and connected to the first device (11) by the serial bus (14), of the sequential access request, - For each address of the plurality of contiguous memory addresses, conversion (23), by the address conversion module (13) of the network, of the address into an address converted from predefined descriptors, - Transmission (24), by the address conversion module (13) of the network,of a request for access to the memory of the second device (12), each access request comprising at least one converted memory address.,

2. Memory access method (2) according to the preceding claim wherein each predefined descriptor among the predefined descriptors comprises a number of contiguous addresses to be converted, a converted starting address, and offset information to be added to the converted starting address to obtain a next converted address corresponding to the next contiguous address.

3. Method (2) of memory access according to one of the preceding claims in which the memory access is a memory read or a memory write.

4. A memory access method according to claim 3 wherein the sequential access request is a memory write request, wherein the sequential access request further comprises at least one data segment to be written to the memory of the second device (12) and wherein the access request issued by the address conversion module comprises the data segment to be written to the memory of the second device (12).

5. System (10) comprising at least a first (11) and a second (12) device, the system (10) being included in an aircraft, the system (10) being characterized in that it comprises an address conversion module (13) and in that it is configured to implement the memory access method (2) according to one of the preceding claims.

6. System (10) according to the preceding claim in which the first device (11) is a processor and the second device (12) is an input / output manager, the address conversion module (13) being included in the input / output manager.

7. System (10) according to claim 6 wherein the processor is a central computing unit or a microcontroller included in a first physical component, and wherein the input / output manager is an FPGA included in a second physical component, the conversion module (13) being included in the second physical component.

8. System (10) according to claim 5 wherein the system is a multi-chiplet component and wherein the first device (11) is a chiplet dedicated to calculation, the second device (12) is an input / output management chiplet, and wherein the address conversion module (13) is allocated to the input / output management chiplet.

9. System (10) according to one of claims 5 to 8 wherein the first device (11) comprises a first direct memory access controller of the first device (11) and the second device comprises a second direct memory access controller of the second device (12), the first direct memory access controller carrying out the step of transmitting (24) the sequential access request to the second direct memory access controller.

10. System (10) according to one of claims 5 to 9 further comprising a plurality of data acquisition devices connected to the second device (12).

11. System (10) according to one of claims 5 to 10 wherein the serial bus is mapped into memory of the first device (11).

12. System (10) according to one of claims 5 to 10 in which: - the serial bus (14) is not of a type mapped into memory of the first device (11), the first device (11) is configured to transmit (24) the access request according to a predefined protocol, the predefined protocol defining a start and a size of memory space to be accessed, and the conversion module (13) is configured to decode the access request into the predefined protocol.

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