Nested FETs with conformal gate

Abstract

Title: Nested FET transistors with a conformal gate A device comprising first and second transistors (T1, T2), the first transistor (T1) comprising: a first inner gate (G1) a first outer gate (GC) a first channel (C1) surrounding the first inner gate (G1), and surrounded by the first outer gate (GC) dielectric layers (I1, I2) between the first channel (C1) and the first gates (G1, GC), the second transistor (T2) comprising: a second inner gate (GC) a second outer gate (G2) a second channel (C2) surrounding the second inner gate (GC), and surrounded by the second outer gate (G2), dielectric layers (I3, I4) between the second channel (C2) and the second gates (GC, G2). Advantageously, the first external gate and the second internal gate form a single gate (GC), so that the first and second transistors (T1, T2) are nested. Figure for abstract: Fig.1

Description

Title of the invention: Nested FET transistors with a conformal gate Technical field

[0001] The invention relates to the field of microelectronic technologies. It finds a particularly advantageous application in the manufacture of advanced FET (Field-Effect Transistor) type devices with a coated gate. STATE OF THE ART

[0002] The constant increase in transistor performance was first made possible by the reduction in transistor dimensions, for a classic MOSFET (“Metal-Oxide-Semiconductor Field-Effect Transistor”) architecture based on silicon.

[0003] This classic architecture then gave way to other types of architectures better suited to the performances specified in technological nodes below 12 nm. The so-called "finFET" architecture, for example, makes it possible to meet the performances set by the 7 nm technological node.

[0004] For the next technological nodes, in particular from 3 nm, other architectures offering improved gate confinement are necessary. An architecture envisaged to address the problems of these next technological nodes includes wrapped gate transistors called GAA transistors (acronym for Gate Ail Around), stacked on top of each other.

[0005] The document "INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2021, VOL. 67, NO. 1, PP. 29-34" discloses different MOSFET transistor architectures. In particular, a so-called DSG architecture (acronym for "Double Surrounding Gate") is considered in this document. The integration of these transistors is however not optimal.

[0006] Furthermore, stronger integration, better electrostatic control in the conduction channel, reduced leakage currents and / or limited power consumption remain major challenges for the development of MOSFET transistor architectures.

[0007] One objective of the invention is to propose a device that meets these challenges. Another objective of the invention is to at least partially overcome the drawbacks of known architectures. SUMMARY

[0008] To achieve these objectives, according to one embodiment, a device is provided comprising a first transistor and a second transistor, said first and second transistors being metal-oxide-semiconductor field effect transistors (MOSFET), the first transistor comprising: - a first internal grid, - a first external grid, - a first channel at least partly surrounding the first internal grid, and surrounded at least partly by the first external grid - a first dielectric layer between the first internal grid and the first channel, - a second dielectric layer between the first channel and the first external gate.

[0009] The second transistor comprises: - a second internal grid, - a second external grid, - a second channel at least partly surrounding the second internal grid, and surrounded at least partly by the second external grid, - a third dielectric layer between the second internal grid and the second channel, - a fourth dielectric layer between the second channel and the second external gate.

[0010] Advantageously, the first external gate and the second internal gate form a single gate called an intermediate gate, so that the first and second transistors are nested.

[0011] Thus, unlike known devices which at best envisage a stack of transistors, the architecture of the device according to the invention is based on the nesting or interlocking of at least two transistors. The size of the device is thus reduced. This makes it possible to improve the integration of the transistors. The drain current in the on state is also increased. Each of these transistors also benefits from a configuration with multiple wrapping gates. This makes it possible to improve electrostatic control and reduce the effects of small geometries. Leakage currents are reduced or even eliminated in such a configuration. The energy consumption of the device is reduced. The switching frequency of the transistors can also be increased. The performance of the device is thus generally improved.

[0012] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. BRIEF DESCRIPTION OF THE FIGURES

[0013] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0014] [Fig.l] [Fig.l] illustrates a block diagram of a nested transistor device according to one embodiment of the present invention.

[0015] [Fig.2] [Fig.2] illustrates a block diagram of a transistor device nested according to another embodiment of the present invention.

[0016] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, on the schematic diagrams, the thicknesses and / or dimensions of the different layers and patterns are not representative of reality. DETAILED DESCRIPTION

[0017] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0018] According to one example, the first transistor is an N-type transistor and the second transistor is a P-type transistor. The nested transistors are typically complementary MOS transistors. This makes it possible to integrate multi-gate transistors in CMOS technology with reduced bulk.

[0019] According to one example, the first internal grid, the first dielectric layer, the first channel, the second dielectric layer, the intermediate grid, the third dielectric layer, the second channel, the fourth dielectric layer, the second external grid are arranged concentrically around a longitudinal axis (O). According to one example, the first internal grid is in the form of a cylinder of circular section and the other elements are in the form of concentric rings around the first cylindrical internal grid.

[0020] According to one example, the first internal grid, the first dielectric layer, the first channel, the second dielectric layer, the intermediate grid, the third dielectric layer, the second channel, the fourth dielectric layer, the second external grid have a symmetry of revolution around the longitudinal axis (O).

[0021] According to one example, the first internal grid is a solid cylinder of circular or rectangular or square section.

[0022] According to one example, at least one of the first channel and the second channel is based on a 2D material such as a transition metal dichalcogenide or other 2D materials.

[0023] According to one example, at least one of the first channel and the second channel is based on a 2D material such as a transition metal dichalcogenide of the type MX2 where M is a transition metal, for example is molybdenum (Mo) or tungsten (W) and X is a chalcogen, for example sulfur (S) or selenium (Se).

[0024] According to one example, the first channel only partially surrounds the first inner gate, and is only partially surrounded by the intermediate gate. According to one example, the second channel only partially surrounds the intermediate gate, and is only partially surrounded by the second outer gate. According to one example, the first dielectric layer, the first channel, the second dielectric layer, the intermediate gate, the third dielectric layer, the second channel, the fourth dielectric layer, the second outer gate have a U-shape in an xy plane perpendicular to the longitudinal axis (O). These elements typically surround the first inner gate on three sides.

[0025] According to one example, the first internal gate, and / or the intermediate gate, and / or the second external gate are based on a ferroelectric material. This allows better control of the surface potential of each channel. The switching between the blocking state (OFF) and the conducting state (ON) of the first and second transistors is more abrupt, which makes it possible to improve the performance of the transistors at low voltage.

[0026] According to one example, the first channel is connected on one side to a first N+ doped source and on an opposite side to a first P+ doped drain, and the second channel is connected on said side to a second N+ doped source and on the opposite side to a second P+ doped drain, such that the first and second transistors are tunnel field effect transistors (TFETs). According to another example, the first channel is connected on one side to a first N+ doped source and on an opposite side to a first P+ doped drain, and the second channel is connected on said side to a second P+ doped drain and on the opposite side to a second N+ doped source.

[0027] According to an example, the first channel is of type N and connected on one side to a first N+ doped source and on an opposite side to a first N+ doped drain, and the second channel is of type P and connected on said side to a second P+ doped source and on the opposite side to a second P+ doped drain, so that the first and second transistors are complementary metal-oxide-semiconductor field effect transistors (MOSFETs). The second P+ doped source and the second P+ doped drain can be interchanged.

[0028] According to an example, the first channel and the second channel respectively have a first section and a second section, taken in an xy plane, and the second section has a surface area greater than that of the first section. Advantageously, the second channel is of type P and the first channel of type N. The difference in carrier mobility between the first NMOS transistor and the second PMOS transistor is thus compensated by increasing the section of the second channel, for the second PMOS transistor. The performances of the first and second NMOS and PMOS transistors are thus substantially equivalent, which improves the performances of the CMOS.

[0029] According to one example, the first internal grid and the second external grid are connected to each other, so as to present the same potential.

[0030] According to another example, the device comprises only the intermediate grid. It does not comprise the first internal grid, nor the second external grid.

[0031] Unless incompatibility exists, it is understood that all of the above optional features may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.

[0032] The invention relates generally to a microelectronic device architecture with GAA (acronym for Gate Ail Around) transistors, which can also be referred to as GAIA (acronym for Gate Ail Inside and Around). The channels of the transistors can be in the form of nanotubes or nanosheets wrapped around each other.

[0033] Advantageously, such an architecture can be implemented in CMOS (acronym for Complementary Metal-Oxide-Semiconductor) technologies for 5 nm and sub-5 nm technology nodes.

[0034] A microelectronic device comprising nested GAA or GAIA transistors can be advantageously integrated into logic systems having 3D architectures. These transistors can in particular be associated with other structural or functional elements so as to design complex systems, for example non-volatile memories. Such non-volatile memories can advantageously take advantage of the particular architecture of the device according to the invention to increase the storage capacities over several bits, for example by storing charges in the internal and / or external gates of the transistors.

[0035] A particular aspect of the invention concerns the implementation of 2D materials to produce the nanotubes or nanosheets of the device.

[0036] 2D materials typically correspond to compounds with a lamellar structure consisting of two-dimensional sheets. The atomic bonds within each sheet are strong, covalent in nature. The bonds between sheets are much weaker, of the Van der Waals type. These two-dimensional sheets are also called monolayers.

[0037] In the context of the present invention, the monolayers are preferably semiconductor monolayers of the MX2 type where M is a transition metal and X a chalcogen. Each “monolayer” is here composed of a sheet of cations metallic M inserted between two sheets of anions X. A monolayer therefore typically comprises three atomic sheets or planes: the atoms of the transition metal (for example Mo or W) form a plane or a sheet sandwiched between two planes or sheets of chalcogens (S, Se or Te, for example).

[0038] The monolayers of transition metal dichalcogenides MX2 are preferably based on molybdenum disulfide MoS2, MoSe2, MoTe2, WS2, WSe2.

[0039] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0040] A substrate, a film, a layer, “based” on a material A, is understood to mean a substrate, a film, a layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements.

[0041] The doping ranges associated with the different types of doping indicated in the present application are as follows: - P++ or n++ doping: greater than 1 x 1020 cm3 - p+ or n+ doping: 1 x 1018 cm3 to 9 x 1019 cm3 - p or n doping: 1 x 1017 cm3 to 1 x 1018 cm3 - intrinsic or non-intentionally doped doping: 1 x 1015 cm3 to 1 x 1017 cm3

[0042] In the following, the following abbreviations relating to a material M are optionally used:

[0043] Mi refers to the intrinsic or unintentionally doped material M, according to the terminology usually used in the field of microelectronics for the suffix -i.

[0044] Mn refers to the n, n+ or n++ doped material M, according to the terminology usually used in the field of microelectronics for the suffix -n.

[0045] Mp refers to the p, p+ or p++ doped material M, according to the terminology usually used in the field of microelectronics for the suffix -p.

[0046] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator.

[0047] A preferably orthonormal reference frame, comprising the axes x, y, z is shown in the attached figures.

[0048] In the present patent application, we will preferentially speak of thickness for a layer or a film, and of height for a device or a structure. The thickness is taken in a direction normal to the main extension plane of the layer or film. Thus, for a layer extending around a cylinder and typically having a symmetry of revolution around a longitudinal axis of this cylinder, the thickness is measured radially, in a direction of the xy plane. The relative terms “on”, “overcomes”, “under”, “underlying” refer to positions taken in a radial direction of the xy plane.

[0049] The terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the limits are included, unless otherwise stated.

[0050] The following description presents an example of the principle of the device according to the invention as a basic building block for microelectronic technologies. The scope of this description is obviously not limiting of the invention.

[0051] [Fig.l] schematically illustrates a device comprising nested GAIA transistors, according to a first embodiment.

[0052] The first transistor T1 comprises the first internal gate Gl, the first dielectric layer II, the first channel Cl, the second dielectric layer 12 and the intermediate gate GC.

[0053] The second transistor T2 comprises the intermediate gate GC, the third dielectric layer 13, the second channel C2, the fourth dielectric layer 14 and the second external gate G2.

[0054] The first and second transistors T1, T2 share the intermediate gate GC. This intermediate gate GC is therefore common to the two transistors T1, T2.

[0055] Such a “nested” architecture advantageously makes it possible to save space when integrating transistors T1, T2 on a microelectronic chip. This makes it possible to increase the total number of transistors on a given area of ​​the chip. The integration density is increased.

[0056] Each of the first and second transistors T1, T2 further comprises two encapsulating gates, in particular an “internal” gate and an “external” gate. For a concentric nesting configuration as illustrated in [Fig.l], the channel C1 of the transistor T1 faces the internal gate G1 and the external gate GC at any point of the channel. In the same way, the channel C2 of the transistor T2 faces the internal gate GC and the external gate G2 at any point of the channel. This makes it possible to improve the figures of merit of the transistors T1, T2, which in particular have: - A better drain current in the ON state of the transistor. This is interesting for the frequency performance of each of the transistors. - Higher drain current at lower voltage. This allows operation at lower voltage. Static and dynamic power consumption are advantageously reduced. - Lower current in the OFF state of the transistor. This reduces static power consumption. - Improved transition between OFF and ON state.

[0057] In the configuration illustrated in [Fig.l], the channel C1 is similar to a first tube of annular section, inside which the gate G1 is located and around which the gate GC extends. The channel C2 is similar to a second tube of annular section, inside which the gate GC is located and around which the gate G2 extends. The different elements of the transistors T1, T2 are typically concentric, around the longitudinal axis (O). In [Fig.l], the channels C1, C2 are partially uncovered to illustrate the nesting of the different constituent layers of the transistors T1, T2. A person skilled in the art will know how to adjust the dimensions along z of each of the channels C1, C2 and of each of the layers II, I2, GC, I3, I4, G2 so as to obtain a connected and integrated structure. The channels Cl, C2 are respectively connected along z to the sources and drains SI, DI and S2, D2. The connection of the grid G1 can typically be made along z.The connection of the G2 grid can typically be made along a direction of the xy plane. The connection of the GC grid can be made either along z or along a direction of the xy plane.

[0058] The dielectric layers II, 12, 13, 14 may be of the same nature, for example based on SiO2, and have substantially identical thicknesses. Other choices of materials and / or other thickness dimensions are conceivable, depending on the intended applications.

[0059] The Cl, C2 channels may be based on silicon or germanium or a III-V material, the semiconductor material being able to be strained or not. Alternatively, the Cl, C2 channels may be based on a 2D material, for example based on a transition metal dichalcogenide MX2 where M is a transition metal and X a chalcogen.

[0060] According to one possibility, one or more of the gates G1, G2, GC are based on a ferroelectric material. This allows better control of the surface potential of the channels C1 and / or C2. The switching between the OFF state and the ON state of each transistor can thus be more abrupt and be done at a lower voltage.

[0061] According to one possibility, the transistors T1, T2 are respectively NMOS and PMOS transistors. The channel C1 is of type N. The source S1 and the drain D1 have the same type of conductivity, for example N+. The channel C2 is of type P. The source S2 and drain D2 have the same conductivity type, for example P+. The integration of nested NMOS and PMOS transistors is facilitated.

[0062] The nesting of the NMOS and PMOS transistors also makes it easier to manage the sizing of these NMOS and PMOS transistors. This makes it possible to balance the performance of each of the NMOS and PMOS transistors. In particular, the section of the C2 channel is increased with respect to the section of the Cl channel, for the same thickness of the Cl, C2 channel layer. This makes it possible to compensate for the lower mobility of the carriers in the PMOS, compared to the NMOS. This architecture thus promotes performances for the balanced NMOS and PMOS transistors. This architecture is particularly interesting for improving the performance of CMOS technologies.

[0063] According to another possibility, the transistors T1, T2 are tunnel field effect transistors (TFETs). The channel C1 is typically unintentionally doped, Si-i for example. The source SI and the drain DI have opposite conductivity types, typically N+ and P+. The channel C2 is typically unintentionally doped, Si-i for example. The source S2 and the drain D2 have opposite conductivity types, typically N+ and P+. The association of the TFET transistors with the nested GAIA architecture allows in particular better control of the tunnel effect transport between source, channel and drain. The tunnel current between source and drain can thus be higher than that achievable by known TFET architectures.

[0064] The nesting of the transistors according to this first embodiment is not limited to the annular shape of the tubes illustrated in [Fig.l]. The different tube-shaped elements of the transistors T1, T2 may have a square or rectangular section for example. This makes it possible, for example, to optimize the integration of the nested transistors within a larger system. For each transistor, the internal gate in this case covers four sides of the corresponding channel, and the external gate also covers four sides of this channel. This GAIA transistor configuration can thus be described as “8G”, i.e. an eight-gate configuration.

[0065] [Fig.2] illustrates a second embodiment where the nested transistor structure comprises two “6G” transistors, where the inner and outer gates of each transistor each cover three sides of the channel of the transistor in question. The principles and advantages, and the variants described above for the 8G transistor structure are also applicable to this 6G transistor structure.

[0066] Increasing the number of gates in 6G or 8G configuration allows for better electrostatic control of the nested transistor channels. Short channel effects and leakage currents are reduced. The inversion or accumulation slope of the transistors is optimized. It approaches the ideal slope of MOS transistors at room temperature (60mV / decade), and may be lower than this value for TFET transistors.

[0067] In view of the preceding description, it appears clearly that the nesting of the transistors combined with the increase in the number of gates controlling the conduction channel, equivalent to six or eight gates, allows better integration and an overall improvement of the electrical properties of the transistors. This architecture is furthermore advantageously compatible with standard microelectronics methods. The invention is however not limited to the embodiments previously described.

Claims

Claims

1. Device comprising a first transistor (Tl) and a second transistor (T2), said first and second transistors (Tl, T2) being field effect transistors (FET), the first transistor (Tl) comprising: • a first internal gate (Gl) • a first external gate (GC) • a first channel (Cl) at least partly surrounding the first internal gate (Gl), and surrounded at least partly by the first external gate (GC) • a first dielectric layer (II) between the first internal gate (Gl) and the first channel (Cl), • a second dielectric layer (I2) between the first channel (Cl) and the first external gate (GC), the second transistor (T2) comprising: • a second internal gate (GC) • a second external gate (G2) • a second channel (C2) at least partly surrounding the second internal gate (GC), and surrounded at least partly by the second external gate (G2),• a third dielectric layer (13) between the second internal gate (GC) and the second channel (C2), • a fourth dielectric layer (14) between the second channel (C2) and the second external gate (G2), said device being characterized in that the first external gate and the second internal gate form a single gate (GC) called intermediate, so that the first and second transistors (T1, T2) are nested.,

2. Device according to the preceding claim in which the first transistor (T1) is an N-type transistor and the second transistor (T2) is a P-type transistor.

3. Device according to any one of the preceding claims in which the first internal gate (Gl), the first dielectric layer (II), the first channel (Cl), the second dielectric layer (12), the intermediate gate (GC), the third dielectric layer (13), the second channel (C2), the fourth layer dielectric (14), the second external grid (G2) are arranged concentrically around a longitudinal axis (0).

4. Device according to the preceding claim in which the first internal grid (Gl), the first dielectric layer (II), the first channel (Cl), the second dielectric layer (12), the intermediate grid (GC), the third dielectric layer (13), the second channel (C2), the fourth dielectric layer (14), the second external grid (G2) have a symmetry of revolution around the longitudinal axis (0).

5. Device according to any one of the preceding claims in which the first internal grid (Gl) is a solid cylinder of circular or rectangular section.

6. A device according to any preceding claim wherein at least one of the first channel (Cl) and the second channel (C2) is based on a 2D material such as a transition metal dichalcogenide of the MX2 type where M is a transition metal, for example molybdenum (Mo) or tungsten (W) and X is a chalcogen, for example sulfur (S) or selenium (Se).

7. Device according to any one of the preceding claims in which the first channel (Cl) only partly surrounds the first internal grid (Gl), and is only partly surrounded by the intermediate grid (GC), and in which the second channel (C2) only partly surrounds the intermediate grid (GC), and is only partly surrounded by the second external grid (G2).

8. Device according to any one of the preceding claims in which the first internal grid (G1), and / or the intermediate grid (GC), and / or the second external grid (G2) are based on a ferroelectric material.

9. Device according to any one of the preceding claims in which the first channel (Cl) is connected on one side (PI) to a first source (SI) doped N+, and on an opposite side (P2) to a first drain (Dl) doped P+, and the second channel (C2) is connected on said side (PI) to a second source (S2) doped N+ and on the opposite side (P2) to a second drain (D2) doped P+, so that the first and second transistors (Tl, T2) are tunnel field effect transistors (TFET).

10. Device according to any one of claims 1 to 8 in which the first channel (Cl) is of type N and connected on one side PI) to a first source (SI) doped N+ and on an opposite side (P2) to a first drain (Dl) doped N+, and the second channel (C2) is of type P and connected from said side (PI) to a second source (S2) doped P+ and on the opposite side (P2) to a second drain (D2) doped P+, so that the first and second transistors (Tl, T2) are complementary field effect transistors of the metal-oxide-semiconductor type (MOSFET).

11. Device according to any one of the preceding claims in which the first channel (Cl) and the second channel (C2) respectively have a first section and a second section, taken in an xy plane, and the second section has a surface greater than that of the first section.

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