Short-range radar and radar operating method

Abstract

Short-range radar and radar operating method. This description relates to a radar (50) comprising an electromagnetic wave receiver (30) including an electromagnetic wave receiving antenna (32) connected to an integrated circuit including a low-noise differential amplifier (35) and an attenuation circuit (ATT) interposed between the receiving antenna (32) and the low-noise differential amplifier (35), the attenuation circuit (ATT) comprising at least first, second, third, and fourth transistors. Figure for the abstract: Fig. 5

Description

Title of the invention: Short-range radar and method of operating a radar. Technical field

[0001] This description relates generally to short-range radars, in particular ultra-wideband radars, and to the operating methods of short-range radars. Previous technique

[0002] Radar (an acronym for radio detection and ranging) is a remote sensing device that uses electromagnetic waves to detect the presence and determine the position and speed of objects, also called targets. The waves emitted by the transmitter are reflected by the target, and the returning signals (called radar echoes) are captured and analyzed by the receiver. The distance is obtained from the round-trip time of the signal.

[0003] A pulsed radar is a radar that emits pulses of electromagnetic waves and then switches to listening mode for the echo returned by the target. A pulsed radar can be an ultra-wideband radar, or UWB radar (English acronym for Ultra Wideband), when the emitted signal covers a very wide frequency spectrum, for example, according to the IEEE 802.15.4 standard.

[0004] Radar is said to be short-range when it is capable of detecting a target close to the receiver. This implies that the radar receiver must be able to detect an echo received shortly after the end of pulse transmission. However, coupling phenomena between the transmitter and the receiver can make this detection difficult. Summary of the invention

[0005] One embodiment overcomes all or part of the known disadvantages of short-range radars.

[0006] One embodiment provides for a radar comprising an electromagnetic wave receiver including an electromagnetic wave receiving antenna connected to an integrated circuit including a low noise differential amplifier and an attenuation circuit interposed between the receiving antenna and the low noise differential amplifier, the attenuation circuit including at least first, second, third, and fourth transistors.

[0007] According to one embodiment, the first, second, third, and fourth transistors are insulated-gate field-effect transistors.

[0008] According to one embodiment, the radar includes a first symmetrical line between the receiving antenna and the attenuation circuit and a second symmetrical line between the attenuation circuit and the low-noise differential amplifier.

[0009] According to one embodiment, the attenuation circuit comprises: - a first node connected to a first conductive track of the first symmetrical line; - a second node connected to a second conductive track of the first symmetrical line; - a third node connected to a first conductive track of the second symmetrical line; - a fourth node connected to a second conductive track of the second symmetrical line; - the first transistor, one of whose drain and source is connected to the first node and the other of whose drain and source is connected to the third node, and whose gate receives a first binary signal; - the second transistor, one of whose drain and source is connected to the first node and the other of whose drain and source is connected to the fourth node, and whose gate receives a second binary signal; - the third transistor, one of whose drain and source is connected to the second node and the other of whose drain and source is connected to the third node, and whose gate receives the second binary signal; and - the fourth transistor, one of whose drain and source is connected to the second node and the other of whose drain and source is connected to the third node, and whose gate receives the first binary signal.

[0010] According to one embodiment, the radar further includes a balun interposed between the receiving antenna and the attenuation circuit and connected to the first balanced line.

[0011] According to one embodiment, the radar further comprises an electromagnetic wave transmitter including an electromagnetic wave transmitting antenna, which is either in conjunction with or separate from the receiving antenna, and connected to a control circuit configured to control the transmitting antenna, the control circuit being further configured to control the attenuation circuit.

[0012] According to one embodiment, in a first mode of operation, the control circuit is configured to control the switching of the first and fourth transistors and the blocking of the second and third transistors, and, in a second mode of operation, the control circuit is configured to control the switching of the first, second, third, and fourth transistors.

[0013] According to one embodiment, each of the first, second, third, and fourth transistors comprises N MOS transistors in parallel, where N is an integer greater than or equal to 2.

[0014] An embodiment also provides for a method of operating the radar as defined above, comprising, in a first mode of operation, switching the first and fourth transistors on and switching the second and third transistors off, and, in a second mode of operation, switching the first, second, third, and fourth transistors on.

[0015] According to one embodiment, the method comprises switching from the first operating mode to the second operating mode, and maintaining the second operating mode for a determined time, upon control by the control circuit, of the emission of a pulse of electromagnetic waves, and switching from the second operating mode to the first operating mode upon completion of the determined time.

[0016] According to one embodiment, the method comprises, in the first mode of operation, switching on the N MOS transistors of the first and fourth transistors and switching off the N MOS transistors of the second and third transistors, in the second mode of operation, switching on the N MOS transistors of the first, second, third, and fourth transistors, and comprises, in a third mode of operation, switching on the N MOS transistors of the first and fourth transistors, switching on a part of the N MOS transistors of the second and third transistors and switching off the rest of the N MOS transistors of the second and third transistors. Brief description of the drawings

[0017] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0018] [Fig.1] is an electrical diagram of an example of a radar;

[0019] [Fig.2] is a timing diagram of signals used by the radar of [Fig.1];

[0020] [Fig. 3] is an electrical diagram of an example of a radar implementing a coupling reduction process;

[0021] [Fig.4] is an electrical diagram of another example of a radar implementing a coupling reduction method;

[0022] [Fig.5] is an electrical diagram of an embodiment of a radar;

[0023] [Fig. 6] is an electrical diagram of an embodiment of an attenuation circuit of the radar of [Fig.5];

[0024] [Fig.7] is an electrical diagram of the attenuation circuit of [Fig.6] illustrating the current flow paths in a first operating mode;

[0025] [Fig.8] is an electrical diagram of the attenuation circuit of [Fig.6] illustrating the current flow paths in a second operating mode;

[0026] [Fig.9] represents timing diagrams of signals used by the radar of [Fig.5]

[0027] [Fig. 10] illustrates the evolution of the maximum transmission gain of the attenuation circuit of [Fig. 6] as a function of the frequency of the received signal in the first operating mode and in the second operating mode;

[0028] the [Fig.1 1] is a curve of evolution, as a function of the frequency of the received signal, of the difference between the maximum transmission gain of the attenuation circuit of the [Fig.6] in the first operating mode and in the second operating mode;

[0029] [Fig. 12] is an enlargement of [Fig. 10] and [Fig. 13] is an enlargement of [Fig. 11];

[0030] The [Fig. 14] is a timing diagram of an example of the input signal of the attenuation circuit of the [Fig.6] and the [Fig. 15] is a curve of the evolution of the output signal obtained;

[0031] [Fig. 16] is a curve showing the evolution of the gain of the attenuation circuit of [Fig. 6] as a function of the power of the received signal;

[0032] [Fig. 17] is an electrical diagram of another embodiment of the radar attenuation circuit of [Fig. 5]; and

[0033] [Fig. 18] represents timing diagrams of signals used for the control of the attenuation circuit of [Fig. 17]. Description of the implementation methods

[0034] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0035] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the methods of emitting electromagnetic waves by a pulsed radar are well known to those skilled in the art and are not described in detail.

[0036] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without intermediate elements other than conductors, and when referring to two connected (in English "coupled") elements between them, this means that these two elements can be connected or linked via one or more other elements.

[0037] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures or to a ... in a normal position of use.

[0038] Unless otherwise specified, the expressions "approximately", "give or take", "in the order of", and "within the range of" mean to the nearest 10% or 10°, preferably to the nearest 5% or 5°. Furthermore, a "binary signal" is a signal that alternates between a first constant state, for example a low state, denoted "0", and a second constant state, for example a high state, denoted "1". The high and low states of different binary signals in the same electronic circuit may be different. In practice, binary signals may correspond to voltages or currents that may not be perfectly constant in the high or low state.

[0039] A MOS transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET). A UWB radar is a pulsed radar in which the frequency spectrum of the emitted pulse has a center frequency between 6.5 GHz and 9.5 GHz, and a bandwidth between 500 MHz and 1.35 GHz. For example, a UWB system conforms to the IEEE 802.15.4 standard.

[0040] Fig. 1 represents, in a partial and schematic way, an example of a pulsed radar 10, for example a UWB radar.

[0041] The radar 10 comprises an electromagnetic wave transmitter 20 and an electromagnetic wave receiver 30. The transmitter 20 comprises a symmetrical output transmitting electronic circuit 21 connected to an electromagnetic wave transmitting antenna 22 via a balun 23. The balun 23 is an electrical circuit used to link a symmetrical transmission line from the transmitting circuit 21 to an asymmetrical transmission line connected to the transmitting antenna 22. The receiver 30 comprises a symmetrical input receiving electronic circuit 31 connected to a receiving antenna 32 via a balun 33. The balun 33 is an electrical circuit used to link an asymmetrical transmission line connected to the receiving antenna 32 to a symmetrical transmission line from the receiving circuit 31. Each balun 23, 33 may include a two-winding transformer.In the example shown in [Fig. 1], the transmitting antenna 22 and the receiving antenna 32 are distinct. Alternatively, the transmitting antenna 22 and the receiving antenna 32 may be considered the same.

[0042] The transmitting electronic circuit 21 includes a pulse generator 24 that supplies an IN signal to a power amplifier 25, which amplifies the IN signal and provides an analog TX signal to the balun 23. The balun 23 transforms the differential analog TX signal into an asymmetric signal that is transmitted by the transmitting antenna 22 in the form of electromagnetic waves. The receiving electronic circuit 31 includes a signal processing circuit 34 for the signals supplied by a low-noise amplifier 35. The receiving antenna 32 is sized to capture electromagnetic waves and provide an analog signal to the balun 33, which transforms this analog signal into a differential analog RX signal transmitted to the low-noise amplifier 35.

[0043] For a pulsed radar, the transmitting electronic circuit 21 shapes the signals supplied to the transmitting antenna 22 for the emission of an electromagnetic wave pulse of a given duration, for example less than 1 ns, preferably less than 0.5 ns. The electromagnetic wave pulse is reflected by an object present in the emission field, and the reflected electromagnetic waves, also called an echo, are captured by the receiving antenna 32. The processing circuit 34 is then adapted to determine the distance between the radar 10 and the object as a function of the time between the emission of the electromagnetic wave pulse and the reception of the echo.

[0044] The radar 10 is generally designed to be able to detect an object located between a minimum and a maximum distance. For a short-range radar, the minimum distance is small, for example less than 50 cm, so that a first echo can reach the receiving antenna 32 shortly after the radar pulse is emitted by the transmitting antenna 22. This first echo can lead to an RX signal with a high amplitude that the receiving circuit 31 must be able to process.

[0045] Coupling phenomena can occur between the emitter 20 and the receiver 30, which is schematically represented by an arrow C in [Fig.1].

[0046] Figure 2 shows the evolution curves of the average electrical power P of the TX signal (curve P_TX) and the RX signal (curves P1_RX, P2_RX, P3_RX, and P4_RX) as a function of time, illustrating coupling phenomena. Each curve P_TX, P_RX, P2_RX, P3_RX, and P4_RX includes a pulse, which is schematically represented by a square wave in Figure 2. In Figure 2, the signals P1_RX, P2_RX, P3_RX, and P4_RX are essentially constant in the absence of echo reception, at different, albeit very low, levels, and represent the signal unintentionally emitted by the radar in the absence of a pulse to transmit.

[0047] The pulses of the curves P1_RX and P2_RX correspond to echoes received by the radar 10 for objects located at different distances from the radar 10 or echoes coming from the same object but having followed different propagation paths. The P1_RX signal pulse is obtained for an object close to radar 10 insofar as the duration of 1 ns between the start of the pulse of the P_TX curve and the start of reception of the pulse of the P1_RX curve corresponds to an object 15 cm away in direct line of sight from radar 10.

[0048] Curve P4_RX illustrates a first type of radar coupling 10, corresponding to coupling between the transmitting circuit 21 and the receiving circuit 31 when these are formed on the same integrated circuit. As a result, the supply of a TX signal pulse leads to the almost simultaneous formation of an RX signal pulse. Curve P3_RX illustrates a second type of radar coupling 10, corresponding to coupling between the transmitting antenna 22 and the receiving antenna 32, which are generally close to each other, or even coincident. As a result, the supply of a TX signal pulse also leads to the almost simultaneous formation of an RX signal pulse. As shown in [Fig.2], the electrical power of the coupling pulses can be high, in particular greater than 16 dBm, and in particular greater than the electrical power of a pulse corresponding to an echo on an object close to the radar.

[0049] The low-noise amplifier 35 must therefore be able to receive the impulses due to coupling phenomena without being damaged, which may lead to oversizing the low-noise amplifier 35 relative to the power levels it receives in the case of true echoes. It is desirable to protect the low-noise amplifier 35 against impulses due to coupling phenomena.

[0050] Figure 3 is an electrical diagram of an example of a radar 40 implementing a method for reducing coupling phenomena. The radar 40 shown in Figure 3 comprises all the elements of the radar 10 shown in Figure 1, with the pulse generator 24 further adapted to control the temporary deactivation of the low-noise amplifier 35, in particular by temporarily stopping the power supply to the low-noise amplifier 35. Specifically, the pulse generator 24 controls the deactivation of the low-noise amplifier 35 for a predetermined duration after the emission of a pulse so that the low-noise amplifier 35 does not transmit to the processing circuit 34 the amplified pulses of the RX signal that are due to coupling phenomena. The low-noise amplifier 35 must be reactivated before the first echo is received by the receiving antenna 32.An attenuation of approximately 10 dB can generally be achieved with the low-noise amplifier 35 in 1 ns. One drawback is that such attenuation may not be sufficient to block pulses due to coupling phenomena.

[0051] Figure 4 is an electrical diagram of an example of a radar 45 implementing another method for reducing coupling phenomena. The radar 45 shown Figure 4 comprises all the elements of the radar 10 shown in Figure 1, and also includes a switch SW between the receiving antenna 32 and the balun 33. The pulse generator 24 is configured to control the opening and closing of the switch SW. Specifically, the pulse generator 24 controls the opening of the switch SW for a predetermined duration after the transmission of a pulse of the IN signal so that the low-noise amplifier 35 does not receive the RX signal pulses that are due to coupling phenomena. The switch SW must be closed before the first echo is received by the receiving antenna 32. One drawback is that the switch SW represents an additional electronic component or circuit besides the receiving circuit 21.It can be difficult to achieve proper synchronization between the pulses supplied by the pulse generator 24 and the opening and closing phases of the SW switch.

[0052] The [Fig.5] is an electrical diagram of an embodiment of a radar 50 implementing a method for reducing coupling phenomena.

[0053] The radar 50 shown in [Fig.5] comprises all the elements of the radar 10 shown in [Fig.1], the receiving circuit 31 further comprising an attenuation circuit ATT connecting the balun 33 to the low noise amplifier 35. The balun 33 provides an RXin signal to the attenuation circuit ATT and the attenuation circuit ATT provides an RXout signal to the receiving circuit 31. According to one embodiment, the attenuation circuit ATT and the low noise amplifier 35 constitute an integrated circuit.

[0054] According to one embodiment, the receiving circuit 31 is a differential circuit. In other words, the receiving circuit 31 has a symmetrical structure. This means that the RXin and RXout signals are transmitted via symmetrical lines. A symmetrical line is a pair of conductive tracks having exactly the same ground relationship, carrying an electrical signal from a source to a load. Since the signal is the potential difference between the two conductive tracks, this is called differential signaling. The RXin signal corresponds to a voltage between the two conductive tracks of a symmetrical line LI between the balun 33 and the attenuation circuit ATT, and the RXout signal corresponds to a voltage between the two conductive tracks of a symmetrical line LO between the attenuation circuit ATT and the low-noise amplifier 35.

[0055] The [Fig.6] is an electrical diagram of an embodiment of the ATT attenuation circuit.

[0056] The ATT attenuation circuit comprises: - a first input node II, having a potential RXin+, and intended to be connected to the first conductive track, not shown, of the symmetric line LI linking the attenuation circuit ATT to the balun 33; - a second input node 12, having a potential RXin-, and intended to be connected to the second conductive track, not shown, of the symmetric line LI linking the attenuation circuit ATT to the balun 33; - a first output node 01, having a potential RXout+, intended to be connected to the first conductive track, not shown, of the symmetric line LO linking the attenuation circuit ATT to the low noise amplifier 35; - a second output node 02, having a potential RXout-, intended to be connected to the second conductive track, not shown, of the symmetric line LO linking the attenuation circuit ATT to the low noise amplifier 35; - a first MOS transistor Tl, for example with an N-channel, whose drain is connected, preferably connected to node 01, whose source is connected, preferably connected, to node II, and whose gate receives a binary signal SI; - a second MOS transistor T2, for example N-channel, whose drain is connected, preferably connected to node 02, whose source is connected, preferably connected, to node II, and whose gate receives a binary signal S2; - a third MOS transistor T3, for example an N-channel transistor, whose drain is connected, preferably connected, to node 01, whose source is connected, preferably connected, to node 12, and whose gate receives the binary signal S2; and - a fourth MOS transistor T4, for example an N-channel transistor, whose drain is connected, preferably connected, to node 02, whose source is connected, preferably connected, to node 12, and whose gate receives the binary signal SL

[0057] The RXin signal corresponds to the voltage between nodes II and 12 and the RXout signal corresponds to the voltage between nodes 01 and 02.

[0058] According to one embodiment, the MOS transistors T1, T2, T3, and T4 are identical.

[0059] In a first operating mode, the attenuation circuit ATT is controlled so that the RXout signal is substantially equal to the RXin signal. In a second operating mode, the attenuation circuit ATT is controlled so that the RXout signal is substantially zero regardless of the RXin signal.

[0060] Figure 7 represents the attenuation circuit ATT in the first operating mode and illustrates the current flow paths. Signals S1 and S2 are provided so that transistors T1 and T4 are in the conducting state and transistors T2 and T3 are in the blocking state. In the case where transistors T1, T2, T3, and T4 are N-channel MOS transistors, in the first operating mode, signal S1 is high and signal S2 is low. Current can flow from node 11 to node 01 (path CH1) and from node 12 to node 02 (path CH2). Due to the parasitic capacitances of transistors T2 and T3, a very small current can flow from node II to node O2 (path CH3) and from node I2 to node O1 (path CH4). The potential RXout+ is approximately equal to the potential RXin+, and the potential RXout- is approximately equal to the potential RXin-, with a small attenuation due to the parasitic resistance of transistors T1 and T4. The voltage RXout is then approximately equal to the voltage RXin, with a small attenuation. The attenuation circuit ATT then behaves like a closed switch with low attenuation.

[0061] Figure 8 represents the attenuation circuit ATT in the second operating mode and illustrates the current flow paths. Signals S1 and S2 are provided so that transistors T1, T2, T3, and T4 are in the conducting state. If transistors T1, T2, T3, and T4 are N-channel MOS transistors, in the second operating mode, signals S1 and S2 are high. Current can flow from node II to node O1 (path CH1), from node 12 to node O2 (path CH3), from node II to node O2 (path CH3), and from node 12 to node O1 (path CH4).

[0062] The potential RXin+ at node II is substantially in opposite phase to the signal RXin- at node 12. It is as if the potentials RXin+ and RXin- are summed at node 01, so that the potential RXout+ is substantially zero, and the potentials RXin+ and RXin- are summed at node 02, so that the potential RXout- is substantially zero. The voltage RXout is therefore substantially zero. The attenuation circuit then behaves like an open switch. A strong attenuation of the RXin signal is thus obtained in the second operating mode. Preferably, an attenuation of the RXin signal greater than 30 dB is obtained in the second operating mode. This advantageously blocks pulses due to coupling phenomena and protects the low-noise amplifier 35 against these pulses.

[0063] Transistors T1 and T4 are therefore in the conducting state in both the first and second operating modes. The signal SI can thus be constant. Transistors T2 and T3 are in the blocking state in the first operating mode and in the conducting state in the second operating mode.

[0064] According to one embodiment, the attenuation circuit ATT can be further controlled in a third operating mode all transistors T1, T2, T3, and T4 are in the blocked state.

[0065] The time required to switch the attenuation circuit ATT from the first operating mode to the second operating mode is less than 1 ns, preferably less than 200 ps, ​​for example between 10 ps and 200 ps. Advantageously, the switching of the attenuation circuit ATT between the first and second operating modes can be performed quickly.

[0066] Figure 9 shows timing diagrams of the IN and S2 control signals for transistors T2 and T3 of the ATT attenuation circuit. The IN signal comprises P_IN pulses for each emission of an electromagnetic wave pulse, and the S2 signal comprises a P_S2 pulse for each pulse of the P_IN signal. In one embodiment, the P_IN pulses have a duration D and the P_S2 pulses have a duration D'. The P_S2 pulses are characterized by two parameters, A and δ. The parameter A corresponds to the time between the rising edge of the P_IN pulse and the rising edge of the corresponding P_S2 pulse. The parameter δ corresponds to the difference between the durations D' and D, with D' being greater than D. The durations D, D', A, and δ depend on the intended applications, and in particular on the radio frequency band used. According to one embodiment, the duration D is between 200 ps and 1 ps.According to one embodiment, the duration D' is between D and 10 times D. According to another embodiment, the duration A is between 0 and D. According to another embodiment, the duration ô is between 0 and 9 times D.

[0067] Simulations were carried out. The simulations include the inevitable variations during the design of the integrated circuit.

[0068] Figure 10 shows the MG_0n curve of the maximum transmission gain of the attenuation circuit ATT as a function of the frequency F of the signal RXin in the first operating mode, and the MG_Off curve of the maximum transmission gain of the attenuation circuit ATT as a function of the frequency F of the signal RXin in the second operating mode. Figure 11 shows the MG_diff curve of the difference between the MG_0n and MG_Off curves. Figure 12 is an enlargement of Figure 10, and Figure 13 is an enlargement of Figure 11 for frequencies ranging from 3 GHz to 11 GHz, which correspond to the majority of ultra-wideband applications. An attenuation of the signal RXin greater than 40 dB is obtained in the second operating mode.

[0069] Figure 14 is a timing diagram of the RXin signal supplied to the attenuation circuit of Figure 6, and Figure 15 is a curve showing the evolution of the RXout signal obtained when the RXin signal is a sinusoidal signal with a frequency of 8 GHz injected at time t = 1 ns. The RXin signal is transmitted with little attenuation (the amplitude drops from 25 mV for the RXin signal to approximately 15 mV for the RXout signal), although in the present simulation there was no impedance matching and default impedances of 50 ohms were used. At time t = 2 ns, the attenuation circuit is activated for a duration significantly less than 1 ns. A very rapid and substantial attenuation can be observed for the RXout signal.

[0070] Figure 16 shows the evolution of the transmission gain G of the attenuation circuit ATT as a function of the power P of the signal RXin when the frequency The RXin signal frequency is equal to 83.3 GHz. A decrease in gain G is visible when the power P is greater than 0 dBm.

[0071] [Fig. 17] is an electrical diagram of another embodiment of the attenuation circuit ATT. The attenuation circuit ATT shown in [Fig. 17] has the same structure as the attenuation circuit ATT shown in [Fig. 6] except that the transistor T1 is composed of N MOS transistors T1_1 to T1_N, for example N-channel, connected in parallel, that the transistor T2 is composed of N MOS transistors T2_1 to T2_N, for example N-channel, connected in parallel, that the transistor T3 is composed of N MOS transistors T3_1 to T3_N, for example N-channel, connected in parallel, and that the transistor T4 is composed of N MOS transistors T4_1 to T4_N, for example N-channel, connected in parallel. More specifically, for each MOS transistor Tl_i, i varying from 1 to N, the drain of transistor Tl_i is connected, preferably connected to node 01, and the source of transistor Tl_i is connected, preferably connected, to node II.For each MOSFET T2_i, where i ranges from 1 to N, the drain of T2_i is connected, preferably to node 02, and the source of T2_i is connected, preferably to node II. For each MOSFET T3_i, where i ranges from 1 to N, the drain of T3_i is connected, preferably to node 01, and the source of T3_i is connected, preferably to node 12. For each fourth MOSFET T4_i, where i ranges from 1 to N, the drain of T4_i is connected, preferably to node 02, and the source of T4_i is connected, preferably to node 12. The gate of each MOSFET T1_i, where i ranges from 1 to N, receives a gate control signal S1_i. The gate of each MOSFET T2_i, where i ranges from 1 to N, receives a gate control signal S2_i. The gate of each transistor T3_i, i varying from 1 to N, receives a gate control signal S2_i.The gate of each transistor T4_i, i varying from 1 to N, receives a gate control signal S l_i. .

[0072] According to one embodiment, the control method for the attenuation circuit ATT shown in [Fig. 17] can be identical to that described previously for the attenuation circuit ATT shown in [Fig. 6]. In this case, the signals S1_1 to S1_N are identical, and the signals S2_1 to S2_N are identical.

[0073] Fig. 18 represents an evolution curve of the transmission gain G of the attenuation circuit ATT of Fig. 17 illustrating another embodiment in which, in a third operating mode, the signals S2_l to S2_N are not always identical.

[0074] In [Fig. 18], a PI phase, a P2 phase, and phases P3_1, P3_2, P3_3 are shown. The PI phase corresponds to the first operating mode described previously in which transistors T1_1 to T1_N and transistors T4_1 to T4_N are in the conducting state while transistors T2_1 to T2_N and transistors T3_1 to T3_N are in the off state. The gain G is at its maximum value Gmax. In [Fig. 18], phase P2 corresponds to the second operating mode described previously, in which transistors T1_1 to T1_N, transistors T2_1 to T2_N, transistors T3_1 to T3_N, and transistors T4_1 to T4_N are in the on state. The gain G is at its minimum value Gmin. In phases P3_1, P3_2, and P3_3, the gain G is between the values ​​Gmin and Gmax. In these phases, transistors T1_1 to T1_N and transistors T4_1 to T4_N are in the on state. Furthermore, a number K of transistors T2_l to T2_N are in the conducting state, with K ranging from 1 to Nl, while the remaining transistors T2_l to T2_N are in the blocking state. Similarly, a number K of transistors T3_l to T3_N are in the conducting state, and the remaining transistors T3_l to T3_N are in the blocking state. The gain G varies according to the number K. The higher the number K, the closer G is to Gmin.The lower the K number, the closer G is to Gmax. The K number can be different from one phase P3_1, P3_2, P3_3 to another.

[0075] Such an embodiment allows for moderate attenuation of the RXin signal without completely blocking it. This is particularly advantageous for protecting the low-noise amplifier 35 when the RXin signal corresponds to the echo of a target close to the radar 50 and may have high power. This makes it possible, in particular, to use a highly sensitive low-noise amplifier 35, suitable for detecting distant targets, also for detecting nearby targets.

[0076] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, in the embodiments described above, the attenuation circuit ATT comprises MOS transistors T1, T2, T3, T4. However, each MOS transistor can be replaced by another type of transistor, in particular a bipolar transistor or a modulated-doping field-effect transistor, also known as a MODFET (English acronym for modulated-doping field-effect transistor) or HEMT (English acronym for High Electron Mobility Transistor).

[0077] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Radar (50) comprising an electromagnetic wave receiver (30) including an electromagnetic wave receiving antenna (32) connected to an integrated circuit including a low noise differential amplifier (35) and an attenuation circuit (ATT) interposed between the receiving antenna (32) and the low noise differential amplifier (35), the radar further comprising a first symmetrical line (LI) between the receiving antenna (32) and the attenuation circuit (ATT) and a second symmetrical line (LO) between the attenuation circuit (ATT) and the low noise differential amplifier (35), the attenuation circuit (ATT) comprising at least first, second, third, and fourth transistors (T1, T2, T3, T4).

2. Radar according to claim 1, wherein the first, second, third, and fourth transistors (T1, T2, T3, T4) are insulated-gate field-effect transistors.

3. Radar according to claim 1 or 2, wherein the attenuation circuit (ATT) comprises: - a first node (II) connected to a first conductive track of the first balanced line (LI); - a second node (12) connected to a second conductive track of the first balanced line (LI); - a third node (01) connected to a first conductive track of the second balanced line (LO); - a fourth node (02) connected to a second conductive track of the second balanced line (LO); - the first transistor (T1), one of whose drain and source is connected to the first node (II) and the other of whose drain and source is connected to the third node (01), and whose gate receives a first binary signal (SI); - the second transistor (T2), one of whose drain and source is connected to the first node (II) and the other of whose drain and source is connected to the fourth node (02), and whose gate receives a second binary signal (S2);- the third transistor (T3), one of whose drain and source is connected to the second node (12) and the other of whose drain and source; is connected to the third node (01), and whose gate receives the second binary signal (S2); and - the fourth transistor (T4), one of whose drain and source is connected to the second node (12) and the other of whose drain and source is connected to the third node (01), and whose gate receives the first binary signal (SI).

4. Radar according to any one of claims 1 to 3, further comprising a balun (33) interposed between the receiving antenna (32) and the attenuation circuit (ATT) and connected to the first balanced line (LI).

5. Radar according to any one of claims 1 to 4, further comprising an electromagnetic wave transmitter (20) including an electromagnetic wave transmitting antenna (22), which is either in conjunction with or separate from the receiving antenna (32), and connected to a control circuit (24) configured to control the transmitting antenna, the control circuit (24) further being configured to control the attenuation circuit (ATT).

6. Radar according to claim 5, wherein, in a first operating mode, the control circuit (24) is configured to control the switching on of the first and fourth transistors (T1, T4) and the switching off of the second and third transistors (T2, T3), and wherein, in a second operating mode, the control circuit (24) is configured to control the switching on of the first, second, third, and fourth transistors (T1, T2, T3, T4).

7. Radar according to any one of claims 1 to 6, wherein each of the first, second, third, and fourth transistors (T1, T2, T3, T4) comprises N MOS transistors in parallel, where N is an integer greater than or equal to 2.

8. Method of operating the radar (50) according to any one of claims 1 to 7, comprising, in a first mode of operation, switching the first and fourth transistors (T1, T4) on and switching the second and third transistors (T2, T3) off, and, in a second mode of operation, switching the first, second, third, and fourth transistors (T1, T2, T3, T4) on.

9. A method according to claim 8, the radar (50) being according to claim 5, comprising the passage of the first mode of

10. operation in the second operating mode, and the maintenance of the second operating mode for a determined duration (D1), upon command by the control circuit (24), of the emission of a pulse of electromagnetic waves, and the transition from the second operating mode to the first operating mode upon completion of the determined duration (D1). The method according to claim 8, the radar (50) being according to claim 7, comprising, in the first mode of operation, switching on the N MOS transistors of the first and fourth transistors (T1, T4) and switching off the N MOS transistors of the second and third transistors (T2, T3), in the second mode of operation, switching on the N MOS transistors of the first, second, third, and fourth transistors (T1, T2, T3, T4), and comprising, in a third mode of operation, switching on the N MOS transistors of the first and fourth transistors (T1, T4), switching on a portion of the N MOS transistors of the second and third transistors (T2, T3) and switching off the remainder of the N MOS transistors of the second and third transistors (T2, T3).

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