Memory circuit based on a phase-change material

Abstract

Memory circuit based on a phase change material This description relates to an electronic device comprising a memory circuit, the circuit comprising: - a substrate in and on which selection transistors are arranged; - an interconnect stack;- a plurality of memory elements (M) arranged above the interconnect stack and organized in a matrix, forming rows and columns, each memory element comprising a stack of a heating resistive element, a layer of a phase-change material (47) and an upper electrode (53), the upper electrode being common to the memory elements of the same row, in which the memory elements of two successive bit rows are separated by a trench (58) having, in a lower part, an enclosed space filled with a gas or a vacuum, the trench being closed by an insulating layer (59) extending over the upper face of the memory elements and into an upper part of the trench. Figure for the abstract: Fig. 5B;

Description

Title of the invention: Memory circuit based on a phase-change material. Technical field

[0001] This description relates generally to the field of electronic devices and more particularly to the field of electronic chips comprising a memory circuit, based on a phase change material, and their manufacturing processes. Previous technique

[0002] A phase-change material is a material that has the ability to change its crystalline state under the effect of heat, and more specifically to switch between a crystalline state and an amorphous state, which is more resistive than the crystalline state. This phenomenon is used to define two memory states, for example 0 and 1, differentiated by the resistance measured across the phase-change material.

[0003] There is a need for improvement of electronic chips comprising a memory circuit based on a phase change material. Summary of the invention

[0004] To this end, one embodiment provides an electronic device comprising a memory circuit, the memory circuit comprising: - a semiconductor substrate in and on which selection transistors are arranged; - an interconnect stack, arranged on an upper face of the semiconductor substrate; - a plurality of memory elements arranged above the interconnect stack and organized in a matrix, forming rows and columns, each memory element comprising a stack of a heating resistive element, a layer of phase-change material and an upper electrode, the upper electrode being common to the memory elements of the same row so as to form bit lines, in which the memory elements of two successive bit lines are separated by a trench having, in a lower part, an enclosed space filled with a gas or vacuum, the trench being closed by an insulating layer extending over the upper face of the memory elements and into an upper part of the trench.

[0005] According to one embodiment, the enclosed space is filled with air.

[0006] According to one embodiment, the trench has a width of less than 150 nm, by example less than 118 nm, for example less than 100 nm.

[0007] According to one embodiment, the insulating layer is made of silicon nitride.

[0008] According to one embodiment, the insulating layer has a thickness, on the face upper electrode, greater than 75 nm.

[0009] According to one embodiment, the memory elements of the same column are memory elements of the same word row, each selection transistor associated with the memory elements of the same word row being connected to a conductor via through the interconnect stack.

[0010] Another embodiment provides for a method of manufacturing an electronic device comprising a memory circuit having a plurality of memory elements arranged in a matrix, forming rows and columns, each memory element comprising a stack of a heating resistive element, a layer of a phase-change material and an upper electrode, the upper electrode being common to the memory elements of the same row so as to form bit lines, wherein the memory elements of two successive bit lines are separated by a trench, the method comprising the steps of: a) forming selection transistors in and on a semiconductor substrate; b) formation of an interconnect stack, arranged on an upper face of the semiconductor substrate; c) formation of the memory elements above the interconnect stack; and d) formation of an insulating layer extending over the upper surface of the memory elements and into an upper portion of the trenches so as to close the trenches and create, in a lower portion of each trench, an enclosed space filled with a gas.

[0011] According to one embodiment, the formation of the memory elements comprises the steps of: - formation of heating resistive elements; - deposition of the layer in the phase-change material; - deposition of the upper electrode; and - etching of the layer in the phase change material and of the upper electrode.

[0012] According to one embodiment, the process comprises, after step c), a step of depositing another insulating layer on the top face and sides of the memory elements.

[0013] According to one embodiment, the other insulating layer is formed by an atomic thin film deposition method.

[0014] According to one embodiment, the insulating layer is formed, in step d), by a plasma-assisted chemical vapor deposition method.

[0015] According to one embodiment, the insulating layer is formed, in step d), by a physical vapor phase deposition method.

[0016] According to one embodiment, the method comprises, after step b), a step of forming a plurality of openings traversing the entire height of the interconnection stack and a step of filling these openings with a metallic material so as to form conductive vias.

[0017] Another embodiment provides for a method of using an electronic device as described above, the method comprising applying a current in the heating resistive element of one of the memory elements, resulting in a crystalline phase change of the layer into the phase-change material of the memory element, allowing the storage of a bit of data.

[0018] Brief description of the drawings

[0019] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0020] [Fig. 1] is a partial and schematic perspective view of an example of an electronic device according to one embodiment; and

[0021] [Fig.2], [Fig.3], [Fig.4], [Fig.5A] and [Fig.5B] are partial and schematic views illustrating steps of an example of a manufacturing process for the electronic device illustrated in [Fig.1]. Description of the implementation methods

[0022] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0023] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0024] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0025] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0026] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0027] In the present description, the embodiments of figures 1 to 5B are represented in space according to a direct orthogonal XYZ frame, the Z axis of the frame being orthogonal to the upper face of the electronic device.

[0028] Figure 1 is a partial, schematic perspective view of an example of an electronic device according to one embodiment. More particularly, Figure 1 is a perspective view in which part of the device has been removed so as to reveal the interior of the device and, more particularly, to reveal the interior of the device along the cross-sections of the two orthogonal planes XZ and YZ.

[0029] Device 11 is, for example, an electronic chip.

[0030] The device 11 includes a semiconductor substrate 13. By way of example, the substrate 13 is made of silicon or silicon-based.

[0031] The substrate 13 comprises, for example, a semiconductor layer, not shown, doped with a first type of conductivity, for example of type N, for example doped with arsenic or phosphorus atoms. The N-type doped layer rests, for example, on, and is, for example, in contact with, another semiconductor layer of the substrate 13 doped with a second type of conductivity, opposite to the first type of conductivity, for example of type P, for example doped with boron atoms.

[0032] By way of example, the substrate 13 includes another semiconductor layer, not shown, flush with its upper surface and resting, for example, on the N-type doped layer. The upper semiconductor layer is, for example, a layer formed by epitaxy from the upper surface of the N-type doped layer. The upper semiconductor layer is, for example, made of silicon, for example, single-crystal silicon. The upper semiconductor layer comprises, for example, a plurality of regions of two opposing conductivity types, for example, a plurality of P-type regions and a plurality of N-type regions, extending longitudinally as lines in a first direction. By way of example, the regions of the upper semiconductor layer extend in the direction of the X-axis.The substrate 13 thus comprises, at its upper face, lines comprising an alternation of P-type regions and N-type regions extending in the direction of the X-axis.

[0033] By way of example, the device comprises a plurality of transistors formed in and on the substrate 13. Each transistor comprises, for example, a single N-type region and a single P-type region.

[0034] By way of example, the P-type and N-type regions of the same transistor are separated and are, for example, electrically isolated by an insulating trench 31. The Insulating trenches 31 are, for example, very shallow insulation trenches (SSTI, from the English "Super Shallow Trench Isolation"). The trenches 31 extend longitudinally in the direction of the X axis.

[0035] The insulating trenches 31 extend, for example, from the upper surface of the substrate 13 into the substrate 13. The trenches 31 preferably extend into a portion of the upper semiconductor layer and into the N-type layer without reaching the P-type layer. The insulating trenches 31 are, for example, filled with a dielectric material, for example, silicon oxide. The depth of the trenches 31 is, for example, between 20 nm and 40 nm.

[0036] Each trench 31 is, for example, surmounted by a grid pattern 21 (in English, a "dummy gate") arranged on the upper face of the substrate 13, for example, extending longitudinally in the direction of the X-axis. The grid patterns 21 extend, for example, along the entire length of the trenches 31. Each grid pattern 21 is, for example, made of a semiconductor material, for example, polycrystalline silicon. By way of example, the vertical sides of each grid pattern 21 are covered by spacers 23. The spacers 23 are, for example, made of a dielectric material, for example, a nitride.

[0037] The transistors are, for example, separated from each other and electrically isolated by insulating trenches 14. The insulating trenches 14 are, for example, shallow trench isolation (STI). The trenches 14 extend longitudinally in the direction of the X-axis. By way of example, the trenches 14 are separated by an assembly formed by a trench 31 and a grid pattern 21.

[0038] The insulating trenches 14 extend, for example, from the upper surface of the substrate 13 into the substrate 13. The trenches 14 preferably extend into a portion of the upper semiconductor layer of the substrate 13, into the N-type layer and into a portion of the P-type layer. The insulating trenches 14 are, for example, filled with a dielectric material, for example, silicon oxide. By way of example, the trenches 14 are deeper than the trenches 31. The depth of the trenches 14 is, for example, between 250 nm and 400 nm.

[0039] Transistors are for example arranged in a matrix comprising rows and columns.

[0040] Each transistor is contained within an elementary memory cell. Each memory cell further comprises a memory element M, preferably formed at least partially opposite said transistor, for example opposite the P-type region of said transistor. N-type regions, unlike P-type regions, are not, for example, surmounted by memory elements M. By way of example, within of each memory cell, the transistor is a memory element selection transistor M.

[0041] The memory elements M are organized, in top view, according to a matrix of rows and columns. These are referred to respectively as wordlines extending along the Y-axis and bitlines extending along the X-axis. For example, each memory element M is located at the intersection of a bitline and a wordline. For example, the memory elements M in the XZ plane are memory elements M of the same wordline WL, while the memory elements in the YZ plane are memory elements of the same bitline BL.

[0042] The device 11 includes, for example, an insulating layer 18 covering the upper face of the semiconductor substrate 13 and more specifically the upper face of the semiconductor layer of the substrate 13. The insulating layer 18 is, for example, in contact with the upper face of the upper semiconductor layer of the substrate 13. The insulating layer 18 covers, for example, the entire upper face of the upper semiconductor layer of the substrate 13. The insulating layer 18 has, for example, a thickness between 80 nm and 300 nm, for example between 120 nm and 200 nm.

[0043] Layer 18 is, for example, traversed by vias 20 and 22. The vias 20 and 22 are, for example, in contact, by their lower faces, with the upper face of the semiconductor layer so that each N-type and P-type region is surmounted by a via 20 or 22. The vias 20 and 22 extend, for example, over the entire height of layer 18. The vias 20 and 22 thus extend from the upper face of layer 18 to the lower face of layer 18. The vias 20 and 22 are, for example, made of a conductive material, for example tungsten.

[0044] The device includes an interconnect stack 35, covering for example the layer 18. In this example, the interconnect stack 35 is formed between the substrate 13 and the memory elements M. The interconnect stack 35 is formed for example on the upper face of the insulating layer 18 and covers for example the entire surface of the insulating layer 18.

[0045] The interconnection stack 35 is, for example, formed of a succession of levels 36, each level 36 comprising an insulating layer 37 and an insulating layer 39. The interconnection stack 35 includes, for example, a level 36a, comprising an insulating layer 39a formed on and in contact with the upper face of the insulating layer 18. The interconnection stack 35 further includes, in level 36a, an insulating layer 37a formed on the insulating layer 39a. The insulating layer 37a is, for example, formed over the entire surface of the insulating layer 39a. A For example, the insulating layer 37a is in contact, by its lower face, with the upper face of the insulating layer 39a.

[0046] The interconnect stack 35 may further comprise additional levels formed on the level 36a, i.e., on and in contact with the insulating layer 37a. In [Fig. 1], the interconnect stack 35 comprises three additional levels 36b, 36c, and 36d, for example, formed respectively from layers 37b and 39b, layers 37c and 39c, and layers 37d and 39d. In practice, the number of levels in the interconnect stack 35 may be different from four, for example, greater than four.

[0047] By way of example, the interconnect stack 35 has a thickness between 300 nm and 800 nm, for example between 400 nm and 700 nm, for example on the order of 500 nm.

[0048] By way of example, the insulating layers 18 and 37 are made of a material with a low dielectric constant, for example, a material having a dielectric constant (corresponding to the permittivity of said material relative to the permittivity of free space) of less than 5, for example, less than 4. The insulating layers 37 are, for example, made of silicon dioxide (SiOC), porous silicon dioxide, SiOCH, or porous SiOCH. By way of example, the insulating layers 39 are made of a low-permittivity oxide, known as "low k" or "ultra low k".

[0049] Each level 36 comprises conductive vias 69 and conductive tracks 71, the tracks 71 extending into the layer 39, for example, from the upper face of the layer 39, thus being flush with the upper face of the layer 39. Preferably, the tracks 71 of a level 36 extend exclusively within the layer 39 of said level 36. The vias 69 of a level of the stack 35 extend through the layer 39 and through the layer 37 of that same level 36. More precisely, the vias 69 of a level of the stack 35 extend from the lower face of a track 71 of the same level to the lower face of the layer 37 or to the upper face of a via 20 or 22 passing through the layer 18. By way of example, the heating element 49 rests and is in contact, by its lower face, with the upper face of via 69 crossing layer 39 of the highest level 36 of the stack 35.

[0050] The conductive vias and tracks 71 and 69 are for example made of a metallic material, for example tungsten.

[0051] By way of example, each memory element M is electrically connected to the selection transistor to which it is associated via a conductor via 63 passing through, for example, only a portion of the levels 36 of the interconnect stack 35. By way of example, the via 63 passes through all the levels 36 of the interconnect stack 35 except, for example, the top level of the stack 35. In the embodiment of [Fig. 1], the vias 63 pass then levels 36a, 36b and 36c without crossing level 36d of stack 35. Here, the vias then extend from the lower face of layer 39a to the upper face of layer 37c.

[0052] The via 63 is for example in contact, by its lower face, with a conductive via 22, itself in contact with the upper face of the P-type region of the transistor associated with the memory element M.

[0053] The via conductor 63 is, for example, made of a metallic material. The via conductor 63 is, for example, made of copper. Alternatively, the via conductor 63 is made of cobalt or tungsten.

[0054] One advantage of forming the memory elements M above the stack 35 is that it eliminates the risks of contamination of the phase change layer 47 caused by the formation of the stack 35 and the different metallic levels 36.

[0055] One advantage of controlling word lines via vias 63 is that it allows one to overcome the constraints of dimensioning the metal levels for the integration of the phase change elements, and thus bring the word lines closer to the memory elements M, the width of the vias 63 being able to be less than the width of a conductive track.

[0056] In the embodiment of [Fig.1], the memory elements M are formed on the upper face of the stack 35.

[0057] The memory elements M are phase-change memory elements. Each element comprises a layer 47 made of a phase-change material, for example, a chalcogenide material, for example, a germanium-antimony-tellurium (GeSbTe) alloy, also known as GST. The layer 47 has, for example, a thickness between 30 nm and 100 nm, for example, on the order of 50 nm. The memory elements M of the same bit row comprise, for example, a common layer 47. Thus, the device 11 comprises, for example, as many layers 47 as there are bit rows. Each layer 47 thus extends in the direction of the bit rows.

[0058] In each memory element M, the phase-change material is controlled by the metallic heating resistive element 49 located beneath the phase-change material. The element 49 is, for example, in contact, by its upper face, with the lower face of the layer 47. The element 49 is, for example, laterally surrounded by a layer of thermal insulation 51. For example, each element 49 has an "L" shape in the YZ plane of section. By way of example, the element 49 is made of tantalum nitride or silicon titanium nitride. By way of example, the layer 51 is made of silicon carbonitride. By way of example, the heating element 49 has, for example, a thickness between 30 nm and 100 nm, for example, on the order of 60 nm.

[0059] Layer 47 is surmounted by a layer 53, for example, made of a conductive material, for example, a metallic material. More precisely, the upper surface of each layer 47 is, for example, at least partially covered, for example, entirely covered, by a layer 53. Each layer 53 preferably extends, in the direction of the bit lines, over the entire length of layer 47. Layer 53 is, for example, made of titanium nitride. By way of example, layer 53 has a thickness of between 10 nm and 50 nm, for example, on the order of 20 nm.

[0060] By way of example, in each memory element M, the metallic element 49 and the layer 53 form, respectively, a lower and an upper electrode of the memory element M, and more precisely, electrodes of the resistive element with variable resistance formed by the layer 47 in the phase-change material. The memory elements M of the same bit row are surmounted by the same layer 53. In other words, the upper electrodes 53 of the memory elements M of the same bit row are interconnected.

[0061] The layer 53 is, for example, surmounted by a layer 57, for example, made of an insulating material, for example, a dielectric material. The insulating layer 57 is, for example, made of a nitride, for example, silicon nitride. The upper surface of each layer 53 is, for example, at least partially covered, for example, completely covered, by a layer 57. Each layer 57 preferably extends, in the direction of the bit lines, over the entire length of the layer 53. By way of example, the layer 57 has a thickness of between 10 nm and 50 nm, for example, on the order of 25 nm.

[0062] Each memory element M is, for example, covered by an insulating layer 55 protecting, for example, the layer 47 made of the phase-change material from oxidation. By way of example, the layer 55 covers the upper surface of the layer 57 and the sides of the layers 53, 57, 47, and 51. The layer 55 is, for example, made of a dielectric material. The insulating layer 55 is, for example, made of a nitride, for example, silicon nitride.

[0063] The memory elements M of adjacent bit lines are isolated from each other by an enclosed space 61 surmounted by an insulating layer 59. The enclosed space 61 is filled with a gas or a vacuum. For example, the enclosed space 61 is filled with air. Alternatively, the enclosed space 61 is filled with a neutral gas. The insulating layer 59 is, for example, made of a dielectric material, for example a nitride, for example silicon nitride. The layer 59 covers the upper surface of the memory elements M and extends only to the upper part of the depth of the trenches separating the bit lines of the memory elements M. The enclosed space 61 is, for example, laterally delimited by the layer 55 covering two adjacent memory elements M. The enclosed space 61 is further delimited by the upper surface of the layer 37d or, where applicable, the layer 55 which covers layer 37d. In addition, the closed space 61 is delimited by the lower face of layer 59. Each closed space 61 extends between two bit lines, for example over the entire length of the bit lines, for example in the direction of the Y axis.

[0064] In order to apply potentials to the word lines of the memory elements M, the vias 63 and 22 extend, for example, longitudinally in the direction of the X-axis outside the device illustrated in [Fig. 1]. In order to apply potentials to the bit lines of the memory elements M, layer 53, which corresponds to the upper electrode, extends, for example, longitudinally in the direction of the Y-axis outside the device illustrated in [Fig. 1].

[0065] Fig. 2, Fig. 3, Fig. 4, Fig. 5A and Fig. 5B are partial views and schematics, illustrating steps in an example manufacturing process of the electronic device shown in [Fig.1].

[0066] Figure 2 illustrates a starting structure and more particularly a view in perspective of the initial structure.

[0067] By way of example, the starting structure comprises the semiconductor substrate 13 on which the interconnect stack 35 has been formed. The structure further comprises the layer 51 in which the heating resistive elements 49 are formed.

[0068] Figure 3 illustrates a structure obtained at the end of a formation step of memory elements M on the upper face of the structure illustrated in [Fig.2]. More specifically, [Fig.3] illustrates a perspective view of the structure.

[0069] In this step, layers 47, 53 and 57 are, for example, deposited successively on the upper face of the structure illustrated in [Fig. 2]. In this step, layers 47, 53 and 57 are, for example, deposited in full plate form so as to cover the entire surface of layer 51.

[0070] After the deposition of layers 47, 53, and 57, they are, for example, etched to form trenches 58 in these layers, delimiting the bit lines in the stack of the aforementioned layers. As an example, during this step, layer 51 and the heating resistive element 49 are also etched.

[0071] Figure 4 illustrates a structure obtained after a step of deposition of layer 55 on the upper face of the structure illustrated in Figure 3. More particularly, Figure 4 illustrates a perspective view of the structure.

[0072] During this step, layer 55 is deposited, for example, over the entire upper surface of the structure illustrated in [Fig. 3], and more specifically on the upper surface of layer 57, on the upper surface of layer 37d, in the trenches 58, and on the sides of layers 57, 53, 47, and 51. By way of example, layer 55 is deposited conformally, that is, with a constant thickness. For example, layer 55 has a thickness between 1 nm and 70 nm, for example, between 20 nm and 40 nm, for example, on the order of 33 nm.

[0073] By way of example, layer 55 is deposited by an atomic thin film deposition (ALD) method.

[0074] At the end of this step, layer 55 is for example removed from the upper face of layer 37d, at the bottom of trenches 58, so as to be kept only on the sides of layers 57, 53, 47 and 51 and on the upper face of layer 57.

[0075] Figures 5A and 5B illustrate a structure obtained after a step of deposition of layer 59 on the upper face of the structure illustrated in [Fig.4]. More specifically, [Fig.5B] corresponds to an enlargement of region B of [Fig.5A], [Fig.5A] corresponding to a perspective view of the structure and [Fig.5B] corresponding to a cross-sectional view of the structure.

[0076] During this step, layer 59 is deposited above trenches 58 by an unconventional deposition process so as to form a plug. The ambient air or gas (in the treatment chamber during this step) is then trapped in trenches 58, forming the enclosed space 61.

[0077] The gas contained within the enclosed space 61 is, for example, a neutral gas or air. By way of example, the gas is nitrogen or argon. The enclosed space 61 has, for example, a height H between 50 nm and 170 nm, for example on the order of 90 nm.

[0078] The bit lines are preferably all regularly spaced, the trenches 58 therefore all having a substantially identical width L.

[0079] By way of example, the width L of the trenches 58 is less than 150 nm, for example less than 118 nm, for example less than 100 nm.

[0080] The deposition of layer 59 is, for example, carried out by successive deposition of several sub-layers, for example, identical sub-layers. By way of example, the deposition of layer 59 is carried out by successive deposition of three sub-layers. Alternatively, the deposition of layer 59 is carried out by successive deposition of more than three sub-layers.

[0081] The sublayers of layer 59 are, for example, deposited by a less conformal deposition method than ALD deposition. For example, the sublayers of layer 59 are not deposited by ALD. For example, the sublayers of layer 59 are deposited by a chemical vapor deposition (CVD) method, for example, by a plasma-enhanced chemical vapor deposition (PECVD) method. Alternatively, layer 59 is deposited by a physical vapor deposition (PVD) method.

[0082] By way of example, layer 59 is inserted into trench 58 to a depth or distance D along the walls of the bit lines. The depth D is, for example, between 10 nm and 100 nm, or for example between 30 nm and 60 nm.

[0083] In order for the layer 59 to form a plug above and in an upper part of the trench 58, the layer 59 is deposited with a thickness E, starting from of the top face of layer 55, greater than or equal to half the width L. The thickness E of layer 59 is, for example, greater than or equal to 50 pm, for example greater than or equal to 59 nm, for example greater than or equal to 75 nm.

[0084] An advantage of the present embodiment is that the introduction of gas into a trench makes it possible to decrease the relative permittivity of the trenches separating two bit lines with respect to trenches filled with a dielectric material, for example silicon nitride.

[0085] Another advantage of the present embodiment is that it limits the thermal conductivity between the bit lines. This limits the thermal disturbance of memory elements M, during programming, to neighboring elements.

[0086] Yet another advantage of the present embodiment is that it allows the bit lines to be brought closer together and thus reduces the size of the memory circuits.

[0087] Many applications are likely to benefit from the advantages provided by the electronic device 11, the electronic device 11 being able to be integrated into various types of devices.

[0088] By way of example, the electronic device 11 can be integrated into a device intended for the automotive industry. The electrification of motor vehicles is causing a sharp increase in the number of electronic components present in vehicles. The device includes, for example, thyristors, rectifiers, transient voltage suppression diodes, modules, etc., intended to be incorporated into said vehicles. Furthermore, driver assistance and driving automation are leading to an increase in the number of electronic components in vehicles. The device includes, for example, transient voltage suppression diodes, electrostatic discharge protection, and common-mode filters to protect the device against electrical hazards.

[0089] By way of example, the electronic device 11 can be integrated into a device intended for industrial use. In particular, the device is used, for example, for the development of green energy or for the electrification of infrastructure, for example, for charging stations or for solar energy collection. The device can also be used in the field of the Internet of Things or in the field of smart homes. The device is intended, for example, to be implemented in electrical power supply circuits for equipment, including, for example, 800 V or 1200 V thyristors, ultrafast 1200 V and silicon carbide diodes, transient voltage suppression diodes, and electrostatic discharge protection devices. The device can also be used for the implementation of cloud computing systems and communication networks. 5G radio frequency, data centers and servers. The device includes, for example, wide band gap materials.

[0090] By way of example, the electronic device 11 can be integrated into a device intended for use in personal electronics, for example, to increase the volume of information exchanged via radio frequency communication, in 5G communication systems, or more generally in any connected device. The device is, for example, a mobile phone, or smartphone, or is part of an Internet of Things network. The device is, for example, connected via 5G, Wi-Fi, or broadband communication. The device includes, for example, high-speed interfaces, for example, with advanced filtering and protection against electrostatic discharge.

[0091] By way of example, the electronic device 11 can be integrated into a device intended for use in communication equipment, or in computers and peripherals. The device is used, for example, in 5G infrastructures and dedicated data centers. The device includes, for example, silicon carbide diodes, Schottky power transistors, electrostatic discharge protection devices, and transient voltage suppression diodes. The device can also be used in satellites, including, for example, integrated passive devices for radio frequency applications.

[0092] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art. In particular,

[0093] Furthermore, although embodiments have been described in which the memory elements M are covered with a layer 55, this layer can be omitted. In this case, layer 59 is deposited directly on the upper surface of layer 57 and extends along the lateral sides of the memory elements M. To preserve the chemical stability of layers 51, 47, 53, and 57, and in particular to protect them from oxidation, layer 59 in this embodiment extends along the entire lateral sides of the memory elements M until it reaches the upper surface of layer 37d. In this embodiment, layer 59 has a thickness greater than or equal to 2 nm.

[0094] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Electronic device (11) comprising a memory circuit, the memory circuit comprising: - a semiconductor substrate (13) in and on which selection transistors are arranged; - an interconnect stack (35), arranged on an upper face of the semiconductor substrate;- a plurality of memory elements (M) arranged above the interconnect stack and organized in a matrix, forming rows and columns, each memory element (M) comprising a stack of a heating resistive element (49), a layer of a phase-change material (47) and an upper electrode (53), the upper electrode (53) being common to the memory elements of the same row so as to form bit lines (BL), in which the memory elements (M) of two successive bit lines are separated by a trench (58) having, in a lower part, an enclosed space (61) filled with a gas or vacuum, the trench being closed by an insulating layer (59) extending over the upper face of the memory elements (M) and into an upper part of the trench (58).;

2. Electronic device according to claim 1, wherein the enclosed space (61) is filled with air.

3. Device according to claim 1 or 2, wherein the trench (58) has a width less than 105 nm, for example less than 118 nm, for example less than 100 nm.

4. Device according to any one of claims 1 to 3, wherein the insulating layer (59) is made of silicon nitride.

5. Device according to any one of claims 1 to 4, wherein the insulating layer (59) has a thickness, on the upper face of the upper electrode (53), greater than 75 nm.

6. Device according to any one of the claims wherein the memory elements (M) of the same column are memory elements (M) of the same word line (WL), each selection transistor associated with the memory elements (M) of the same word line being connected to a conductor via (63) through the interconnect stack (35).

7. A method for manufacturing an electronic device (11) comprising a memory circuit having a plurality of memory elements arranged in a matrix, forming rows and columns, each memory element (M) comprising a stack of a heating resistive element (49), a layer of a phase-change material (47) and an upper electrode (53), the upper electrode (53) being common to the memory elements of the same row so as to form bit lines (BL), in which the memory elements (M) of two successive bit lines are separated by a trench, the method comprising the steps of: a) forming selection transistors in and on a semiconductor substrate (13); b) forming an interconnect stack (35), disposed on an upper face of the semiconductor substrate; c) forming the memory elements (M) above the interconnect stack;and d) formation of an insulating layer (59) extending over the upper face of the memory elements (M) and in an upper part of the trenches (58) so as to close the trenches and create, in a lower part of each trench, an enclosed space (61) filled with a gas.;

8. A method according to claim 7, wherein the formation of the memory elements comprises the steps of: - formation of the heating resistive elements (49); - deposition of the layer in the phase change material (47); - deposition of the upper electrode (53); and - etching of the layer in the phase change material and of the upper electrode (53).

9. Method according to claim 7 or 8, comprising, after step c), a step of depositing another insulating layer (55) on the top face and sides of the memory elements (M).

10. A method according to claim 9, wherein the other insulating layer is formed by an atomic thin film deposition method.

11. A method according to any one of claims 7 to 10, wherein the insulating layer (59) is formed, in step d), by a plasma-assisted chemical vapor deposition method.

12. A method according to any one of claims 7 to 10, wherein the insulating layer (59) is formed, in step d), by a physical vapor phase deposition method.

13. A method according to any one of claims 7 to 12, comprising, after step b), a step of forming a plurality of openings through the entire height of the interconnect stack (35) and a step of filling these openings with a metallic material so as to form conductive vias (63).

14. A method of using an electronic device (11) according to any one of claims 1 to 6, comprising applying a current to the heating resistive element (49) of one of the memory elements (M), resulting in a crystalline phase change of the layer into the phase-change material (47) of the memory element (M), enabling the storage of a bit of data.

Images