Method and device for the flexible unmapping of a modulation symbol

Abstract

Method for unmapping a modulation symbol comprising: a classification (101) of each bit of the symbol into a first group or a second group; a determination (102) of different pairs, each defining a slope and a y-intercept of an edge of a Voronoi sector defined for a bit belonging to the second group and taking the value '0' or '1' in a first quadrant of the constellation; for each bit of the first group, a calculation (103) of LLR as a product between a multiplicative factor and a real or imaginary part of the symbol; a verification (104) of inequalities; for each bit of the second group, a calculation (108) of LLR as a function of the real and imaginary parts of the symbol and as a function of parameters selected (107) from subsets of the results obtained for the inequalities (105, 106). Figure for the abstract: Fig. 1

Description

Title of the invention: Method and device for the flexible unmapping of a modulation symbol. Field of the invention

[0001] The present invention relates to the field of digital signal demodulation. More particularly, the invention relates to a method for calculating a logarithmic likelihood ratio for the flexible demapping of modulation symbols. State of the art

[0002] Methods for calculating a log-likelihood ratio (LLR) are commonly used in soft-input decoding algorithms. By way of non-limiting example, this may concern the BCJR algorithm (maximum a posteriori decoding algorithm for error-correcting codes defined on lattices, such as turbo codes), successive cancellation decoding (SC) for polar codes, or belief propagation-based algorithms (BP) for decoding low-density parity check codes (LDPC codes).

[0003] LLR calculation is used in soft demapping methods for modulation symbols (soft decision-based symbol decoding). In the field of LDPC decoding, soft demapping methods are generally preferred because of their superior performance compared to hard decision-based decoding.

[0004] However, soft demapping operations can prove costly in terms of computational complexity, particularly for high-order modulations. For example, the DVB-S2 (“Digital Video Broadcasting - Satellite 2”, second-generation digital video broadcasting via satellite), DVB-S2X (an extension of the DVB-S2 standard), CCSDS (“Consultative Committee for Space Data Systems”), and 5G standards use high-order amplitude and phase modulations, for example, 2M-APSK (“Amplitude and Phase Shift Keying”) modulations, where M is greater than or equal to five. M is the number of bits of information represented by a modulation symbol, and 2M corresponds to the number of symbols in the constellation.

[0005] The exact calculation of an LLR can be obtained by the maximum a posteriori method (MAP), or by the maximum likelihood method (ML) when the symbols are equiprobable. The ML method is often used as a benchmark for comparing the performance of LLR approximation methods. The ML method is a soft demodulation approach based on calculating the probability that a received symbol corresponds to each of the possible symbols in the constellation. The LLR for each bit is calculated by taking the logarithmic ratio of the sum of the probabilities that each symbol is transmitted, separating them into two subsets: the numerator considers symbols such that the transmitted bit is '0', and the denominator those such that the transmitted bit is '1'. The exact calculation of an LLR for a bit bj of a symbol with jg {0, ..., M-1} is then given by the following formula:

[0006] [Math.l] LLR(bj) j

[0007] with

[0008]

[0009] where is the set of indices of symbols for which bj = 0; i is the set of indices of symbols for which bj = 1; V} is the Gaussian probability density function of the symbol4 knowing that the symbol s< has been transmitted; s' corresponds to a symbol of index 1 in the constellation; <r2 est la variance du bruit du canal de propagation (on se place dans le cas d’un canal avec un bruit additif blanc gaussien, AWGN en anglais pour « Additive White Gaussian Noise »)•

[0010] It should be noted, however, that we are not necessarily limited to an AWGN type propagation channel. Any propagation channel for which the probabilities P(j) can be calculated could be taken into consideration.

[0011] To reduce the complexity of calculating the LLR, and thus limit the hardware complexity of a receiving device, several methods for approximating the calculation of the LLR have been proposed.

[0012] The "Max LLR" method is an approximation of the ML method used to reduce computational complexity without significantly compromising decoder performance. In this approximation, instead of summing the probabilities of all possible symbols for a given bit, only the probability of the most likely symbol (or its logarithm, to be more precise) is considered for each case (bit set to 1 or bit set to 0). This simplification can, however, lead to a degradation in decoding performance compared to the ML method, because all contributions from other symbols are ignored. The ML method is generally used as a benchmark in terms of maximum achievable performance.

[0013] The method described in the document "Efficient Soft Demapping for M-ary APSK," by Meixang Zhang et al., relies on soft demapping based on firm decision thresholds. However, this method requires fairly complex calculations of norms and angles. For implementation on an FPGA target, these angle calculations cannot be easily implemented, and it is therefore necessary to make approximations that lead to a performance degradation in addition to that indicated in the document.

[0014] The document "Efficient Demodulation of General APSK Constellations", Magnus Sandell et al., describes a flexible demapping method based on decision trees.

[0015] The document "Look-Up Table Based Low Complexity LLR Calculation for High-Order Amplitude Phase Shift Keying Signais", Nan Wu et al., describes a flexible demapping method based on a lookup table.

[0016] There are also unmapping methods that rely on dividing the constellation plane into different Voronoi sectors and solving inequalities to determine which sectors the different bits of a symbol to be unmapped belong to. Again, the proposed methods are generally not optimal for implementation on an FPGA target. Description of the invention

[0017] The present invention aims to provide a new method for calculating LLR for the flexible demapping of modulation symbols. The proposed method aims in particular to avoid, as far as possible, calculations of magnitude or angle and multiplications or divisions by non-constant values. The method also aims to exhibit constant complexity regardless of the received symbol (in other words, the number of calculations should remain the same regardless of the received symbol). Furthermore, the proposed method is adaptable to different types of modulations and constellations. The proposed method offers performance very similar (bordering on equal) to that of the ML method.

[0018] Thus, according to a first aspect, a method for unmapping a modulation symbol is proposed. The modulation symbol represents several bits of information. The method aims to calculate a logarithmic likelihood ratio (LLR) for each bit of the symbol. The method is implemented by a unmapping module of a receiving device. The modulation presents a constellation of symbols with half-plane symmetry for one or more symbol bits belonging to a first group, and quadrant symmetry for one or more symbol bits belonging to a second group. The method comprises: - a classification of each symbol bit into the first group or the second group, - a determination of N pairs (¾. ), & E [ 1, tV ], N being an integer strictly greater than one, the A pairs being different in pairs and each defining a slope at and an ordinate at the origin of a line forming an edge of a Voronoi sector defined for a symbol bit belonging to the second group and taking the value '0' or the value '1' in a first quadrant of the constellation, - for each bit of the symbol s belonging to the first group, a calculation of the LLR for said bit in the form of a product between a multiplicative factor and a real part or an imaginary part of the symbol ', a verification of A7 inequalities ak\Re^)\+Pk<\Im(s)|, &E [ 1, N], - for each bit of the symbol * belonging to the second group: • for each value '0' or '1' that can be taken by the bit, a determination of a subset of the results obtained for the A inequalities, and a comparison of the subset of results with predetermined candidate values, • a selection of a set of parameters defined by an index m representing the candidate value corresponding to the subset of results for the case where the bit value is '1' and an index n representing the candidate value corresponding to the subset of results for the case where the bit value is '0', • a calculation of the LLR for the bit based on the selected parameters and based on the real and imaginary parts of the symbol.

[0019] In particular modes of implementation, the method may further include one or more of the following characteristics, taken individually or in all technically possible combinations.

[0020] In particular embodiments, the modulation is an APSK modulation in phase and amplitude, or a QAM amplitude modulation in quadrature.

[0021] In particular embodiments, the modulation comprises 2M symbols, M being an integer greater than or equal to four.

[0022] In particular embodiments, the modulation is APSK modulation, M is equal to five, and A is equal to eighteen.

[0023] In particular modes of implementation, the modulation presents a constellation defined in a DVB-S2, DVB-S2X, CCSDS or 5G communication standard.

[0024] In particular embodiments, for each value equal to '0' or '1' that can be taken by a bit bj belonging to the second group, the result subset and each candidate value are each defined as a field of [) bits, with A^ai) < N.

[0025] In particular embodiments, the multiplicative factor is calculated in the form Vai, where <72 is an estimated value of a variance of additive white Gaussian noise of a propagation channel of a signal carrying the symbol

[0026] In particular embodiments, 2 takes at least two possible values ​​depending on the value of the real part R^s) or the imaginary part of the symbol s.

[0027] According to a second aspect, a module for unmapping a modulation symbol s is proposed. The modulation symbol represents several bits of information. The modulation presents a constellation of symbols with half-plane symmetry for one or more symbol bits belonging to a first group, and quadrant symmetry for one or more symbol bits belonging to a second group. The unmapping module is configured to store N pairs ( a^, ), k ∈ G[1, N], where N is an integer strictly greater than one, the N pairs being different in pairs, each defining a slope ai and a y-intercept fk of a line forming an edge of a Voronoi sector defined for a symbol bit belonging to the second group and taking the value '0' or '1' in a first quadrant of the constellation. The demapping module is also configured to implement the following steps: - for each bit of the symbol s belonging to the first group, a calculation of a logarithmic likelihood ratio (LLR) for said bit in the form of a product between a multiplicative factor and a real part R^(s) or an imaginary part of the symbol A, a verification of N inequalities ak\Re(s)\+Pk<\ Im(s) |, k G [ 1, N ], - for each bit of the symbol 4 belonging to the second group: • for each value '0' or '1' that can be taken by the bit, a determination a subset of the results obtained for the N inequalities, and a comparison of the subset of results with predetermined candidate values, • a selection of a set of parameters defined by an index m representing the candidate value corresponding to the subset of results for the case where the bit value is '1' and an index n representing the value candidate corresponding to the subset of results for the case where the bit value is '0', • a calculation of an LLR for the bit based on the selected parameters and based on the real and imaginary parts of the symbol.

[0028] In particular embodiments, the unmapping module may further include one or more of the following characteristics, taken individually or in all technically possible combinations.

[0029] In particular embodiments, the modulation is an APSK modulation in phase and amplitude, or a QAM amplitude modulation in quadrature, comprising 2'w symbols, M being an integer greater than or equal to four.

[0030] In particular embodiments, the modulation is an APSK modulation, M is equal to five, and N is equal to eighteen.

[0031] In particular embodiments, for each value equal to '0' or T that can be taken by a bit bj belonging to the second group, the subset of results and each candidate value are each defined in the form of a bit field, with A^oii) < N.

[0032] In particular embodiments, the multiplicative factor is calculated in the form Ver2, where ° is an estimated value of a standard deviation of an additive white Gaussian noise of a propagation channel of a signal carrying the symbol s.

[0033] In particular embodiments, 2 takes at least two possible values ​​depending on the value of the real part / ^^5) or the imaginary part Jf^s) of the symbol.

[0034] According to a third aspect, a receiving device is proposed comprising a demapping module according to any one of the preceding embodiments.

[0035] According to a fourth aspect, a satellite is proposed intended to be placed in orbit around the Earth and comprising such a receiving device according to the invention.

[0036] According to a fifth aspect, a ground station comprising a receiving device according to the invention is proposed.

[0037] According to a sixth aspect, the invention relates to a satellite communications system comprising at least one satellite having a receiving device according to the invention and / or at least one ground station having a receiving device according to the invention. Presentation of the figures

[0038] The invention will be better understood upon reading the following description, given by way of non-limiting example, and made with reference to the following figures:

[0039] [Fig-1] a schematic representation of the main steps of a method of putting into implementation of the unmapping method according to the invention,

[0040] [Fig.2] a schematic representation of a satellite carrying a receiving device comprising a demapping module according to the invention,

[0041] [Fig.3] a representation of an example constellation of a 32-APSK modulation,

[0042] [Fig. 4] a representation of the symbols in the constellation of Figure 3 for which bit b is equal to '0', and those for which bit b is equal to '1',

[0043] [Fig. 5] a representation of the symbols in the constellation of Figure 3 for which bit b2 is equal to '0', and those for which bit b2 is equal to '1',

[0044] [Fig. 6] a graph representing the calculated value of the LLR of bit b as a function of the value of the imaginary part of the symbol, for the ML method and for a first example of implementation of the method according to the invention,

[0045] [Fig.7] a graph representing the calculated value of the LLR of bit bu as a function of the value of the imaginary part of the symbol, for the ML method and for a second example of implementation of the method according to the invention,

[0046] [Fig.8] a representation of the symbols in the constellation of Figure 3 for which the bit b{} is equal to '0', and those for which the bit bQ is equal to '1',

[0047] [Fig.9] a representation of the Voronoi sectors of the symbols in the first quadrant of the constellation of Figure 3 for which the bit bü is equal to '1',

[0048] [Fig. 10] a representation of the Voronoi sectors of the symbols in the first quadrant of the constellation in Figure 3 for which the bit bQ is equal to '0',

[0049] [Fig. 11] a representation of the symbols in the constellation in Figure 3 for which the bit b2 is equal to '0', and those for which the bit b3 is equal to '1',

[0050] [Fig. 12] a representation of the Voronoi sectors of the symbols in the first quadrant of the constellation in Figure 3 for which the bit b2 is equal to '1',

[0051] [Fig. 13] a representation of the Voronoi sectors of the symbols in the first quadrant of the constellation in Figure 3 for which the bit b2 is equal to '0',

[0052] [Fig. 14] a representation of the symbols of the constellation in Figure 3 for which bit b4 is equal to '0', and those for which bit b4 is equal to '1',

[0053] [Fig.

[15] a representation of the Voronoi sectors of the symbols in the first quadrant of the constellation in Figure 3 for which the bit b4 is equal to '1',

[0054] [Fig. 16] a representation of the Voronoi sectors of the symbols in the first quadrant of the constellation in Figure 3 for which the bit b4 is equal to '0'. .

[0055] In these figures, identical reference numerals from one figure to another designate identical or analogous elements. For clarity, the elements shown are not necessarily to the same scale, unless otherwise stated. Detailed description of the invention

[0056] Fig. 1 schematically represents the main steps of an implementation of method 100 according to the invention for unmapping a modulation symbol.

[0057] A modulation symbol represents several bits of information. For example, a 32-APSK modulation has thirty-two symbols, and each symbol represents five bits of information. Typically, the number of symbols in the modulation constellation is written in the form 2M, where M is the number of bits represented by a symbol in the constellation. The demapping method aims to calculate a logarithmic likelihood ratio, LLR, for each bit of a received symbol.

[0058] Figure 2 schematically represents a receiving device 20 comprising a demapping module 23 configured to implement the demapping method 100 according to the invention. This device 20 may, in particular, be a receiving device for a radio signal or an optical signal. The receiving device 20 may, in particular, be carried on a satellite 10 placed in orbit around the Earth, for receiving signals on an uplink from a ground station. The receiving device 20 may also be integrated into a ground station, for receiving signals on a downlink from the satellite 10. However, nothing would prevent other applications of the invention. For example, the invention could also be applied to a receiving device for a mobile terminal in a terrestrial communication system.

[0059] As illustrated in [Fig. 2], the receiving device 20 includes an antenna 21 for receiving a radio signal or an optical signal sent by a transmitting device. The receiving device 20 also includes a demodulation module 22. Conventionally, the demodulation module 22 is configured to determine a real and an imaginary part of at least one modulation symbol contained in the received signal. The unmapping module 23 is adapted to calculate a logarithmic likelihood ratio, LLR, for each bit of a received symbol, from the real and imaginary parts of the symbol. The receiving device 20 also includes a channel decoding module 24, for example an LDPC decoder, adapted to decode the received signal from the calculated LLRs. Conventionally, at the input of the unmapping module 23, the symbol frame is synchronized in time, frequency, and phase.

[0060] In the example considered, the demodulation module 22, the demapping module 23, and the channel decoding module 24 are implemented as FPGA (Field-Programmable Gate Array) type programmable integrated circuits. However, in alternative implementations, they could be implemented as an ASIC (Application-Specific Integrated Circuit) type integrated circuit, or using a processor. or a microcontroller. More generally, the demapping module 23 is hereafter considered to include software and / or hardware means configured to implement method 100 according to the invention. The demapping module 23 may, in particular, include memory, for example RAM (Random Access Memory), to store the parameters necessary for implementing method 100.

[0061] In the following description, we will consider, by way of non-limiting example, the case of a phase-amplitude modulation comprising thirty-two symbols (32-APSK modulation, with M ≥ 5). The invention is indeed particularly well suited to high-order 2M-APSK modulations, for example, modulations for which M is at least equal to four (M > 4). 32-APSK modulation is notably used in the DVB-S2, DVB-S2X, and CCSDS communication standards.

[0062] Figure 3 illustrates an example of a constellation for 32-APSK modulation. This constellation is similar to that used in the DVB-S2X standard. As illustrated in Figure 3, the constellation comprises thirty-two symbols s to s32 represented in a complex plane equipped with a coordinate system whose x-axis represents the real parts of the symbols and the y-axis represents the imaginary parts of the symbols. Each symbol represents five bits of information, named bj, JE [0, ..., 4]. In the example considered, the bit with index j = 0 corresponds to the least significant bit (the rightmost bit in the notation used in Figure 3), and the bit with index θ = 4 corresponds to the most significant bit (the leftmost bit in the notation used in Figure 3). As an example, the symbol s9 corresponds to the binary value bOlOOl; for this symbol, we have b0 = 1, bi = 0, b2 = 0, b3 = 1, and b4 = 0.

[0063] It should be noted, however, that the invention could also be applied to other types of modulation, in particular quadrature amplitude modulation (QAM). High-order QAM modulations (for example, with constellations comprising thirty-two, sixty-four, or one hundred and twenty-eight symbols) are notably used in the 5G communication standard.

[0064] Also, for a given modulation, the invention can be applied to different examples of constellations. In particular, different constellations can correspond to different ways of distributing the bit values ​​of the symbols in the constellation.

[0065] However, it is appropriate to limit oneself to symbol constellations with half-plane symmetry for some symbol bits (bits belonging to a first group), and quadrant symmetry for other symbol bits (bits belonging to a second group).

[0066] Half-plane symmetry means that, for a bit belonging to the first group, the set of symbols for which the bit value is '0' is symmetric to the set of symbols for which the bit value is '1' with respect to the x-axis or y-axis of the constellation's coordinate system. In the present application, a first set of symbols is considered symmetric with respect to a second set of symbols if each symbol in the first set has a symmetrical counterpart in the second set, and vice versa.

[0067] For the constellation illustrated in Figure 3, the bit b exhibits half-plane symmetry with respect to the x-axis. Indeed, as illustrated in Figure 4, the set of symbols for which the bit b takes the value '0' (symbols represented by dots in Figure 4) is symmetric to the set of symbols for which the bit b takes the value '1' (symbols represented by crosses in Figure 4) with respect to the x-axis. For example, the symbol s9 for which the bit b takes the value '0' is symmetric to the symbol s1 for which the bit b takes the value '1'; the symbol s16 for which the bit b takes the value '0' is symmetric to the symbol s18 for which the bit b takes the value '1'; and so on.

[0068] For the constellation illustrated in Figure 3, bit b2 exhibits half-plane symmetry with respect to the y-axis. Indeed, as illustrated in Figure 5, the set of symbols for which bit b2 takes the value '0' (symbols represented by dots in Figure 5) is symmetric to the set of symbols for which bit b2 takes the value '1' (symbols represented by crosses in Figure 5) with respect to the y-axis. For example, the symbol s9 for which bit b2 takes the value '0' is symmetric to the symbol s13 for which bit b2 takes the value '1'; the symbol s16 for which bit b2 takes the value '0' is symmetric to the symbol s20 for which bit b2 takes the value '1'; and so on.

[0069] Quadrant symmetry means that, for a bit belonging to the second group, the set of symbols for which the value of the bit is '0' (respectively '1') in one quadrant of the constellation is symmetric, for each of the other quadrants of the constellation, to the set of symbols for which the value of the bit is '0' (respectively '1') in said other quadrant.

[0070] For example, let us number the quadrants of the constellation illustrated in Figure 3, starting with the first quadrant at the top right, and proceeding clockwise. The first quadrant includes symbols whose real and imaginary parts are positive, the second quadrant includes symbols whose real part is positive and whose imaginary part is negative, the third quadrant includes symbols whose real and imaginary parts are negative, and the fourth quadrant includes symbols whose real part is negative and whose imaginary part is positive. Then, for certain bits, the symbols of the first Symbols in the second quadrant can exhibit symmetry with respect to the x-axis with the symbols in the second quadrant, symbols in the first quadrant can exhibit symmetry with respect to the y-axis with the symbols in the fourth quadrant, and symbols in the first quadrant can exhibit symmetry with respect to the origin of the coordinate system with the symbols in the third quadrant. This is the case, in particular, for bits 60, b3, and b4.

[0071] In particular, and as illustrated in Figure 8, the set of symbols for which the bit b0 takes the value '0' in the first quadrant is symmetric, for each of the three other quadrants of the constellation, to the set of symbols for which the bit b0 takes the value '0' in said other quadrant. Indeed, the set of symbols {s0, s8, s24, s16} for which the bit b0 takes the value '0' in the first quadrant is symmetric to the set of symbols {s2, s10, s26, s18} in the second quadrant with respect to the x-axis; the set of symbols {s0, s8, s24, s16} is symmetric to the set of symbols {s6, ​​s14, s30, s22} in the third quadrant with respect to the origin of the coordinate system; the set of symbols {sO, s8, s24, s16} is symmetric to the set of symbols {s4, sl2, s28, s20] in the third quadrant with respect to the ordinate axis.

[0072] Similarly, the set of symbols for which the bit b0 takes the value '1' in the first quadrant is symmetric, for each of the other three quadrants of the constellation, to the set of symbols for which the bit b0 takes the value '1' in said other quadrant. Indeed, the set of symbols {s17, si, s9, s25] for which the bit b0 takes the value '1' in the first quadrant is symmetric to the set of symbols {s19, s3, s11, s27] in the second quadrant with respect to the x-axis; the set of symbols {s17, si, s9, s25] is symmetric to the set of symbols {s23, s7, s15, s31} in the third quadrant with respect to the origin of the coordinate system; the set of symbols {sl7, si, s9, s25] is symmetric to the set of symbols {s21, s5, sl3, s29] in the fourth quadrant with respect to the ordinate axis.

[0073] Similarly, and as illustrated in Figure 11, the set of symbols for which bit b3 takes the value '0' (respectively '1') in the first quadrant is symmetric, for each of the three other quadrants of the constellation, to the set of symbols for which bit b3 takes the value '0' (respectively '1') in that other quadrant.

[0074] Finally, and as illustrated in Figure 14, the set of symbols for which bit b4 takes the value '0' (respectively '1') in the first quadrant is symmetric, for each of the three other quadrants of the constellation, to the set of symbols for which bit b4 takes the value '0' (respectively '1') in that other quadrant.

[0075] As illustrated in Figure 1, for the constellation considered, method 100 comprises a classification step 101 of each symbol bit into the first group (bits with half-plane symmetry) or into the second group (bits with quadrant symmetry). For the example considered, bits b1 and b2 are classified into the first group, and bits b4, b3, and b4 are classified into the second group.

[0076] Method 100 also relies on the concept of a Voronoi diagram. A Voronoi diagram is a division of the constellation plane into several sectors. Each sector takes the form of a polygon, the number of sides of the polygon varying from one sector to another. Each sector surrounds a symbol of the constellation, such that any point in a given sector is closer to the symbol associated with that sector than to any other symbol of the constellation. The division into Voronoi sectors is performed for each symbol bit, and for each '0' or '1' value that that bit can take.

[0077] The LLR of a bit of a received symbol can then be calculated by determining the two Voronoi sectors corresponding respectively to the values ​​'0' and '1' of the bit in question in which the symbol is located.

[0078] Each edge of a Voronoi sector (that is, each side of the polygon forming the sector) corresponds to a straight line equidistant between two symbols of the constellation. Each edge of a sector can therefore be represented by a slope and a y-intercept. It is then possible to determine in which Voronoi sectors a received symbol lies by solving a set of inequalities involving the real and imaginary parts of the received symbol, each inequality corresponding to an edge of a Voronoi sector for a given value of a symbol bit.

[0079] In method 100 according to the invention, and as will be detailed later, Voronoi sectors are used only for the bits of the second group (bits exhibiting quadrant symmetry). It is then possible to limit the number of inequalities to be solved by taking into account, on the one hand, quadrant symmetry, and on the other hand, the fact that some sectors have common edges. Indeed, thanks to quadrant symmetry, for a given case bj = (011), the Voronoi sectors of the first quadrant are found by symmetry in the other three quadrants. Thus, it suffices to determine in which sector of the first quadrant lies the symbol having a real part |Re(s)| and an imaginary part |Im(s)| (this symbol being the image of the symbol s in the first quadrant).

[0080] Thus, and as illustrated in Figure 1, method 100 comprises a step 102 of determining A pairs ( ), k G [ 1, N ], A being a strictly integer greater than one (steps 101 to 102 shown in Figure 1 are implemented upstream, for example in the design of the receiving device 20; the others steps are implemented for each new symbol received). The pairs are different in pairs and each defines a slope ai and an ordinate of the origin of a line forming an edge of a Voronoi sector defined for a symbol bit belonging to the second group and taking the value '0' or the value '1' in the first quadrant of the constellation.

[0081] In the example considered of the 32-APSK constellation of Figure 3, we have N = 18. The eighteen lines are represented by the references dl to dl8 in Figures 9, 10, 12, 13, 15 and 16. For each case bj = (011), it is appropriate to consider four Voronoi sectors in the first quadrant (for each case there are 2M / 8 symbols for which the bit bj takes a given value).

[0082] Figure 9 is a representation of the Voronoi sectors of the symbols si, s9, s17, and s25 in the first quadrant of the constellation for which the bit b0 is equal to '1'. The sector corresponding to the symbol si is delimited by the lines d2, d5, and d3. The line d2 is located equidistant between the symbol si and the symbol s9. The line d3 is located equidistant between the symbol si and the symbol s25. The line d5 is located equidistant between the symbol si and the symbol s17. The sector corresponding to the symbol s9 is delimited by the lines d1 and d2. The line d1 is located equidistant between the symbol s9 and the symbol s25. The sector corresponding to the symbol s25 is delimited by the lines d1, d3, and d4. The line d4 is located equidistant between the symbol s17 and the symbol s25. The sector corresponding to the symbol s 17 is delimited by the lines d4 and d5.For the case b0 = 1, it is then possible to determine in which sector the image of the symbol ' is located in the first quadrant by verifying five inequalities corresponding to the five lines dl to d5, each inequality being written in the form: .

[0083] [Math.2] ad.\Re(s)\+ Pâ<\Im(s)\, ie{l, ...,5}

[0084] Figure 10 is a representation of the Voronoi sectors of the symbols sO, s8, s16, and s24 in the first quadrant of the constellation for which the bit bQ is equal to '0'. The sector corresponding to the symbol sO is delimited by the lines d6 and d9. The line d6 is located equidistant between the symbol sO and the symbol s8. The line d9 is located equidistant between the symbol sO and the symbol s16. The sector corresponding to the symbol s8 is delimited by the lines d6, d7, and d10. The line d7 is located equidistant between the symbol s8 and the symbol s24. The line d10 is located equidistant between the symbol s8 and the symbol s16. The sector corresponding to the symbol s24 is delimited by the lines d7 and d8. The line d8 is located equidistant between the symbol s16 and the symbol s24. The sector corresponding to the symbol s16 is delimited by the lines d8, d9, and d10. For the case bQ = 0, it is then possible to determine in In which sector is the image of the symbol s located in the first quadrant by satisfying five inequalities corresponding to the five lines d6 to d10, each inequality being written in the form:

[0085] [Math.3] ad.\Re(s)\+ fid < fe{6, ...,10}

[0086] Figure 12 is a representation of the Voronoi sectors of the symbols s9, s25, s8, and s24 in the first quadrant of the constellation for which the bit ^3 is equal to '1'. The sector corresponding to the symbol s9 is delimited by the line dl. The sector corresponding to the symbol s25 is delimited by the lines dl and dl1. The line dl1 is located equidistant between the symbols s25 and s8. The sector corresponding to the symbol s8 is delimited by the lines d7 and dl1. The sector corresponding to the symbol s24 is delimited by the line d7. For the case b3 = 1, it is then possible to determine in which sector the image of the symbol 4 is located in the first quadrant by verifying three inequalities corresponding to the three lines dl, d7, and dll, each inequality being written in the form:

[0087] [Math.4] ad.\Re(s) | +0d.^ [Imis') |, ze {1,7,11}

[0088] Figure 13 is a representation of the Voronoi sectors of the symbols sO, si, s16, and s17 in the first quadrant of the constellation for which bit b3 is equal to '0'. The sector corresponding to the symbol si is delimited by the lines d5 and dl3. The line dl3 is located equidistant between the symbol sO and the symbol si. The sector corresponding to the symbol sO is delimited by the lines d9, dl2, and dl3. The line dl2 is located equidistant between the symbol sO and the symbol s17. The sector corresponding to the symbol s16 is delimited by the lines d9 and dl4. The line dl4 is located equidistant between the symbol s16 and the symbol s17. The sector corresponding to the symbol s17 is delimited by the lines d5, dl2, and dl4.For the case b3 = 0, it is then possible to determine in which sector the image of the symbol4 is located in the first quadrant by verifying five inequalities corresponding to the five lines d5, d9, dl2, dl3 and dl4, each inequality being written in the form: .

[0089] [Math.5] ad.\Re(s)\+fid< ie {5,9, 12,13,14}

[0090] Figure 15 is a representation of the Voronoi sectors of the symbols s25, s17, s16, and s24 of the first quadrant of the constellation for which the bit b4 is equal to '1'. The sector corresponding to the symbol s25 is delimited by the lines d4, dl5, and dl6. The line dl5 is located equidistant between the symbol s25 and the symbol s16. The line dl6 is located equidistant between the symbol s25 and the symbol s24. The sector corresponding to the symbol s17 is delimited by the lines d4 and dl4. The sector The sector corresponding to the symbol s16 is delimited by the lines d8, dl4, and dl5. The sector corresponding to the symbol s24 is delimited by the lines d8 and dl6. For the case b4 = 1, it is then possible to determine in which sector the image of the symbol 4 is located in the first quadrant by verifying five inequalities corresponding to the five lines d4, d8, dl4, dl5, and dl6, each inequality being written in the form:

[0091] [Math.6] a^Rets) \ + 0d < îe {4,8, 14,15,16}

[0092] Figure 16 is a representation of the Voronoi sectors of the symbols sO, si, s8, and s9 in the first quadrant of the constellation for which the bit b4 is equal to '0'. The sector corresponding to the symbol sO is delimited by the lines d6, dl3, and dl8. The line dl8 is located equidistant between the symbol sO and the symbol s9. The sector corresponding to the symbol si is delimited by the lines d2 and dl3. The sector corresponding to the symbol s8 is delimited by the lines d6 and dl7. The line dl7 is located equidistant between the symbol s8 and the symbol s9. The sector corresponding to the symbol s9 is delimited by the lines d2, dl7, and dl8. For the case b4 = 0, it is then possible to determine in which sector the image of the symbol 4 is located in the first quadrant by verifying five inequalities corresponding to the five lines d2, d6, dl3, dl7 and dl8, each inequality being written in the form:

[0093] [Math.7] a{i.\Re(s) i + 0d< [Imis)], îe {2,6, 13,17,18}

[0094] In Figures 9, 10, 12, 13, 15 and 16, some sectors appear open. However, it should be considered that these sectors are also delimited by a line representing a maximum value for the real part and / or by a line representing a maximum value for the imaginary part.

[0095] The symbol bit classification steps 101 and the determination steps 102 of the pairs (Pk) are, for example, carried out during the design of the receiving device 20, based on the constellation of the envisaged modulation. Then, and as illustrated in Figure 1, for each received symbol 4, the method 100 comprises the following steps for unmapping the symbol.

[0096] For each bit of the symbol 4 belonging to the first group, the method 100 includes a calculation 103 of the LLR for that bit in the form of a product between a multiplicative factor and a real part Re(s) or an imaginary part In^s) of the symbol s.

[0097] More specifically, the LLR of bit bx (which has symmetry with respect to the x-axis) can be calculated in the form:

[0098] [Math. 8] LLR^b^

[0099] and the LLR of bit b2 (which has symmetry with respect to the y-axis) can be calculated in the form:

[0100] [Math.9] LLR(b2)=^Re(s)

[0101] <r2 est une valeur estimée d’une variance d’un bruit additif blanc gaussien du propagation channel of a signal carrying the symbol 4 (it is conventionally assumed that the receiving device 20 is equipped with a noise estimator allowing this value to be determined). 2 is a weighting parameter whose optimal value can be found empirically; for example, the value — -X- is used. Tïo

[0102] Figure 6 is a graph showing the calculated LLR value of bit b as a function of the value of the imaginary part of the symbol, for the ML method and for method 100 according to the invention. It can be observed that the results obtained for the two methods are relatively close, and that the loss of precision due to the approximation of the calculation is quite acceptable in view of the resulting simplification of complexity.

[0103] To gain precision, it is also possible to perform a multi-part linear interpolation, using at least two possible values ​​for the parameter 2 depending on the value of the real or imaginary part (Irtis) of the symbol '. This amounts to performing a linear interpolation with several slopes; the slope values ​​are the same for the bit where the real part of the symbol is used and for the bit where the imaginary part is used.

[0104] Figure 7 illustrates this particular method of implementation for calculating with two values ​​for parameter 2 depending on the value of the imaginary part (Inis) of the symbol s: a value of 2 when the imaginary part is less than or equal to 0.5 and a value of 22 when the imaginary part is greater than 0.5. As illustrated in Figure 7, such arrangements allow for results closer to those of the ML method. This linear interpolation approach with two slopes increases accuracy at the cost of increased complexity (in particular, calibration may be necessary because the position of the slope change can vary depending on the amount of noise). In the example considered, 2] = 0.4286 and 22 = 1.0712.

[0105] Steps 104 to 108 shown in [Fig.1] relate to the bits of the second group.

[0106] Step 104 corresponds to a verification of the N inequalities ak\Re(s)\+Pk<\Irris)\ ,kE. [ 1, N]. In the example considered, each of these inequalities are associated with one of the lines dl to dl8. For each inequality associated with a line d^, the inequality is verified if the image of the symbol 5 in the first quadrant is located above the line in the first quadrant of the constellation, and the inequality is not verified if the image of the symbol ' is located below the line in the first quadrant of the constellation.

[0107] The result of verifying each of these N inequalities can be represented by a bit, with the bit taking the value '1' when the inequality is verified and the value '0' when the inequality is not verified. The set of results obtained for the A' inequalities can therefore be written as a bit field:

[0108] [Math. 10] R=[R^Rd2, ...,¾]

[0109] where R^ is a bit taking the value '1' when the inequality associated with the line d is verified and the value '0' when the inequality is not verified.

[0110] For each bit of the symbol 4 belonging to the second group, and for each value '0' or '1' that can be taken by this bit, method 100 then involves a determination 105 of a subset of the results obtained for the N inequalities. Each subset is defined in terms of the lines that define the Voronoi sectors for the case considered.

[0111] Thus, for the case b0 = 1, the subset of results can be written in the form:

[0112] [Math. 11] Rb^i = [ Rd^ Rdf

[0113] For the case bQ = 0, the subset of results can be written in the form:

[0114] [Math. 12] Rb^ - [Rdff Rd? Rd^ Rdf ^l0]

[0115] For the case b3 = 1, the subset of results can be written in the form:

[0116] [Math. 13] Rb^=[Rd,RdM

[0117] For the case b3 = 0, the subset of results can be written in the form:

[0118] [Math. 14]

[0119] For the case b4 = 1, the subset of results can be written in the form:

[0120] [Math. 15] Rb^R^R*^^^

[0121] For the case b4 = 0, the subset of results can be written in the form:

[0122] [Math. 16] Rb^ = Rd(Rdif Rd^ Æ < / IS]

[0123] In general, for a case denoted Xj corresponding to bj = (01), the subset of results can be denoted:

[0124] [Math. 17] Rxj = [ Rx^ ^x^ .. •, RxjjvX / ]

[0125] The value of Nxf can vary for different cases (this depends on the number of inequalities to be checked to determine the Voronoi sector in the first quadrant for the case considered). N y, is less than N.

[0126] For each case, it is possible to determine which sector the image of the symbol s belongs to in the first quadrant by comparing the subset of results with different possible candidate values ​​(by focusing on certain bits of the subset of results for each sector). For example, for the case bQ = 1, the received symbol can be considered to be in the sector corresponding to the symbol s9 if the inequalities corresponding to the lines d1 and d2 are satisfied, that is, if:

[0127] [Math. 18] & [ 1,1, 0,0, 0] = = [ 1,1, 0,0, 0]

[0128] The & operator corresponds to the "bitwise AND" operator. For example, this first equality can be associated with an index ni = 1 (this amounts to associating the sector corresponding to the symbol s9 for the case b0 = 1 with the index ni = 1).

[0129] Still for the case b0 - 1, we can consider that the received symbol is in the sector corresponding to the symbol if the inequalities corresponding to the lines d2 and d3 are not verified and if the one corresponding to the line d5 is verified, that is to say if:

[0130] [Math. 19] R^ & [0,1,1,0, 1] = = [0,0,0,0,1]

[0131] We can for example associate this second equality with an index m = 2 (this amounts to associating the sector corresponding to the symbol if for the case = 1 with the index ni = 2).

[0132] Similarly, the received symbol can be considered to be in the sector corresponding to the symbol s 17 if the inequalities corresponding to the lines d4 and d5 are not satisfied, that is to say if:

[0133] [Math.20] Rb-x & [0.0, 0.11] = = [0.0,0.0, 0]

[0134] For example, this third equality can be associated with an index ni = 3 (this amounts to associating the sector corresponding to the symbol s 17 for the case b0 = 1 with the index ni - 3).

[0135] Finally, we can consider that the received symbol is in the sector corresponding to the symbol s25 if the inequality corresponding to the line dl is not verified, and if the inequalities corresponding to the lines d3 and d4 are verified, that is to say if:

[0136] [Math.21] Rb^ & [1,0,1,10] = = [0,0, 1,1,0]

[0137]

[0138]

[0139]

[0140]

[0141]

[0142]

[0143]

[0144]

[0145]

[0146]

[0147]

[0148]

[0149]

[0150]

[0151]

[0152]

[0153] For example, we can associate this fourth equality with an index ni = 4 (this amounts to associating the sector corresponding to the symbol s25 for the case b^ = 1 with the index m = 4). For a received symbol, only one of the four above equalities is verified, and the corresponding index represents the Voronoi sector in which the received symbol is located. Similarly, we can identify in which sector the received symbol is located for the case b0 = 0. More specifically, the symbol is located in the sector corresponding to the symbol sO, associated with an index n = 1, if: [Math.22] Rb(^ & [ 1,0,0,1, 0] = = [0.0, 0.1, 0] The symbol is located in the sector corresponding to the symbol s8, associated with an index n = 2, if: [Math.23] Rb^ & [1,10,0,1]= =[1,1,0,0,1] The symbol is located in the sector corresponding to the symbol s 16, associated with an index n = 3, if: [Math.24] Rb-Q & [0,0,1,1, 1] = =[0,0, 1,0,0] The symbol is located in the sector corresponding to the symbol s24, associated with an index n = 4, if: [Math.25] Rb^ & [0,1,1,0,0]= = [0.0, 0,0,0] The LLR value for bit b0 can then be calculated in the form: [Math.26] ++ 5^ with = ■1'"OM")) Ob())nji ~ 2 Sb [m) is the symbol associated with the index m for the case b0 = 1 (it is the symbol of the constellation closest to the symbol s for which b0 = 1). is the symbol s9; $ (M is the symbol if; ç 00 is the symbol s 17; $ L0 is the symbol s25. $ O is the symbol associated with the index n for the case b0 = 0 (it is the symbol of the constellation closest to the symbol for which bQ = 0). is 'c sSymbole sO ; ç Ml is the symbol s8 ; ç M\ is the symbol s 16 ; ç Ml is the symbol s24.

[0154] The indices m and n each take their value from the set {0, 2, 3}. As As explained previously, the index m (respectively n) identifies the sector of the first quadrant corresponding to the received symbol for the case where the value of the bit considered is '1' (respectively for the case where the value of the bit considered is '0').

[0155] The reasoning that has been developed above for the bit bQ can be carried out in a similar way for the bits M and b^.

[0156] In general, and as illustrated in Figure 1, method 100 comprises, for each bit bj of the symbol s belonging to the second group: - for each case denoted Xj corresponding to ^bj — ( 011 ), a determination 105 of a subset Rxj — Rx^, •.., of the results obtained for the X inequalities, and a comparison 106 of said subset of results with predetermined candidate values, - a selection of 107 from a set of parameters defined by an index m representing the candidate value corresponding to the subset of results for the case where the value of the bit is '1' and an index n representing the candidate value corresponding to the subset of results for the case where the value of the bit is '0' (the index m identifies the sector of the first quadrant for the case bj = 1, and the index n identifies the sector of the first quadrant for the case bj — 0), - a calculation 108 of the LLR for the bj bit based on the selected parameters and depending on the real part and the imaginary part of the symbol:

[0157] [Math.27] LLR(bj) = ^Re{s) +

[0158] with 101591 =«'KH - 4M"))

[0160] . r Je I \\ t (o / ïi [Oiôi] O b pmi ~ 2

[0162] As previously seen in detail for bit b{}, the result subset Rx, and each candidate value Cx^p are each defined in the form of a field of X x, bits, with Nxj < N. The comparison 106 of the subset R\. with the candidate values ​​amounts to making bit-by-bit comparisons of the type:

[0163] [Math.28] J 2M 1 Rxj & Mxj,P= -Cx^.p, 11,2,

[0164] is a binary mask to be applied to the result RxP and Cxrp is a value predetermined candidate. A mask and a candidate value are defined for each sector of the first quadrant for the case Xj considered. There are 2^ sectors in the 8 first quadrant for each case.

[0165] However, nothing would prevent the comparison step 106 from being implemented differently, for example by expressing Rxj in decimal form and identifying the different decimal values ​​that can be taken by Rxj in each sector of the first quadrant.

[0166] The above description clearly illustrates that, by its various characteristics and their advantages, the present invention achieves the stated objectives.

[0167] In particular, the proposed solution does not use angle calculations, nor multiplication or division by non-constant values ​​(noise power normalization is not taken into account). In the example considered, for each symbol to be unmapped, method 100 comprises: - twenty-four additions (eighteen additions in formulas [Math.2] to [Math.7], and two additions in formula [Math. 27] for each of the three bits of the second group), - twenty-six multiplications by constant values ​​(eighteen multiplications in formulas [Math.2] to [Math.7], two multiplications in formula [Math. 27] for each of the three bits of the second group, and one multiplication in formulas [Math. 8] and [Math. 9] for each of the two bits of the first group), - eighteen comparisons in formulas [Math.2] to [Math.7], and - twenty-four bit-by-bit comparisons according to formula [Math.28] for each of the three bits of the second group.

[0168] In addition, method 100 has the same number of calculations to unmap a symbol, regardless of the symbol received.

[0169] These characteristics are particularly interesting when the method is implemented by a demapping module 23 implemented on an FPGA target.

[0170] The values ​​of parameters 2, ak, can be determined at the design of the receiving device 20, according to the constellation envisaged, and stored by the unmapping module 23.

[0171] Advantageously, the sets of steps 105 to 108 performed respectively for the different bits of the second group can be executed in parallel. Similarly, the steps 103 performed respectively for the different bits of the first group can be executed in parallel with each other and with the sets of actions 105 to 108 performed for the bits of the second group.

[0172] It should be noted that the implementation and embodiment methods considered above have been described by way of non-limiting examples, and that other variations are therefore conceivable. The invention has been described considering a particular 32-APSK modulation. However, nothing precludes, following other examples, considering other constellations or other modulations (for example, by changing the arrangement of the symbols, the number of symbols, and / or the type of modulation).

Claims

Demands

1. Method (100) for unmapping a modulation symbol s, said symbol representing several bits of information, the method for calculating a logarithmic likelihood ratio, LLR, for each bit of the symbol, the method (100) being implemented by a unmapping module (23) of a receiving device (20), the modulation having a symbol constellation with half-plane symmetry for one or more symbol bits belonging to a first group, and quadrant symmetry for one or more symbol bits belonging to a second group, the method (100) being characterized in that it comprises: a classification (101) of each symbol bit into the first group or into the second group, a determination (102) of V pairs (0k), k G [1, 2V], V being an integer strictly greater than one, the V pairs being different in pairs and each defining a slope ai and an ordinate of the origin of a line forming an edge of a Voronoi sector defined for a symbol bit belonging to the second group and taking the value '0' or the value '1' in a first quadrant of the constellation, for each bit of the symbol4 belonging to the first group, a calculation (103) of the LLR for said bit in the form of a product between a multiplicative factor and a real part R^s) or an imaginary part of the symbol 4, a verification (104) of V inequalities ak\ Re(s) | +fik < 17^)1 ' fce [t^], for each bit of symbol4 belonging to the second group: - for each value '0' or '1' that can be taken by the bit, a determination (105) of a subset of the results obtained for the V inequalities, and a comparison (106) of the subset of results with predetermined candidate values, - a selection (107) of a set of parameters defined by an index m representing the candidate value corresponding to the subset of results for the case where the bit value is '1' and an index n representing the candidate value

2.

3.

4.

5.

6.

7.

8.

9. corresponding to the subset of results for the case where the bit value is '0', - a calculation (108) of the LLR for the bit as a function of the selected parameters and as a function of the real part and the imaginary part of the symbol. Method (100) according to claim 1 wherein the modulation is an APSK modulation in phase and amplitude, or a QAM amplitude modulation in quadrature. Method (100) according to claim 2, wherein the modulation comprises 2^ symbols, M being an integer greater than or equal to four. Method (100) according to claim 3, wherein the modulation is APSK modulation, M is equal to five, and N is equal to eighteen. Method (100) according to any one of claims 1 to 4, wherein the modulation exhibits a constellation defined in a DVB-S2, DVB-S2X, CCSDS, or 5G communication standard. Method (100) according to any one of claims 1 to 5 wherein, for each value equal to '0' or '1' that can be taken by a bit bj belonging to the second group, the subset of results and each candidate value are each defined in the form of a bit field, with < N. Method (100) according to any one of claims 1 to 6 wherein the multiplicative factor is calculated in the form  / ^, where <72 is an estimated value of a variance of additive white Gaussian noise of a propagation channel of a signal carrying the symbol Method (100) according to claim 7, wherein 2 takes at least two possible values ​​depending on the value of the real part (Re) or the imaginary part of the symbol. Module (23) for unmapping a modulation symbol s, said symbol representing several bits of information, the modulation having a constellation of symbols with half-plane symmetry for one or more symbol bits belonging to a first group, and quadrant symmetry for one or more symbol bits belonging to a second group, the unmapping module (23) being characterized in that it is configured to store N pairs (a^,k) [1, N], N being an integer strictly greater than one, the N pairs being pairwise different and defining each a slope at and an ordinate of a line forming an edge of a Voronoi sector defined for a symbol bit belonging to the second group and taking the value '0' or the value '1' in a first quadrant of the constellation, and to implement the following steps: for each symbol bit belonging to the first group, a calculation (103) of a logarithmic likelihood ratio, LLR, for said bit in the form of a product between a multiplicative factor and a real part Re(s) or an imaginary part of the symbol *, a verification (104) of N inequalities | + < |Z^ç)|, Æe [1, ^], for each symbol bit belonging to the second group: - for each value '0' or '1' that can be taken by the bit, a determination (105) of a subset of the results obtained for the A inequalities, and a comparison (106) of the subset of results with predetermined candidate values,- a selection (107) of a set of parameters defined by an index m representing the candidate value corresponding to the subset of results for the case where the value of the bit is '1' and an index n representing the candidate value corresponding to the subset of results for the case where the value of the bit is '0', - a calculation (108) of an LLR for the bit as a function of the selected parameters and as a function of the real and imaginary parts of the symbol.

10. Demapping module (23) according to claim 9 wherein the modulation is an APSK modulation in phase and amplitude, or a QAM amplitude quadrature modulation, comprising 2M symbols, M being an integer greater than or equal to four.

11. Demapping module (23) according to claim 10 wherein the modulation is an APSK modulation, M is equal to five, and A' is equal to eighteen.

12. A demapping module (23) according to any one of claims 9 to 11 wherein, for each value equal to '0' or '1' that can be taken by a bit bj belonging to the second group, the subset of results and each candidate value are each defined as a 2V^ai) bit field, with N b ^ai) < N.

13. Demapping module (23) according to any one of claims 9 to 12 wherein the multiplicative factor is calculated in the form ^- / ^1, where is an estimated value of a standard deviation of Gaussian white additive noise of a propagation channel of a signal carrying the symbol s.

14. Demapping module (23) according to claim 13 wherein 2 takes at least two possible values ​​depending on the value of the real part or the imaginary part of the symbol s.

15. Receiving device (20) comprising a demapping module (23) according to any one of claims 9 to 14.

16. Satellite (10) comprising a receiving device (20) according to claim 15.

17. Ground station comprising a receiving device according to claim 15.

18. Communication system comprising at least one satellite according to claim 16 and / or at least one ground station according to claim 17.

Images