Device and method for synchronizing or adapting a software clock signal

Abstract

The invention relates to a device for synchronizing or adapting a clock signal for software. This device includes a processor executing the software based on a clock signal. It includes a measurement timer module that increments a time value based on the device's clock, as well as an output unit. An input unit is provided for receiving an input signal. The device also includes a register unit that stores the current value of the measurement timer at the end of the synchronization period. Upon receiving an input signal, the measurement timer module is designed to reset its value to a starting value. The invention is characterized by a comparison unit that compares the time value stored in the register unit with the synchronization period and adapts it by at least one subsequent period of the clock signal. Figure 1

Description

Title of the invention: Device and method for synchronizing or adapting a software clock signal

[0001] The present invention relates to a device and a method for synchronizing or adapting the clock signal of a software program, as well as a corresponding system.

[0002] For security reasons, it is often advantageous for several instances of the same software or even differently designed software to be run on independent processors, for example to perform critical functions in the control or monitoring of a land or air vehicle in a redundant manner and as decoupled from each other as possible.

[0003] However, it is advantageous for the different software programs to be executed synchronously. Since the clocks of different computing units can never be operated in a completely synchronous manner due to existing tolerances, a shift in the clock signals of the respective computing units occurs over time, which disrupts the temporal synchronization of the different software programs on the respective computing units.

[0004] Typical application areas for the synchronous, time-dependent operation of software on different computing units, controllers, or processors include the redundant implementation of critical software functions. The concept of the present invention can also be integrated into a control / monitoring architecture, where the synchronous, time-dependent execution of different software is also important.

[0005] In real-time applications, the control software is generally executed with a fixed period of a few milliseconds. If two controllers operate asynchronously, the data transmission time between the controllers may vary (jitter) from the duration of the software period. This must be taken into account during system design, resulting in additional effort.

[0006] Jitter caused by asynchronous execution of the software also affects the reaction time to external events requiring coordination between controllers.

[0007] For application-level timebase synchronization, various protocols are available in the state of the art, such as the Network Time Protocol (NTP) and the Precision Time Protocol (PTP). These protocols allow network participants to synchronize via a digital bus. The drawback is that protocol-based synchronization increases the effort and execution time of the software for processing the communication, leaving less time for actual control tasks. Furthermore, the transmission time via the bus limits the achievable accuracy.

[0008] The objective of the present invention is to create a device, method, or system that overcomes, or at least mitigates, the aforementioned drawbacks. More particularly, the objective of the present invention is to synchronize the starting point of a software period on two independent controllers with the least possible computation time and high precision (-1 ps).

[0009] According to the invention, a device is provided, more particularly a microcontroller, for synchronizing or adapting a clock signal for software, comprising a processor for executing the software on the basis of the clock signal, in which the clock signal defines the beginning or end of a software period, a measuring timer module that increments a timing value on the basis of a clock of the device, an output unit designed to output a signal to a signal output of the device at the beginning of a synchronization period defined by the software period or a multiple of the software period, and an input unit designed to receive an input signal at a signal input of the device, a register unit designed to record a current timing value of the measuring timer module at the end of a synchronization period,in which the measurement timing module is designed to reset the timing value to a starting value, more particularly to zero, upon receiving an input signal. The invention is characterized by a comparison unit designed to compare the timing value recorded in the register unit with the synchronization period and to adapt, based on a comparison result, at least one subsequent period duration of the clock signal for the software running on the processor, more particularly lengthening or shortening it.

[0010] The device, or microcontroller, is capable of resetting a timer value (or counter value) based on an input signal. The signal received via the input unit may indicate the start of a synchronization period for another entity. The device thus learns how much its synchronization period is offset relative to the synchronization period of the other entity, so that an adjustment of the synchronization period is possible based on the determined offset.

[0011] The possibility of restoring synchronicity between the two synchronization periods of different devices reduces the jitter that could otherwise result from the asynchronous execution of different instances of the same software when comparing the software's output signals. Furthermore, according to the invention, no protocol-based synchronization is necessary, as the advantages of the device described above do not require a protocol.

[0012] Furthermore, according to the present invention, a device, more particularly a microcontroller, can also be provided to synchronize or adapt a signal a clock for software, comprising a processor for executing the software on the basis of the clock signal, wherein the clock signal defines the beginning or end of a software period, a measurement timer module that increments a timer value on the basis of a clock of the device, an output unit designed to output an output signal to a signal output of the device at the beginning of a synchronization period defined by the software period or a multiple of the software period, and an input unit designed to receive an input signal at a signal input of the device, a register unit designed to record a current timer value of the measurement timer module upon receiving an input signal, wherein the measurement timer module is designed to reset the timer value to a starting value, more particularly to zero, at the beginning of a synchronization period.The invention is characterized by a comparison unit designed to compare the timing value recorded in the register unit with the synchronization period and to adapt, based on a comparison result, at least one subsequent period duration of the clock signal for the software running on the processor, more particularly to lengthen or shorten it.

[0013] Fig. 2 shows that this time it is no longer TCapture, but directly AT which is determined, synchronization being present when the timing value of the measurement timing module is at 0 or a slightly different value.

[0014] According to an optional development of the present invention, it may be provided that the clock of the device has a frequency higher than the clock frequency for the execution of the software running on the processor, the clock of the device having, preferably, a frequency more than 100 times, even more preferably, more than 1000 times higher than the clock frequency for the execution of the software running on the processor.

[0015] The device clock typically corresponds to the processing clock of the device and, for known state-of-the-art microcontrollers, is in a range of several hundred MHz or a few Gigahertz.

[0016] This must be distinguished from the clock signal for the software executed by the processor, since the latter typically has a frequency significantly lower than the device clock. It is therefore easily possible to detect or specify the software period or even the synchronization period as a multiple of the device clock. A timing module that is incremented with each beat of the device can thus determine quite accurately the duration of the software period or the synchronization period, or a sub-section thereof.

[0017] According to an advantageous development of the present invention, the comparator unit can be designed to lengthen or shorten, depending on the As a result of the comparison, the duration of the next period of the clock signal for the software running on the processor is half the time difference determined by the result of the comparison.

[0018] Thus, if, with the device according to the invention, a shift is detected at the beginning of the synchronization period, a start of the synchronization period of another device having been communicated via the input unit, the entire shift is not necessarily compensated in one of the devices compared with each other, but, according to this advantageous implementation, each of the two devices can also compensate half of the shift, so that a subsequent start of the synchronization period of the compared devices begins simultaneously.

[0019] However, it is clear to a person skilled in the art that the compensation due to the observed discrepancy can also be implemented in only one of the several devices, which is nevertheless the least preferred implementation.

[0020] According to another optional development of the present invention, it may be provided that the comparator unit is designed to lengthen or shorten, depending on the result of the comparison, several subsequent periods of the clock signal for the software running on the processor by a fraction of the time difference determined by the result of the comparison, preferably the fraction being -L or A, where N is the number of several subsequent periods of the clock signal to be lengthened or shortened for the software running on the processor.

[0021] When different software programs need to be synchronized, the software periods to be synchronized often have different durations. In such a case, the synchronization period is the least common multiple of the two software periods of different lengths. If a deviation is then observed in the comparison of the synchronization, it is advantageous not to compensate for this synchronization lag within a single software period, because the degree of compensation, i.e., the deviation from an uncorrected software period, would be significantly greater than if the desired compensation were implemented over several software periods.

[0022] For this reason, it is proposed not to compensate for the observed discrepancy with respect to the synchronization period within a single software period, but to use the total number of available software periods (within a synchronization period). The factor of 0.5 results, as explained above, from the consideration that the other device with which synchronization is to be achieved also performs equal compensation for its synchronization period.

[0023] Furthermore, according to the present invention, it may be provided that the comparator unit is designed to divide the timing value recorded in the register unit by a frequency characterizing the device's clock in order to obtain a measurement period.

[0024] Since the timing value represents one period of the device clock, the time measured with the timing value can be obtained by dividing by the processor clock frequency (= device clock frequency).

[0025] According to an optional development of the present invention, it may be provided that the device further comprises a clock timing module which increments a timing value on the basis of the device clock and emits an interrupt signal when a predefined target timing value is reached, the predefined target timing value divided by the frequency of the device clock giving the software period, and the comparator unit being designed to execute the next period duration at least of a clock signal for the software running on the processor by adapting the target timing value.

[0026] The interrupt signal then signals the end of the software period. To adjust the duration of the software period according to the considerations outlined above, i.e., to shorten or lengthen it, the target value of the timer is modified accordingly. Thus, if an extension of the software period is necessary to achieve synchronization, the previously used target value of the timer is increased (only once). Conversely, if a reduction of the software period is necessary to achieve synchronization, the previously used target value of the timer is decreased (only once).

[0027] According to an advantageous development of the present invention, it may further be provided that the input unit is implemented by a Capture / Compare unit (CCU), configured in Capture mode, and / or that the output unit is implemented by a general purpose input / output unit (GPIO).

[0028] A Capture Compare Unit (CCU) is a special functional unit in microcontrollers and other digital signal processors that enables the precise acquisition and processing of signals. This unit allows for the capture and recording of specific time points of external events, as well as performing comparison operations to carry out precise and timed control tasks.

[0029] In Capture mode, the CCU captures the current timer value (or counter value) as soon as the end of the synchronization period is detected, for example, by detecting a falling edge of the synchronization period. Furthermore, the CCU is designed to reset its built-in timer to zero when the input unit receives a specific input signal (for example, a rising or falling edge).

[0030] A GPIO, or General Purpose Input / Output, is a universally usable digital pin on microcontrollers and other integrated circuits, which can be designed as both an input and an output. These pins provide a versatile interface for a microcontroller to interact with the outside world.

[0031] Designed as an output, a GPIO pin can control external devices, the synchronization signal characterizing the synchronization time of the associated microcontroller being emitted here, so that it can be received by another device via the input unit, more particularly the CCU.

[0032] The invention further relates to a system for synchronizing or adapting a clock signal of several software programs running in parallel, comprising a first device according to one of the configurations previously discussed, and a second device according to one of the configurations previously discussed, in which the output unit of the first device is connected to the input unit of the second device and the output unit of the second device is connected to the input unit of the first device, preferably each software program of the several software programs running in parallel is run by the respective processor of the several devices.

[0033] This describes the advantageous interaction of several devices according to the invention as a system, in which the software operating independently of each other of the individual devices can be synchronized with each other.

[0034] It can advantageously be provided that the synchronization period is the lowest common multiple of the software period of the first device and the software period of the second device.

[0035] The invention further relates to a method for synchronizing or adapting a respective clock signal for several software programs executed in parallel, more particularly with a device according to one of the configurations described or a system according to the configurations previously described, comprising the following steps: defining a respective software period for the several software programs to be synchronized with each other, which are executed by respective computing units, preferably as a multiple of a device clock of a respective computing unit (processor) which executes an associated software program; definition of a synchronization period as the least common multiple of the several respective software periods; realization of a time measurement, in which the starting point of the time measurement for a first calculation unit is the beginning of the synchronization period of a second calculation unit and the ending point of the time measurement for the first calculation unit is the end of the synchronization period of the first calculation unit, and the starting point of the time measurement for a second calculation unit is the beginning of the synchronization period of a first calculation unit and the point The final time measurement for the second computing unit is the end of the synchronization period of the second computing unit, in which Each calculation unit compares the result of the time measurement with the synchronization period and, based on this, adapts a respective subsequent synchronization period by at least one, more specifically extending or shortening it.

[0036] Similar to what occurs in the device, in the method according to the invention, the beginning of the synchronization period of another computing unit is also used to reset a counter, so that a deviation of its own synchronization period from the other synchronization period can be detected at the end of its own synchronization period. Depending on the determined deviation, the next synchronization period is then lengthened or shortened to restore synchronous operation with the other synchronization period, which can also be lengthened or shortened accordingly.

[0037] The invention further relates to a method for synchronizing or adapting a respective clock signal for several software programs executed in parallel, more particularly with a device according to one of the configurations described or a system according to the configurations previously described, comprising the following steps: defining a respective software period for the several software programs to be synchronized with each other, which are executed by respective computing units, preferably as a multiple of a device clock of a respective computing unit (processor) which executes an associated software program; definition of a synchronization period as the least common multiple of the several respective software periods; realization of a time measurement, in which the starting point of the time measurement for a first computing unit is the beginning of its own synchronization period and the ending point of the time measurement for the first computing unit is the beginning of a synchronization period for a second computing unit, and the starting point of the time measurement for a second computing unit is the beginning of its own synchronization period and the ending point of the time measurement for the second computing unit is the beginning of the synchronization period of the first computing unit, in which Each calculation unit compares the result of the time measurement with the synchronization period and, based on this, adapts a respective subsequent synchronization period by at least one, more specifically extending or shortening it.

[0038] According to another advantageous modification of the present invention, it may be provided that, if the software period is equal to the synchronization period, the next software period is extended or shortened by half of the difference observed in the comparison.

[0039] Alternatively or in addition, it may be provided that, if the software period is an N- multiple of the synchronization period, the following N software periods are extended or shortened by the value _1_ times or by the value JL times the observed difference 1 b 2N N in the comparison.

[0040] The factor of can for example be omitted if only one of the two devices to operate synchronously carries out an adaptation and the other continues to operate without adaptation.

[0041] According to another advantageous development of the present invention, it can be provided that, if a value measured by the measurement timing module during the comparison is greater than twice the synchronization period, it is concluded that an error is present, preferably that the other parallel software is inactive.

[0042] If the value measured by the time measurement is more than twice the synchronization period, there is an error, which allows us to conclude that the other software is no longer accessible or available.

[0043] According to another advantageous development of the present invention, it can be provided that a sequence of comparison results obtained during each comparison is recorded and analyzed, and that in the event of reaching a predefined threshold of comparison results over a predefined number of consecutive comparisons, an error is concluded, more particularly an imminent loss of synchronization.

[0044] Thus, according to the present invention, it can also be provided that the measured value obtained during a time measurement is recorded, so that over time, a multitude of recorded measured values ​​(TCapture) are available and can be subjected to analysis. If it is observed that, for a certain period of time, the measured value is permanently above or below a predefined threshold, i.e., that the restoration of synchronization must be continuously ensured by adapting the synchronization period, this allows us to conclude that the discrepancy cannot be corrected. It must then be assumed that one of the two software programs or devices to be executed synchronously is not (permanently) respecting the synchronization period. The loss of synchronization can therefore be detected very early, but it cannot be determined which of the software programs or devices to be executed synchronously is the cause.

[0045] The invention also relates to an aircraft with a device according to one of the configurations previously discussed, a system according to the configurations previously discussed or a control unit for the execution of a process according to one of the configurations previously discussed.

[0046] Other features, details, and advantages of the invention will become apparent from the description in the following figures. The following figures show: [Fig. 1]: a schematic representation of a system according to the invention with two devices according to the invention, and [Fig.2]: Schematics for the representation of the synchronization period and the time-incrementing time value of the measurement time-delay module for the devices of [Fig.1].

[0047] Figure 1 represents a system 10 comprising two devices 1 according to the invention. According to the embodiment shown, each device 1 consists of a microcontroller (MCU 1 and MCU 2), in which the output unit 2 of the first device 1 is connected to the input unit 3 of the second device 1. In addition, the output unit 2 of the second device is connected to the input unit 3 of the first device.

[0048] As shown, output unit 2 can be implemented by a GPIO pin (GPIO: General Purpose Input / Output), while input unit 3 can be a Capture / Compare Unit (CCU), which is operated in Capture mode. In this mode, a counter register incremented by the processor's internal clock is reset to zero when the state of the CCU pin changes. The CCU is designed so that the register is reset with only one edge (either rising or falling) of a signal applied to the corresponding pin, but not with both types of edges.

[0049] The output unit 2 is designed so that a signal is emitted during an upward edge of a synchronization period, so that the other device 1 is informed of the start of the synchronization period (via a signal to the input unit 3).

[0050] [Fig.2] explains the synchronization process of the two devices 1, as shown in [Fig.1].

[0051] Synchronization takes place alternately in two consecutive phases: the measurement phase and the adaptation phase.

[0052] In the measurement phase, a shift in the synchronization period (TSync) relative to the other device 1 is first determined in each device 1, and then this shift is compensated for in the subsequent adaptation phase. This is done by adapting the synchronization period (TSync) by a value dependent on the determined shift.

[0053] First, the synchronization period (TSync) of the two devices 1 must be defined, as this depends on a period duration of the software executed on the first device 1 and on the second device 1. A software period (Tsw) defines a work cycle of the respective software, the frequency of which is significantly lower than the clock frequency of the processor used to execute the software.

[0054] If the software is executed on both devices 1, or microcontrollers, with the same period (Tsw), then the synchronization period (TSync) corresponds to the software period (Tsw). If, on the other hand, the software periods (Tsw) of the two programs executed by the respective processors of the different devices 1 are different, the The synchronization period (TSync) corresponds to the least common multiple of the two different software periods (Tsw) - H therefore applies here: TSync = kgV (TSW1, TSW2) where Tswi is the software period of the software on the first device 1 and TSW2 is the software period of the software on the second device 1.

[0055] A possible AT correction value for the synchronization period (TSync) can then be distributed over the respective number of software periods (Tsw) if the software periods (Tsw) are different.

[0056] Fig. 2 represents the synchronization period (TSync) for each of the two devices to be synchronized, as well as the incremental progression of the measurement timing module, which is reset during an upward slope of the synchronization period of the other device.

[0057] In the measurement phase, a signal is emitted to the other device 1 on the basis of the synchronization period (TSync) prevailing in a device 1. To this end, a signal is sent via the output unit during an upward edge of the synchronization period (TSync) to the input unit 3 of the other device, which, in the device 1 that receives the signal, causes a reset of the value of the counter of the measurement timing module.

[0058] The example of the first microcontroller MCU 1 shows at the beginning the rising edge, which, represented by a dashed arrow, causes a reset of the measurement timing module of the second microcontroller MCU 2 to a starting value, in this case zero.

[0059] The measurement timing module of the first microcontroller MCU 1 is also reset in the same way during a rising edge of the synchronization period (TSync) in the second microcontroller MCU 2, this reset occurring with an offset of ATh

[0060] In each of the two microcontrollers MCU1 and MCU2, the current timing value (counter state) of the measurement timing module is recorded during a falling edge of the corresponding synchronization period (TSync), this value being designated by TCapture in [Fig. 2]. The measurement timing module may be part of a CCU of the device.

[0061] In the adaptation phase, the recorded timing value of the measurement timing module, which indicates the time between a last reset and a falling edge of the synchronization period (TSync), is used to determine a deviation (TA) of the device with respect to the other device.

[0062] There are essentially the different cases represented below, which can be determined in a device from the measured time (TCapture) relative to the synchronization period: Tcapture ~ TSync: the measured time corresponds exactly to the synchronization period or only slightly deviates from it (it is therefore within a predefined deviation from the synchronization period), so we can assume that the two devices or the two microcontrollers are operating synchronously or almost synchronously. No adaptation is necessary. Tcapture < TSync: the measured time is less than the synchronization period, indicating that the synchronization period is "too early." In [Fig. 2], this applies to the first microcontroller, MCU1. The duration of the next phase should therefore be extended to restore synchronous operation with the other microcontroller. Tcapture > TSync: the measured time is greater than the synchronization period, indicating that the synchronization period is "too late." In [Fig. 2], this applies to the second microcontroller, MCU2. The duration of the next phase should therefore be shortened to restore synchronous operation with the other microcontroller. Tcapture > 2 x TSync: this indicates that no synchronization signal has been detected on the opposite side. It is therefore assumed that the opposite side is not active and that no synchronization is possible, which is considered an error case.

[0063] Figure 2 shows that during the adaptation phase, the deviation detected by each microcontroller is compensated by half. Since each of the two controllers performs half compensation, with one microcontroller extending the next phase and the other shortening it, the synchronization period of the two microcontrollers is synchronized again after the adaptation phase, so that subsequent synchronization periods again begin at the same time.

[0064] The invention may also provide that only one of the two microcontrollers performs an adaptation of its synchronization period. In this case, of course, the entire observed deviation must be adjusted. This could be advantageous for the microcontroller that does not have to adjust its phase, since a corresponding unit for adjusting the synchronization period is not required.

[0065] Another advantage is that if only unilateral compensation is performed, several participants can synchronize. Although exclusively bilateral synchronization is faster, it only allows two participants.

[0066] If the synchronization period is different from the software period of the software running on the microcontroller, the value to be corrected can be distributed over the respective number of software periods that elapse during a synchronization period.

[0067] Thus, for example, for a microcontroller that compensates for half of the observed discrepancy, the compensation value can be distributed equally over the number of software periods that, together, correspond to a synchronization period and elapse during that period. This allows for a large number of small adjustments, which has fewer negative effects than a larger temporal adjustment of a single software period.

[0068] The concrete implementation of a software-corrected period is typically achieved by modifying a load register in a hardware timer. The synchronization period is also generally controlled by a timing module that generates an interrupt when a predefined time value is reached, to signal that the synchronization period has ended. A value in the load register is used to start a new synchronization period; this value determines the time until the interrupt signal is generated. To shorten or lengthen the synchronization period, the value in the load register is adjusted accordingly, so that a deviation from the previous value of the load register results in a shortening or lengthening of the synchronization period.

[0069] Furthermore, an error can be detected if the measured time is more than twice the synchronization period. Normally, this indicates that one of the microcontroller's two clock generators is faulty, preventing the software from executing with the expected period. Typically, a watchdog timer with an independent clock generator is used to ensure the software's real-time behavior. If the software's period length deviates too much, the affected processor is reset or other error handling is initiated. It would then be detected that, due to a deviation (TCapture > 2 x TSync), the interlocutor is no longer available.

[0070] Furthermore, according to the invention, it can also be provided that the measured time values ​​TCapture are stored and analyzed, in order to detect if a discrepancy is persistently too large. This would indicate that a discrepancy in the synchronization of the two devices cannot be compensated, so it must be assumed that one of the two sides cannot meet the required synchronization period time (Tsync)*

[0071] Although this does not allow us to determine which side deviates, a loss of synchronization can be detected earlier than with a watchdog.

[0072] The present invention achieves the advantages described above with little effort in hardware and software, using standard components, and achieves very high precision.

Claims

Demands

1. Device (1), more particularly a microcontroller, for synchronizing or adapting a clock signal for software, comprising: a processor for executing the software on the basis of the clock signal, the clock signal defining the beginning or end of a software period; a timing module that increments a timing value on the basis of a clock of the device; an output unit (2), designed to output a signal to a signal output of the device at the beginning of a synchronization period (TSync) defined by the software period or a multiple of the software period; an input unit (3), designed to receive an input signal at a signal input of the device (1);and a register unit, designed to record a current timing value (TCapture) of the measurement timing module at the end of a synchronization period (Tsync), wherein the measurement timing module is designed to reset, upon receiving an input signal, the timing value to a starting value, more particularly to zero, characterized by a comparison unit, designed to compare the recorded timing value (TCapture) with the synchronization period (Tsync) and, based on a comparison result (AT), adapt at least one subsequent period duration of the clock signal for the software running on the processor, more particularly lengthening or shortening it.

2. Device (1) according to claim 1, wherein the clock of the device has a frequency higher than the clock frequency for the execution of the software running on the processor, preferably the clock of the device having a frequency more than 100 times, more preferably more than 1000 times higher than the clock frequency for the execution of the software running on the processor.

3. Device (1) according to one of the preceding claims, wherein the comparison unit is designed to, depending on the comparison result (AT), extend or shorten the duration of the next period of the clock signal for the software running on the processor of half the time difference determined by the comparison result (AT).

4. Device (1) according to any one of the preceding claims, wherein the comparator unit is designed to, depending on the comparator result (AT), lengthen or shorten several subsequent periods of the clock signal for the software running on the processor by a fraction of the time difference determined by the comparator result (AT), wherein, preferably, the fraction is JL, where N is the number of several subsequent periods of the clock signal to be lengthened or shortened for the software running on the processor.

5. Device (1) according to one of the preceding claims, wherein the comparator unit is designed to divide the recorded timing value (TCapture) by a frequency characterizing the device clock, in order to obtain a measurement period.

6. Device (1) according to one of the preceding claims, further comprising: a clock timing module, which increments a timing value on the basis of the device clock and emits an interrupt signal when a predefined timing target value is reached, wherein the predefined timing value divided by the frequency of the device clock gives the software period, and the comparator unit is designed to execute the next period duration at least of a clock signal for the software running on the processor by an adjustment of the timing target value.

7. Device (1) according to one of the preceding claims, wherein: the input unit (3) is realized by a capture and compare unit (CCU), configured in Capture mode; and / or the output unit (2) is realized by a general purpose input / output unit (GPIO).

8. A system (10) for synchronizing or adapting a clock signal of several software programs running in parallel, comprising: a first device (1) according to claims 1 to 7 and a second device (1) according to any one of claims 1 to 7, wherein the output unit (2) of the first device (1) is connected to the input unit (3) of the second device (1) and the output unit (2) of the second device (1) is connected to the input unit (3) of the first device (1), preferably wherein a respective software of the several software executed in parallel is executed by the respective processor of the several devices (1).

9. System (10) according to claim 8, wherein the synchronization period (TSync) is the lowest common multiple of the software period of the first device (1) and the software period of the second device (1).

10. A method for synchronizing or adapting a respective clock signal for several software programs running in parallel, more particularly with a device (1) according to any one of claims 1 to 7 or a system (10) according to claims 8 to 9, comprising the following steps: defining a respective software period for the several software programs to be synchronized with each other, which are run by respective computing units, preferably as a multiple of a device clock of a respective computing unit, which runs an associated software program; defining a synchronization period (TSync) as the least common multiple of the respective software periods; and performing a time measurement.in which the starting point of the time measurement for a first computing unit is the beginning of the synchronization period (TSync) of a second computing unit and the ending point of the time measurement for the first computing unit is the end of the synchronization period (TSync) of the first computing unit, and the starting point of the time measurement for a second computing unit is the beginning of the synchronization period (TSync) of a first computing unit and the ending point of the time measurement for the second computing unit is the end of the synchronization period (TSync) of the second computing unit, in which each computing unit compares the result of the time measurement with the synchronization period (TSync) and, based on the latter, adapts at least one subsequent synchronization period (TSynch), more specifically extending or shortening it.

11. A method according to claim 10, wherein, if the software period is equal to the synchronization period (TSync), the next software period is extended or shortened by half of the difference observed in the comparison.

12. A method according to any one of claims 10 or 11, wherein, if the software period is an N-multiple of the synchronization period (TSync), subsequent software periods are extended or shortened by _1_ times the value of the deviation observed in the 2N comparison.

13. A method according to any one of claims 10 to 12, wherein, if a measured value observed during the comparison is greater than twice the synchronization period (TSync), it is indicated that an error case is present, preferably that the other parallel software is inactive.

14. A method according to any one of claims 10 to 13, wherein a sequence of comparison results (AT) obtained in each comparison is stored and analyzed, and if a predefined threshold of several comparison results (AT) is reached on a predefined number of consecutively performed comparisons, an error case is inferred, more particularly an imminent loss of synchronization.

15. Aircraft with a device (1) according to any one of claims 1 to 7, a system (10) according to claims 8 or 9, or a control unit for carrying out a process according to any one of claims 10 to 14.

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