Quantum qubit device in a heterostructure

Abstract

A qubit quantum device in a heterostructure. A qubit quantum device (200) comprising: - a stack (210) extending in a plane, including first, second, and third semiconductor layers (212, 214, 216) on a semiconductor substrate (102), the second layer being adapted to confine a charge carrier, and the semiconductors of the first and third layers each having a lattice parameter different from that of the second semiconductor; - a gate structure (120) positioned on a first face (210A) of the stack and adapted to control the displacement of the charge carrier confined in the second layer; - a recess (222) extending from the first face through the third and second layers, located at a distance D from a center of the gate structure in the plane and having a depth T such that the ratio D / T is in the interval ]0;10]. Figure for the abstract: Fig. 2

Description

Title of the invention: Quantum device with a qubit in a heterostructure. Technical field

[0001] This description relates generally to the field of quantum information or quantum computing. It relates in particular to quantum devices with quantum bits, called "quantum bits" in English, or "qubits", that is to say, elementary units of quantum information.

[0002] Advantageously, the present description applies to the development of quantum processors in which qubits are encoded in semiconductor regions, in particular for spin qubits where quantum information is encoded in the spin states of a charge carrier (electron or hole) confined in a semiconductor region by electrostatic potentials delivered by control gates. Previous technique

[0003] Quantum computing is based on the use of a two-level measurable quantum state as an information vector, called a quantum bit or, in English, "qubit". Laws and properties of quantum mechanics, such as superposition, entanglement, and measurement, are exploited to execute algorithms. A quantum device comprising qubits allows manipulation of the quantum state of these qubits.

[0004] Spin or charge qubits can be formed in a semiconductor. Semiconductor technologies such as CMOS (Complementary Metal Oxide Semiconductor) and, in particular, technologies derived from field-effect transistors (FETs), have been studied for the realization of qubits. In such qubits, electrons or holes (charge carriers) are confined at cryogenic temperatures in nanometer-sized confinement structures defined within a region of a semiconductor, which can be silicon. These confinement structures correspond to quantum dots. A quantum dot behaves like a potential well confining one or more charge carriers within the semiconductor region.

[0005] To confine a charge carrier within the quantum dot formed in the semiconductor region, and to control this quantum dot, it is necessary to be able to adjust the energy depth of this quantum dot in the semiconductor, that is, the minimum potential energy level, or potential, of the quantum dot. Furthermore, To control the occupancy, in terms of the number of electric charges, of several quantum dots formed side-by-side in the semiconductor region, in addition to controlling the potential, it is necessary to adjust the energy height of the tunneling barriers, or tunneling barriers—that is, the maximum level of the tunneling barriers—that separate the quantum dots. The control of the tunneling barriers and the potential is generally achieved through voltages applied to electrostatic control grids. For example, to transfer a charge carrier from one quantum dot to another, a technique known as "hopping," one can manipulate some of these control grids to lower the height of the tunneling barrier between the two quantum dots and / or raise the potential of these quantum dots.

[0006] In a quantum dot device in a semiconductor, certain control gates (plunger gates) are generally arranged above the semiconductor region covered by a layer of insulating material forming the gate oxide. Charge carrier confinement is sensitive to the presence of trapped electric charges, primarily at the interfaces between the semiconductor and the insulating material. This creates charge disorder, which is a cause of variability between the qubits.

[0007] However, a quantum processor generally comprises a large number of qubits, and the realization of such a number of qubits within the same quantum device poses technological problems, in particular problems of managing variability between qubits.

[0008] To address this problem of charge disorder and variability, designers of quantum qubit devices are turning to semiconductor heterostructures, that is, structures obtained by stacking several semiconductor layers, at least two of which are made of different semiconductors. One of these semiconductor layers is designed to form a quantum confinement region, or confinement region, for one (or more) charge carrier(s), forming a qubit. The confinement region is, for example, a quantum dot. The different semiconductors generally have different bandgap energies and different lattice sizes.

[0009] A magnetic field is applied to separate the spin states and define the qubit. This static magnetic field is preferably aligned parallel to the plane of the semiconductor layers in the case of Ge / SiGe heterostructures in order to limit so-called "hyperfine" interactions with the nuclear spins in the semiconductor layers. The qubit can be manipulated by applying RF (radio frequency) electric or magnetic fields with a frequency equal to the energy gap between the different spin states, or by hopping between them. quantum dots when the magnetic field is aligned parallel to the plane of the semiconductor layers.

[0010] Quantum devices, including quantum devices with semiconductor heterostructures, are often sensitive to even minimal misalignment of the magnetic field with respect to the plane of the semiconductor layers. Such misalignment can create problems in the case of spin manipulation by "hopping" between quantum dots. Summary of the invention

[0011] There is a need for a quantum device to overcome all or part of the aforementioned drawbacks, in particular to address the problems of variability and sensitivity of the quantum device.

[0012] One embodiment overcomes all or part of the drawbacks of known quantum devices.

[0013] One embodiment provides for a quantum device with qubits, the quantum device comprising:

[0014] - a stack of semiconductor layers extending in an (XY) plane, the stacking including at least a first layer of a first semiconductor on a semiconductor substrate, a second layer of a second semiconductor on the first layer, and a third layer of a third semiconductor on the second layer, the second layer being adapted to confine a charge carrier, and the first and third semiconductors each having a lattice parameter different from the lattice parameter of the second semiconductor, such that the second layer has a stress (e) in the plane, the first layer further having a residual stress (er) in the plane;

[0015] - a grid structure, comprising at least one control grid, positioned at- above a first face of the stack, said grid structure being adapted to control the displacement of the load carrier confined in the second layer; and

[0016] - at least one recess extending from the first face through at least the third and second layers, said at least one recess being located at a non-zero distance (D, D') from a center of the grid structure in the (XY) plane and having a depth (T, T') such that the ratio of the distance (D, D') to the depth (T, T') is between a value strictly greater than 0 and less than or equal to 10.

[0017] According to a particular embodiment, the plane (XY) includes a first direction (X) and a second direction (Y), the at least one recess comprising at least one first recess extending in the second direction (Y) or two first recesses positioned on either side of the grid structure in the first direction (X).

[0018] According to a particular embodiment, the at least one recess further comprises at least one second recess extended in the first direction (X) or two second recesses on either side of the grid structure in the second direction (Y).

[0019] According to a particular embodiment, the at least one second recess includes at least one second trench and / or is positioned at a first edge of the stack.

[0020] According to a particular embodiment, the at least one first recess includes at least one first trench and / or is positioned at a second edge of the stack.

[0021] According to a particular embodiment, for each recess:

[0022] - the distance (D, D') is less than or equal to 2.5 pm, and for example greater than or equal to 0.5 pm; and / or

[0023] - the depth (T, T') is greater than or equal to 0.25 pm, and for example less or equal to 1 pm; and / or

[0024] - a length (W; W') of each recess is greater than or equal to the distance (D ; D').

[0025] According to a particular embodiment, the at least one recess comprises a peripheral recess extending over the entire periphery of the stack around the grid structure, said peripheral recess defining an island corresponding to a non-peripheral portion of the stack.

[0026] According to a particular embodiment, at least one first recess is located in the island.

[0027] According to a particular embodiment, at least one second recess is located in the island.

[0028] According to a particular embodiment, the peripheral recess has a single depth, for example said depth is greater than or equal to 0.25 pm, or the peripheral recess has several different depths (Tx, Tyl, Ty2), for example said depths are all greater than or equal to 0.25 pm.

[0029] According to a particular embodiment, one of the stress (e) and the residual stress (er) is a compressive stress, while the other is a tensile stress.

[0030] According to a particular embodiment:

[0031] - the semiconductor layers of the stack are epitaxial layers; and / or

[0032] - the band gap energy of the second semiconductor is less than the energy of band gap of each of the first and third semiconductors; and / or

[0033] - the first and third layers each form a potential barrier of confinement with respect to the load carrier in the second layer; and / or

[0034] - the first and third semiconductors are made of a silicon-germanium alloy and The second semiconductor is germanium.

[0035] According to a particular embodiment, said at least one recess is filled totally or partly by at least one material, preferably dielectric.

[0036] A method for implementing a quantum qubit device is also proposed, comprising at least:

[0037] - realization of a stack of semiconductor layers extending in a (XY) plane, the stacking including at least a first layer of a first semiconductor on a semiconductor substrate, a second layer of a second semiconductor on the first layer, and a third layer of a third semiconductor on the second layer, the second layer being adapted to confine a charge carrier, and the first and third semiconductors each having a lattice parameter different from the lattice parameter of the second semiconductor, such that the second layer has a constraint (e) in the plane, the first layer further having a residual constraint (er) in the plane;

[0038] - realization of a grid structure, comprising at least one control grid, positioned above a first face of the stack, said grid structure being adapted to control the movement of the load carrier confined in the second layer; and

[0039] - creation of at least one recess extending from the first face to through at least the third and second layers, said at least one recess being located at a non-zero distance (D, D') from a center of the grid structure in the (XY) plane and having a depth (T, T') such that the ratio of the distance (D, D') to the depth (T, T') is between a value strictly greater than 0 and less than or equal to 10. Brief description of the drawings

[0040] These features and advantages, as well as others, will be described in detail in the following non-limiting description of particular embodiments in relation to the accompanying figures, among which:

[0041] [Fig.1A] is a schematic three-dimensional view representing an example of a quantum device;

[0042] [Fig.1B] is a schematic cross-sectional view of the quantum device of [Fig.1A];

[0043] [Fig.2] is a schematic and partial cross-sectional view representing a quantum device according to one embodiment;

[0044] Figure 3 represents a curve giving values ​​of the stress in the first direction as a function of the elevation in the first direction relative to the center of a grid structure of a quantum device according to one embodiment; and

[0045] Fig. 4 represents curves giving values ​​of the stress and the gyromagnetic tensor in the first direction as a function respectively of the width, distance and depth of the recesses of a quantum device according to one embodiment;

[0046] [Fig.5] represents curves giving Rabi frequency values ​​as a function of the misalignment angle of a magnetic field with respect to the plane of the semiconductor layers of two quantum devices;

[0047] [Fig.6A] and [Fig.6B] are top and cross-sectional views representing a quantum device according to another embodiment;

[0048] [Fig.7A] and [Fig.7B] are top and cross-sectional views representing a quantum device according to another embodiment;

[0049] [Fig.8] is a top view representing a quantum device according to another embodiment;

[0050] [Fig.9] is a top view representing a quantum device according to another embodiment;

[0051] [Fig.1OA], [Fig.1OB] and [Fig.1OC] are top and cross-sectional views representing a quantum device according to another embodiment;

[0052] [Fig. 11 A], [Fig. 11B] and [Fig. 11C] are top and cross-sectional views representing a quantum device according to another embodiment;

[0053] [Fig.12A] and [Fig.12B] are top and cross-sectional views representing a quantum device according to another embodiment;

[0054] [Fig. 13] is a top view representing a quantum device according to another embodiment;

[0055] [Fig. 14] is a top view representing a quantum device according to another embodiment. Description of the implementation methods

[0056] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0057] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the details of the quantum structures and control grids, as well as their fabrication process, have not been detailed.

[0058] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0059] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0060] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0061] In the following description, unless otherwise specified, references to a substrate mean a semiconductor substrate, references to a region mean a semiconductor region, and references to a layer mean a semiconductor layer. Furthermore, references to a device mean, unless otherwise specified, a quantum device.

[0062] In the following description, for the semiconductor layers, a length corresponds to a dimension in a first direction of the plane of the semiconductor layers, and a width corresponds to a dimension in a second direction of this plane, orthogonal to the first direction. For the recesses or portions of recesses, a width corresponds to the smallest dimension in this plane, and a length corresponds to the largest dimension in this plane. For all elements, a thickness or a depth corresponds to a dimension in a direction perpendicular to the first and second directions. The plane corresponds to the XY plane shown in the figures. The first direction corresponds to the horizontal X direction shown in the figures. The second direction corresponds to the horizontal Y direction shown in the figures. The perpendicular direction corresponds to the vertical Z direction shown in the figures.

[0063] In a particular configuration, these directions can be aligned with the crystal directions of the semiconductors used. For example, the Z-axis can be parallel to the (001) direction, the X-axis can be parallel to the (100) direction, and the Y-axis can be parallel to the (010) direction. Alternatively, the X-axis could be parallel to the (110) direction, or the Y-axis could be parallel to the (110) direction.

[0064] Throughout the description, the term "on" is used without distinction as to the spatial orientation of the element to which the term refers. For example, In the expression or feature "on a face of a layer," this face is not necessarily oriented upwards but may correspond to a face oriented in any direction. Furthermore, the arrangement of a first element on a second element should be understood as either having the first element directly against the second element, without any intermediate element between the first and second elements, or having the first element on the second element with one or more intermediate elements arranged between the first and second elements.

[0065] Throughout the description, the term "center" of a structure does not necessarily refer to the middle of that structure, but more broadly means a point far from the edges of the structure.

[0066] Throughout this description, a recess refers to a portion hollowed out within the thickness of the stack of semiconductor layers. It can be described as a pit or a depression. A recess may be located at one or more edges of the stack. A recess may also be located at a distance from the edges of the stack, thus forming a trench.

[0067] Fig. 1A is a schematic three-dimensional view representing an example of a quantum device 100. Fig. 1B is a schematic and partial cross-sectional view of the quantum device 100 of Fig. 1A. In Fig. 1B, the quantum device 100 is represented in a cross-sectional plane XZ.

[0068] Fig. 1 A represents in particular an example of a stacking 110 of semiconductor layers formed from a substrate 102.

[0069] The substrate 102 corresponds for example to a wafer, or plate, based on Silicon (Si), Germanium (Ge), Gallium Arsenide (GaAs), or any other suitable semiconductor.

[0070] The layers of the stack 110 are epitaxial layers, that is to say, layers formed one on top of the other by stages of epitaxial growth, or epitaxy, from the substrate 102.

[0071] The stack 110 shown in [Fig.1A] comprises three semiconductor layers: - a layer 112 of a first semiconductor on the substrate 102; - a layer 114 of a second semiconductor on top of layer 112; and - a layer 116 of a third semiconductor on layer 114.

[0072] The set of these layers, i.e. the stacking 110, forms a heterostructure.

[0073] The band gap energy of the second semiconductor may be lower than those of the first and third semiconductors, for example such that the first and third layers 112 and 116 form potential confinement barriers vis- with respect to electrons or holes intended to be localized in one or more confinement regions formed in the second layer 114.

[0074] Moreover, the first and third semiconductors advantageously each have a different mesh size from the mesh size of the second semiconductor, so as to induce stresses in the second layer 114.

[0075] Thus, one or more charge carriers (electrons or holes) are intended to be confined in the second shell 114, forming one or more qubits, this second shell generally being constrained. A qubit 106 in the second shell 114 is shown in [Fig. 1B], it being understood that there may be several qubits in this second shell.

[0076] In the example shown in Figures IA and IB, the first and third semiconductors are a silicon-germanium (SiGe) alloy, and the second semiconductor is Ge. The second semiconductor layer 114 is then adapted to confine one (or more) hole spin qubit(s). Since SiGe alloys have a smaller lattice size than Ge, a compressive stress is induced in the Ge.

[0077] However, the second semiconductor layer could be adapted to confine one (or more) electron spin qubit(s); for example, the second semiconductor could be Si. According to another variant, the second layer 114 could comprise GaAs.

[0078] The thickness e2 of layer 112 is, for example, greater than or equal to one micrometer (pm), for example, a few micrometers. A significant thickness of layer 112 may be necessary in some cases to relieve stresses induced by differences in lattice size between layer 112 and substrate 102. The stoichiometric composition of layer 112 can vary during epitaxial growth in order to obtain a desired composition with a desired stress state.

[0079] The thickness e4 of layer 114 is for example between 5 and 50 nanometers (nm), or even between 5 and 20 nm, for example equal to about 10 nm.

[0080] The thickness e6 of layer 116 is for example between 10 and 100 nanometers (nm), or even between 20 and 60 nm.

[0081] A grid structure 120 comprising one or more electrically conductive control grids (“plunger gate”) is positioned above the stack 110.

[0082] In the example shown in [Fig. 1A], the grid structure 120 comprises: - a central control grid 122 which is, for example, a potential control grid for the qubit 106 to confine it under this grid, creating a quantum dot, the qubit otherwise being able to move into the second semiconductor layer 114; and - peripheral control grids 124, around the central control grid 122, which are for example tunnel barrier control grids between neighboring qubits, and which can also contribute to confining qubit 106 in the quantum dot.

[0083] The quantum device 100 may also include one or more back gates (not shown), below the substrate 102 or the semiconductor layer 112.

[0084] An insulating layer 104 is positioned between the control grids 121, 122 and the stack 110. The insulating layer 104 is, for example, made of an oxide such as silicon dioxide (SiO2) or aluminum oxide. The insulating layer 104 forms, for example, a grid oxide. The thickness e8 of the insulating layer 104 is advantageously less than or equal to 20 nm, for example, between 2 and 20 nm, for example, approximately 5 nm.

[0085] In [Fig.1B], for the sake of simplicity, the quantum device 100 has been represented without the substrate 102, and without the insulating layer 104. In addition, the scales have been modified compared to [Fig.1A], the grid structure 120 being schematically represented by a simple rectangle above the qubit 106.

[0086] Although not shown, a magnetic field generator adapted to expose qubit 106 to a homogeneous magnetic field B can operate jointly with quantum device 100.

[0087] To manipulate a spin qubit, and when the first and third semiconductors contain SiGe and the second semiconductor contains Ge, the magnetic field B is preferably oriented in a plane parallel to the XY plane of the semiconductor layers, for example to allow the application of sufficient AE energy to the qubit to make it pass from one spin state to another, according to the Zeeman effect.

[0088] Spin manipulation can exploit electronic spin resonance, or ESR, for an electron spin. Spin manipulation can advantageously exploit spin-orbit coupling in the qubit, particularly in the technique known as EDSR, from the English "Electronic Dipole Spin Resonance." Other techniques exist.

[0089] The relationship between the magnetic field B and the energy AE is defined by the following equation:

[0090] [Math.l] &E=n B \gB\

[0091] where pB is the Bohr magneton and g is the gyromagnetic tensor.

[0092] The energy AE and the magnetic field B are vectors each having components in the X, Y and Z directions, and the gyromagnetic tensor g can be expressed in the form of the following matrix:

[0093] [Math.2] M 0 o\ g = 0 S y 0 0 0 s zl

[0094] where gx, gy and gz are the components of the gyromagnetic tensor in each of the directions X, Y and Z.

[0095] In some cases, the gyromagnetic tensor is highly anisotropic, with the gz component of the gyromagnetic tensor generally being much larger than the gx and gy components. This has been observed, for example, in the case of hole qubits formed in a germanium layer. For instance, the gz component is between 10 and 14, while each gx and gy component is between 0.02 and 0.2.

[0096] Furthermore, the inventors observed that the operation of quantum devices was highly sensitive to even a minimal misalignment of the magnetic field B with respect to the XY plane of the semiconductor layers, when gz » gx and gz » gy. For example, a misalignment can lead to errors in the manipulation or reading of spin qubits, in particular difficulties in manipulating spin qubits because spin manipulation by EDSR becomes inefficient.

[0097] It has also been observed that the manipulation of spin during a movement of a charge carrier between quantum dots, "hopping", could be impacted by such misalignment.

[0098] Furthermore, it has been found that even small variations in the gx and gy components of the gyromagnetic tensor can produce large variabilities in the AE energy required to move a spin qubit from one spin state to another, when the values ​​of gx and gy are small, for example in the case of hole qubits in germanium.

[0099] There is therefore a need for a quantum device with a semiconductor heterostructure that can overcome all or part of the aforementioned drawbacks, in order to improve the performance of this quantum device, in particular to address the problems of qubit variability and sensitivity to external parameters such as misalignment of the magnetic field applied to a qubit.

[0100] In Figures 2, 6A, 6B, 7A, 7B, 8, 9, 10A, 10B, 10C, 1 IA, 1 IB, 1 IC, 12A, 12B, and as in Figures IA and IB, the quantum device comprises, on a substrate 102, a stack 210 of semiconductor layers.

[0101] The 210 stack comprises three semiconductor layers: - a first layer 212 of a first semiconductor on the substrate 102; - a second layer 214 of a second semiconductor on the 212 layer; and - a third layer 216 of a third semiconductor on layer 214.

[0102] The set of these layers, i.e. the stack 210, forms a heterostructure. Layer 212 is arranged between substrate 202 and layer 214, and layer 214 is arranged between layer 212 and layer 216. In the examples shown, the top face 210A (first face) of the stack 210 corresponds to the top face of layer 216.

[0103] The thicknesses of these layers may be similar to those of layers 112, 114, 116 described in connection with [Fig.1A].

[0104] The band gap energy of the second semiconductor is advantageously lower than those of the first and third semiconductors, for example such that the first and third layers 212 and 216 form potential confinement barriers with respect to electrons or holes intended to be localized in the second layer 214.

[0105] Moreover, the first and third semiconductors advantageously each have a different mesh size from the mesh size of the second semiconductor, so as to induce stresses in the second layer 214.

[0106] One or more charge carriers (electrons or holes) are intended to be confined in the second semiconductor layer 214, forming one or more qubits, this second semiconductor layer being constrained.

[0107] In Figures 2, 6A, 6B, 7A, 7B, 8, 9, 10A, 10B, 10C, 1IA, 1IB, 1IC, 12A, 12B, and as in [Fig. 1B], for the sake of simplicity, the quantum device is shown without the substrate 102 (except in [Fig. 2]), and without the insulating layer 104, and the grid structure 120 is schematically represented by a simple rectangle above the qubit (not shown). The grid structure 120 comprises one or more qubit control grids.

[0108] The grid structure 120 is positioned around a center C of this grid structure. The center C is defined in the XY plane of the stack 210.

[0109] The assembly formed by the grid structure 120 and the portion 214A (identified in [Fig. 2] by a double arrow) of the second layer 214 located beneath this grid structure forms a quantum structure. The center C of the grid structure can thus correspond to the center of the quantum structure.

[0110] In Figures 2, 6A, 6B, 7A, 7B, 8, 9, 10A, 10B, 10C, 11A, 11B, IC1, 12A, 12B, the second semiconductor is considered to be Ge, and the first and third semiconductors are a SiGe alloy, with, for example, a proportion of 80% germanium and 20% silicon. The second semiconductor layer is then adapted to confine one (or more) hole spin qubit(s). However, the embodiments can be applied to a second semiconductor layer adapted to confine an electron spin qubit, for example, made of Si, and more generally to any heterostructure in which a semiconductor layer is adapted to confining one (or more) charge-carrying qubit(s), that is, one (or more) spin (or charge) qubit(s) of electrons (or holes).

[0111] Advantageously, the first and third SiGe semiconductors have the same material identity, i.e., the same percentages of Si and Ge in the alloy. This allows for substantially the same stresses in the first and third layers.

[0112] Since SiGe alloys have a smaller mesh size than Ge, a compressive stress is induced in the second Ge layer 214. Furthermore, the first SiGe layer 212 exhibits a residual tensile stress due to the silicon used in the substrate 102.

[0113] The constraints indicated in the first and second layers of the stack are in the XY plane of this stack, that is to say the plane of the semiconductor layers s.

[0114] Beyond the combinations of semiconductor materials indicated above, the embodiments can be applied generally to any type of heterostructure obtained by stacking several layers of semiconductors, with at least two different semiconductor materials.

[0115] The [Fig.2] is a schematic and partial cross-sectional view representing a quantum device 200 according to one embodiment.

[0116] The quantum device 200 of [Fig.2] includes common elements with the quantum device 100 of Figures 1A and 1B. These common elements will not be described again below.

[0117] The quantum device 200 of [Fig.2] differs from the quantum device 100 of Figures IA and IB in that it comprises two recesses 222 and 224 which extend in the stack 210 from the first face 210A (top face) of this stack to a depth in the first layer 212, i.e. through the third layer 216 and the second layer 214, and partially into the first layer 212, the depth in the stack 210 being designated by the reference T.

[0118] Each recess 222, 224 is at a non-zero distance from the grid structure 120. Each recess 222, 224 is at a distance D from the center C of the grid structure 120. Furthermore, each recess 222, 224 has a width L in the X direction and a length W in the Y direction (visible in Figures 6A, 7A, 8, 9, 12A). In the realized structure, these dimensions are such that W ≈ 2D.

[0119] In the example of [Fig. 2], the recesses 222 and 224 are positioned on either side of the grid structure 120, and furthermore, they are substantially equidistant D from the center C, and they have substantially the same width L, the same length W, and the same depth T. This is not limiting and two recesses may not have the same values ​​of distance D, width L, length W and / or depth T.

[0120] The first layer 212 exhibits a residual stress er in tension. For example, the erxx component of the residual stress is approximately 0.26% in the X direction, and the residual component eryy of the stress is approximately 0.26% in the Y direction. The values ​​of these components may, however, vary and be dependent on the growth conditions. The recesses 222, 224 thus introduced deep into the first layer 212 allow at least partial release of the residual stress erx x in the X direction, as indicated by the arrows S in [Fig.2], which increases the compressive stress £xx of the second layer 214 in the X direction. On the other hand, the compressive stress eyy of the second layer 214 in the Y direction is not, or only slightly, impacted by the recesses 222, 224, which creates an asymmetry of the stress ede of the second layer 214 between the first X direction and the second Y direction.

[0121] For example, the compressive stress exx in the X direction was -0.6% in device 100 of Figures IA and IB (without recesses), and it becomes less than -0.6% in device 200 of [Fig. 2] (with recesses), i.e., the second layer 214 has a compressive stress exx in the X direction that is higher (in absolute value) than that of Figures IA and IB. The compressive stress eyy in the Y direction can remain substantially equal to -0.6%.

[0122] In this example, a residual tensile stress in the first layer 212 and a compressive stress in the second layer 214 were considered, but depending on the semiconductors of these layers, this can be reversed. Thus, a residual compressive stress in the first layer 212 and a tensile stress in the second layer 214 could be considered.

[0123] Figure 3 represents a curve 300 giving values ​​of the stress exx of the second layer 214 in the first direction X as a function of the elevation in this first direction relative to the center C of a grid structure of a quantum device according to one embodiment. The quantum device considered corresponds to the quantum device 200 of Figure 2, with D equal to approximately 2.5 pm, T equal to approximately 0.5 pm, and L equal to approximately 1000 pm.

[0124] It can be observed that even at the center C of the grid structure 120, due to the presence of the recesses 222, 224, the exx stress of the second layer 214 in the first direction X has increased in absolute value, since it is approximately -0.673% instead of -0.6% without the recesses, this absolute value of the exx stress increasing further as one moves away from the center C. The increase in value absolute stress exx reaches its maximum point near each of the recesses 222, 224, since it is equal to approximately -0.692%.

[0125] The inventors have determined that this asymmetry between the exx and eyy stresses of the second layer 214, obtained in this example by increasing the exx component, makes it possible to increase the gx and gy components of the gyromagnetic tensor in the XY plane, and in particular to reduce the ratio between the gz component and the gx component and between the gz component and the gy component. Each of the gx and gy components of the gyromagnetic tensor can thus reach values ​​between 0.5 and 1.5, which constitutes a significant increase (for example, between 5 and 7 times) compared with the values ​​indicated earlier, between 0.02 and 0.2. Alternatively, the eyy component could be increased instead of the exx component, for substantially the same results on the gyromagnetic tensor.

[0126] The exx component, and thus the gx and gy components can vary in particular according to the values ​​of width L, distance D and depth T, as described in [Fig.4] described below.

[0127] Figure 4 shows curves giving values ​​of the stress exx and the gyromagnetic tensor gxx in the first direction X as a function, respectively, of the width L, the distance D and the depth T of the recesses of a quantum device according to one embodiment. The quantum device considered corresponds to the quantum device 200 of Figure 2.

[0128] Curve 411 plots the values ​​of the exx component of the stress as a function of the width L. Curve 421 plots the values ​​of the gxx component of the gyromagnetic tensor as a function of the width L. Curve 412 plots the values ​​of the exx component of the stress as a function of the distance D. Curve 422 plots the values ​​of the gxx component of the gyromagnetic tensor as a function of the distance D. Curve 413 plots the values ​​of the exx component of the stress as a function of the depth T. Curve 423 plots the values ​​of the gxx component of the gyromagnetic tensor as a function of the depth T.

[0129] It appears from these curves that the width L has only a small influence on exx and gxx, whereas the distance D and the depth T have a significant impact on exx and gxx. More precisely, exx and gxx decrease with distance D but increase with depth T. Furthermore, W » D.

[0130] For example, the distance D can advantageously be less than 3 pm, or even less than 2.5 pm. For example, the depth T can be greater than or equal to 250 nm, or even greater than 500 nm. As for the width L, given that it has little impact, it can be chosen according to the space remaining in the stack 210. The width L is, of course, strictly greater than zero to form a recess. Furthermore, it is possible to have the D / T ratio which is less than or equal to 5. More generally, the D / T ratio can have a value strictly greater than 0 and less than or equal to 10, and for example between (inclusive limits) 0.5 and 10 to release the constraint in the active layer in which the charge carrier(s) are confined.

[0131] The inventors also found that increasing the gx and gy components makes the quantum devices less sensitive to misalignment of the magnetic field with respect to the XY plane of the semiconductor layers when the spin is manipulated by EDSR. This is explained with [Fig. 5] described below.

[0132] Fig. 5 represents curves giving Rabi frequency values ​​fR as a function of the misalignment angle 0 (deg) of a magnetic field with respect to the axis perpendicular to the plane of the semiconductor layers of two quantum devices.

[0133] The curves shown correspond to simulation results performed to compare a quantum device according to one embodiment with a prior art quantum device. Curve 501 (No Trench) corresponds to the prior art quantum device, without a trench, and curve 502 (Optimal Trench) corresponds to the quantum device according to the embodiment. The two quantum devices are comparable, apart from the trenches in the quantum device according to the embodiment, which corresponds to quantum device 200 of [Fig. 2], with D equal to approximately 2 pm, T equal to approximately 1 pm, and L equal to approximately 1000 pm.

[0134] The Rabi frequency is defined as the oscillation frequency of a two-energy-level system in an oscillating electromagnetic field at a frequency close to the system's resonance. In the example shown, the Rabi frequency represents the qubit's operating speed.

[0135] It can be seen in [Fig.5] that curves 501 and 502 are in the form of peaks, with a wider peak for curve 502 than for curve 501, reflecting the fact that the presence of indentations makes it possible to reduce the loss of operating speed during a misalignment problem, thus making quantum devices less sensitive to a misalignment of the magnetic field with respect to the plane of the semiconductor layers s.

[0136] The inventors have also determined that increasing the gx and gy components minimizes the loss of efficiency of spin manipulation using "hopping" in case of misalignment of the magnetic field with respect to the XY plane of the semiconductor layers.

[0137] In addition, the inventors have determined that increasing the components gx and gy reduces the variability in the AE energy required to move a spin qubit from one spin state to another.

[0138] In [Fig. 2], the recesses are shown as each being along an edge of the stack 210, in this example a lateral edge 210C (second edge), that is, an edge extending in the Y direction. Other recess configurations are possible. The following figures show other, non-limiting, examples of recess configurations in the stack 210. For example, as described later, the recesses may not be on edges of the stack, and may form trenches.

[0139] Fig. 6A and Fig. 6B are top and cross-sectional views representing a quantum device 600 according to another embodiment.

[0140] The device 600 of Figures 6A and 6B differs from the device 200 of [Fig. 2] in that it comprises only one recess 622 and that this recess is not positioned along a lateral edge 210C of the stack 210. In other words, a non-zero distance separates the lateral edge 210C from the recess 622, forming a trench (first trench). Thus, the sum of the distance D and the width L of the trench 622 is less than half the length LS of the stack 210.

[0141] The trench 622 extends in the Y direction and is also at a distance from the longitudinal edge 210D (first edge) of the stack 210, i.e. the edges that extend in the X direction. Thus, in the example of Figures 6A and 6B, the length W of the trench 622 is less than the width WS of the stack 210. Alternatively, the trench 622 could reach the longitudinal edges 210D of the stack 210, i.e. the length W of the trench could be equal to the width WS of the stack 210.

[0142] Fig. 7A and Fig. 7B are top and cross-sectional views representing a quantum device 700 according to another embodiment.

[0143] The device 700 of Figures 7A and 7B differs from the device 200 of [Fig. 2] in that the recesses 622 and 624 are not positioned along a lateral edge 210C of the stack 210. In other words, a non-zero distance separates each of the recesses 622 and 624 from each lateral edge 210C, forming trenches (first trenches). Each trench 622, 624 extends in the Y direction and is also at a distance from the longitudinal edges 210D of the stack 210. The trench 622 is similar to the trench described in connection with Figures 6A and 6B. Furthermore, in the example shown, trench 624 is similar to trench 622. In other words, device 700 in figures 7A and 7B differs from device 600 in figures 6A and 6B in that it includes another trench 624 similar to trench 622.

[0144] This embodiment is advantageous in that having two elongated trenches in the Y direction on either side of the grid structure 120 allows the residual X-axis stress erxx of the first layer 212 to be released more, and thus the X-axis stress exx of the second layer 214 to be increased more, compared to a single elongated trench in the Y direction, thus further increasing the gx and gy components of the gyromagnetic tensor in the XY plane.

[0145] As with the recesses 222 and 224 of [Fig.2], the trenches 622 and 624 are positioned on either side of the grid structure 120, approximately equidistant D from the center C. In the example shown, the trenches 622 and 624 have approximately the same width L, the same length W and the same depth T. This is not limiting, and these trenches may have different values ​​of distance D, width L, length W and / or depth T.

[0146] The inventors have determined that, for a distance D of 2 pm, a depth T of 1 pm, components gx and gy of the gyromagnetic tensor can be obtained equal to approximately 1.2, while the component gz is equal to approximately 14.5.

[0147] Fig. 8 is a top view representing a quantum device 800 according to another embodiment.

[0148] The device 800 of [Fig. 8] differs from the device 700 of Figures 7A and 7B in that it includes another trench 623 (second trench) which also extends into the stack 210 from the first face 210A down into the first layer 212. The trench 623 has a length W' in the X direction and a width L' in the Y direction. Since, by convention, the width L' of a trench is less than the length W', the trench 623 is therefore elongated in the X direction. The trench 623 is at a non-zero distance from the grid structure 120, and at a distance D' from the center C of the grid structure 120.

[0149] Trench 623 is at a non-zero distance from the longitudinal edges 210D of the stack 210. Thus, the sum of the distance D' and the width L' of trench 623 is less than half the width WS of the stack 210. Trench 623 is also at a distance from the lateral edges 210C of the stack 210. Thus, in the example of [Fig. 8], the length W' of trench 623 is less than the length LS of the stack 210. Alternatively, trench 623 could reach the lateral edges 210C of the stack 210, i.e., the length W' of trench 623 could be equal to the length LS of the stack 210.

[0150] Fig. 9 is a top view representing a quantum device 900 according to another embodiment.

[0151] Device 900 of [Fig.9] differs from device 800 of [Fig.8] in that it includes another trench 625 (second trench), which is preferably similar to trench 623.

[0152] Trenches 623 and 625 (second trenches) are positioned on either side of the grid structure 120, approximately equidistant D' from the center C of the grid structure 120. In the example shown, trenches 623 and 625 have approximately the same width L', the same length W', and the same depth T' (shown in parentheses in Figures 8 and 9). This is not a limitation, and trenches 623 and 625 may have different values ​​for distance D', width L', length W', and / or depth T'.

[0153] In the example shown, trenches 623 and 625 (second trenches) are similar to trenches 622 and 624 (first trenches), except that they are rotated 90°. This is not a limiting factor, and all these trenches may have different values ​​of distance D, D', length W, W', length L, L' and / or depth T, T'. Furthermore, the cross-sections of these trenches may be rectangular or any other shape.

[0154] An advantage of having three or four trenches on either side of the grid structure 120, of which at least one is elongated in the Y direction and at least one is elongated in the X direction, is that this can allow differentiated action on the release of the residual stress erxx in X and the residual stress eryy in Y in the first layer 212, and thus differentiated action on the stress exx in X and the stress eyy in Y in the second layer 214, for example by differentiated action on the values ​​of distance D', width L', length W' and / or depth T' of the trenches elongated in X, and / or on the values ​​of distance D, width L, length W and / or depth T of the trenches elongated in Y.

[0155] Indeed, in certain applications, such as spin qubit manipulation applications exploiting tunnel magnetoresistance (g-TMR, from the English "g-Tensor Modulation Resonance"), in particular exploiting spin-orbit coupling (SOC, from the English Spin Orbit Coupling), it may be interesting to play on the two components exx and eyy in the XY plane of the constraint e and / or to play on the value of the sum of these two components to control the intensity of the spin-orbit coupling.

[0156] In the embodiments described in connection with Figures 6A to 9: - the distance D, D' of each trench is advantageously less than or equal to 2.5 pm; for example, the distance D, D' is between 500 nm and 2.5 pm, inclusive of markers; - the depth T, T' of each trench is advantageously greater than or equal to 250 nm; for example, the depth T, T' is between 250 nm and 1 pm, inclusive; - the width L, L' of each trench, knowing that it has little impact, is greater than zero and can be increased, within the limit of the space in the stack of 210 semiconductor layers.

[0157] The length W of each elongated trench in Y is less than or equal to the width WS of the stack 210. The length W' of each elongated trench in X is less than or equal to the length LS of the stack 210.

[0158] When the lengths W of the trenches 622 and 624 extended in the Y direction are each equal to the width WS of the stack 210, and the lengths W' of the trenches 623 and 625 extended in the X direction are each equal to the length LS of the stack 210, a continuous trench can be obtained around the grid structure 120.

[0159] When the elongated recesses in the Y direction are positioned along the lateral edges 210C of the stack 210 and the length W is equal to the width WS of the stack 210, and the elongated recesses in the X direction are positioned along the longitudinal edges 210D of the stack 210, and the length W' is equal to the length LS of the stack 210, a continuous recess can be obtained which extends over the entire periphery of the stack 210, around the grid structure 120. This can be referred to as a peripheral recess. This peripheral recess defines, and frames, an island corresponding to a non-peripheral portion of the stack 210. The grid structure 120 is positioned above this island, and the portion of the second layer 214 positioned below the grid structure 120 is included in this island.Figures 10A, 10B, 11A and 11B described below illustrate non-limiting examples of peripheral recesses around an island.

[0160] Fig.1OA, Fig.1OB and Fig.1OC are top and cross-sectional views representing a quantum device 1000 according to another embodiment.

[0161] The quantum device 1000 of Figures 10A to 10C differs from the quantum device 100 of Figures IA and IB in that it includes a peripheral indentation 1020 around the entire periphery of the stack 210, all around the grid structure 120. As with the indentations and trenches described previously, this peripheral indentation 1020 extends into the stack 210 from the first face 210A (top face) of this stack down into the first layer 212, that is, through the third layer 216 and the second layer 214, and partially into the first layer 212. The peripheral indentation 1020 defines an island 1010, which in this example is centered with respect to the stack 210.

[0162] The peripheral recess 1020 comprises portions 1022 (first portions) extending in the Y direction and portions 1023 (second portions) extending in the X direction. The depth of the peripheral recess 1020 in the stack 210 is designated by the reference numeral Tx in the portions 1022 and by the reference numeral Ty in the portions 1023. The values ​​of Tx and Ty may or may not be identical on each side of the symmetry axes of the island. The peripheral recess 1020 is at a non-zero distance from the grid structure 120, which is positioned on the island 1010. The distance D between the peripheral recess 1020 and the center C of the grid structure 120 is designated by the reference numeral Dx for the portions 1022 and by the reference numeral Dy for the portions 1023.

[0163] In the example of Figures 10A to 10C, a rectangular island 1010 is shown with one side longer than the other, for example with a distance Dx greater than the distance Dy. For example, Dx and Dy can be equal to a few micrometers, for example less than 5 pm or between 3 and 5 pm.

[0164] Alternatively, the island can have a more pronounced rectangular shape, with a distance Dx much greater than the distance Dy. For example, Dx could be a few micrometers, or even less than 5 pm, and Dy could be less than 2.5 pm, or conversely, Dy could be a few micrometers, or even less than 5 pm, and Dx could be less than 2.5 pm. The inventors have determined that, in this variant, the eyy component of the compressive stress e in the second layer 214 could be made much less than -0.6%. Similarly, the absolute value of the exx component of the compressive stress e in the second layer 214 could be made much less than -0.6% with a distance Dy much greater than the distance Dx.

[0165] In the example of Figures 10A to 10C, the portions 1022 are at substantially the same distance Dx from the center C, the portions 1023 are at substantially the same distance Dy from the center C, and the island 1010 is thus substantially centered with respect to the stack 210. Furthermore, in the example of Figures 10A to 10C, the portions 1022 and 1023 all have substantially the same depth, that is, Tx is substantially equal to Ty. This example is not limiting, and other configurations can be considered by those skilled in the art. For example, the island may not be centered, the first portions may not necessarily all have the same depths, the second portions may not necessarily all have the same depths, and / or the first and second portions may not necessarily have the same depths.

[0166] Fig. 11 A, Fig. 1 IB and Fig. 1 IC are top and cross-sectional views representing a quantum device 1100 according to another embodiment.

[0167] On the one hand, Figures 1 IA to 1 IC illustrate the variant described above in which the distance Dx is much greater than the distance Dy.

[0168] On the other hand, device 1100 of Figures 1 IA to 1 IC differs from device 1000 of Figures 10A to 10C in that the island 1110 is off-center with respect to the center C of the grid structure 120 in the Y direction. The peripheral recess 1120 comprises portions 1122 (first portions) extending in the Y direction and portions 1123, 1125 (second portions) extending in the X direction. The off-centering arises from the fact that portion 1123 is closer to the center C than portion 1125. In other words, the distance Dy1 between portion 1123 and the center C is greater than the distance Dy2 between portion 1125 and the center C. In other words, portion 1125 is wider than portion 1123.

[0169] Furthermore, the depths Ty 1 and Ty2 of the two portions 1123 and 1125 are different. In the example shown, the depth Ty 1 of portion 1123 is greater than the depth Ty2 of portion 1125, but it could be the other way around.

[0170] The inventors have determined that, for the embodiment of Figures 1 IA to 1 IC, with Dx greater than 10 pm, and Dy2 less than 2.5 pm, the eyy component of the stress e in the second layer 214 decreases, for example is made much less than -0.6%, while the exx component of the stress e is maintained at about -0.6%.

[0171] In the example of Figures 1 IA to 1 IC, the portions 1122 extended in the Y direction are similar, i.e., the distance Dx is substantially identical for both portions 1122, as is the depth Tx. Alternatively, the island 1110 could be offset from the center C of the grid structure 120 in the X direction, either in addition to or instead of the offset in the Y direction. Alternatively, the depth Tx could be different between the two portions 1122. The component eyy of the stress e could thus also be affected.

[0172] In embodiments of Figures 10A to 1 IC: - the depths Tx, Ty, Tyl, Ty2 of the portions of the peripheral recess are preferably greater than or equal to 250 nm; - the distances Dx, Dy, Dyl, Dy2 of the portions of the peripheral recess relative to the center C are preferably less than or equal to 5 pm.

[0173] Fig. 12A and Fig. 12B are top and cross-sectional views representing a quantum device according to another embodiment.

[0174] Device 1200 of Figures 12A and 12B differs from device 1000 of Figures 10A to 10C in that it further comprises, in addition to the peripheral recess 1020, a trench 1222 in the block 1010.

[0175] Figures 12A and 12B show a single trench 1222 extending in the Y direction with a width W equal to the width WM of block 1010, but the width W may be less than the width WM of block 1010 in other embodiments. Other variations may be considered by a person skilled in the art. In particular, an off-center island can be used, as described in connection with Figures 11A to 1 IC. Specifically, the embodiments of Figures 10A to 10C or Figures 11A to 1 IC can be combined with each of the embodiments of Figures 6A to 9, i.e., one or more trenches can be provided in the X and / or Y direction within the island 1010 formed in the stack 210. The examples of distance D, depth T, width L, and length W described in connection with Figures 6A to 9 can be applied to one or more trenches within an island, bearing in mind that the length LM and width WM of the island are then considered rather than the length LS and width WS of the stack.

[0176] The inventors have determined that, for the embodiment shown in Figures 12A and 12B, the exx component of the stress e in the second layer 214 decreases, for example, is well below -0.6%, while the exx component of the stress e is maintained at approximately -0.6%. The eyy component is also less than -0.6% when Dy is less than 3 pm, with however eyy > exx.

[0177] The examples in Figures 2, 6A to 12B show that one can act on several parameters, such as the number of indentations, the type of indentations (trench(s), indentation(s) at the edge of the stack, peripheral indentation), the depths of the indentations or portions of indentations, the distances of the indentations or portions of indentations from the center of the grid structure, and even, to a lesser extent, the widths and lengths of the indentations, and that one can vary these parameters according to the indentations or portions of indentations, in order to act on the exx component and / or the eyy component of the stress e in the second layer 214, and thus have a positive impact in terms of variability (to decrease it), of the sensitivity of the quantum device to the misalignment of the magnetic field (to decrease it), more generally to improve the performance of the quantum device.

[0178] Recesses can be formed by standard trenching processes in semiconductor layers. An example of such a process for creating recesses is described here by way of non-limiting illustration, the process comprising: - the optional deposition of a thin protective layer, for example a SiO2 layer with a thickness between 2 and 5 nm, on the top face of the stack of semiconductor layers; - the formation by lithography of an etching mask on the upper face of the stack of semiconductor layers, possibly covered with the thin protective layer, the etching mask comprising openings whose patterns correspond to the shapes in the plane of the stack, and indentations to be formed; - the etching of the semiconductor layer stack, starting from the top surface and through the etching mask, deep into the first layer; then - the removal of the engraving mask.

[0179] To form indentations at the edge of the stack, the openings of the engraving mask are positioned at the edge of the stack.

[0180] In the case of a peripheral recess, the removal of the engraving mask can be followed by a Pilot planarization step.

[0181] In particular, two examples of methods for making a peripheral recess are described below.

[0182] A first example of an embodiment method consists of creating the peripheral recess at the end of the so-called "front end of line" (FEOL) process, i.e., the process of manufacturing the electronic components in the semiconductor layers, and before the process of forming the interconnect structure, known as the "back end of line" (BEOL) process. The BEOL process can be adapted, in particular the thickness of the PMD (Pre-Metal Dielectric) dielectric layer, to allow the recess to be filled with PMD.

[0183] A second example of an embodiment method consists of making the peripheral recess before the FEOL process, the peripheral recess being able to be filled afterwards with a material which is not necessarily PMD.

[0184] Figure 13 is a top view of a quantum device according to another embodiment. This embodiment corresponds to that of Figures 7A and 7B, with the addition of interconnection tracks 1300 connected to the gate structure 120. Figure 13 shows that the presence of recesses does not prevent the interconnection of the control gates, as the tracks can bypass the recess(es). When the recess(es) are filled with a dielectric material, the contacts can pass over the recess(es).

[0185] Fig. 14 is a top view representing a quantum device 1400 according to another embodiment.

[0186] This quantum device 1400 comprises several quantum structures (represented by several grid structures 120) linked by long-distance qubit couplers 1402, with indentations 1420 between the qubits which may be similar to one or the other of the indentations described previously.

[0187] In the various embodiments described above, the heterostructures are formed by the first, second, and third semiconductor layers. Alternatively, the heterostructure(s) may comprise more than three semiconductor layers. In all possible configurations, the recess(es) are formed through at least the layer adapted for confinement. of the load carrier(s) as well as the layers resting on this containment layer.

[0188] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, the recess(s) can be filled, for example, with a dielectric material, for example SiO2 or Al2O3, the filling being carried out after stress relaxation in the first layer.

[0189] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Quantum device (200; 600; 700; 800; 900; 1000; 1100; 1200; 1400) with qubits, the quantum device comprising: - a stack (210) of semiconductor layers extending in a plane (XY), the stack including at least a first layer (212) of a first semiconductor on a semiconductor substrate (102), a second layer (214) of a second semiconductor on the first layer (212), and a third layer (216) of a third semiconductor on the second layer (214), the second layer being adapted to confine a charge carrier, and the first and third semiconductors each having a lattice parameter different from the lattice parameter of the second semiconductor, such that the second layer has a constraint (e) in the plane, the first layer further having a residual constraint (er) in the plane;- a grid structure (120), comprising at least one control grid, positioned above a first face (210A) of the stack, said grid structure being adapted to control the displacement of the load carrier confined in the second layer; and - at least one recess (221, 222; 621, 622, 623, 624; 1020; 1120; 1222) extending from the first face (210A) through at least the third and second layers, said at least one recess being located at a non-zero distance (D, D') from a center of the grid structure (120) in the (XY) plane and having a depth (T, T') such that the ratio of the distance (D, D') to the depth (T, T') is between a value strictly greater than 0 and less than or equal to 10.

2. Quantum device (200; 600; 700; 800; 900; 1200) according to claim 1, wherein the plane (XY) includes a first direction (X) and a second direction (Y), the at least one recess comprising at least one first recess (221, 222; 621, 622; 1222) extended in the second direction (Y) or two first recesses (221, 222; 621, 622) positioned on either side of the grid structure (120) in the first direction (X).

3. Quantum device (800; 900) according to claim 2, wherein the at least one recess further comprises at least one second recess (623, 625) extended in the first direction (X) or two second recesses (623, 625) on either side of the grid structure (120) in the second direction (Y).

4. Quantum device (800; 900) according to claim 3, wherein at least one second indentation (623, 625) includes at least one second trench and / or is positioned in a first edge (210D) of the stack (210).

5. Quantum device (600; 700; 800; 900) according to any one of claims 2 to 4, wherein at least one first indentation (621, 622) includes at least one first trench and / or is positioned in a second edge (210C) of the stack (210).

6. Quantum device according to any one of the preceding claims, wherein, for each indentation: - the distance (D, D') is less than or equal to 2.5 pm, and for example greater than or equal to 0.5 pm; and / or - the depth (T, T') is greater than or equal to 0.25 pm, and for example less than or equal to 1 pm; and / or - a length (W; W') of each indentation is greater than or equal to the distance (D; D').

7. Quantum device (1000; 1100; 1200) according to any one of the preceding claims, wherein the at least one indentation comprises a peripheral indentation (1020; 1120) extending over the entire periphery of the stack (210) around the grid structure (120), said peripheral indentation defining an island (1010; 1110) corresponding to a non-peripheral portion of the stack (210).

8. Quantum device (1200) according to claim 7 in its dependence on any one of claims 2 to 5, wherein at least one first indentation (1222) is located in the island (1010).

9. Quantum device according to claim 7 or 8 in its dependence on any one of claims 3 or 4, wherein at least a second recess is located in the island.

10. Quantum device (1000; 1200) according to any one of claims 7 to 9, wherein the peripheral recess (1020) has a single depth, for example said depth is greater than or equal to 0.25 pm, or wherein the recess peripheral (1120) has several different depths (Tx, Tyl, Ty2), for example said depths are all greater than or equal to 0.25 pm.

11. Quantum device according to any one of claims 7 to 10, wherein one of the stress (e) and the residual stress (er) is a compressive stress, while the other is a tensile stress.

12. Quantum device according to any one of claims 7 to 11, wherein: - the semiconductor layers of the stack (210) are epitaxial layers; and / or - the band gap energy of the second semiconductor is less than the band gap energy of each of the first and third semiconductors; and / or - the first and third layers each form a confinement potential barrier with respect to the charge carrier in the second layer; and / or - the first and third semiconductors are made of a silicon-germanium alloy and the second semiconductor is germanium.

13. Quantum device (200; 600; 700; 800; 900; 1000; 1100; 1200; 1400) according to any one of the preceding claims, wherein said at least one recess (221, 222; 621, 622, 623, 624; 1020; 1120; 1222) is filled by at least one dielectric material.

14. A method for realizing a quantum device (200; 600; 700; 800; 900; 1000; 1200; 1400) with qubits, comprising at least: - realization of a stack (210) of semiconductor layers extending in an (XY) plane, the stack including at least a first layer (212) of a first semiconductor on a semiconductor substrate (102), a second layer (214) of a second semiconductor on the first layer (212), and a third layer (216) of a third semiconductor on the second layer (214), the second layer being adapted to confine a charge carrier, and the first and third semiconductors each having a parameter of lattice different from the lattice parameter of the second semiconductor, so that the second layer has a stress (e) in the plane, the first layer also having a residual stress (er) in the plane; realization of a grid structure (120), comprising at least one control grid, positioned above a first face (210A) of the stack, said grid structure being adapted to control the displacement of the load carrier confined in the second layer; and realization of at least one recess (221, 222; 621, 622, 623, 624; 1020; 1120; 1222) extending from the first face (21 OA) through at least the third and second layers, said at least one recess being located at a non-zero distance (D, D') from a center of the grid structure (120) in the (XY) plane and having a depth (T, T') such that the ratio of the distance (D, D') to the depth (T, T') is between a value strictly greater than 0 and less than or equal to 10.

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