Frequency divider

Abstract

Frequency Divider This description relates to a frequency divider (300), comprising at least two flip-flops (302, 304) and in which a pull-up current (Itail) of each flip-flop is controlled by a reference current (IDAC). Figure for the abbreviation: Fig. 3

Description

Title of the invention: Frequency divider technical field

[0001] The present description relates in general to frequency dividers and their operating methods. Previous technique

[0002] Frequency dividers are used in many radio frequency devices, for example in radio frequency receiving chains or for data transfer. In radio frequency receiving chains, frequency dividers are used, for example, to bring a local oscillator operating in the GHz range closer to a crystal oscillator operating in the MHz range. Frequency dividers can also be used to generate the phase shift required for quadrature modulation.

[0003] Current frequency dividers are limited, particularly with regard to the adjustment of the amplitude and frequency ranges within which they can operate. Their power consumption is also high. Summary of the invention

[0004] There is a need to provide a frequency divider whose amplitude and frequency ranges are improved while limiting their power consumption.

[0005] One embodiment overcomes all or part of the disadvantages of known frequency dividers.

[0006] One embodiment provides a frequency divider, comprising at least two flip-flops and in which a pull-up current of each flip-flop is controlled by a reference current.

[0007] One embodiment provides a method of operating a frequency divider comprising at least two flip-flops, the method comprising controlling a pull-up current of each flip-flop to a reference current.

[0008] According to one embodiment, the flip-flops are in series and each flip-flop includes: - a first node, common to both flip-flops, for applying a first clock signal; - a second node, common to both flip-flops, for applying a second clock signal different from the first clock signal; and - a first pull-up transistor whose control node is connected to the first node.

[0009] According to one embodiment, the frequency divider includes a control loop comprising a reference current application node connected to the second node.

[0010] According to one embodiment, the control loop comprises a differential amplifier of which: - a first input is connected to a first application terminal of a first reference voltage via a first resistor; - a second input is connected to a first conduction node of the first transistor of each flip-flop, said first conduction node of the first transistor being connected to the first terminal via a pull-up resistor; and - an output is connected to a control node of the first transistor.

[0011] According to one embodiment, the output of the amplifier is connected to the control node of the first transistor via a second resistor.

[0012] According to one embodiment, the control loop includes at least one current mirror, connected to the amplifier, and configured to copy the reference current.

[0013] According to one embodiment, said at least one current mirror is configured to copy the reference current and supply the amplifier with the copied current.

[0014] According to one embodiment, the flip-flops each comprise: - a first branch having a second and a third transistor in series between a second terminal for applying a second reference voltage and a second conduction node of the first transistor; and - a second branch having a fourth and a fifth transistors in series between said second terminal and the second node; a control node of the second transistor being connected to a midpoint of the fourth and fifth transistors, and a control node of the fourth transistor being connected to a midpoint of the second and third transistors.

[0015] According to one embodiment, the flip-flops each comprise: a sixth transistor connecting the second terminal and the midpoint of the second and third transistors; and a seventh transistor connecting the second terminal and the midpoint of the fourth and fifth transistors; the second node being connected to a control node of the sixth and seventh transistors.

[0016] According to one embodiment, the reference current application node is connected to the second node of each of the flip-flops via a third resistor.

[0017] According to one embodiment: - a control node of the third transistor of a first flip-flop of the frequency divider is connected to the midpoint of the fourth and fifth transistors of a second flip-flop (304) of the frequency divider; and - a control node of the fifth transistor of the first flip-flop is connected to the midpoint of the second and third transistors of the second flip-flop.

[0018] According to one embodiment, the first reference voltage is ground and the second reference voltage is VDD.

[0019] According to one embodiment, the reference current is derived from a digital-to-analog converter.

[0020] One embodiment provides, a radio frequency device comprising a receiving or transmitting chain including a frequency divider as described above. Brief description of the drawings

[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0022] [Fig.1] represents an example of a frequency divider;

[0023] [Fig.2] represents a circuit of the frequency divider of [Fig.1];

[0024] [Fig.3] represents a frequency divider according to one embodiment;

[0025] [Fig. 4] represents a frequency divider circuit of [Fig. 3] according to a mode of implementation; and

[0026] [Fig.5] represents an operating chronograph of the frequency divider of [Fig.3]. Description of the implementation methods

[0027] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0029] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0030] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0032] In the text, the term radio frequency refers to a frequency range between 1 and 120 GHz.

[0033] Fig. 1 represents an example of a frequency divider 100.

[0034] In the example shown, the frequency divider 100 comprises two flip-flops 102 and 104 in series. In other words, the outputs Q_P and Q_M of flip-flop 102 are connected, preferably connected, to the inputs D_P and D_M of flip-flop 104. Flip-flops are asynchronous circuits that store a bit of information, i.e., a memory location, and retain its value until it is updated by new input signals.

[0035] In the example shown, flip-flops 102 and 104 are identical or similar, except for manufacturing differences. Each of flip-flops 102 and 104 includes CLK_INP and CLK_INM inputs configured to receive different clock signals CLK_M and CLK_P, respectively, for example, 180° out of phase, i.e., in opposite phase. These inputs are common to both flip-flops; that is, they are connected to each other.

[0036] In the example of [Fig.1], each flip-flop 102, 104 is connected to an application terminal of a reference voltage VSS, for example connected to ground, and is connected to an application terminal of another reference voltage, for example VDD.

[0037] Each of the flip-flops 102, 104 includes input nodes NVBIAS_M and NVBIAS_P configured to receive DC bias voltages VBIAS_M and VBIAS_P respectively. VBIAS_M and VBIAS_P are intended to be applied indirectly, via a resistor, to transistor gates of the flip-flops 102, 104. In particular, in one example, VBIAS_M is applied to the flip-flops 102, 104 to bias the control gate of a pull-up transistor of these flip-flops.

[0038] Not illustrated in [Fig.1], each of the flip-flops 102, 104 also includes an input configured to receive a BACK_GATE_TUNING transistor back gate control signal.

[0039] To obtain a frequency divider, the outputs Q_P and Q_M of the flip-flop 104 are connected, preferably connected, respectively to the inputs D_M and D_P of the flip-flop 102.

[0040] The example in [Fig.1] allows a division by two, however a division by a higher number can be implemented by a person skilled in the art by increasing the number of flip-flops in series, for example four flip-flops in series for the generation of signals having a frequency divided by four.

[0041] Figure 2 represents a circuit of the frequency divider of Figure 1. The example shown illustrates in particular an example of one of the flip-flops 102, 104.

[0042] The flip-flop 102, 104 shown includes a pull-up transistor Ml, used as a transconductor, which is for example of the NMOS type, and whose main control node is connected to the input node CLK_INP, for example via an optional capacitor Cl which serves as DC isolation.

[0043] The illustrated flip-flop 102, 104 comprises a first branch having transistors M4 and M6 in series between the application terminal of the reference voltage VDD and a conduction node NS of transistor ML. In one example, transistor M4 is of the PMOS type and transistor M6 is of the NMOS type. The illustrated flip-flop 102, 104 further comprises a second branch having transistors M5 and M7 in series between the application terminal of the reference voltage VDD and the conduction node NS of transistor ML. In one example, transistor M5 is of the PMOS type and transistor M7 is of the NMOS type. A main control node of transistor M4 is connected to a midpoint N2 of transistors M5 and M7, and a main control node of transistor M5 is connected to a midpoint NI of transistors M4 and M6.

[0044] In the example of the flip-flop 102, 104 illustrated in [Fig. 2], a transistor M2 connects the voltage application terminal of the reference voltage VDD to the midpoint N1 of transistors M4 and M6. In addition, a transistor M3 connects the voltage application terminal VDD to the midpoint N2 of transistors M5 and M7. In one example, transistors M2 and M3 are of the PMOS type.

[0045] In the example shown, the CLK_INM node is connected, preferably connected, for example via an optional isolation or filtering capacitor C2, to a main control node of transistors M2 and M3.

[0046] The NVBIAS_P node is connected to the CLK_INM node via a resistor R2 on the side of transistor M2, and respectively R3 on the side of transistor M3. In one example, the resistors R2 and R3 have the same value or are a single resistor.

[0047] In the illustrated example, the NVBIAS_M node is connected to the main control node, i.e., the front gate for example, of transistor M1 via a resistor RL

[0048] In [Fig.2], the nodes NI and N2 are differential outputs, respectively Q_M, Q_P, of the flip-flop, and the main control nodes of transistors M6 and M7 are differential inputs, respectively D_P, D_M, of the flip-flop.

[0049] In one example, to implement the frequency divider, the main control node of transistor M6 of flip-flop 102 is connected to the midpoint N2 of transistors M5, M7 of the other flip-flop 104 of the divider. Furthermore, the main control node of transistor M7 of flip-flop 102 is connected to the midpoint N1 of transistors M4, M6 of flip-flop 104.

[0050] In the example in [Fig. 2], transistors M1, M2, M3, M4, M5, M6, and M7 are manufactured using fully depleted silicon on insulator (FDSOI) technology. They have a main control gate, also called the main control node or front gate, and a back gate or secondary control node. In the example shown, the back gates of transistors M1, M6, and M7 are connected to the VDD voltage application terminal. The back gates of transistors M2, M3, M4, and M5 are connected together and configured to receive the back gate control signal BACK_GATE_TUNING.

[0051] CLK_INP and CLK_INM control both the control gate of transistor M1 and transistors M2 and M3. Transistors M6 and M7 draw current according to the inputs D_P and D_M, respectively. Transistors M4 and M5 generate a memory point that enables division by two. The back-gate control signal BACK_GATE_TUNING modifies their threshold voltage, which in turn varies the drain-source resistance Rds of the transistors. In summary, the flip-flop example in [Fig. 2] allows increasing the operating frequency range (frequency tuning) of the frequency divider 100, based on a back-gate control voltage of the transistors in flip-flops 102 and 104.

[0052] The examples in Figures 1 and 2 nevertheless suffer from harmonic distortion. Furthermore, power consumption is high, even doubled, because the pull-up current, i.e., the current through transistor M1, varies according to the amplitude of the incoming radio frequency signals. The usable frequency range is limited because the back-gate drive voltage is limited. Finally, these examples are limited to an implementation using FDSOI technology.

[0053] In order to overcome these drawbacks, the embodiments presented below propose that a pull-out current of each flip-flop be controlled by a reference current.

[0054] This allows implementation in technologies that are not limited to FDSOI, such as FinFet technology with finned field-effect transistors or so-called "3D" transistors. This also allows the range of The radio frequency signal to be processed has little impact on the draw current. Finally, this allows for increased amplitude and frequency adjustment capabilities.

[0055] Figure 3 represents a frequency divider 300 according to one embodiment, and Figure 4 represents a circuit of the frequency divider 300 of Figure 3 according to another embodiment. More particularly, Figure 4 represents a flip-flop 302, 304 of the divider 300.

[0056] Flip-flops 302 and 304 of divider 300 are similar to flip-flops 102 and 104, except that transistors M1, M2, M3, M4, M5, M6, and M7 are not necessarily manufactured using FDSOI technology and there is no dynamic back-gate control. Therefore, flip-flops 302 and 304 do not have an input configured to receive the BACK_GATE_TUNING signal.

[0057] In the example in [Fig. 4], transistors M2, M3, M4, and M5 have their substrate, or back gate depending on the technology used in their manufacture, biased at VSS, i.e., to ground. In one example, this biasing could be VDD or another fixed voltage such as VDD / 2. Transistors M1, M6, and M7 have their substrate, or back gate, biased at VDD.

[0058] Unlike the example in [Fig.2], in the example in [Fig.4], the transistor Ml connects the NS node to an NVSOURCE node, which is a conduction node of Ml, and which is connected to ground by a resistance Rtail also called a pull-up resistance.

[0059] The frequency divider 300 of [Fig. 3] further includes a feedback loop formed by a differential amplifier Al, one input of which is connected to ground via a resistor Rref. In the example shown, the differential amplifier Al also includes another input connected to the NVSOURCE node of each of the flip-flops 302 and 304. An output of the differential amplifier Al is connected to the NVBIAS_M node of the flip-flops 302 and 304. The VBIAS_M signal, present at the NVBIAS_M node, is the signal from the amplifier AL. The NVBIAS_M node is connected to the control node of transistor M1 via the resistor RL. The feedback loop further includes a NIBIAS application node for the IDAC reference current. In one example, the IDAC reference current is generated by a digital-to-analog converter (DAC).In the example shown, the feedback loop also includes a PI transistor, for example a PMOS type, connecting the NIBIAS node and the VDD voltage application terminal. A control gate of the PI transistor is connected in current mirror to the NIBIAS node. The NIBIAS node is connected to the NVBIAS_P node. The signal on the NVBIAS_P node is thus linked to the IDAC current.

[0060] In one example, an optional RC type filter connects the NIBIAS node to the NVBIAS_P node. This filter includes, for example, a resistor R4 connecting the NIBIAS node and the NVBIAS_P node, and a capacitor C2 connecting the NVBIAS_P node to the VDD voltage application terminal.

[0061] In one example, the feedback loop comprises two transistors P2 and P3, for example of the PMOS type, copying the IDAC reference current and connected to the amplifier Al. Each of the transistors, P2 and P3, connects the application terminal of the VDD voltage to the amplifier Al. The control nodes of transistors P2 and P3 are connected to each other and to the NVBIAS_P node of each flip-flop 302, 304. Thus, the current in transistors M2 and M3 of the flip-flops is linked to the current in PI. The role of transistors P2 and P3 is to set the currents of flip-flops 302 and 304 by regulating the voltage across resistor Rref with the voltage across resistor Rtail so that Rtail * Itail equals Rref * Iref. The current in P3 is fixed and also flows through resistor Rref. The current in transistor P2 is found through resistor Rtail associated with the current of the two flip-flops.In an example, Itail is on the order of mA, Iref is on the order of pA and Rtail < Rref. Iref being the current through the resistance Rref and Itail the current through the resistance Rtail.

[0062] During operation, the drain-source resistance of transistors M2 and M3 is modulated according to the IDAC current. When the IDAC current increases, the current in PI, P2, and P3 increases. This results in an increase in the current in M2 and M3, as well as a decrease in the drain-source resistance Rds of these transistors M2 and M3, and an increase in the reference current Iref through the reference resistor Rref. The feedback loop controls the control voltage on the gate of transistor M1 to keep it in saturation. This ensures the proper operation of the divider, i.e., that the division is performed correctly, according to the operating parameters. The feedback loop thus controls the current Itail through the pull-up resistor Rtail (also called the toe-down current) so that Rtail * Itail equals Rref * Iref.The current in transistors M4 and M5 remains fixed and independent of the IDAC current, thus fixing the output voltages Q_M and Q_P regardless of the IDAC control current and accelerating the operation of the frequency flip-flops. The current through each flip-flop (DC current) is not, or only slightly, affected by the amplitude of the radio frequency signal (input signal voltage swing). The IDAC current allows the selection of the appropriate amplitude relative to the radio frequency signal input to the divider.

[0063] The examples in Figures 3 and 4 result in a consumption reduced by half compared to the examples in Figures 1 and 2, or compared to flip-flop-based dividers implemented in CML (Current Mode Logic) technology, at least for frequencies between 12 GHz and 35 GHz. The amplitude and frequency adjustment capability is also increased and the resulting jitter is low, for example on the order of a few tens of femtoseconds.

[0064] Fig. 5 represents an operating chronograph of the frequency divider 300 of Fig. 3.

[0065] In particular, [Fig. 5] shows the 0UT_IM and OUT_IP signals present at the Q_P and Q_M outputs of flip-flop 302, and the OUT_QM and OUT_QP signals present at the Q_P and Q_M outputs of flip-flop 304. The OUT_QP and OUT_QM signals are 180° out of phase with each other, and at the output of flip-flop 302, the OUT_IP and OUT_IP signals are also 180° out of phase with each other. Furthermore, the OUT_IP signal is in quadrature with the OUT_QP signal. Similarly, the 0UT_IM signal is in quadrature with the 0UT_QM signal.

[0066] The frequency divider described in the examples presented can be used in applications involving, for example, radio frequency signal reception or transmission chains, for example, between 10 and 100 GHz. Furthermore, the frequency divider can be used in receivers for positioning devices such as GPS (Global Positioning System), Galileo, etc. The described frequency divider can be integrated into 5G or 6G communication systems, particularly in reception or transmission chains, or for data transmission. Devices requiring quadrature signals and seeking lower power consumption can also use the described divider.

[0067] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, transistors described as NMOS could become PMOS and vice versa. In such cases, those skilled in the art will modify the connections at the first and second terminals accordingly, as well as the associated substrate or back-gate voltages.

[0068] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional indications given above. In particular, with regard to the amplifier A1, a person skilled in the art can implement it according to their knowledge, taking into account, for example, the power supply via the current mirror(s) from transistors P2 and / or P3, the inputs connected to Rtail and Rref respectively, and the output proportional to the difference between the two inputs connected to Rtail and Rref respectively.

Claims

Demands

1. Frequency divider (300), comprising at least two flip-flops (302, 304) and wherein a pull-up current (Itail) of each flip-flop is controlled by a reference current (IDAC).

2. Frequency divider according to claim 1, wherein the flip-flops are in series and each flip-flop comprises: - a first node (CLK_INP), common to both flip-flops, for applying a first clock signal; - a second node (CLK_INM), common to both flip-flops, for applying a second clock signal different from the first clock signal; and - a first pull-up transistor (M1) of which a control node is connected to the first node (CLK_INP).

3. Frequency divider according to claim 2, wherein the frequency divider (300) comprises a control loop including a reference current application node (NIBIAS) (IDAC) connected to the second node (CLK_INM).

4. Frequency divider according to claim 3, wherein the control loop comprises a differential amplifier (Al) of which: - a first input is connected to a first application terminal of a first reference voltage (GND) via a first resistor (Rref); - a second input is connected to a first conduction node (NVSOURCE) of the first transistor (Ml) of each of the flip-flops, said first conduction node (NVSOURCE) of the first transistor (Ml) being connected to the first terminal via a pull-up resistor (Rtail); and - an output is connected to a control node of the first transistor (Ml).

5. Frequency divider according to claim 4, wherein the output of the amplifier (Al) is connected to the control node of the first transistor (Ml) via a second resistor (RI).

6. Frequency divider according to any one of claims 3 to 5, wherein the feedback loop includes at least one current mirror, connected to the amplifier (Al), and configured to copy the reference current (IDAC).

7. Frequency divider according to the preceding claim, wherein said at least one current mirror is configured to copy the reference current (IDAC) and supply the amplifier (Al) with the copied current.

8. Frequency divider according to any one of claims 1 to 7, wherein the flip-flops (302, 304) each comprise: - a first branch having a second and a third transistor (M4, M6) in series between a second application terminal of a second reference voltage (VDD) and a second conduction node (NS) of the first transistor (M1); and - a second branch having a fourth and a fifth transistor (M5, M7) in series between said second terminal and the second node (NS); a control node of the second transistor (M4) being connected to a midpoint (N2) of the fourth and fifth transistors (M5, M7), and a control node of the fourth transistor (M5) being connected to a midpoint (NI) of the second and third transistors (M4, M6).

9. Frequency divider according to the preceding claim, wherein the flip-flops (302, 304) each comprise: a sixth transistor (M2) connecting the second terminal and the midpoint (NI) of the second and third transistors; and a seventh transistor (M3) connecting the second terminal and the midpoint (N2) of the fourth and fifth transistors; the second node (CLK_INM) being connected to a control node of the sixth and seventh transistors (M2, M3).

10. Frequency divider according to any one of claims 2 to 9, wherein the reference current application node (NVBIAS_P) is connected to the second node (CLK_INM) of each of the flip-flops via a third resistor (R2, R3).

11. Frequency divider according to any one of claims 8, or 9 or 10 in their dependence on claim 8, wherein: - a control node of the third transistor (M6) of a first flip-flop (302) of the frequency divider (300) is connected to the midpoint (N2) of the fourth and fifth transistors (M5, M7) of a second flip-flop (304) of the frequency divider (300); and - a control node of the fifth transistor (M7) of the first flip-flop (302) is connected to the midpoint (NI) of the second and third transistors (M4, M6) of the second flip-flop (304).

12. Frequency divider according to any one of claims 4, or 5 to 11 in their dependence on claim 4, wherein the first reference voltage is ground and the second reference voltage is VDD.

13. Frequency divider according to any one of claims 1 to 12, wherein the reference current (IDAC) is derived from a digital-to-analog converter (DAC).

14. Radio frequency device comprising a receiving or transmitting chain comprising a frequency divider according to any one of claims 1 to 13.

15. Method of operating a frequency divider according to any one of claims 1 to 13, the method comprising controlling a pull current (Itail) of each flip-flop to a reference current (IDAC).

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