Method for making a CFET transistor device

Abstract

Method for manufacturing a CFET transistor device. A method for manufacturing a CFET transistor device, comprising: - fabrication, on a first dielectric bonding layer (108), of a first stack (102) comprising first and second semiconductor layers (104, 106) arranged one on top of the other and which can be selectively etched; - etching, through the first stack (102), of trenches forming active regions in the form of nanosheets; - deposition of a dielectric filling material in the trenches; - bonding of the first dielectric bonding layer to a second stack (126) comprising third and fourth semiconductor layers (128, 130) arranged one on top of the other and which can be selectively etched; - annealing carried out at a temperature greater than or equal to 200°C. Figure for the abstract: Fig. 6

Description

Title of the invention: Method for implementing a CFET transistor device. Technical field

[0001] This description relates generally to the field of semiconductor device manufacturing, and more particularly to the realization of CFET (Complementary Field-Effect Transistors) devices. Previous technique

[0002] A CFET transistor device comprises, on a substrate, semiconductor nanosheets superimposed on the substrate and forming the active regions of transistors of different conductivity types, nMOS and pMOS. The nanosheets forming the active regions of the nMOS transistors are separated from those forming the active regions of the pMOS transistors by dielectric material.

[0003] The nanosheet stacks used for the realization of a CFET transistor device can be manufactured in two different ways: monolithic or sequential.

[0004] The sequential fabrication of these stacks consists of separately creating, from different substrates, stacks of layers, or super-lattices, used to create the active regions of different types of transistors in the form of two independent and distinct structures, and then joining them by gluing. One of the two substrates used is then removed, leaving only one to support the resulting assembly.

[0005] Compared to monolithic manufacturing in which the layers used to create the active regions of the two types of transistors are made successively one on top of the other in the form of a single stack on the same substrate, sequential manufacturing of super-networks makes it possible to optimize each of them separately before bonding, and thus consider obtaining more efficient CFET transistors.

[0006] The bonding is carried out between two dielectric layers, each formed at the top of one of the fabricated superlattices. Ideally, the thicknesses of these dielectric layers are small, typically such that the total thickness of the dielectric material between the superlattices is less than 50 nm. The bonding is generally a direct hydrophilic bond. A consolidation anneal, for example at a temperature of 500°C or higher, is then performed.

[0007] However, it is very difficult to achieve direct hydrophilic bonding with such thin dielectric layers because defects will be generated at the bonding interface during the annealing process used to consolidate this interface. Indeed, defects appear at the bonding interface when the consolidation annealing is carried out, particularly at a temperature of 500°C or higher, and especially when the thin dielectric layers contain semiconductor oxide. These defects are created due to water trapped at the bonding interface, which passes through the dielectric layers and reacts with the semiconductor against which the dielectric layers are placed. This reaction generates hydrogen gas, which becomes trapped and leads to the formation of bubbles at the bonding interface. Summary of the invention

[0008] There is a need to propose a method for implementing a CFET transistor device that does not have the disadvantages of known methods of implementation.

[0009] An embodiment overcomes all or part of the drawbacks of known methods and proposes a method for implementing a CFET transistor device, comprising at least:

[0010] - creation, on a first dielectric bonding layer, of a first stack comprising at least a first semiconductor layer and a second semiconductor layer arranged one on top of the other, one of the first and second semiconductor layers being configured to be selectively etched with respect to the other;

[0011] - engraving, through the first stacking, of trenches such as portions remaining from the first or second semiconductor layer form nanosheets configured to form active regions of CFET transistors;

[0012] - deposit of at least one dielectric filling material in the trenches;

[0013] - bonding of the first dielectric bonding layer to a second stack comprising at least one third semiconductor layer and one fourth semiconductor layer arranged one on top of the other, one of the third and fourth semiconductor layers being configured to be selectively etched with respect to the other;

[0014] - annealing carried out at a temperature greater than or equal to 200°C.

[0015] According to a particular embodiment, annealing can be carried out at a temperature greater than or equal to 500°C.

[0016] According to a particular embodiment, the bonding of the first dielectric bonding layer to the second stack corresponds to a direct hydrophilic bonding.

[0017] According to a particular embodiment, the bonding of the first dielectric bonding layer to the second stack corresponds to a bonding of the first dielectric bonding layer to a second dielectric bonding layer to which the second stack is attached, the second dielectric bonding layer being disposed between the first dielectric bonding layer and the second stack.

[0018] According to a particular embodiment, the thickness of the first dielectric bonding layer is less than or equal to 50 nm, or, when the bonding is carried out between the first and second dielectric bonding layers, the total thickness of the first and second dielectric bonding layers bonded to each other is less than or equal to 50 nm.

[0019] According to a particular embodiment, the process further comprises, between the making of the first stack and the engraving of the trenches through the first stack, the making of a hard mask on the first stack, the trenches then being engraved in the first stack according to the pattern defined by the hard mask.

[0020] According to a particular embodiment, the process further comprises, after annealing, an etching of the dielectric filling material disposed in the trenches.

[0021] According to a particular embodiment, the method further comprises, after etching the dielectric filling material arranged in the trenches, etching, according to the pattern defined by the etching mask, through at least the first dielectric bonding layer and the second stack such that remaining portions of the third or fourth semiconducting layers form nanosheets configured to form active regions of CFET transistors.

[0022] According to a particular embodiment, the first dielectric bonding layer corresponds to an oxide layer buried in a first SOI-type substrate, and the process further comprises, between the deposition of the filling dielectric material and the bonding of the first dielectric bonding layer to the second stack:

[0023] - securing a temporary support layer to the first stack such that the first stack should be placed between the temporary support layer and the first substrate;

[0024] - removal of a massive layer of the first substrate, freeing one face of the first dielectric bonding layer intended to be bonded to the second stack.

[0025] According to a particular embodiment, the first SOI-type substrate comprises a buried dielectric stack including a semiconductor nitride layer disposed between first and second buried oxide layers, the first bonding dielectric layer corresponding to the second buried oxide layer disposed between a semiconducting surface layer of the first substrate and the layer of semiconductor nitride, and the process further comprises, between the removal of the bulk layer of the first substrate and the bonding of the first dielectric bonding layer to the second stack, a removal of the first buried dielectric layer and of the semiconductor nitride layer.

[0026] According to a particular embodiment, the process further comprises, before the first stacking on the first dielectric bonding layer:

[0027] - production of the first dielectric bonding layer on a layer semiconducting surface of a first SOI-type substrate;

[0028] - deposition of an etching layer on the first dielectric bonding layer, the etching layer comprising a material configured to be selectively etched with respect to the first dielectric bonding layer;

[0029] - bonding of a mechanical support substrate to the etching layer;

[0030] - removal of a massive layer and a buried dielectric layer from the first substrate;

[0031] and the method further comprises, between the deposition of the dielectric filling material and the bonding of the first dielectric bonding layer to the second stack:

[0032] - securing a temporary support layer to the first stacking such as the the first stack should be placed between the temporary support layer and the mechanical support substrate;

[0033] - removal of the mechanical support substrate.

[0034] According to a particular embodiment:

[0035] - the bonding of the temporary support layer to the first stack includes bonding the temporary support layer to a temporary adhesive layer placed on top of the first stack, and

[0036] - the temporary support layer is removed after annealing.

[0037] According to a particular embodiment, the process further comprises, between the deposition of the dielectric filling material and the bonding of the temporary support layer to the first stack, the implementation of a mechano-chemical polishing forming hollows on the surface of the portions of the dielectric filling material, and:

[0038] - the bonding of the temporary support layer to the first stack includes bonding the temporary support layer to the hard mask, and

[0039] - the temporary support layer is detached, after annealing, by laser at a wavelength at which the temporary support layer is transparent.

[0040] According to a particular embodiment, the first and third semiconductor layers comprise silicon, and / or the second and fourth semiconductor layers comprise SiGe.

[0041] According to a particular embodiment, the first stack comprises several first semiconductor layers and several second semiconductor layers arranged alternately on top of each other, and / or the second stack comprises several third semiconductor layers and several fourth semiconductor layers arranged alternately on top of each other.

[0042] According to a particular embodiment, the method further comprises, after annealing, etching remaining portions of the first or second semiconductor layer and / or etching remaining parts of the third or fourth semiconductor layer, and deposition of a gate dielectric and a gate conductive material around at least a part of the portions of the remaining semiconductor layers forming channels of the CFET transistors, and epitaxy from flanks of the portions of the remaining semiconductor layers forming source and drain regions of the CFET transistors. Brief description of the drawings

[0043] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0044] - [Fig.l], [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7], [Fig.8], [Fig.9] and [Fig.10] schematically represent steps of a first example of a process for making a CFET transistor device according to a particular embodiment;

[0045] - [Fig.l 1], [Fig.12], [Fig.13], [Fig.14], [Fig.15], [Fig.16] and [Fig.17] represent part of the steps of a second example of a process for realizing a CFET transistor device according to a particular embodiment;

[0046] - [Fig. 18] represents an intermediate structure obtained during a third example of a method for making a CFET transistor device according to a particular embodiment. Description of the implementation methods

[0047] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional, and material properties. In the figures, to facilitate their reading, the different elements and the different material layers are not shown at the same scale relative to each other.

[0048] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, different The steps implemented after the trenches are extended through the second stack and relating to the fabrication of CFET transistor components other than nanosheets are not detailed. Those skilled in the art will be able to implement such steps based on the description given here.

[0049] Unless otherwise specified, when referring to two elements connected between them, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected or coupled (in English "coupled") to each other, this means that these two elements can be connected or linked via one or more other elements.

[0050] In the following description, when reference is made to absolute positional qualifiers, such as "front," "back," "top," "bottom," "left," "right," etc., or relative positional qualifiers, such as "above," "below," "superior," "inferior," etc., or to orientational qualifiers, such as "horizontal," "vertical," etc., unless otherwise specified, reference is made to the orientation of the figures in a normal operating position. However, these terms do not imply the actual position and orientation of the device during use.

[0051] Unless otherwise specified, the expressions "approximately", "about", "Approximately" and "on the order of" mean within 10%, preferably within 5%.

[0052] A first example of a method for making a CFET transistor device is described below in relation to figures 1 to 10.

[0053] A first stack 102 comprising at least one first semiconductor layer 104 and at least one second semiconductor layer 106 arranged one on top of the other is made on a first dielectric bonding layer 108. The first stack 102 forms a first super-network of semiconductor layers 104, 106 arranged on the first dielectric bonding layer 108.

[0054] In this first embodiment, the first stack 102 comprises several first semiconductor layers 104 and several second semiconductor layers 106 arranged alternately on top of each other. Alternatively, the first stack 102 could comprise a single first semiconductor layer 104 and / or a single second semiconductor layer 106.

[0055] In this first embodiment, the first dielectric bonding layer 108 corresponds to a buried oxide layer, or BOX, of a first substrate 110 of the SOI (Silicon-On-Insulator, or silicon-on-insulator) type, or more generally of the semiconductor-on-insulator type, also comprising a bulk layer 112, or support layer, and a semiconducting surface layer which, in this example, is intended to form the first semiconductor layer 104. The first dielectric layer of The bonding 108 is arranged between the massive layer 112 and the semiconducting surface layer (corresponding to the first semiconducting layer 104 on the [Fig. 1]).

[0056] According to a particular example, the first substrate 110 has a diameter of approximately 300 mm. The bulk layer 112 has, for example, a thickness of several hundred microns and comprises, for example, silicon or another semiconductor or any other suitable material. The semiconducting surface layer has, for example, a thickness of 20 nm or, more generally, between 5 nm and 50 nm, and comprises, for example, silicon or another semiconductor.

[0057] The first bonding dielectric layer 108 comprises, for example, SiO2 or any other suitable dielectric material, and has, for example, a thickness of 20 nm. In this first embodiment, the first substrate 110, when it is of the SOI type, is chosen such that its buried dielectric layer has a thickness corresponding to that desired for the first bonding dielectric layer 108. The thickness of the first bonding dielectric layer 108 is less than or equal to 50 nm, or advantageously less than or equal to 30 nm, or 20 nm, or 10 nm, or 3 nm.

[0058] Furthermore, in the embodiment described here, since the semiconductor surface layer of the first substrate 110 is intended to be used to form one of the first semiconductor layers 104, if the initial thickness of the semiconductor surface layer corresponds to the desired thickness of this first semiconductor layer 104, the other layers of the first stack 102 can be fabricated directly on the semiconductor surface layer. If the initial thickness of the semiconductor surface layer is too great, the semiconductor surface layer can be thinned before fabricating the other layers of the first stack 102 on it.

[0059] For example, to achieve such thinning, thermal oxidation can be carried out, for example at a temperature of 950°C under a dry O2 atmosphere. This oxidation thins the semiconductor surface layer by creating a thermal oxide layer on its surface. In the described embodiment, this oxidation thins the semiconductor surface layer to a thickness of, for example, 17.5 nm and forms a thermal oxide layer with a thickness of, for example, 5 nm. The thermal oxide layer can then be removed, for example by using a 10% HF solution. The remaining semiconductor thickness of the surface layer forms the first semiconductor layer 104, on which the other layers of the first stack 102 will then be formed.

[0060] Advantageously, when the semiconductor layers 104, 106 of the first stack 102 are intended to be used for the realization of active regions of nMOS-type transistors, the surface semiconductor layer of the first substrate 110 can may contain crystalline silicon (100). Similarly, when the semiconductor layers 104, 106 of the first stack 102 are intended for use in the realization of active regions of pMOS or nMOS transistors, the surface semiconductor layer of the first substrate 110 may contain crystalline silicon (110). The crystalline orientation of the semiconductor in the bulk layer 112 of the first substrate 110 may or may not be the same as that of the semiconductor in the surface layer of the first substrate 110.

[0061] In the example described, because the other semiconductor layers 104, 106 of the first stack 102 are formed by epitaxy from the upper face of the surface layer of the first substrate 110, which forms one of the first semiconductor layers 104, the crystal orientation of the semiconductor from which the epitaxy is carried out—that is, the crystal orientation of the semiconductor in the surface layer—is also that of the semiconductors in the other layers 104, 106 formed subsequently. Thus, electron mobility is favored when the active regions of nMOS transistors are made from semiconductor material with a crystal orientation (100), and hole mobility is favored when the active regions of pMOS transistors are made from semiconductor material with a crystal orientation (110).

[0062] The semiconductors of layers 104, 106 are such that one of the first and second layers 104, 106 can be selectively etched with respect to the other. This etching selectivity will subsequently be used to etch the second layers 106 before creating gates around portions of the first layers 104 intended to form channels of the CFET transistors, or to etch the first layers 104 before creating gates around portions of the second layers 106 intended to form channels of the CFET transistors. In the example described, the first stack 102 is made such that the first layers 104 contain silicon and the second layers 106 contain SiGe. Conversely, it is possible that the first layers 104 contain SiGe and the second layers 106 contain silicon.For example, the second 106 layers contain SiO>7 5GeO>2 5 and each has a thickness of approximately 10 nm, while the first 104 layers contain silicon and each has a thickness of approximately 17.5 nm. More generally, the thickness of each of the first 104 layers can be between approximately 5 nm and 22.5 nm and / or the thickness of each of the second 106 layers can be between approximately 5 nm and 22.5 nm. Furthermore, the germanium content of the SiGe can be between 20% and 35%.

[0063] Alternatively, semiconductor materials other than silicon and SiGe are possible for the realization of the semiconductor layers 104, 106 of the first stack 102.

[0064] The number of first layers 104 and second layers 106 of the first stack 102 depends in particular on the number of nanosheets intended to form the active regions of the transistors that will subsequently be fabricated from these nanosheets. In the example of [Fig. 1], the first stack 102 comprises three first layers 104 and three second layers 106. For example, the first stack 102 may have a total number of first layers 104 and second layers 106 ranging from two to six, or even more.

[0065] Alternatively, the first dielectric bonding layer 108 can be made from a bulk semiconductor substrate, for example by oxidation or deposition, then the first stack 102 can be made on this first dielectric bonding layer 108, for example transferred onto the first dielectric bonding layer 108 by bonding the stack 102 made beforehand on another suitable substrate.

[0066] Alternatively, the first bonding dielectric layer 108 may comprise a dielectric material other than an oxide, for example semiconductor nitride or a so-called "low-k" dielectric material, or one with low permittivity, such as SiOCH, or a so-called "high-k" dielectric material, or one with high permittivity, such as HfO2.

[0067] Alternatively, the first dielectric bonding layer 108 can correspond to a stack of several superimposed layers formed of different dielectric materials.

[0068] As an alternative to the example described above, the first stack 102 may include additional layers of materials in addition to those described above.

[0069] In the first embodiment, the semiconductor layers 104, 106 of the stack 102 are produced by epitaxy from the surface layer of the first substrate 110.

[0070] After the first stack 102 is formed, a hard mask 114 is applied to the first stack 102. For example, the hard mask 114 comprises silicon nitride. Furthermore, the hard mask 114 can be produced by a deposition, for example, of the LPCVD (Low-Pressure Chemical Vapor Deposition) type, carried out at a temperature, for example, less than or equal to 700 °C, for example, on the order of 650 °C or even 600 °C. The hard mask 114 has, for example, a thickness of 100 nm, or more generally, between 20 nm and 500 nm. The thickness of the hard mask 114 can in particular be chosen such that after having engraved trenches in the first stack 102, the remaining thickness of the hard mask 114 is sufficient to extend these trenches through a second stack as described later.

[0071] The structure obtained at this stage of the process is shown in [Fig. 1].

[0072] A trench engraving 116 is then implemented through the first stacking 102, such that remaining portions of the first and second semiconductor layers 104, 106, form stacks of nanosheets. The trenches 116 are such that the remaining portions of the first stacking 102 form fins, or slivers, with a width (dimension parallel to the X-axis in [Fig. 2]) for example equal to one or more tens of nanometers. The width of the remaining portions of the first stacking 102 is for example less than 1 pm, or even less than 100 nm, or less than 50 nm, or less than 20 nm. The width of the trenches 116 is for example between two and three times that of the remaining portions of the first stacking 102. In the first embodiment described, the trenches 116 are etched into the first stacking 102 according to the pattern defined by the hard mask 114.This pattern corresponds to the desired one so that the remaining portions of the 102 stack geometrically define the future active areas of the CFET transistors that will be fabricated later. Thus, the width of the remaining portions of the first 102 stack corresponds approximately to the channel lengths of the transistors that will be fabricated from these remaining portions.

[0073] In the described example, the trenches 116 are etched through all the semiconductor layers 104, 106 of the stack 102, the etching being stopped at the first bonding dielectric layer 108. For example, to create the trenches 116, ion etching or reactive ion etching can be implemented. A slight over-etching can be implemented to locally thin portions of the first bonding dielectric layer 108 directly above the trenches 116. For example, for a first bonding dielectric layer 108 with a thickness of 20 nm, the thickness of the portions of the first bonding dielectric layer 108 located directly above the trenches 116 can be 15 nm after this over-etching. The structure obtained after this etching is shown in [Fig. 2].

[0074] According to a particular example, the width of the unengraved areas of the stack 102, i.e. the remaining portions of the stack 102, is for example equal to 25 nm, and the width of the trenches 116 is for example equal to 50 nm.

[0075] A dielectric filling material 118 is then deposited in the trenches 116. This dielectric filling material 118 corresponds, for example, to SiO2. According to a particular example, the dielectric filling material 118 can be an oxide obtained from TEOS (tetraethyl orthosilicate), the thickness of which is, for example, equal to 600 nm and deposited, for example, at a temperature of 400°C.

[0076] In the described embodiment, the dielectric material used to fill the trenches 116 and form the filling dielectric material 118 is also deposited outside the trenches 116, above them and on the remaining portions of the first stack 102, forming a dielectric layer called the temporary bonding layer 120. Chemical mechanical polishing (CMP) can be used to flatten and remove part of the thickness of the temporary bonding layer 120, and prepare the surface for subsequent bonding on the upper surface of this layer. For example, for a temporary bonding layer 120 with a thickness of 600 nm, the chemical mechanical polishing can remove a thickness of 300 nm, thus leaving a temporary bonding layer 120 with a thickness of 300 nm on the dielectric filler material 118 deposited in the trenches 116 and on the remaining portions of the first stack 102. The structure obtained after polishing is shown in [Fig. 3].

[0077] Alternatively, the filling dielectric material 118 and that of the temporary bonding layer 120 may comprise a dielectric material other than an oxide, for example semiconductor nitride or a so-called "low-k" dielectric material, or one with low permittivity, such as SiOCH, or a so-called "high-k" dielectric material, or one with high permittivity, such as HfO2.

[0078] A temporary support layer 122, intended to serve as a mechanical handle, is then attached to the first stack 102 such that the first stack 102 is positioned between the temporary support layer 122 and the first substrate 110. In the first embodiment described, the temporary support layer 122 is attached to the temporary bonding layer 120. According to one embodiment, the temporary support layer 122 corresponds to a semiconductor substrate, for example, silicon, with at least the same diameter as that of the first substrate 110 (300 mm in this example) and a thickness of several hundred microns, for example, 775 pm. Alternatively, the temporary support layer could comprise another type of material, for example, surface-oxidized silicon or glass.

[0079] In the example described, this bonding corresponds to gluing the temporary support layer 122 onto the temporary bonding layer 120, for example, direct bonding. Before this bonding is carried out, the temporary bonding layer 120 and the temporary support layer 122 may be subjected to one or more cleaning and / or preparation and / or surface treatment steps. According to a particular example, it is possible to carry out particulate cleaning, for example, using a very high frequency ultrasonic generator, or megasound, with a frequency, for example, of 1 MHz, in liquid phase, for example, with a 1% solution of dilute ammonia, at a power of 2 W / cm² and for a duration of 60 s. This is followed by plasma treatment, for example, at 0.3 mbar. Oxygen can be applied to each surface to be bonded using two electrodes at 397 kHz and 40 kHz, with a power of 75 and 100 W respectively, for a duration of 30 s. For example, at least one of the following plasmas can be used: O2, N2, CF4 0.2% in O2 or N2, or SF6 0.2% in O2 or N2. A single-electrode plasma treatment chamber operating at 13.56 MHz can be used, for example. Finally, an ethalonamine-based solution with a concentration of 10⁴ M is applied to the surfaces to be bonded. Alternatively, ethalonamine can be replaced with, for example, diethylethalonamine, sodium hydroxide, or hydrazine. Plasma treatment as described above strengthens the bond subsequently achieved. Such plasma treatment is optional; treatment with ethalonamine alone can be performed.

[0080] Other types of treatment, cleaning and / or preparation of surfaces to be bonded may be carried out before bonding.

[0081] The bonding between the temporary bonding layer 120 and the temporary support layer 122 is then carried out, for example under vacuum.

[0082] A consolidation annealing of the bond between the temporary bonding layer 120 and the temporary support layer 122 is then carried out at a temperature, for example, of 500°C, and more generally between 100°C and 700°C, or even between 200°C and 500°C. A waiting period between bonding and the application of this annealing is preferably between 0 and 2 hours. Furthermore, this annealing can, for example, be carried out under a nitrogen atmosphere, for example, for a period of two hours, or between 10 minutes and 10 hours, or between 1 and 5 hours.

[0083] The structure obtained at this stage of the process is shown in [Fig.4].

[0084] The structure produced is inverted and the massive layer 112 of the first substrate 110 is then removed, exposing a face 124 of the first bonding dielectric layer 108 opposite the face against the first stack 102. For example, the bulk layer 112 can be removed by lapping until a remaining thickness of the bulk layer 112 of a few microns, for example 5 µm, is obtained. This remaining thickness of the bulk layer 112 can then be removed, for example, by wet etching with TMAH (having, for example, a concentration of 25%) at a temperature of approximately 70°C, using the first bonding dielectric layer 108 as a stop layer for this etching. The technique used to remove the bulk layer 112 can be such that the surface of the first bonding dielectric layer 108 freed is suitable for subsequent bonding on this surface.

[0085] The structure obtained at this stage of the process is shown in [Fig.5].

[0086] Concurrently or after the realization of this structure, a second stack 126 comprising at least a third semiconductor layer 128 and at least a fourth semiconductor layer 130 arranged one on top of the other is realized. The second stack 126 forms a second super-lattice of semiconductor layers 128, 130.

[0087] This second stack 126 can be made in the same way as the first stack 102, except that the hard mask 114, lithography, and ion etching through this hard mask are not implemented for this second stack 126. This second stack 126 also has a second thin dielectric layer on its surface. The crystal orientation of this second stack 126 can be different from that of the first stack 102.

[0088] In the described embodiment, the second stack 126 comprises several third semiconductor layers 128 and several fourth semiconductor layers 130 arranged alternately on top of each other. Alternatively, the second stack 126 could comprise a single third semiconductor layer 128 and / or a single fourth semiconductor layer 130.

[0089] In the described embodiment, the second stack 126 is made for example by epitaxy on a second substrate 132 which corresponds for example to a semiconductor substrate, bulk or SOI, or any type of substrate suitable for making the second stack 126.

[0090] Advantageously, when the third and fourth semiconductor layers 128, 130 are intended for use in the realization of active regions of nMOS transistors, the second substrate 132 may comprise silicon with a crystalline orientation (100). When the third and fourth semiconductor layers 128, 130 are intended for use in the realization of active regions of pMOS transistors, the second substrate 132 may comprise silicon with a crystalline orientation (110). When the second substrate 132 is of the bulk type, the entire semiconductor, for example silicon, of the second substrate 132 may have this crystalline orientation. When the second substrate 132 is of the SOI type, the semiconductor of the surface semiconductor layer of the second substrate 132 may have this crystalline orientation, although the orientation of the semiconductor of the bulk layer of the SOI substrate may or may not be different.In the example described, because the semiconductor layers 128, 130 of the second stack 126 are made by epitaxy from the second substrate 132, the crystal orientation of the semiconductor from which the epitaxy is performed is also that of the semiconductors of the layers 128, 130 subsequently made. Thus, electron mobility is favored when the active regions of nMOS transistors are made from a semiconductor with a crystal orientation of (100), and hole mobility is [missing information]. favoured when the active regions of pMOS transistors are made from crystalline orientation semiconductor (110).

[0091] The semiconductors of the third and fourth layers 128, 130 are such that one of the third and fourth layers 128, 130 can be selectively etched with respect to the other. This etching selectivity will subsequently be used to etch the fourth layer 130 before creating gates around portions of the third layers 128 intended to form channels of the CFET transistors, or to etch the third layers 128 before creating gates around portions of the fourth layers 130 intended to form channels of the CFET transistors. In the example described, the second stack 126 is arranged such that the third layers 128 contain silicon and the fourth layers 130 contain SiGe. Conversely, it is possible for the third layers 128 to contain SiGe and the fourth layers 130 to contain silicon.For example, the fourth 130 layers contain SiO>7 5GeO>2 5 and are approximately 10 nm thick, while the third 128 layers contain silicon and are approximately 17.5 nm thick. More generally, the thickness of each of the third 128 layers can range from approximately 5 nm to 22.5 nm, and / or the thickness of each of the fourth 130 layers can range from approximately 5 nm to 22.5 nm. Furthermore, the germanium content of the SiGe can range from 20% to 35%.

[0092] Alternatively, semiconductor materials other than silicon and SiGe are possible for the realization of the semiconductor layers 128, 130 of the second stack 126.

[0093] The number of third layers 128 and fourth layers 130 of the second stack 126 depends in particular on the number of nanosheets intended to form the active regions of the transistors that will subsequently be made from these nanosheets. In the example described, the second stack 126 has three third layers 128 and three fourth layers 130. For example, the second stack 126 may have a total number of third layers 128 and fourth layers 130 ranging from two to six, or even more, this number of layers being either the same as or different from the number of layers in the first stack 102.

[0094] As an alternative to the example described above, the second stack 126 may include additional material layers to those described above, such as for example an additional dielectric layer obtained for example by thermal oxidation.

[0095] It is possible that the second stack 126 is not terminated by a dielectric. Furthermore, if such a dielectric is present on the surface of the second element 126, this dielectric can be removed by implementing the bonding.

[0096] One or more cleaning and / or preparation and / or treatment steps, similar to those previously described for bonding between the temporary bonding layer 120 and the temporary support layer 122, can be implemented in order to prepare the bonding of the first dielectric bonding layer 108 to the second stack 126.

[0097] Bonding of the first dielectric bonding layer 108 to the second stack 126 is then carried out. In the example described, this bonding corresponds to a direct hydrophilic bond. This bonding can be performed under vacuum.

[0098] A consolidation anneal is then carried out. This anneal is carried out here, for example, at a temperature of 500°C or higher. Because the trenches 116 are filled with the dielectric filler material 118, the total thickness of dielectric material directly above the trenches 116 is significant. The area of ​​the bonding interface where a small total thickness of dielectric material is present is very small (only directly above the remaining portions of the first stack 102). This configuration prevents the formation of defects at the bonding interface between the second stack 126 and the first dielectric bonding layer 108.

[0099] According to one embodiment, the annealing temperature can be greater than or equal to 600°C, or 650°C, or more generally between 200°C and 700°C, a higher temperature potentially leading to a risk of inter-diffusion of the chemical elements that constituted the layers of stacks 102 and 126. This annealing is, for example, carried out for a period of between approximately 10 minutes and 10 hours, and more specifically 2 hours. Advantageously, this annealing is carried out at a temperature greater than 500°C, for example between 550°C and 700°C, and for example equal to 650°C, for approximately 30 minutes. Furthermore, this annealing process is carried out, for example, under an atmosphere of N2 or Ar. As an example, annealing can be carried out under a humid atmosphere, for example in an autoclave at a temperature of 500°C under a pressure of 250 bars where the water is then a supercritical fluid.

[0100] The structure obtained at this stage of the process is shown in [Fig.6].

[0101] Alternatively, prior to the bonding between the first bonding dielectric layer 108 and the second stack 126, a second bonding dielectric layer can be formed on the face of the second stack 126 intended to be bonded to the first bonding dielectric layer 108. The second bonding dielectric layer can be formed on top of the second stack 126. For example, the second bonding dielectric layer is similar to the first bonding dielectric layer 108, obtained by thermal oxidation. The embodiments previously described for the first bonding dielectric layer 108 can be applied to the second bonding dielectric layer. The second layer The dielectric bonding can be achieved by thermal oxide of the last semiconductor layer of the second stack 126, which contains, for example, silicon, to a thickness of up to 10 nm or even 3 nm. The subsequent bonding between the first and second dielectric bonding layers can then correspond to a direct oxide-to-oxide bond.

[0102] This second stack 126 can be made in the same way as the first stack 102, except that the hard mask 114, lithography, and ion etching through this hard mask are not implemented for this second stack 126. This second stack 126 also has a second thin dielectric layer on its surface. The crystal orientation of this second stack 126 can be different from that of the first stack 102.

[0103] In this embodiment, the thicknesses of the first and second dielectric bonding layers are such that the sum of these thicknesses is less than or equal to 50 nm, or advantageously less than or equal to 30 nm, or 20 nm, or 15 nm, or 6 nm. The thicknesses of the first and second dielectric bonding layers may or may not be equal to each other. In this embodiment, the total thickness formed by the assembly of the first and second dielectric bonding layers corresponds to the desired dielectric insulation thickness between the pMOS and nMOS transistors.

[0104] According to a particular example, prior to the bonding between the first dielectric bonding layer 108 and the second stack 126, the first dielectric bonding layer 108 can be thinned, for example, such that its remaining thickness is equal to 3 nm. This thinning can be achieved by performing an over-etching during the removal of the bulk layer 112 or by means of HF etching.

[0105] The structure produced is then turned over and the temporary support layer 122 is removed. This removal may involve, for example, grinding or mechanical thinning to a thickness of a few microns, for example 5 pm, then wet etching with TMAH (having a concentration of 25%) at 70°C, or dry etching, may be carried out using the temporary bonding layer 120 as a stop layer.

[0106] The structure obtained at this stage of the process is shown in [Fig.7].

[0107] The temporary bonding layer 120 as well as the dielectric material of The filler 118, placed in the trenches 116, is then removed, for example, by etching using a 10% HF solution. When the thickness of the temporary bonding layer 120 is 200 nm and the thickness of the dielectric filler material 118 is also approximately 200 nm, and given that the etching speed of a 10% HF solution is about 100 nm / min for oxide deposited and annealed at about 500°C, the etching time is The etching process takes approximately 4 minutes. The parameters for this etching are chosen to avoid etching the first dielectric bonding layer 108 and risking lateral etching of this layer. To avoid this risk, it is possible to stop the etching before reaching the last semiconductor layer of the first stack 102, for example, by stopping the etching at approximately half the thickness of the last semiconductor layer of the first stack 102.

[0108] The structure obtained at this stage of the process is shown in [Fig.8].

[0109] The hard mask 114 is then used to perform an etching and extend The trenches 116 cut through at least the first dielectric bonding layer 108 and the second stack 126, such that remaining portions of the third or fourth semiconductor layers 128, 130 of the second stack 126 form nanosheets configured to form active regions of CFET transistors. This etching corresponds, for example, to ion etching or reactive ion etching, and no additional photolithography step is required, the hard mask 114 being reused for this etching in self-alignment with the definition of the trenches 116.

[0110] The structure obtained at this stage of the process is shown in [Fig.9].

[0111] The hard mask 114 can then be removed, for example by implementing a another ionic engraving, as shown in [Fig. 10]. Alternatively, the hard mask 114 can be retained.

[0112] CFET transistors are completed from the obtained nanosheet stacks. The steps implemented to complete the realization of CFET transistors are, for example, similar to those described in the document by S. Liao et al., “Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Eogic Technology Scaling” 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, or in the document “3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore's Law Scaling”, C.-Y. Huang et al., Technical Digest, International Electron Devices Meeting, IEDM, 2020, pp. 20.6.1-20.6.4.In general, the fabrication of CFET transistors from the structure obtained after the previously described steps involves at least the fabrication of the gates. This includes selective etching of the remaining portions of the second and fourth semiconductor layers 106, 130 relative to the layers 104, 128, and the deposition of a gate dielectric and a gate conductor around the remaining portions of the first and third semiconductor layers 104, 128, and the implementation of selective epitaxies to form the sources and drains of the transistors. Other steps, not detailed here, are also implemented to complete the fabrication of the CFET transistors.

[0113] Alternatively, the fabrication of CFET transistors from the structure obtained after the steps described above may include at least the fabrication of gates which includes selective etching of the remaining portions of the first and third semiconductor layers 104, 128 with respect to layers 106, 130, and deposition of a gate dielectric and a gate conductive material around a portion of the remaining portions of the second and fourth semiconductor layers 106, 130, and the implementation of selective epitaxies to form the source and drain of the transistors. Other steps not detailed here are also implemented to complete the fabrication of the CFET transistors.If selective etching of layers 106 and 128 with respect to layers 104 and 130, or selective etching of layers 104 and 130 with respect to layers 106 and 128 is desirable, it is possible to carry out this selective etching in two stages, alternately protecting the sides of the parts of the fins formed by the remaining portions of the first and second stacks 102, 126 and the other layers which must be preserved during each of these etchings.

[0114] A second example of a method for realizing a CFET transistor device is described below in relation to Figures 11 to 17.

[0115] Unlike the previous example in which the first stack 102 is directly formed on a first SOI-type substrate 110 having a buried dielectric layer of thin thickness, corresponding substantially to the thickness required to form the first bonding dielectric layer 108 (less than 50 nm in the described example), the first stack 102 is here formed on a first SOI-type substrate 110 having a thick buried dielectric layer, referenced 136 in [Fig. 11], and a thick semiconducting surface layer, referenced 138 in [Fig. 11]. For example, the thickness of the buried dielectric layer 136 is 145 nm, and that of the semiconducting surface layer 138 is 100 nm.

[0116] The first bonding dielectric layer 108 is formed on the semiconducting surface layer 138. In this example, the semiconducting surface layer 138 is first thinned. This thinning can correspond to a first thermal oxidation, creating an oxide-based dielectric layer with a thickness, for example, of approximately 160 nm. After the removal of this dielectric layer, the remaining thickness of the semiconducting surface layer 138 is, in this example, 20 nm. A second thermal oxidation can then be carried out, such that the remaining thickness of the semiconductor of the semiconducting surface layer 138 is 17.5 nm, as in the first embodiment. The oxide layer formed on the semiconducting surface layer 138 by this second thermal oxidation corresponds to the first dielectric bonding layer 108 and has, in this example, a thickness of 5 nm (see [Fig. 12]).

[0117] An etching layer 140 is then deposited on the first dielectric bonding layer 108 (see [Fig. 13]). The material of the etching layer 140 is configured so that it can be selectively etched with respect to the first dielectric bonding layer 108. For example, the etching layer may be a polycrystalline or amorphous silicon layer with a thickness of 100 nm, for example deposited by LPCVD at 700°C.

[0118] Another dielectric layer 142 can then be deposited on the etched layer 140. For example, this other dielectric layer 142 corresponds to a TEOS oxide deposited at 400 °C and having a thickness of 500 nm. A densification anneal is then carried out, for example at a temperature of 800 °C, to densify it. A CMP can then be carried out to remove part of the dielectric layer 142 and prepare a free surface of the dielectric layer 142 for bonding. For example, this CMP can be carried out so as to remove a thickness of approximately 100 nm from the dielectric layer 142. Alternatively, this other dielectric layer 142 may not be produced.

[0119] A mechanical support substrate 144 is then bonded to the dielectric layer 142 (or directly to the etching layer 140 in the absence of the dielectric layer 142). For example, the mechanical support substrate 144 may be a semiconductor substrate subjected to thermal oxidation, forming, on each side of the substrate, an oxide layer with a thickness, for example, of 145 nm. The mechanical support substrate 144 is, for example, bonded to the dielectric layer 142, and then a consolidation anneal is carried out, for example, at a temperature of 1100 °C (see [Fig. 14]).

[0120] The bulk layer 112 of the first substrate 110 is then removed, for example by grinding until a remaining thickness of the bulk layer is on the order of 10 pm, and then by chemical etching, for example based on HF / HNO3 with concentrations of 1% by volume of an HF solution (for example at 49% HF) and an HNO3 solution (for example at 70% HNO3), carried out only on the side of the first substrate 110. The chemical etching is stopped on the buried dielectric layer 136 (see [Fig. 15]).

[0121] The buried dielectric layer 136 is then etched, the etching being stopped on the semiconducting surface layer 138 (see [Fig. 16]). This etching is carried out, for example, with a 10% HF solution.

[0122] Alternatively, it is possible that the thinning of the semiconducting surface layer 138 is not carried out before the fabrication of the first dielectric bonding layer 108. In this case, this thinning can be carried out after the etching of the buried dielectric layer 136 (see [Fig. 17]). According to another variant, the semiconducting surface layer 138 can have the desired thickness from the outset, with no thinning of this layer being implemented in this case.

[0123] The process is then continued in a manner substantially similar to the first example described above, by implementing the following steps:

[0124] - realization of the first stacking 102 by epitaxy from the surface layer semiconductor 138;

[0125] - realization of the hard mask 114 on the first stack 102;

[0126] - engraving of trenches 116;

[0127] - deposition of the filling dielectric material 118, which can also form the temporary adhesive layer 120;

[0128] - securing the temporary support layer 122 to the first stack 102 (via the temporary bonding layer 120 if this layer is present);

[0129] - removal of the mechanical support substrate 144 by lapping and / or chemical etching using layers 142, 140 and 108 as successive stopping layers;

[0130] - bonding of the first dielectric bonding layer 108 to the second stack 126 (possibly via the second dielectric bonding layer);

[0131] - consolidation annealing;

[0132] - removal of the temporary support layer 122;

[0133] -removal of the temporary adhesive layer 120 if present;

[0134] - removal of the filling dielectric material 118;

[0135] - extension of trenches 116 through the second stack 126;

[0136] - possibly, removal of the hard mask 114.

[0137] The different variants previously described for the first embodiment can be applied to this second embodiment.

[0138] In the preceding embodiments, the temporary support layer 122 is bonded to the temporary adhesive layer 120. As an alternative to these examples, it is possible to implement, between the steps of deposition of the dielectric filler material 118 and the bonding of the temporary support layer 122 to the first stack 102, a mechano-chemical polishing process that removes the temporary adhesive layer 120 and also attacks the dielectric filler material 118 so as to form pits 146 on the exposed surfaces of the portions of the dielectric filler material 118. The depth of these pits 146 can be greater than 5 nm, or even greater than 10 nm, so that the temporary support layer 122 is bonded only to the hard mask 114 and to avoid, during the bonding of the temporary support layer 122 at the first stacking 102, any contact between the temporary support layer 122 and the filling dielectric material 118.

[0139] In this embodiment, the temporary support layer 122 is chosen such that it is transparent to at least one wavelength of a laser that will be used subsequently to detach the temporary support layer 122 from the hard mask 114. For example, the temporary support layer 122 may be a sapphire substrate several hundred microns thick, such a layer being able to be detached using a laser with a wavelength, for example, of 266 nm, the beam of which is directed to the bonding interface between the temporary support layer 122 and the hard mask 114. In this embodiment, the hard mask 114 may comprise PAIN and / or TiN and / or WN. Alternatively, the temporary support layer 122 may comprise silicon, and the detachment of such a layer may be implemented as described in document WO 2024 / 104550 A1.

[0140] As an alternative to the various examples previously described, the buried dielectric layer of the first SOI-type substrate 110 can correspond to an ONO (Oxide-Nitride-Oxide) stack, with the oxide layer of this stack positioned against the semiconducting surface layer corresponding to the first bonding dielectric layer 108. The thickness of this ONO stack can be greater than 100 nm. The nitride layer of the ONO stack can serve as an additional arrest layer during the removal of the bulk layer 112 of the first substrate 110, this nitride layer then being able to be removed, for example, using an orthophosphoric acid solution with arrest on the first bonding dielectric layer 108.

[0141] In all examples and variations, between the two stacks of nanosheets used to fabricate the CFET transistors, a very thin dielectric (thickness less than 50 nm) is present, which could create bonding defects during annealing at a temperature greater than or equal to 500°C. However, the areas of this thin dielectric are very small (because they are located only directly above the nanosheets) and surrounded by larger areas of thicker dielectric, which prevents the formation of bubbles at the bonding interface.

[0142] Furthermore, the same hard mask can be used for both the engraving of the first stack and that of the second stack in a self-aligned manner, and this without having to carry out a new photolithography for the engraving of the second stack.

[0143] The process for making the device described above makes it possible to obtain, between the first and second stacks 102, 112, a dielectric portion of small thickness, for example less than 50 nm, consolidated and without defects at the bonding interface.

[0144] Cleaning and / or preparation and / or treatment steps other than those previously described may be implemented.

[0145] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0146] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for making a CFET transistor device, comprising at least: - forming, on a first bonding dielectric layer (108), a first stack (102) comprising at least a first semiconductor layer (104) and a second semiconductor layer (106) arranged one on top of the other, one of the first and second semiconductor layers (104, 106) being configured to be selectively etched with respect to the other; - etching, through the first stack (102), trenches (116) such that remaining portions of the first or second semiconductor layer (104, 106) form nanosheets configured to form active regions of the CFET transistors; - depositing at least one filling dielectric material (118) in the trenches (116);- bonding of the first dielectric bonding layer (108) to a second stack (126) comprising at least a third semiconducting layer (128) and a fourth semiconducting layer (130) arranged one on top of the other, one of the third and fourth semiconducting layers (128, 130) being configured to be selectively etched with respect to the other; - annealing carried out at a temperature greater than or equal to 200°C.

2. Method according to claim 1, wherein the bonding of the first dielectric bonding layer (108) to the second stack (126) corresponds to a direct hydrophilic bonding.

3. A method according to any one of the preceding claims, wherein the thickness of the first dielectric bonding layer (108) is less than or equal to 50 nm.

4. A method according to any one of the preceding claims, wherein the bonding of the first dielectric bonding layer (108) to the second stack (126) corresponds to a bonding of the first dielectric bonding layer (108) to a second bonding dielectric layer to which the second stack (126) is attached, the second bonding dielectric layer being disposed between the first bonding dielectric layer (108) and the second stack (126).

5. A method according to claim 4, wherein the total thickness of the first (108) and second dielectric bonding layers bonded to each other is less than or equal to 50 nm.

6. A method according to any one of the preceding claims, further comprising, between the making of the first stack (102) and the engraving of the trenches (116) through the first stack (102), making a hard mask (114) on the first stack (102), the trenches (116) then being engraved in the first stack (102) according to the pattern defined by the hard mask (114).

7. A method according to any one of the preceding claims, further comprising, after annealing, an engraving of the dielectric filling material (118) disposed in the trenches (116).

8. A method according to claims 6 and 7, further comprising, after etching the dielectric filling material (118) disposed in the trenches (116), etching, according to the pattern defined by the etching mask (114), through at least the first dielectric bonding layer (108) and the second stack (126) such that remaining portions of the third or fourth semiconducting layers (128, 130) form nanosheets configured to form active regions of CFET transistors.

9. A method according to any one of the preceding claims, wherein the first bonding dielectric layer (108) corresponds to an oxide layer embedded in a first SOI-type substrate (110), and further comprising, between the deposition of the filling dielectric material (118) and the bonding of the first bonding dielectric layer (108) to the second stack (126): - bonding of a temporary support layer (122) to the first stack (102) such that the first stack (102) is disposed between the temporary support layer (122) and the first substrate (110); - removal of a bulk layer (112) from the first substrate (110), exposing a face (124) of the first layer bonding dielectric (108) intended to be bonded to the second stack (126).

10. A method according to claim 9, wherein the first SOI-type substrate (110) comprises a buried dielectric stack including a semiconductor nitride layer disposed between first and second buried oxide layers, the first bonding dielectric layer (108) corresponding to the second buried oxide layer disposed between a semiconducting surface layer of the first substrate (110) and the semiconductor nitride layer, and further comprising, between the removal of the bulk layer (112) of the first substrate (110) and the bonding of the first bonding dielectric layer (108) to the second stack (126), a removal of the first buried dielectric layer and the semiconductor nitride layer.

11. A method according to any one of claims 1 to 8, further comprising, prior to the first stacking (102) on the first dielectric bonding layer (108): - forming the first dielectric bonding layer (108) on a semiconducting surface layer of a first SOI-type substrate (110); - depositing an etching layer (140) on the first dielectric bonding layer (108), the etching layer (140) comprising a material configured to be selectively etched with respect to the first dielectric bonding layer (108); - bonding a mechanical support substrate (144) to the etching layer (140); - removing a bulk layer (112) and a buried dielectric layer (136) from the first substrate (110);and further comprising, between the deposition of the dielectric filling material (118) and the bonding of the first dielectric bonding layer (108) to the second stack (126): - bonding of a temporary support layer (122) to the first stack (102) such that the first stack (102) is disposed between the temporary support layer (122) and the mechanical holding substrate (144); - removal of the mechanical holding substrate (144).

12. A method according to any one of claims 9 to 11, wherein: - the bonding of the temporary support layer (122) to the first stack (102) includes bonding the temporary support layer (122) to a temporary bonding layer (120) disposed on the first stack (102), and - the temporary support layer (122) is removed after annealing.

13. A method according to claim 6 and according to any one of claims 9 to 11, further comprising, between the deposition of the dielectric filling material (118) and the bonding of the temporary support layer (122) to the first stack (102), the implementation of a mechano-chemical polishing forming hollows (146) on the surface of the portions of the dielectric filling material (118), and in which: - the bonding of the temporary support layer (122) to the first stack (102) includes a bonding of the temporary support layer (122) to the hard mask (114), and - the temporary support layer (122) is detached, after annealing, by laser at a wavelength at which the temporary support layer (122) is transparent.

14. A method according to any one of the preceding claims, wherein the first and third semiconductor layers (104, 128) comprise silicon, and / or wherein the second and fourth semiconductor layers (106, 130) comprise SiGe.

15. A method according to any one of the preceding claims, wherein the first stack (102) comprises several first semiconductor layers (104) and several second semiconductor layers (106) arranged alternately on top of each other, and / or wherein the second stack (126) comprises several third semiconductor layers (128) and several fourth semiconductor layers (130) arranged alternately on top of each other.

16. A method according to any one of the preceding claims, further comprising, after annealing, etching remaining portions of the first or second semiconductor layer (104, 106) and / or etching remaining portions of the third or fourth semiconductor layer (128, 130), and deposition of a gate dielectric and a gate conductive material around at least a portion of the remaining portions of the semiconductor layers forming CFET transistor channels, and epitaxy from the flanks of the remaining semiconductor layers and forming source and drain regions of CFET transistors.