Quantum device and associated manufacturing process

Abstract

Title: Quantum Device and Associated Manufacturing Method The invention relates to a quantum device (100) comprising, stacked along a z-direction, a support layer (S), an active layer (10) based on a semiconductor material overlying the support layer and having a thickness e10, a dielectric layer (15) overlying the active layer, and a network of first gates (20) overlying the dielectric layer, the first adjacent gates of the network being separated from each other by inter-gate spaces (30), the device (1) being characterized in that the active layer (10) comprises, below the inter-gate spaces (30), thinned regions (11) based on the semiconductor material, said thinned regions (11) each having at least a thickness e11 > 0 such that e11 < e10. Figure for the abstract: Fig. 1G

Description

Title of the invention: Quantum device and associated manufacturing process. Technical field

[0001] The present invention relates to the technical field of quantum information. It finds, for example, a particularly advantageous application in the encoding of information on the spin of "quantum bits" or "Qubits". STATE OF THE ART

[0002] Quantum dots form the basic building blocks of a quantum electronic device. Quantum dots are typically formed in an active layer of semiconductor material alternating with layers of other materials, along at least one spatial direction. In this active layer, potential wells are implemented to confine carriers, electrons or holes, in the three dimensions of space. Quantum information can then be encoded via the spin of the carrier. These are then referred to as spin qubits.

[0003] According to one approach, electrons are confined by field effect under the effect of gate electrodes similar to those used in transistor structures, and the information is encoded in the spin of these electrons. These control gates are arranged above the set of quantum dots.

[0004] Electrostatic confinement is often insufficient to guarantee proper positioning of the quantum dots under the grid, thus creating charge disorder. This charge disorder makes it difficult to define, in a reproducible manner, the position of a quantum dot by adjusting the electrical potentials applied to the grids.

[0005] One solution to limit this charge disorder is to manage charge trapping at the interfaces between the active layer and the other layers. Another solution disclosed in document FR3143798 consists of supplementing the electrostatic confinement of the charges with lateral structural confinement by creating openings in the active layer between the gates, across the entire thickness of the active layer. However, this limits tunneling coupling between the qubits.

[0006] One object of the present invention is to provide an alternative solution aimed at improving the positioning of quantum dots under the grid. Another object of the present invention is to optimize the tunneling coupling between the quantum dots. SUMMARY

[0007] To achieve this objective, according to one embodiment, a quantum device is provided comprising, in a stacking arrangement along a direction z: • a support layer, • an active layer based on a semiconductor material, placed above the support layer and having a thickness elO, • a dielectric layer overlying the active layer, • a network of first grids above the dielectric layer, the first adjacent grids of the network being separated from each other by so-called inter-grid spaces,

[0008] Advantageously, the active layer comprises, below the inter-grid spaces, thinned areas based on the semiconductor material, said thinned areas each having at least a thickness el 1 > 0 such that el 1 < el0.

[0009] This quantum device thus improves the structural confinement of quantum dots within the active layer. Vertical confinement, along the z-direction, is higher in the thinned regions. This limits the mobility of the quantum dots within the active layer. This structural confinement therefore strengthens the control over the position of the quantum dots. This makes the positioning of the quantum dots under the first grids more favorable. This structural confinement of the quantum dots, orthogonal to the plane of the active layer and referred to as vertical confinement hereafter, notably improves the precision and homogeneity of the positioning of the quantum dots. This significantly reduces the impact of charge disorder on the qubits. Thanks to vertical confinement, the probability of quantum dot fusion is significantly decreased.Furthermore, the non-zero thickness of the thinned regions advantageously allows for the maintenance of satisfactory tunneling coupling between two neighboring quantum dots.

[0010] The invention also provides, according to a second aspect, a method for manufacturing such a quantum device. This method comprises: • the supply of a support layer and an active layer based on a semiconductor material overlying the support layer, said active layer having a thickness elO, • the formation of a dielectric layer overlying the active layer, • the formation, on the dielectric layer, of a network of first grids, the first adjacent grids of the network being separated from each other by spaces called inter-grid spaces, • a only partial thinning of the active layer, along the z direction directly above the inter-grid spaces, so as to form the thinned zones in the active layer.

[0011] The advantages described above with regard to the device apply mutatis mutandis to the process according to the invention. BRIEF DESCRIPTION OF THE FIGURES

[0012] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0013] [Fig.1A] [Fig.1B] [Fig.1C] [Fig.1D] [Fig.1E] [Fig.1F] [Fig.1G] Figures IA to IG illustrate in an xz plane, cross-sections representing different stages of the manufacturing process of a quantum device according to an example of embodiment.

[0014] [Fig.2A] [Fig.2B] [Fig.2C] [Fig.2D] [Fig.2E] [Fig.2F] [Fig.2G] [Fig.2H] [Fig.2I] [Fig.2J] Figures 2A to 2J schematically illustrate in an xz plane, cross-sections representing different stages of the manufacturing process of a quantum device according to another example of embodiment.

[0015] [Fig.3A] [Fig.3B] [Fig.3C] [Fig.3D] [Fig.3E] [Fig.3F] [Fig.3G] [Fig.3H] The Figures 3A to 3H schematically illustrate in an xz plane, cross-sections representing different stages of the manufacturing process of a quantum device according to another example of implementation.

[0016] [Fig.4] Fig.4 schematically illustrates a quantum device from a top view final according to an example of implementation.

[0017] [Fig.5] Fig.5 schematically illustrates in an xz plane, a cross-section of a final quantum device according to an example of an embodiment.

[0018] [Fig.6A] [Fig.6B] [Fig.6C] Figures 6A to 6C illustrate simulation results of the position of neighboring quantum dots in a quantum device according to the present invention.

[0019] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the thicknesses and / or dimensions of the different layers, patterns and reliefs are not representative of reality. DETAILED DESCRIPTION

[0020] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0021] According to one example, at least one thickness el 1 of the thinned regions is such that el 1 < 0.8*el0. Controlling the thickness of the thinned regions allows both adjusting the structural confinement of the quantum dots and optimizing the tunneling coupling between neighboring quantum dots.

[0022] According to one example, the active layer is silicon-based, and the thickness el0 of the active layer is on the order of 10 nm. The thickness el1 of the thinned areas is here between 8 nm and 2 nm, preferably on the order of 6 nm. When the thickness el1 of the thinned regions is less than 2 nm, structural confinement within the thinned region is strong and tunneling coupling is reduced. When the thickness el1 of the thinned regions is greater than 8 nm, structural confinement is weak and tunneling coupling is increased. Quantum dot fusion may occur more readily. For this set of parameters, the best compromise between satisfactory tunneling coupling and satisfactory structural confinement is obtained for a thickness el1 around 6 nm, corresponding to a material removal on the order of 4 nm. The residual thickness el1 is preferably on the order of 4 nm ± 2 nm to prevent quantum dot fusion.

[0023] According to one example, the inter-grid spaces can be between 5 nm and 40 nm, typically for grids having widths of 5 nm to 40 nm respectively.

[0024] According to one example, the quantum device further comprises an array of second grids arranged in the inter-grid spaces alternately with the first grids, such that each second grid surmounts a thinned region. The first grids, or first-level grids, allow electrostatic control of the position of the quantum dots. The second grids, or second-level grids, which are arranged above the thinned regions, allow control of the tunneling coupling between neighboring quantum dots.

[0025] According to one example, the second grids have one end located below a plane passing through an upper face of the active layer. This allows the second grids to be brought closer to the active layer, at the level of the thinned areas. This further increases the control of the tunnel coupling.

[0026] According to one example, the quantum device comprises at least one spacer layer covering the flanks of the first grids, said at least one spacer layer being interposed between the second grids and the thinned regions. The spacer layer notably provides isolation between the first and second grids, thereby improving the performance of the device.

[0027] According to one example, at least one spacer layer is in direct contact with the thinned areas, and preferably directly in contact with the second grids. When the spacer layer is made of silicon nitride, there is no oxide layer between the spacer layer and the active layer.

[0028] According to one example, the device comprises at least one additional layer overlying the active layer and in direct contact with the active layer. According to one example, the additional layer and the substrate are SiGe-based and the active layer is Si- or Ge-based, such that the substrate, the active layer and the additional layer form a SiGe / Si / SiGe or SiGe / Ge / SiGe heterostructure.

[0029] According to one example, a first part of the thinned areas has a first thickness el 11 < el0, and a second part of the thinned areas has a second thickness ell2 <el0. Les épaisseurs e 111 etell2 sont différentes entre elles. Cela permet de moduler localement le confinement structurel dans la couche active.

[0030] According to one example, the thinned areas of the first part are located under inter-grid spaces situated between first grids along a first direction x. According to another example, the thinned areas of the second part are located under inter-grid spaces situated between first grids along a second direction y. The structural confinement is not uniform along x and y.

[0031] According to one example, the thinning is achieved, after selective removal of the dielectric layer in the inter-gate spaces, by a local and only partial oxidation along the z-direction of the active layer. The selective removal of the dielectric layer exposes the active layer directly above the inter-gate spaces. This allows easier access to the active layer. The thinning by oxidation locally reduces the thickness of the active layer based on the semiconductor material. A thinned zone of the active layer, delimited by an oxidized zone of the active layer, is thus formed.

[0032] According to one example, during thinning by oxidation, the sides of the first grids are also oxidized. This does not interfere with the operation of the first grids and allows for the addition of an insulating layer between the first and second grids.

[0033] According to one example, the thinning is achieved, after selective removal of the dielectric layer in the inter-grid spaces, by a only partial etching along the z direction of the active layer.

[0034] According to one example, the etching of the active layer is a wet etching.

[0035] According to one example, the process further comprises, before thinning the layer Actively, a first spacer layer is deposited on the flanks of the first grids to protect them during thinning. This first spacer layer typically forms a first spacer only on the flanks of the first grids. Besides protecting the grid flanks during thinning, this first spacer also allows control over the lateral dimensions of the final thinned regions. This helps to avoid or limit the formation of a "bird's beak" when thinning is performed by oxidation. By adjusting the thickness of this first spacer, the width of the thinned region can be reduced. This also allows for adjustment of the tunneling coupling strength between neighboring quantum dots.

[0036] According to one example, the process further comprises, after thinning the active layer, a deposit of a second layer of spacer on the sides of the first grids and on exposed parts of the thinned areas.

[0037] According to one example, the process further comprises, after deposition of the second layer of spacer, the formation of a network of second grids arranged in the inter-grid spaces, alternating with the first grids.

[0038] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposit or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0039] A substrate, film, or layer "based" on a material A is understood to mean a substrate, film, or layer comprising only that material A or that material A and possibly other materials, for example, dopant elements or alloying elements. Thus, a spacer based on silicon nitride (SiN) may, for example, comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even silicon oxynitride (SiON).

[0040] The term "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 20.

[0041] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated, the adjective "successive" does not necessarily imply, although this is generally preferred, that the steps follow each other immediately; intermediate steps may separate them.

[0042] Furthermore, the term "step" refers to the execution of a part of the process, and can designate a set of sub-steps.

[0043] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may, in particular, be followed by actions related to a different step, and other actions from the first step may be repeated later. Thus, the term "step" does not necessarily imply unitary actions that are inseparable in time and in the sequence of phases of the process.

[0044] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" means an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting an etching speed of material A greater than the etching speed of material B.

[0045] A preferably orthonormal coordinate system, comprising the x, y, z axes, is shown in the accompanying figures.

[0046] In this patent application, the terms thickness for a layer or film and height for a device or structure will be preferred. Thickness is measured along a direction normal to the principal extension plane of the layer or film. Thus, a surface layer of silicon (topSi) typically has a thickness along the z-axis. A grid pattern formed on such a surface layer has a height along the z-axis. The relative terms "on," "above," "above," "below," "underlying," and "below" refer to positions measured along the z-axis. A "lateral" dimension corresponds to a dimension along a direction of the xy-plane. A "lateral" or "lateral" extension is understood to be an extension along one or more directions of the xy-plane. In this patent application, the thinned areas are typically obtained by material removal and form a "recess" or indentation in the active layer.This recess is not necessarily flat and may have a curved surface. The perimeter or edges of the thinned areas may be thicker. When measuring the thickness of the thinned areas, the measurement is taken at the lowest point of the curved surface. The thickness of the thinned areas therefore corresponds to the minimum thickness measured.

[0047] An element located "in line with" or "directly above" another element means that these two elements are both located on the same line perpendicular to a plane in which extends mainly a lower or upper face of a substrate, that is to say on the same line oriented vertically on the cross-sectional figures.

[0048] The terms "approximately", "around", "in the order of" mean to the nearest 10%, and preferably to the nearest 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the bounds are inclusive, unless otherwise stated.

[0049] The following description presents an example of implementing the method according to the invention in the context of developing a complex 3D device. The scope of this description is obviously not limiting to the invention.

[0050] The manufacturing steps for a quantum device 100, in particular a quantum device with quantum dots or spin qubits, are now described. Figures IA to IG describe the manufacturing process for device 100 according to a first embodiment of the invention.

[0051] As illustrated in [Fig. 1A], the method comprises supplying a support layer S having a top face extending in an xy plane. The layer The support layer S is, for example, based on silicon oxide. The support layer S is topped, in a z direction perpendicular to the x and y directions, by an active layer 10 based on a semiconductor material. The active layer 10 is, for example, a thin silicon film (topSi) extending parallel to the xy plane.

[0052] More generally, the support layer S and the active layer 10 may correspond in part to a substrate of the type SOI (Silicon On Insulator), GeOI (Germanium On Insulator), or SGOI (Silicon-Germanium On Insulator). These known substrates comprise, according to the terminology commonly used by those skilled in the art, a thick silicon layer called "Si bulk" (not shown in the figures), a silicon oxide layer called "BOX" (Burried Oxide), and a thin surface layer, respectively based on silicon, germanium, or silicon-germanium. The BOX oxide layer may correspond to the support layer S. The thin surface layer may advantageously correspond to the active layer 10. The active layer 10 may preferably be based on 28Si when this layer is intended to accommodate electron spin qubits.

[0053] The active layer 10 has a thickness elO. The thickness elO can be between 5 nm and 50 nm, preferably on the order of 10 nm. The thickness of the support layer S can be on the order of a few hundred nanometers.

[0054] Other semiconductor materials can be considered for the active layer 10. In particular, when this active layer 10 is intended to accommodate hole spin qubits, it can be formed of Sii_xGex with x preferably varying between 0% and 70%.

[0055] A first dielectric layer 15 is then formed on the active layer 10, either by deposition or by oxidation. This dielectric layer 15 extends parallel to the xy plane and is superimposed along the z-direction on the active layer 10 and the support layer S. By way of example, the material of the first dielectric layer 15 may be based on: SiO2, HfO2, or Al2O3. The first dielectric layer 15 may be based on a high-permittivity dielectric material or a combination of dielectric materials, for example, SiO2 and HfO2.

[0056] The process further includes a step of forming, on the first dielectric layer 15, a network of first grids 20. This step includes substeps not shown, which are well known to those skilled in the art. The formation of the first grids 20 includes the deposition of a grid stack comprising: a first grid layer 22a on top of the first dielectric layer 15, a second grid layer 22b on top of the dielectric grid layer 22a, a protective layer 23 on top of the second grid layer 22b, and an etching mask 24, also called a hard mask, which allows the first grids 20 to be structured.

[0057] The first gate layer 22a can be TiN-based. The second gate layer 22b can be polycrystalline silicon-based. According to one possibility, the first and second gate layers 22a, 22b form a single layer based on a single material, for example Si, TiN, or a metal. The protective layer 23 is typically silicon oxide-based. The hard mask 24, which remains in place after the gate is etched, is typically silicon nitride (SiN)-based. Its role is to protect the top of the first gates 20 from damage during the subsequent steps, particularly the etching steps.

[0058] The network of first grids 20 is then formed by etching the grid stack, stopping at the first dielectric layer 15. The first grids 20 thus obtained are separated from each other by spaces 30 called "inter-grid spaces". At this stage, the edges of the first grids 20 and the first dielectric layer 15 are exposed within the inter-grid spaces 30.

[0059] After the formation of the network of the first grids 20, the process comprises a partial thinning of the active layer 10 along the z-direction. This thinning is carried out only directly above the inter-grid spaces 30, to form thinned zones 11. The thinning can be implemented according to different variations, which are described below. Figures IB to IG illustrate the different stages of the process according to a first embodiment of the present invention.

[0060] As illustrated in [Fig. 1B], according to the first embodiment, the process comprises, following the formation of the first grids 20, a step of selectively removing the dielectric layer 15 from the inter-grid spaces 30. This removal allows the material of the first dielectric layer 15 to be selectively removed from the materials of the first grids 20 and the active layer 10. This removal exposes portions of the surface of the active layer 10 located directly above the inter-grid spaces 30. This allows direct access to the active layer 10 during the thinning step. The thickness of the active layer 10 in these exposed portions is minimally, if at all, affected by the process steps described above. It is through the thinning step that this thickness is modified in a controlled and targeted manner.

[0061] As illustrated in [Fig. 1C], according to the first variant, thinning is achieved by local oxidation by introducing, through the inter-grid spaces 30, an oxidizing agent that interacts with the material of the active layer 10 to form first oxidized regions 17 in the active layer 10. These first oxidized regions 17 extend laterally along the x and y directions below the inter-grid spaces 30, and vertically along the z direction, without reaching the support layer S. These first oxidized regions 17 delimit thinned zones 11 in the active layer 10. This thinning is achieved only partially along the z-direction such that the thinned regions 11 formed at the end of oxidation have at least a non-zero thickness el 1. Oxidation of the active layer 10 preferably occurs only below the inter-gate gaps 30. The thinned regions 11 are self-aligned with the inter-gate gaps 30. The thinned regions 11 are also homogeneous with each other. The consumption of semiconductor material in the active layer 10, i.e., the thickness of the oxidized regions 17, is on the order of 2 nm to 6 nm.

[0062] During thinning by oxidation, depending on the materials of the first grids 20, the exposed flanks of the first grids 20 can also be oxidized, thus forming second oxidized zones 21. These second oxidized zones 21 do not alter the operation of the first grids 20, and can serve as an insulating layer for the flanks of the first grids.

[0063] As illustrated in [Fig. 1D], the process can, according to the first embodiment, comprise the deposition of a spacer layer 50, following the formation of the thinned zones 11 by oxidation, on the first grids 20 and in the inter-grid spaces 30. This spacer layer 50 thus covers the tops of the first grids 20, the first oxidized zones 17, and the second oxidized zones 21. The spacer layer 50 protects the sides of the first grids 20. The spacer layer 50 also provides electrical insulation for the first grids 20. The spacer layer 50 can be based on silicon nitride SiN or a dielectric material with a low dielectric constant, for example, based on SiCO₃.

[0064] As illustrated in [Fig. 1E], a second dielectric layer 16 is then deposited on the spacer layer 50 so as to cover the first grids 20 and fill the inter-grid spaces 30. The second dielectric layer 16 may, for example, be based on an oxide, preferably SiO2.

[0065] As illustrated in [Fig. 1F], a conventional lithography / etching step is performed on the second dielectric layer 16 to define apertures 60 through the dielectric layer 16 and the inter-grid spaces 30. The apertures 60 extend along the z-direction, directly above the inter-grid spaces 30, to the surface of the spacer layer 50 at the bottom of the inter-grid spaces 30.

[0066] As illustrated in [Fig. 1G], the process further comprises the formation of a network of second gates 40. The formation of the second gates 40 includes the deposition of a heavily doped metallic or semiconducting layer onto the dielectric layer 16 and into the openings 60. This gate layer fills the openings 60. This gate layer can, for example, be based on polycrystalline silicon. This gate layer is then planarized, typically by chemical-mechanical polishing (CMP) with a stop on the second dielectric layer 16. The second gates 40 are thus formed in the inter-grid spaces 30 alternating with the first grids 20. Each second grid 40 surmounts a thinned zone 11.

[0067] A final quantum device 100 is thus obtained. This quantum device 100 comprises thinned regions 11 below the inter-grid spaces 30. These thinned regions 11 exhibit material continuity with the active layer 10. Each of these thinned regions 11 has at least one thickness el 1, such that 0 <el l<el0. De préférence, l’épaisseur ell des zones amincies 11 est telle que ell < 0,8*el0. Le dispositif 100 comprend en outre deux réseaux de grilles. Les premières grilles 20, dites grilles de premier niveau, permettent de réaliser sous l’application d’un potentiel électrique, un confinement électrostatique des particules chargées présentes dans la couche active 10 sous-jacente, pour former une boîte quantique sous chaque première grille 20. Comme décrit précédemment, ce confinement électrostatique est avantageusement renforcé par le confinement structurel provenant des zones amincies 11.This allows for precise control of the positioning of the quantum dots in the active layer 10.

[0068] In particular, in the thinned regions 11 where the active layer 10 is thinner, the position of the quantum dots is less favorable. Conversely, in the thicker parts of the active layer 10 below the first grids 20, the position of the quantum dots is favored. Thanks to this robust structural confinement, the electrostatic irregularities potentially present in the grid stacking have less of an effect on the position of the quantum dots.

[0069] The second grids 40, referred to as second-level grids, allow control of the potential barrier, or tunneling coupling, between two neighboring quantum dots, by applying voltage pulses. The electrostatic control exerted by the first grids 20, and the control of the tunneling coupling exerted by the second grids 40, are carried out independently of each other. This is ensured by the isolation between the two grid levels using the spacer 50 interposed between the first and second grids 20, 40.

[0070] Figures 2A to 2J schematically illustrate the steps of the manufacturing process of the quantum device 100 according to a second variant of the invention.

[0071] As illustrated in [Fig. 2A], following the formation of the first grids 20, and before the thinning of the active layer 10, according to the second variant, a first layer of spacer 50 can be deposited on the first grids 20 and in the inter-grid spaces 30. This first layer of spacer covers the sides of the first grids 20, thus ensuring their protection during the subsequent steps of the process, in particular the thinning step.

[0072] As illustrated in Figures 2B and 2C, the first spacer layer 50 is then etched into the inter-grid spaces 30. The lateral dimension of the spacer layer 50, along x on the cross-sections illustrated in the figures, allows control of the surface area of ​​the exposed active layer 10. The dielectric layer 15 is then selectively removed in the inter-grid spaces 30, thus exposing the underlying active layer 10. The selective removal of the dielectric layer 15 results in the exposure of the flanks of the remaining portions of the dielectric layer 15.

[0073] As illustrated in [Fig. 2D], according to one embodiment, the thinning can be achieved by only partial etching along the z-direction of the active layer 10. This thinning is thus achieved by removing material from the active layer 10 directly above the inter-grid spaces 30, thereby forming material depressions in the active zone 10 and delimiting thinned zones 11. The etching of the active layer 10 can be carried out, for example, by wet etching. This etching can also remove a portion of the exposed edges of the remaining dielectric layer 15.

[0074] As illustrated in [Fig. 2E], according to another embodiment, the thinning of the active layer 10 can be achieved by oxidation as described above. Oxidized zones 17 are thus formed in the active layer 10, these oxidized zones 17 delimiting thinned zones 11 in the active layer 10.

[0075] The spacer layer 50 covering the flanks of the first grids 20 notably protects these flanks against oxidation or etching. This spacer layer 50 also allows, by adjusting its lateral dimension along x in the figures, control of the lateral dimensions of the oxidized areas 17 or the pits formed following etching. The lateral dimension of the thinned areas 11 is thus reduced. A more localized thinning of the active layer 10 can therefore be achieved. This makes it possible, for example, to strengthen the tunneling coupling between two neighboring quantum dots.

[0076] For the sake of simplicity, Figures 2F to 21 illustrate the subsequent steps of the process following thinning by etching. Those skilled in the art could easily adapt these figures to visualize the subsequent steps in the case of thinning by oxidation.

[0077] As illustrated in [Fig. 2F], following the formation of the thinned areas 11, a second layer of spacer 51 can be deposited on the first layer of spacer 50, and in the inter-grid spaces 30. This second layer of spacer 51 covers the exposed parts of the thinned areas 11, as well as the exposed edges of the remaining dielectric layer 15.

[0078] As illustrated in [Fig.2G], a second dielectric layer 16 is then deposited on the spacer 50, 51 so as to cover the first grids 20 and to fill the inter-grid spaces 30.

[0079] As illustrated in [Fig. 2H], a conventional lithography / etching step is carried out on the second dielectric layer 16, in order to define apertures 60 through the dielectric layer 16 and inter-grid spaces 30. The openings 60 extend along the z-direction, directly above the inter-grid spaces 30, to the surface of the spacer layer 51 at the bottom of the inter-grid spaces 30. Preferably, the openings 60 stop within the hollows formed in the active layer 10.

[0080] As illustrated in [Fig. 2I], a network of second grids 40 is then formed. The formation of the second grids 40 comprises, as before, the deposition of a grid layer on the dielectric layer 16 and in the openings 60. This grid layer is then planarized, typically by chemical-mechanical polishing (CMP) with a stop on the second dielectric layer 16. Second grids 40 are thus formed in the inter-grid spaces 30, alternating with the first grids 20. Each second grid 40 overlies a thinned zone 11.

[0081] A final quantum device 100 is thus obtained with etching thinning, as illustrated in [Fig. 2I]. In this example, the second grids 40 can be closer to the thinned areas 11, being separated from them only by the second spacer layer 51. Preferably, the second spacer layer 51 can be in direct contact with the thinned areas 11 and the second grids 40. Advantageously, these second grids 40 can each have a lower end located below a plane passing through an upper face of the active layer 10. In other words, these lower ends are located at least partially within the pits formed in the active layer 10 as a result of etching thinning. This proximity between the second grids 40 and the thinned areas 11 makes it possible to improve the control of tunneling coupling between two neighboring quantum dots.

[0082] Fig. 2J illustrates the final quantum device 100 obtained according to the second variant and with thinning by oxidation.

[0083] Figures 3A to 3H schematically illustrate the steps of the manufacturing process of the quantum device 100 according to a second variant of the invention.

[0084] As illustrated in [Fig.3A], following the formation of the first grids 20, and before the thinning of the active layer 10, according to the third variant, the dielectric layer 15 is selectively removed in the inter-grid spaces 30, thus exposing the underlying active layer 10, and the flanks of the remaining parts of the dielectric layer 15 located in line with the first grids 20.

[0085] Following the removal of the dielectric layer 15 from the inter-grid spaces 30, a first spacer layer 50 is deposited on the first grids 20 and in the inter-grid spaces 30. The first spacer layer 50 is then etched into the inter-grid spaces 30, thus exposing the active layer 10 in the inter-grid spaces 30. This first spacer layer 50 covers the flanks of the first grids 20, as well as the flanks of the remaining parts of the dielectric layer 15. Unlike the second variant, where the flanks of the remaining parts of The dielectric layer 15 remains exposed during the thinning step. In this third variant, the first spacer layer 50 protects the flanks of the first grids 20, as well as the flanks of the remaining portions of the dielectric layer 50, during thinning, particularly by etching. This prevents the phenomenon commonly known as "bird's beak." Bird's beak does not affect the positioning of the quantum dots, but it can alter or disrupt the coupling between the first grids 20 and the underlying active layer 10. According to the third variant, the first spacer layer 50 prevents the formation of bird's beak, thus improving electrostatic control via the first grids 20.

[0086] As illustrated in Figures 3B and 3C, according to this third variant, the thinning can then be carried out, respectively, either by a only partial etching along the z direction of the active layer 10, or by only partial oxidation of the active layer 10 along the z direction.

[0087] Thinning by etching is achieved by removing material from the active layer 10 directly above the inter-grid spaces 30, thus forming hollows of material in the active zone 10, delimiting thinned zones 11, as illustrated in [Fig.3B].

[0088] Oxidation thinning is achieved by forming oxidized zones 17 in the active layer 10, delimiting thinned zones 11 in the active layer 10, as illustrated in [Fig.3C].

[0089] As described previously, the first spacer layer 50 allows control of the lateral dimensions of the oxidized areas 17 or of the hollows formed following the etching, and consequently, those of the thinned areas 11. A localized, almost "point-by-point" thinning of the active layer 10 can thus be obtained.

[0090] For the sake of simplicity, figures 3D to 3G illustrate the following steps of the process, following thinning by etching. Those skilled in the art could easily adapt these figures to visualize the subsequent steps in the case of thinning by oxidation.

[0091] As illustrated in [Fig. 3D], following the formation of the thinned areas 11, a second layer of spacer 51 can be deposited on the first layer of spacer 50, and in the inter-grid spaces 30. This second layer of spacer 51 makes it possible, in particular, to cover the exposed parts of the thinned areas 11.

[0092] As illustrated in [Fig.3E], a second dielectric layer 16 is then deposited on the spacer 50, 51 so as to cover the first grids 20 and to fill the inter-grid spaces 30.

[0093] As illustrated in [Fig. 3F], a conventional lithography / etching step is then carried out on the second dielectric layer 16, in order to define apertures 60 through the dielectric layer 16 and the inter-grid spaces 30. The apertures 60 extend along the z-direction to the surface of the spacer layer 51 in the inter-grid spaces 30. Preferably, the openings 60 stop within the hollows formed in the active layer 10.

[0094] As illustrated in [Fig. 3G], a network of second grids 40 is then formed. The formation of the second grids 40 comprises, as before, the deposition of a grid layer on the dielectric layer 16 and in the openings 60. The grid layer is then planarized, typically by CMP with a stop on the second dielectric layer 16. Second grids 40 are thus formed in the inter-grid spaces 30, alternating with the first grids 20. Each second grid 40 overlies a thinned area 11.

[0095] As with the second variant, a final quantum device 100 is thus obtained, either by etching thinning, as illustrated in [Fig. 3G], or by oxidation thinning as illustrated in [Fig. 3H]. As shown by comparing these two examples illustrated in Figures 3G and 3H, etching thinning brings the second grids 40 closer to the thinned areas 11. Preferably, the second spacer layer 51 can be in direct contact with the thinned areas 11 and the second grids 40. Advantageously, these second grids 40 can have a lower end located below a plane passing through an upper face of the active layer 10.

[0096] In the variants described above, a quantum device 100 comprising an active layer 10 surmounted by an array of first gates 20 juxtaposed along the x-direction has been shown. This device 100 can be, for example, a CMOS (Complementary Metal-Oxide-Semiconductor) type device, in which the active layer 10 is, for example, a silicon-based nanowire extending along the x-direction. This nanowire can have a mesa structure on the support layer S. In the case of mesa-type integration, oxidation can also act on the lateral dimensions of the mesa structures. This silicon nanowire can host quantum dots under the first gates 20 arranged in a one-dimensional (1D) manner.Other types of quantum devices 100 can also be envisaged, such as a two-dimensional (2D) CMOS type device in which the active layer 10 can be surmounted by an array of first grids 20 arranged along the x and y directions, as illustrated in [Fig.4].

[0097] Figure 4 illustrates a top view of a 2D CMOS device 100 in the xy plane. For the sake of simplicity, Figure 4 does not show the spacer 50, the dielectric layer 16, or the second grids 40. In this embodiment, thinned areas 11 can be made according to any of the variants described above. These thinned areas 11 can be located under first inter-grid spaces 30 situated between the first grids 20 in the x direction, as by For example, zones 111. According to another example, the thinned zones 11 can be located under second inter-grid spaces 30 situated between the first grids 20 in the y direction, such as zones 112. According to another example, the thinned zones 11 can be located under inter-grid spaces 30 situated between the first and second inter-grid spaces 30, such as zones 113.

[0098] By way of example, the thinned zones 11, 111, 112, 113 can have different thicknesses, whether in a 1D or 2D device. For example, the zones 111 of [Fig. 4] can have a first thickness 111 <el0, les zones 112 peuvent présenter une deuxième épaisseur el 12<el0 et les zones 113 peuvent présenter une troisième épaisseur el 13< 10, telles que ellUell2#:ell3.

[0099] As illustrated in [Fig. 5], the quantum device 100 may comprise a substrate stacked along the z-direction, consisting of a support layer S, an active layer 10 comprising thinned regions 11, and an additional layer 70 on top of the active layer 10, preferably made of the same material as the support layer S. According to this example, the thinning step of the active layer 10 is carried out before the formation step of the first grids 20. The additional layer 70 is then formed on top of the active layer 10 comprising the thinned regions 11. The stack may also include other layers, such as, for example, a third dielectric layer 80 deposited on top of the layer 70. The first grids 20 can then be formed on the stack, ensuring the alignment of the grids 20 with respect to the thick regions of the active layer 10.In one scenario, the S support and the additional layer 70 are SiGe-based, and the active layer 10 is Si-based. The stacking of the S / 10 / 70 layers then forms a SiGe / Si / SiGe heterostructure. The spin qubit host region is located in the Si-based active layer 10. In an alternative scenario, the S support and the additional layer 70 are SiGe-based, and the active layer 10 is Ge-based. In this case, the stacking of the S / 10 / 70 layers forms a SiGe / Ge / SiGe heterostructure. The spin qubit host region is located in the Ge-based active layer 10.

[0100] Figures 6A to 6C illustrate the results of a simulation of the position of two adjacent quantum dots of the quantum device of the present invention, in an xz plane for different values ​​of the thickness el1 of the thinned regions. The x-axis represents the distance along the x direction and the y-axis represents the distance along the y direction. In this simulation, the active layer 10 is silicon-based and has a thickness el0 = 10 nm.

[0101] As described previously, the trade-off between controlling the position of the QDs by structural confinement and tunnel coupling of the QDs with each other can be optimized by adjusting the thickness el 1 of the thinned zones 11. Indeed, by decreasing the thickness el 1 of a thinned zone 11, the structural confinement increases and the tunnel coupling decreases. By increasing the thickness ell of a thinned zone 11, the structural confinement decreases and the tunnel coupling increases.

[0102] Figure 6A illustrates an example in which the material recession is 0 nm. In this case, the thickness el1 is equal to the thickness el0. The structural confinement is homogeneous throughout the active layer 10. The structural confinement is no greater at the inter-grid gaps than under the grids. The simulation shows that the two quantum dots fuse under the application of an electrical potential on the order of 200 mV to the second grid overlying the unthinned region between the quantum dots.

[0103] Figure 6B illustrates a case where the material shrinkage is on the order of 4 nm (the thickness ell is on the order of 6 nm). In this case, the quantum dots do not fuse, even when potentials above 400 mV are applied. The quantum dot coupling regime remains usable for potential values ​​above 800 mV, corresponding to tunneling coupling above 10³ peV.

[0104] Figure 6C illustrates a case where the material withdrawal is on the order of 8 nm (the thickness ell is on the order of 2 nm). In this case, the overlap between the two quantum dots is limited, and the maximum achievable tunneling coupling is reduced.

[0105] Therefore, for a silicon-based active layer 10 with a thickness of approximately 10 nm, the optimal thickness el 1 of the thinned regions 11 is approximately 6 nm. For material removal greater than 8 nm, tunnel coupling is considerably reduced.

[0106] The invention is not limited to the embodiments previously described.

Claims

Demands

1. Quantum device (100) comprising in stacking along a direction z: • a support layer (S), • an active layer (10) based on a semiconductor material above the support layer (S) and having a thickness elO, • a dielectric layer (15) above the active layer (10), • a network of first grids (20) above the dielectric layer (15), the first adjacent grids (20) of the network being separated from each other by spaces (30) called inter-grids, said device (100) being characterized in that the active layer (10) comprises, below the inter-grid spaces (30), thinned areas (11) based on the semiconductor material, said thinned areas (11) each having at least a thickness el 1 > 0 such that ell < elO.

2. Quantum device (100) according to the preceding claim, wherein at least one thickness ell of the thinned regions (11) is such that ell < 0.8*el0.

3. Quantum device (100) according to any one of the preceding claims, further comprising an array of second grids (40) arranged in the inter-grid spaces (30) alternately with the first grids (20), such that each second grid (40) surmounts a thinned area.

4. Quantum device (100) according to the preceding claim, wherein the second grids (40) have an end located below a plane passing through an upper face of the active layer (10).

5. Quantum device (100) according to any one of the two preceding claims, comprising at least one spacer layer (50) covering flanks of the first grids (20), said at least one spacer layer (50) being intercalated between the second grids (40) and the thinned areas (11).

6. Quantum device (100) according to any one of the preceding claims, wherein a first part of the thinned areas (11) has a first thickness el 11 < elO, and a second part of the thinned zones (11) has a second thickness el 12 < elO, the first thickness el 11 being different from the second thickness ell2.

7. Quantum device (100) according to the preceding claim, wherein the thinned areas (11) of the first part are located under inter-grid spaces (30) situated between first grids (20) along a first direction (x), and wherein the thinned areas (11) of the second part are located under inter-grid spaces (30) situated between first grids (20) along a second direction (y).

8. Quantum device (100) according to any one of the preceding claims, comprising at least one additional layer (70) overlying the active layer (10) and directly in contact with the active layer (10), said additional layer (70) and the substrate (S) being SiGe-based and the active layer (10) being Si- or Ge-based, such that the substrate (S), the active layer (10) and the additional layer (70) form a SiGe / Si / SiGe or SiGe / Ge / SiGe heterostructure.

9. Quantum device (100) according to any one of the preceding claims, wherein the thickness elO of the active layer (10) is on the order of 10 nm and the thickness el 1 of the thinned regions (11) is between 8 nm and 2 nm, preferably on the order of 6 nm.

10. A method for manufacturing a quantum device (1) according to any one of the preceding claims, said method comprising: • providing a support layer (S) and an active layer (10) based on a semiconductor material above the support layer (S), said active layer (10) having a thickness el0, • forming a dielectric layer (15) above the active layer (10), • forming, on the dielectric layer (15), a network of first grids (20), the first adjacent grids (20) of the network being separated from each other by inter-grid spaces (30), the process being characterized in that it further comprises: • a only partial thinning of the active layer (10), along the z direction directly above the intergrid spaces (30), so as to form in the active layer (10) the thinned zones (11).

11. A method according to the preceding claim, wherein the thinning is carried out, after selective removal of the dielectric layer (15) in the inter-grid spaces (30), by a local and only partial oxidation along the z direction of the active layer (10).

12. Method according to claim 10, wherein the thinning is carried out, after selective removal of the dielectric layer (15) in the inter-grid spaces (30), by a only partial etching along the z direction of the active layer (10).

13. A method according to any one of claims 10 to 12, further comprising, before thinning the active layer (10), a deposit of a first spacer layer (50) on flanks of the first grids (20), so as to protect said flanks during thinning.

14. A method according to any one of claims 10 to 13, further comprising, after thinning of the active layer (10), a deposit of a second spacer layer (51) on flanks of the first grids (20) and on exposed parts of the thinned areas (H).

15. Method according to the preceding claim, further comprising, after deposition of the second spacer layer (50), the formation of a network of second grids (40) arranged in the inter-grid spaces (30), alternating with the first grids (20).

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