Field-effect transistor
The MOSFET transistor design with a conductive gate structure and cavities/spacers enhances RF switch performance by reducing RON resistance and parasitic capacitance, addressing the balance challenge in existing technologies.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- CENT NAT DE LA RECH SCI (C N R S)
- Filing Date
- 2024-12-05
- Publication Date
- 2026-06-12
Smart Images
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Abstract
Description
Title of the invention: Field-effect transistor technical field
[0001] This description relates generally to electronic components and more particularly to MOSFET type field-effect transistors (from the English "Metal Oxide Semiconductor Field Effect Transistor"). Previous technique
[0002] MOSFET type transistors are field-effect transistors comprising an electrically conductive gate isolated from a semiconducting layer by a dielectric layer called a gate insulator.
[0003] Various realizations of MOSFET transistors have already been proposed.
[0004] It would be desirable to overcome at least in part some of the drawbacks of known realizations of MOSFET transistors.
[0005] We are particularly interested here in improving the electrical performance of MOSFET transistors intended for radio frequency (RF) signal switching applications, also called RF switches. Summary of the invention
[0006] To this end, one embodiment provides a transistor comprising, on a semiconductor layer, a stack of a gate insulator and a conductive gate disposed on and in contact with the gate insulator, in which: - the conductive grid comprises a lower part and an upper part, the lower part of the conductive grid being shorter than the length of the upper part of the conductive grid; and - two cavities filled with a gas or a vacuum are arranged between the upper part of the conductive grid and the grid insulator, on either side of the lower part of the conductive grid, the transistor further comprising spacers covering the sides of the upper part of the conductive gate, said spacers being separated from the sides of the lower part of the conductive gate by the cavities.
[0007] According to one embodiment, the cavities have a width in the range of 5 nm to 30 nm.
[0008] According to one embodiment, the cavities have a height in the range of 5 nm to 50 nm.
[0009] According to one embodiment, the upper and lower parts of the conductive grid are made of the same material.
[0010] According to one embodiment, the lower and upper parts of the conducting grid are made of polycrystalline silicon.
[0011] According to one embodiment, the lower part and the upper part of the conductive grid are made of two different materials.
[0012] According to one embodiment, the lower part of the conductive grid is made of silicon-germanium and the upper part of the conductive grid is made of polycrystalline silicon.
[0013] According to one embodiment, the semiconductor layer corresponds to a silicon substrate or to a silicon layer of a silicon-on-insulator type substrate.
[0014] Another embodiment provides a method for manufacturing a transistor comprising the steps of: - formation, on a semiconductor layer, of a stack of a grid insulator and a conductive grid, the conductive grid being formed on and in contact with the grid insulator, the conductive grid having a lower part and an upper part, the lower part of the conductive grid having a length less than the length of the upper part of the conductive grid; - formation of spacers covering the sides of the upper part of the conductive grid, the formation of the spacers defining two cavities, filled with a gas or vacuum, arranged between the upper part of the conductive grid and the grid insulator, on either side of the lower part of the conductive grid, said spacers being separated from the sides of the lower part of the conductive grid by the cavities.
[0015] According to one embodiment, the formation of the conductive grid consists of the deposition of a layer of the conductive grid and its etching.
[0016] According to one embodiment, the lower and upper parts of the conductive grid are made of the same material and the conductive grid is formed in a single step.
[0017] According to one embodiment, the etching of the conductive grid is an anisotropic etching.
[0018] According to one embodiment, the lower and upper parts of the conductive grid are made of two different materials and the formation of the conductive grid comprises a first step of forming the lower part of the conductive grid on and in contact with the grid insulator and a second step of forming the upper part of the conductive grid on and in contact with the lower part of the conductive layer.
[0019] According to one embodiment, the etching of the conductive grid comprises an anisotropic etching of the upper part of the conductive grid and an isotropic etching of the lower part of the conductive grid.
[0020] According to one embodiment, the spacers are formed by a non-conforming deposition method. Brief description of the drawings
[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0022] [Fig.1] is a partial and schematic cross-sectional view of an example of a transistor according to a first embodiment;
[0023] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D] and [Fig.2E] are partial and schematic cross-sectional views of structures obtained at the end of successive steps of an example of a manufacturing process for the transistor of [Fig.1];
[0024] [Fig. 3] is a partial, schematic cross-sectional view of an example of a transistor according to a second embodiment; and
[0025] [Fig. 4A], [Fig. 4B], [Fig. 4C], [Fig. 4D], [Fig. 4E], and [Fig. 4F] are partial, schematic cross-sectional views of structures obtained after successive steps in an example of a manufacturing process for the transistor of [Fig. 3]. Description of embodiments
[0026] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.
[0027] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and detailed. In particular, the various applications that the described transistors may have have have not been detailed.
[0028] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.
[0029] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.
[0030] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.
[0031] Fig. 1 is a partial, schematic cross-sectional view of an example of a transistor 10 according to a first embodiment.
[0032] The transistor 10 has a semiconductor layer 11 surmounted by a dielectric layer 13 also called gate insulator.
[0033] The semiconductor layer 11 is, for example, made of silicon, for example, monocrystalline silicon. By way of example, the semiconductor layer 11 may correspond to a silicon substrate. Alternatively, the semiconductor layer 11 may correspond to the upper silicon layer of a silicon-on-insulator (SOI) substrate. The semiconductor layer may, for example, have a thickness in the range of 10 nm to 500 nm, for example in the range of 50 nm to 200 nm, for example on the order of 70 nm.
[0034] By way of example, the grid insulator 13 is made of silicon dioxide (SiO2). By way of example, the grid insulator 13 has a thickness in the range of 1 nm to 15 nm, for example, in the range of 3 nm to 7 nm.
[0035] The grid insulator 13 is for example disposed on and in contact with the semiconductor layer 11.
[0036] The transistor 10 further comprises a conductive layer 17, also called a conductive gate, on the gate insulator layer 13. The conductive gate 17 is disposed on and in contact with the gate insulator 13.
[0037] In this embodiment, the conductive grid 17 comprises a lower part 171 and an upper part 173, the upper part 173 being disposed on and in contact with the lower part 171 and the lower part 171 being formed on and in contact with the grid insulator 13.
[0038] In [Fig.1], the lower part 171 of the conductive grid 17 has a length L1 less than the length L2 of the upper part 173 of the conductive grid 17. Thus, the conductive grid has a shorter length on the side of its lower face, i.e. on the side of the grid insulator 13.
[0039] For example, the length L1 is constant over the entire height of the lower part 171 of the grid 17. For example, the length L2 is constant over the entire height of the upper part 173 of the grid 17.
[0040] By way of example, the upper part 173 of the conductive grid 17 is arranged on the surface of the lower part 171 by being centered on it.
[0041] The conductive grid 17 thus includes, along its entire width, notches 25 ("notch" in English) revealing a part of the upper face of the grid insulator 13. By way of example, the grid 17 includes two notches 25 formed on either side of the grid 17.
[0042] In the embodiment of [Fig.1], the conductive gate 17 is made of doped polycrystalline silicon.
[0043] By way of example, the length L2 is within a range from 50 nm to 300 nm, for example within a range from 80 nm to 200 nm, for example on the order of 100 nm. By way of example, parts 171 and 173 of the conductive grid layer 17 have a length difference within a range from 10 nm to 60 nm, for example on the order of 20 nm. By way of example, the notches 25 have a width (measured in the cutting plane of [Fig. 1]) between 5 nm and 30 nm, for example on the order of 10 nm.
[0044] The conductive grid 17 has, for example, a width in the range from 1 pm to 10 pm, for example on the order of 5 pm.
[0045] The layer 17 has, for example, a thickness in the range from 30 nm to 300 nm, for example in the range from 50 nm to 150 nm, for example on the order of 120 nm.
[0046] By way of example, the lower part 171 has a thickness in the range of 2.5 nm to 50 nm, for example on the order of 10 nm.
[0047] The transistor 10 comprises, for example, a source region 21 and a drain region 23 formed in the semiconductor layer 11. The source region 21 and the drain region 23 are, for example, separated laterally from each other by a body region. An upper portion of the body region constitutes the channel-forming region 24 of the transistor 10. The conductive gate layer 17 is, for example, located above the channel-forming region 24.
[0048] By way of example, the source 21, drain 23 and body regions are flush with the top face of the semiconductor layer 11.
[0049] The transistor 10 is, for example, an N-channel MOS transistor (NMOS), that is to say, a transistor whose source 21 and drain 23 regions are N-type doped, for example doped with arsenic or phosphorus atoms, while the body region is P-type doped, for example doped with boron atoms.
[0050] Alternatively, the transistor 10 is, for example, a P-channel MOS transistor (PMOS), that is to say, a transistor whose source 21 and drain 23 regions are P-type doped, for example doped with boron atoms, while the body region is N-type doped, for example doped with arsenic or phosphorus atoms.
[0051] The transistor 10 further comprises two cavities 27, filled with a gas or a vacuum, arranged on either side of the lower part 171 of the conductive gate 17 in the slots 25. The cavities 27 are arranged between the upper part 173 of the conductive gate 17 and the gate insulator 13. By way of example, the cavities 27 do not extend beyond the opposite side of the upper part 173 of the conductive gate 17. By way of example, the cavities 27 extend over the entire width of the gate 17.
[0052] By way of example, the gas present in the cavities 27 comprises nitrogen, hydrogen bromide, tetraethyl orthosilicate (TEOS), and bis(fluoroxy)perfluoromethane (CF4O2), argon, or any other gas resulting from chemical reactions occurring during transistor manufacturing, for example, reactions between silane (SiH4) and ammonia (NH3), and / or present in the atmosphere of the manufacturing equipment. Alternatively, the cavities 27 are partially filled with a vacuum.
[0053] The transistor 10 further includes spacers 29, covering, on both sides, the flanks of the upper part 173 of the conductive gate 17. By way of example, the transistor 10 includes a first spacer 29 formed, on a first side of the gate 17 on the lateral flanks of the gate 17. By way of example, the transistor 10 further includes a second spacer 29 formed, on a second side of the gate 17, opposite to the first side with respect to the length of the gate 17, on the lateral flanks of the gate 17. The spacers are, for example, in lateral contact with the flanks of the upper part 173 of the conductive gate 17.
[0054] In this embodiment, the spacers 29 extend opposite the sides of the lower part 171 of the conductive grid 17. By way of example, the spacers 29 are in contact, by their lower face, with the upper face of the grid insulation layer 13. Each spacer 29 is spaced from the side of the lower part 171 of the conductive grid 17 which it covers by a cavity 27.
[0055] The spacers 29 extend for example over the entire width of the grid 17.
[0056] In the embodiment illustrated in [Fig. 1], the spacers 29 have a "D" shape "whose lower face is essentially flat.
[0057] Alternatively, the spacers 29 have an "L" shape, the vertical part of which covers the lateral sides of the upper part of the grid 17 and the lateral sides of the cavities 27, and the horizontal part of which covers the upper face of the grid insulator 13.
[0058] The spacers 29 are for example made of an insulating material, for example silicon nitride (Si3N4), tungsten carbide, silicon carbide, aluminium oxide, beryllium oxide, magnesium oxide, zirconium oxide, silicon, aluminium silicate, silicon oxide, borophosphosilicate glass, borosilicate glass, phosphosilicate glass, fluorosilicate glass, undoped silicate glass and / or hexagonal boron nitride (hBN).
[0059] By way of example, the transistor 10 includes an insulating layer, not shown, disposed on and in contact with the sides of the conductive gate 17. This insulating layer is, for example, made of oxide or nitride. By way of example, this insulating layer is made of silicon nitride (Si3N4). The spacers 29 are, for example, in contact with this insulating layer opposite the sides of the upper part 173 of the gate 17.
[0060] The transistors 10 are advantageously RF switches, for example intended to operate at frequencies between 3 kHz and 300 GHz, for example between 100 MHz and 10 GHz, for example on the order of GHz. In such an application, a low parasitic capacitance COFF in the transistor's off state and a low resistance RON in the transistor's on state are desired, while maintaining good voltage handling.
[0061] An advantage of the present embodiment is that the formation of the cavities 27 makes it possible to reduce the length of grid 17 in contact with the grid insulator 13 and thus reduce the RON resistance of the switch.
[0062] Another advantage of the present embodiment is that the provision of cavities 27 in the lower part of the grid allows the COFF capacitance of the switch to be reduced.
[0063] This embodiment therefore makes it possible to optimize the RON and COFF compromise for the RF switch.
[0064] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D and Fig. 2E are partial and schematic cross-sectional views of structures obtained at the end of successive steps of an example of a manufacturing process for the transistor of Fig. 1.
[0065] The [Fig.2A] is a starting structure comprising a stacking of the grid insulator layer 13 on the upper face of the semiconductor layer 11. By way of example, the grid insulator layer 13 is in contact, by its lower face, with the upper face of the semiconductor layer 11.
[0066] By way of example, in the starting structure illustrated in [Fig.2A], the grid insulator layer 13 covers the entire upper face of the semiconductor layer 11. By way of example, the grid insulator layer 13 is formed on the surface of the semiconductor layer 11 by oxidation of the same layer.
[0067] Fig. 2B illustrates a structure obtained after a step of forming the conductive grid layer 17 on the upper face of the grid insulator layer 13. The grid layer 17 is formed, for example, by a diffusion furnace deposition process.
[0068] Alternatively, the grid layer 17 is deposited by a vapor phase deposition process, for example a vapor phase epitaxy process.
[0069] Fig. 2C illustrates a structure obtained after a step of forming a masking layer 30 in resin on the upper face of the structure illustrated in Fig. 2B,
[0070] More specifically, during this step, the masking layer 30 is formed in contact with the upper face of the grid layer 17. After deposition, the masking layer 30 undergoes a photolithography step, i.e., it is locally exposed to rays, for example ultraviolet rays, and then rinsed. The layer mask 30 then corresponds, at the end of these steps, to an etching mask for the underlying layer 17.
[0071] The resin of the mask layer 30 is for example a photosensitive resin, for example a positive photosensitive resin.
[0072] Fig. 2D illustrates a structure obtained after an etching step of the conductive grid layer 17 from the structure illustrated in Fig. 2C.
[0073] By way of example, the conductive grid layer 17 is etched in a single etching operation, which may optionally comprise several steps. By way of example, the etching of the grid 17 includes a dry etching, for example, a chemical plasma etching.
[0074] By way of example, the conductive grid layer 17 is etched in a single etching operation, for example by modifying the bias parameters during etching in order to form the notch 25 in the lower part 171 of the grid layer 17. By way of alternative or complementary method, the formation of the notch 25 may include, after etching the layer 17, a re-oxidation step of a lower part of the grid, followed by a removal step of the re-oxidized part, for example by wet etching, for example, with hydrofluoric acid.
[0075] At the end of this step, the resin layer 30 is for example removed from the upper face of the grid 17.
[0076] Fig. 2E illustrates a structure obtained at the end of a step of forming spacers 29 on the upper face of the structure illustrated in Fig. 2D.
[0077] By way of example, the spacers 29 are formed by a chemical vapor deposition process, for example plasma-assisted.
[0078] The spacers 29 are formed in a non-conforming manner, that is to say they are formed with a non-uniform thickness over the entire surface of the structure illustrated in [Fig.2D].
[0079] The non-conforming characteristic of the deposit allows the notches 25 formed in the grid 17 not to be filled by the material of the spacers 29, thus trapping gas in the notches 25 and forming the cavities 27.
[0080] By way of example, the gas trapped in the cavities 27 corresponds to the precursor gas used during the deposition of the spacers 29.
[0081] Alternatively, the gas trapped in the cavities 27 corresponds to the precursor gas used during the etching of the grid 17.
[0082] By way of example, the cavities 27 have a cubic shape.
[0083] Alternatively, the cavities 27 may have, in the cross-sectional plane of [Fig. 2E], an L-shape or a D-shape. Indeed, the shape of the cavities 27 depends on the filling capacity of the notches 25. Thus, if the notches 25 are easily filled, the material of the spacers 29 will tend to fill at least part of them. The notches 25 and the cavities 27 will have an L shape. Conversely, if the notches 25 are difficult to fill, the material of the spacers 29 will not tend to fill the notches 25 and the cavities 27 will have a cubic shape.
[0084] By way of example, the spacers 29 are formed by depositing a layer of the spacer material over the entire upper face of the structure illustrated in [Fig. 2D]. Following the deposition of said layer, it is, for example, etched by anisotropic dry etching so as to be retained only around the grid 17 and to form the spacers 29.
[0085] Following this step, the source 21 and drain 23 regions are formed, for example, in the structure illustrated in [Fig. 2E] so as to form the transistor 10 illustrated in [Fig. 1]. By way of example, the source 21 and drain 23 regions are formed by implanting dopants in the semiconductor layer 11.
[0086] Figure 3 is a partial, schematic cross-sectional view of an example of a transistor 40 according to a second embodiment.
[0087] Transistor 40 is similar to transistor 10 except that, in transistor 40, the lower part 171 and the upper part 173 of the conductive gate 17 do not have the same natures.
[0088] In the embodiment of [Fig.3], the upper part 173 of the grid 17 is based on polycrystalline silicon.
[0089] In the embodiment of [Fig. 3], the lower portion 171 of the gate 17 is based on germanium-doped polycrystalline silicon. By way of example, the lower portion 171 of the gate has a germanium content in the range of 15% to 35%, for example, on the order of 25% by mass.
[0090] Alternatively, the lower part 171 of the gate layer 17 is made of a material other than silicon-germanium, having an etching rate higher than that of silicon. The lower part 171 of the gate layer 17 is, for example, made of silicon-germanium-carbon (SiGeC), or of doped silicon-germanium (SiGe), comprising, for example, boron, phosphorus, or arsenic atoms as dopants.
[0091] An advantage of the present embodiment is that the silicon-germanium of the lower part 171 of the gate 17 makes it possible to improve the depletion of the polycrystalline silicon of the upper part 173 of the gate 17, that is to say it makes it possible to reduce the poly depletion area, by a better activation of dopants allowing to reduce the threshold voltage.
[0092] Fig. 4A, Fig. 4B, Fig. 4C, Fig. 4D, Fig. 4E and Fig. 4F are partial and schematic cross-sectional views of structures obtained at the end of successive steps of an example of a manufacturing process for the transistor of Fig. 3.
[0093] This manufacturing process is similar to that described in relation to Figures 2A to 2E, with the difference that the lower and upper parts of the grid 17 are made of different materials, which has an impact on their deposition and on the engraving step of the grid 17.
[0094] Fig. 4A illustrates a starting step identical to that illustrated in Fig. 2A.
[0095] Figure 4B illustrates a structure obtained at the end of a formation step of the lower part 171 of the conductive grid layer 17 on the upper face of the grid insulating layer 13.
[0096] By way of example, the lower part 171 of the conductive grid layer 17 is deposited by reduced pressure chemical vapor deposition or RPCVD (from the English "Reduced Pressure Chemical Vapor Deposition").
[0097] The lower part of the conductive grid layer 17 covers, for example, the entire upper face of the grid insulator 13. As an example, the lower part 171 of the conductive grid layer 17 is deposited with a thickness in the range of 5 nm to 100 nm, for example on the order of 40 nm.
[0098] Fig. 4C illustrates a structure obtained at the end of a step of forming the upper part 173 of the conductive grid layer 17 on the upper face of the lower part 173 of the conductive grid layer 17.
[0099] By way of example, the upper part 173 of the conductive grid layer 17 is formed by a vapor phase deposition process, for example a vapor phase epitaxy process.
[0100] By way of example, the upper part 173 of the grid layer 17 is deposited in the same deposition chamber as the lower part 171.
[0101] Alternatively, the deposition of the lower part 171 and the upper part 173 of the layer 17 is carried out in two different deposition chambers. By way of example, the upper part 173 of the layer 17 is deposited in a diffusion furnace.
[0102] The upper part 173 of the conductive grid layer 17 covers, for example, the entire upper face of the lower part 171 of the conductive grid layer 17. As an example, the upper part 173 of the conductive grid layer 17 is deposited with a thickness in the range of 25 nm to 250 nm, by a thickness of approximately 80 nm.
[0103] Fig. 4D illustrates a structure obtained after a step of forming a masking layer 30 in resin on the upper face of the structure illustrated in Fig. 4C.
[0104] The formation of the masking layer 30 is for example similar to what has been described previously in relation to [Fig.2C].
[0105] Fig. 4E illustrates a structure obtained after an etching step of the conductive grid layer 17 from the structure illustrated in Fig. 4D.
[0106] By way of example, the engraving of grid 17 involves three successive engraving steps.
[0107] By way of example, the engraving of the grid 17 includes an anisotropic engraving step of the upper part 173 of the grid 17. This engraving step is, for example, selective so that only the upper part 173 of the grid 17 is engraved.
[0108] During this step, the upper part 173 of the grid 17 is engraved so that, at the end of this step, the sides of the upper part 173 are aligned with the resin layer 30. By way of example, the engraving here is a dry engraving.
[0109] By way of example, the engraving of the grid 17 further includes an anisotropic engraving step of the lower part 171 of the grid 17. This engraving step is, for example, selective so that only the lower part 171 of the grid 17 is engraved.
[0110] During this step, the lower part 173 of the grid 17 is engraved so that, at the end of this step, the sides of the lower part 171 are aligned with the resin layer 30 and the upper part 173 of the grid layer 17. By way of example, the engraving here is a dry engraving.
[0111] By way of example, the engraving of the grid 17 further includes an isotropic engraving step of the lower part 171 of the grid 17. This engraving step is further, for example, selective so that only the lower part 171 of the grid 17 is engraved.
[0112] During this step, the lower part 171 of the grid 17 is engraved laterally, so as to create, under the upper part 173 of the grid layer 17, the notches 25.
[0113] At the end of this step, a lower part 171 is then arranged under the upper part 173 of the grid 17, set back from the sides of the upper part 173 of the grid 17.
[0114] At the end of this step, the sides of the upper part 173 of the grid layer 17 are aligned with the resin layer 30. As an example, the etching here is a dry etching.
[0115] By way of example, these three etching steps are chemical etchings by plasma in which the nature of the species in the plasma, their percentages, the velocity of the flow and the bias make it possible to define the anisotropic or isotropic nature of the etching and its selectivity.
[0116] Alternatively, the isotropic etching of the lower part 171 is a wet etching.
[0117] Alternatively, the etching of the lower part 171 of the grid layer 17 can be carried out in a single isotropic etching operation allowing at the same time the removal of the layer of the lower part 171 outside the face of the resin layer 30 and under a peripheral part of the resin layer 30.
[0118] Fig. 4F illustrates a structure obtained at the end of a step of forming spacers 29 on the upper face of the structure illustrated in Fig. 4E.
[0119] This step is identical to the step described in relation to [Fig.2E].
[0120] At the end of this step, the source 21 and drain 23 regions are formed, for example, in the structure illustrated in [Fig. 4F] so as to form the transistor 40 illustrated in [Fig. 3]. The step of forming the source 21 and drain 23 regions is identical to the cell described at the end of the process described in Figures 2A to 2E.
[0121] An advantage of the second embodiment is that it allows cavities 27 to be formed in the notches 25.
[0122] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.
[0123] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
Claims
Demands
1. Transistor (10; 40) comprising, on a semiconducting layer (11), a stack of a gate insulator (13) and a conductive gate (17) disposed on and in contact with the gate insulator (13), in which: - the conductive gate (17) has a lower part (171) and an upper part (173), the lower part (171) of the conductive gate (17) having a length less than the length of the upper part (173) of the conductive gate (17); and - two cavities (27) filled with a gas or vacuum are disposed between the upper part (173) of the conductive gate (17) and the gate insulator (13), on either side of the lower part (171) of the conductive gate (17), the transistor further comprising spacers (29) covering the flanks of the upper part (173) of the conductive gate (17), said spacers (29) being separated from the flanks of the lower part (171) of the conductive gate (17) by the cavities (27).
2. Transistor according to claim 1, wherein the cavities (27) have a width in the range from 5 nm to 30 nm.
3. Transistor according to claim 1 or 2, wherein the cavities (27) have a height in the range of 5 nm to 50 nm.
4. Transistor according to any one of claims 1 to 3, wherein the upper part (173) and the lower part (171) of the conductive gate (17) are made of the same material.
5. Transistor according to claim 4, wherein the lower part (171) and the upper part (173) of the conductive gate (17) are made of polycrystalline silicon.
6. Transistor according to any one of claims 1 to 3, wherein the lower part (171) and the upper part (173) of the conductive gate (17) are made of two different materials.
7. Transistor according to claim 6, wherein the lower part (171) of the conductive gate (17) is made of silicon-germanium and the upper part (173) of the conductive gate (17) is made of polycrystalline silicon.
8. Transistor according to any one of claims 1 to 7, wherein the semiconductor layer (11) corresponds to a substrate silicon or a silicon layer of a silicon-on-insulator substrate.
9. Method of manufacturing a transistor comprising the steps of: - forming, on a semiconductor layer (11), a stack of a gate insulator (13) and a conductive gate (17), the conductive gate (17) being formed on and in contact with the gate insulator (13), the conductive gate (17) comprising a lower part (171) and an upper part (173), the lower part (171) of the conductive gate (17) having a length less than the length of the upper part (173) of the conductive gate (17);- formation of spacers (29) covering the sides of the upper part (173) of the conductive grid (17), the formation of the spacers (29) defining two cavities (27), filled with a gas or a vacuum, arranged between the upper part (173) of the conductive grid (17) and the grid insulator (13), on either side of the lower part (171) of the conductive grid (17), said spacers (29) being separated from the sides of the lower part (171) of the conductive grid (17) by the cavities (27).;
10. Method according to claim 9, wherein the formation of the conductive grid (17) consists of the deposition of a layer of the conductive grid (17) and its etching.
11. Method according to claim 10, wherein the lower part (171) and the upper part ((173) of the conductive grid (17) are of the same material and the conductive grid (17) is formed in a single step.
12. Method according to claim 11, wherein the etching of the conductive grid (17) is an anisotropic etching.
13. A method according to claim 10, wherein the lower part (171) and the upper part (173) of the conductive grid (17) are made of two different materials and the formation of the conductive grid (17) comprises a first step of forming the lower part (171) of the conductive grid (17) on and in contact with the grid insulator (13) and a second step of forming the upper part (173) of the conductive grid (17) on and in contact with the lower part (171) of the conductive layer (17).
14. A method according to claim 13, wherein the engraving of the conductive grid (17) comprises an anisotropic engraving of the part
15. upper (173) of the conductive grid (17) and an isotropic etching of the lower part (171) of the conductive grid (17). A method according to any one of claims 9 to 14, wherein the spacers (29) are formed by a non-conforming deposition method.